Power MOSFET device and its manufacturing method

Abstract

The present application relates to the field of semiconductor technologies, and discloses a power MOSFET device and a method for manufacturing the same. The power MOSFET device includes: a semiconductor substrate; a body region extending from the surface of the semiconductor substrate into the semiconductor substrate, and a doped region formed in the body region; the body region includes a first region serving as a cell region and a second region located around the first region; a first trench and a second trench passing through the first region, a third trench passing through the second region, the depth of the second trench is less than the depth of the first trench, and gate dielectric layers are provided on the inner walls of the first trench and the second trench; a first metal plug located in the first trench, a second metal plug located in the second trench, and a third metal plug located in the third trench, and a Schottky junction is formed between the second metal plug and the bottom of the second trench. The power MOSFET device can reduce the forward conduction voltage and improve the frequency characteristics of the device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to a power MOSFET device and a method for manufacturing the same. Background Art

[0002] A MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) is a field-effect transistor that can be widely used in analog circuits and digital circuits. A power MOSFET refers to a MOSFET device in the power output stage, usually with an operating current greater than 1 A. Currently, the mainstream power MOSFET types on the market mainly include Planar, Trench, Lateral, SuperJunction, and Advanced Trench MOSFETs with different internal structures formed due to technological changes.

[0003] The Trench type MOSFET is a type of power MOSFET with very high cost performance. For example, a VDMOSFET (Vertical Double Diffused Metal-Oxide-Semiconductor Field-Effect Transistor) with a U-shaped trench, due to having the advantages of both bipolar transistors and ordinary MOS devices, especially having a negative temperature coefficient and no secondary breakdown problem of bipolar power, therefore, whether used as a switching application or a linear application, the U-shaped trench VDMOSFET (referred to as UMOS) is an ideal power device.

[0004] However, the forward on-state voltage drop of traditional UMOS is generally 0.7 V - 0.8 V. In special application scenarios such as high-frequency rectification, switching circuits, and protection circuits under low voltage and high current, a lower forward on-state voltage drop is often required, and traditional UMOS cannot meet the requirements in the above special application scenarios. Summary of the Invention

[0005] In some embodiments of this application, a power MOSFET device and a method for manufacturing the same are provided to reduce the forward on-state voltage drop of UMOS, so as to meet the usage requirements in certain special application scenarios.

[0006] In some embodiments, the power semiconductor device includes:

[0007] A semiconductor substrate;

[0008] A body region extending from the surface of a semiconductor substrate into the semiconductor substrate, and a doped region formed within the body region; the body region includes a first region as a cell region and a second region located around the first region;

[0009] A first trench and a second trench passing through the first region, a third trench passing through the second region, the depth of the second trench being less than the depth of the first trench, and gate dielectric layers being provided on the inner walls of the first trench and the third trench;

[0010] A first metal plug located in the first trench, a second metal plug located in the second trench, and a third metal plug located in the third trench, a Schottky junction being formed between the second metal plug and the bottom of the second trench;

[0011] A first interlayer dielectric layer covering the body region, openings corresponding to the first trench, the second trench, and the third trench being provided on the first interlayer dielectric layer; the first metal plug, the second metal plug, and the third metal plug respectively extend into their corresponding openings, and the tops of the first metal plug, the second metal plug, and the third metal plug are at least not lower than the surface of the first interlayer dielectric layer;

[0012] A second interlayer dielectric layer located on the surface of the first interlayer dielectric layer, the second interlayer dielectric layer covering the first trench, and lead-out openings being provided in the second interlayer dielectric layer to respectively expose the second metal plug and the third metal plug.

[0013] In some embodiments, a method for manufacturing a power semiconductor device includes:

[0014] Forming a body region in a semiconductor substrate, a doped region in the body region, and a first interlayer dielectric layer covering the body region, wherein the body region includes a first region as a cell region and a second region located around the first region, the first interlayer dielectric layer being provided with a first opening and a second opening corresponding to the first region, and a third opening corresponding to the second region;

[0015] Etching the semiconductor substrate corresponding to the first opening and the third opening to form a first trench passing through the first region and a third trench passing through the second region;

[0016] Forming gate dielectric layers on the inner walls of the first trench and the third trench;

[0017] Etching the semiconductor substrate corresponding to the second opening to form a second trench passing through the first region;

[0018] Deposit metal into the first trench, the second trench, and the third trench respectively; react the metal in the second trench with the semiconductor substrate to form a Schottky junction; and perform etch-back or planarization on the deposited metal to respectively form a first metal plug, a second metal plug, and a third metal plug in the first trench, the second trench, and the third trench;

[0019] Form a second interlayer dielectric layer on the upper surface of the first interlayer dielectric layer;

[0020] Etch the second interlayer dielectric layer to form an outlet, exposing the second metal plug and the third metal plug.

[0021] Adopting the power semiconductor device and its manufacturing method provided in the embodiments of the present application has the following technical effects:

[0022] The overlapping part of the trench gate (including the first trench and the third trench) and the body region is the channel region. The metal plugs filled in the first trench and the third trench (including the first metal plug and the third metal plug) and the gate insulating layer (including the first insulating layer and the second insulating layer) constitute a capacitive structure. When the trench gate is at a high potential, the channel region is inverted into the same conduction type as the source and drain, and this inverted channel shorts the Schottky junction to achieve the conduction between the drain and the source; when the high potential of the trench gate disappears, the inverted channel also disappears, and the Schottky junction operates in the reverse cut-off region to achieve the turn-off between the drain and the source. Relying on the Schottky junction to achieve the conduction or turn-off between the drain and the source. At the same time, the forward barrier of the Schottky junction is lower than that of the PN junction, and only one majority carrier participates in conduction when the Schottky junction works, without carrier recombination, and the switching speed is faster. Therefore, integrating the Schottky structure in the UMOS structure can reduce the forward conduction voltage of the UMOS and improve the frequency characteristics of the device to meet the requirements of special application scenarios such as high-frequency rectification, switching circuits, and protection circuits under low voltage and large current. Description of the Drawings

[0023] Figure 1 is a schematic structural diagram of a power MOSFET device provided by an embodiment of the present application;

[0024] Figures 2 to 21 is a schematic structural diagram of a semiconductor device in each step of a manufacturing method of a power MOSFET device provided by an embodiment of the present application;

[0025] Figures 22 to 26 is a schematic diagram of a mask structure in the manufacturing process of a power MOSFET provided by an embodiment of the present application.

[0026] Description of the Reference Numerals:

[0027] 200: Substrate; 300: Epitaxial layer; 400: Body region; 500: Doped region; 600: First interlayer dielectric layer; 700: Second interlayer dielectric layer; 800: Photoresist; 901: First electrode; 902: Gate; 11: First trench; 12: Second trench; 13: Third trench; 21: Gate dielectric layer; 31: First metal plug; 32: Second metal plug; 33: Third metal plug; 41: First metal layer; 42: Second metal layer; 43: Third metal layer; 50: Schottky junction; 61: First opening; 62: Second opening; 63: Third opening; 71: First photoresist opening; 72: Second photoresist opening; 73: Third photoresist opening. Detailed implementation manners

[0028] In order to more comprehensively understand the features and technical content of the embodiments of the present application, the implementation of the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The attached drawings are only for reference and explanation, and are not used to limit the embodiments of the present application. In the following technical description, for the sake of explanation, numerous details are provided to give a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures may be shown in a simplified manner to simplify the drawings.

[0029] The terms "first", "second", etc. in the specification, claims and above-mentioned drawings of the embodiments of the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that such data may be interchanged under appropriate circumstances so as to implement the embodiments of the present application described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion.

[0030] In the embodiments of the present application, the power MOSFET device and its manufacturing method are exemplarily described by applying them to UMOS, which does not constitute a substantial limitation on the power MOSFET device and its manufacturing method provided by the embodiments of the present application. The power MOSFET device and its manufacturing method can also be applied to other types of power MOSFET devices with U-shaped trenches.

[0031] Figure 1 is a schematic structural diagram of a power MOSFET device provided by an embodiment of the present application. Combining Figure 1 as shown, the power MOSFET device includes:

[0032] A semiconductor substrate;

[0033] A body region 400 extending from the surface of a semiconductor substrate into the semiconductor substrate, the body region 400 including a first region as a cell region (Main cell region) and a second region as a gate region, the second region being located around the first region;

[0034] A doped region 500 formed within the body region 400;

[0035] A first trench 11 and a second trench 12 passing through the first region, and a third trench 13 passing through the second region, the depth of the second trench 12 being less than the depth of the first trench 11, and gate dielectric layers 21 being provided on the inner walls of the first trench 11 and the third trench 13; the depths of the first trench 11, the second trench 12, and the third trench 13 are all greater than the thickness of the body region 400;

[0036] A first metal plug 31 located within the first trench 11, a second metal plug 32 located within the second trench 12, and a third metal plug 33 located within the third trench 13, a Schottky junction being formed between the second metal plug 32 and the bottom of the second trench 12;

[0037] A first interlayer dielectric layer 600 covering the body region 400, openings corresponding to the first trench 11, the second trench 12, and the third trench 13 being provided on the first interlayer dielectric layer 600; the first metal plug 31, the second metal plug 32, and the third metal plug 33 respectively extend into their corresponding openings, and the tops of the first metal plug 31, the second metal plug 32, and the third metal plug 33 are at least not lower than the surface of the first interlayer dielectric layer 600;

[0038] A second interlayer dielectric layer 700 located on the surface of the first interlayer dielectric layer 600, the second interlayer dielectric layer 700 covering the first trench 11, and lead-out ports being provided in the second interlayer dielectric layer 700 to respectively expose the second metal plug 32 and the third metal plug 33.

[0039] In specific applications, for different types of power MOSFET devices, the selection of the semiconductor substrate is also different. For UMOS, an epitaxial wafer can be used as the semiconductor substrate; for other types of power MOSFET devices, it is not excluded to use a single crystal wafer as the semiconductor substrate. The epitaxial wafer can be obtained through commercial purchase, or can be obtained by depositing an epitaxial layer on the surface of a substrate using processes such as CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition).

[0040] In the embodiments of the present application, the thickness of the gate dielectric layer 21 is not specifically limited, and those skilled in the art can configure the thickness of the appropriate gate dielectric layer 21 according to the threshold voltage requirements of the device. For example, a gate dielectric layer 21 with a thickness of 250 angstroms can be used.

[0041] It should be noted that in this embodiment, UMOS is taken as an example for illustration. The first trench 11 in the Main Cell area and the third trench 13 in the Gate area are jointly used to form a trench gate. Therefore, based on an achievable layout, the second trench 12 is located in the area defined by the first trench 11 and is arranged in an array within this area; the third trench 13 is located outside the area defined by the first trench 11 and is connected to the first trench 11. In other layout structures, the arrangement of various trenches can also be set according to the trench type and function.

[0042] The overlapping part of the trench gate and the body region 400 is the channel region. The metal plugs filled in the first trench 11 and the third trench 13 (including the first metal plug 31 and the third metal plug 33) and the gate dielectric layer 21 form a capacitive structure. When the trench gate is at a high potential, the channel region is inverted into the same conduction type as the source and drain, and this inverted channel shorts the Schottky junction 50, realizing the conduction between the drain and the source; when the high potential of the trench gate disappears, the inverted channel also disappears, and the Schottky junction 50 operates in the reverse cut-off region, realizing the turn-off between the drain and the source. Relying on the Schottky junction 50 to realize the conduction or turn-off between the drain and the source, at the same time, the forward barrier of the Schottky junction 50 is lower than that of the PN junction, and only one type of majority carrier participates in conduction when the Schottky junction 50 works, and there is no carrier recombination, so the switching speed is faster. Therefore, integrating the Schottky junction 50 in the UMOS structure can reduce the forward conduction voltage of the UMOS and improve the frequency characteristics of the device to meet the requirements of special application scenarios such as high-frequency rectification, switching circuits, and protection circuits under low voltage and large current.

[0043] In addition, different from the properties of the commonly used doped polysilicon semiconductor, the first metal plug 31 is arranged in the first trench 11, and the third metal plug 33 is arranged in the third trench 13. When a bias voltage is applied, effects such as carrier offset and depletion will not occur, the gate withstand voltage is stable, the gate charge is low, and the response speed is fast; the resistance of the metal is low, the gate resistance is low, and the reaction is faster during alternating signals, which can effectively reduce the switching time; the process cost of depositing doped polysilicon is high, and the equipment maintenance cost is high. In the embodiments of the present application, the polysilicon deposition process can be not used, reducing the process cost.

[0044] The aforementioned first metal plug 31 may be a "U"-shaped solid structure that fits the groove shape; or it may also be a "U"-shaped hollow structure, but the side walls of the hollow structure need to be continuous. Similarly, for the aforementioned second metal plug 32 and third metal plug 33, they may be a "U"-shaped hollow structure or a "U"-shaped solid structure (non-hollow structure).

[0045] In a specific application, when the first metal plug 31, the second metal plug 32, and the third metal plug 33 are hollow structures, although there will be a very small loss of the ultimate current-carrying capacity, their respective basic functions can still be ensured. Compared with the solid-structured metal plugs, the metal plugs with hollow structures can not only shorten the process, but also reduce the stress on the wafer caused by the grooves (especially the first groove 11 and the third groove 13), and to a certain extent avoid the warping of the wafer.

[0046] When the first metal plug 31, the second metal plug 32, and the third metal plug 33 are hollow structures, the first metal plug 31, the second metal plug 32, and the third metal plug 33 respectively and independently include a first metal layer 41 and a second metal layer 42; the first metal layer 41 covers the gate dielectric layer 21 and the inner wall of the second groove 12, and extends to the first interlayer dielectric layer 600; the second metal layer 42 is connected to one end of the first metal layer 41 away from the semiconductor substrate; the upper surface of the second metal layer 42 is flush with the upper surface of the first interlayer dielectric layer 600; the first metal layer 41 and the second metal layer 42 define a receiving cavity, and the receiving cavity is a hollow cavity.

[0047] When the first metal plug 31, the second metal plug 32, and the third metal plug 33 are solid structures, the first metal plug 31, the second metal plug 32, and the third metal plug 33 respectively and independently include a first metal layer 41 and a second metal layer 42; the first metal layer 41 covers the gate dielectric layer 21 and the inner wall of the second groove 12, and extends to the first interlayer dielectric layer 600; the second metal layer 42 is connected to one end of the first metal layer 41 away from the semiconductor substrate; the upper surface of the second metal layer 42 is flush with the upper surface of the first interlayer dielectric layer 600; the first metal layer 41 and the second metal layer 42 define a receiving cavity, and the receiving cavity is filled with a third metal layer 43.

[0048] In a specific application, the material for forming the first metal layer 41 may be Ti (titanium) or a Ti / TiN stack; the material for forming the second metal layer 42 may be TiN; the material for forming the third metal layer 43 may be W (tungsten).

[0049] When the first metal plug 31, the second metal plug 32, and the third metal plug 33 are of a hollow structure, the second metal layer 42 can serve as an adhesion layer for increasing metal adhesion and a barrier layer for preventing metal diffusion. For the second metal plug 31, the first metal layer 41 can form a silicide with the epitaxial layer 300 of the semiconductor substrate, and this silicide is the Schottky junction 50.

[0050] When the first metal plug 31, the second metal plug 32, or the third metal plug 33 is of a solid structure, it is equivalent to filling the hollow structure with a third metal layer 43, and the third metal layer 43 can increase the conductivity of the first metal plug 31, the second metal plug 32, or the third metal plug 33. At this time, the second metal layer 42 can wrap the third metal layer 43 to prevent the diffusion of the third metal layer 43.

[0051] Those skilled in the art can select the hollow structure or the solid structure according to the actual situation, and the embodiments of the present application do not make specific limitations in this regard.

[0052] In the specific implementation process, by controlling the filling degree of the first metal layer 41 in the first trench 11 and the third trench 13, especially the thickness of the first metal layer 41 relative to the bottom of the trench, it is possible to effectively improve wafer warping on the premise of ensuring the normal realization of the functions of the power MOSFET device. Practice has proved that when the thickness of the first metal layer 41 in the trench depth direction of the first trench 11 and the third trench 13 is 1 / 6 to 2 / 3 of the trench depth, wafer warping can be reduced; for example, when the thickness of the first metal layer 41 in the trench depth direction of the first trench 11 and the third trench 13 is 1 / 6, 1 / 5, 1 / 3, 1 / 2, or 2 / 3 of the trench depth, especially from 1 / 3 to 1 / 2, wafer warping can be effectively avoided. In actual production, equipment with strong hole filling capabilities such as SIP (Self-Ionized Plasma Physical Vapor Deposition), IMP (Ionized Metal Plasma Physical Vapor Deposition), and RFPVD (Radio Frequency Physical Vapor Deposition) can be selected to control the filling degree of the first metal layer 41 in the above trenches to achieve the above effects. This is not only beneficial to subsequent wafer back thinning and back metallization, reducing the risk of wafer fragmentation, but also even after wafer back thinning, the warping problem is significantly improved, thereby reducing the probability of thinned wafer fragments. In addition, for a single chip, since the stress problem is alleviated, the reliability of the device is actually improved to a certain extent.

[0053] The bottom opening width of the lead-out port of the second interlayer dielectric layer 700 is greater than the top opening widths of the second metal plug 32 and the third metal plug 33, ensuring that the first electrode 901 can contact the second metal plug 32 and not contact the first metal plug 31, and the gate 902 can contact the third metal plug 33, reducing the requirements for lithography and etching accuracy of the second interlayer dielectric layer 700; and generally, the lithography pattern size of the lead-out port is greater than 250 nm, and a lithography device using a KrF light source can be avoided, reducing the processing difficulty.

[0054] Furthermore, the upper width of the lead-out port is greater than or equal to the lower width of the lead-out port, that is, the longitudinal section of the opening is an inverted trapezoid, and the upper base (the shorter side) of the trapezoid is relatively closer to the semiconductor substrate. This facilitates subsequent metal filling.

[0055] A first front top layer metal and a second front top layer metal are formed on the upper surface of the second interlayer dielectric layer 700. Among them, the first front top layer metal covers the first metal plug 31 and the second metal plug 32, and the second front top layer metal covers the third metal plug 33. For a MOSFET, the first front top layer metal can be used as the source electrode, and the second front top layer metal is used as the gate 902.

[0056] An insulating protective layer can be deposited on the surfaces of the first front top layer metal and the second front top layer metal, and a bonding pad area is etched out of the insulating protective layer.

[0057] The back surface of the power MOSFET device is polished to metallize the back surface, serving as the second electrode. For a MOSFET, this electrode is the drain electrode.

[0058] Figures 2 to 19 It is a schematic structural diagram of a MOSFET device in each step of a method for manufacturing a power MOSFET device provided by an embodiment of the present application; Figures 20 to 24 It is a schematic diagram of a mask structure in the manufacturing process of a power MOSFET device.

[0059] Combined Figure 2 As shown, the semiconductor substrate includes a substrate 200 and an epitaxial layer 300 located on the surface of the substrate 200.

[0060] In the embodiments of the present application, the parameters of the substrate 200 and the epitaxial layer 300 are not specifically limited, and those skilled in the art can change parameters such as the resistivity of the substrate 200, the epitaxial resistivity, the epitaxial thickness, and the crystal orientation according to needs. For example, a phosphorus-doped substrate 200 with a resistivity less than 0.02 Ω·cm and a <100> crystal orientation, and a phosphorus-doped epitaxy with a resistivity greater than 0.1 Ω and a thickness greater than 2 μm can be used.

[0061] Combined Figures 3 to 6As shown, a body region 400 is formed in a semiconductor substrate, a doped region 500 is formed in the body region 400, and a first interlayer dielectric layer 600 covering the body region 400. Among them, the body region 400 includes a first region as a cell region and a second region surrounding the first region. The first interlayer dielectric layer 600 is provided with a first opening 61 and a second opening 62 corresponding to the first region, and a third opening 63 corresponding to the second region.

[0062] Combined with Figure 3 As shown, the semiconductor substrate is doped to form the body region 400. The body region 400 can be formed by implanting impurities into the epitaxial layer 300 and then annealing. In specific practice, the subsequent thermal processing will also increase the junction depth of the body region 400. Therefore, annealing after ion implantation is not a necessary step, and whether to perform annealing and adjust the annealing process can be selected according to actual process conditions. The doping impurities and doping concentration used for doping the epitaxial layer 300 can be set according to actual requirements. For example, P-type impurities such as boron with an order of magnitude of E12 or more can be implanted into the epitaxial layer 300 to form a P-type doped region as the body region 400. The body region 400 extends a certain depth from the upper surface of the substrate 200 into the substrate 200, and those skilled in the art can flexibly adjust it according to the parameter performance requirements of the device.

[0063] Combined with Figure 4 As shown, N-type impurity ions with an order of magnitude of E15 / cm 2 or more are implanted into the body region 400 and annealed to form the doped region 500. The doped region 500 extends a set depth from the upper surface of the body region 400 into the interior. Those skilled in the art can flexibly adjust the set depth according to the parameter performance requirements of the device, as long as the set depth is less than the depth of the body region 400. The first interlayer dielectric layer 600 is deposited on the upper surface of the doped region 500. The first interlayer dielectric layer 600 can be obtained by various known silicon oxide growth methods such as PECVD (Plasma Enhanced Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), SACVD (Sub Atmospheric Chemical Vapor Deposition), thermal oxidation, SOG (Spin On Glass), etc. Those skilled in the art can flexibly select the deposition method and thickness according to different application scenarios.

[0064] A photoresist 800 is coated on the first interlayer dielectric layer 600, and then lithography is performed using the first mask as Figure 22 shown to form as Figure 5The photoresist 800 in the shown shape is then used as a mask to etch the first interlayer dielectric layer 600 to form Figure 5 The first interlayer dielectric layer 600 in the shown shape. The first interlayer dielectric layer 600 is provided with a first opening 61 and a second opening 62 corresponding to the first region, and a third opening 63 corresponding to the second region; the first opening 61 is used to locate the first trench 11, the second opening 62 is used to locate the second trench 12, and the third opening is used to locate the third trench 13.

[0065] Using the first mask for photolithography and etching the first interlayer dielectric layer 600 is the most delicate patterning process in the entire power MOSFET device. Generally, a KrF device with a 248nm light source or other devices with shorter wavelength light sources will be used.

[0066] After etching the first interlayer dielectric layer 600, the photoresist 800 is removed to form as Figure 6 The patterned first interlayer dielectric layer 600 as shown. The patterned first interlayer dielectric layer 600 is used as a Hard Mask for subsequent self-aligned etching of silicon.

[0067] Combined with Figure 7 As shown, the semiconductor substrate corresponding to the first opening 61 and the third opening 63 is etched to form the first trench 11 passing through the first region and the third trench 13 passing through the second region.

[0068] First, a photoresist 800 is coated on the first interlayer dielectric layer 600, and photolithography is performed using the second mask as Figure 23 shown to form the first photoresist pattern of the first interlayer dielectric layer 600 as Figure 7 shown. The first photoresist pattern covers all regions except those where the trench gate structure (including the first trench 11 and the third trench 13) needs to be formed. The regions of the first photoresist pattern corresponding to the first opening 61 and the third opening 63 are respectively provided with a first photoresist opening 71 and a second photoresist opening 72. The width of the first photoresist opening 71 is greater than the width of the first opening 61, and the width of the second photoresist opening 72 is greater than the width of the third opening 61. Then, using the first photoresist pattern and the first interlayer dielectric layer 600 as masks, the semiconductor substrate corresponding to the first opening 61 and the third opening 63 is etched to form as Figure 7 shown the first trench 11 passing through the first region and the third trench 13 passing through the second region. Then the photoresist is removed.

[0069] In a specific application, the depths of the first trench 11 and the third trench 13 must be greater than the thickness of the body region 400 so that the first trench 11 and the third trench 13 pass through the body region 400 and extend into the epitaxial layer 300 of the semiconductor substrate.

[0070] During the formation of the first trench 11 and the third trench 13, by selecting the etching conditions, the selectivity ratios of silicon to the photoresist 800 and the first interlayer dielectric layer 600 are ensured, and silicon etching is performed in the areas not covered by the photoresist 800 or the first interlayer dielectric layer 600, thereby achieving self-aligned etching.

[0071] The width of the first photoresist opening 71 is greater than the width of the first opening 61, and the width of the second photoresist opening 72 is greater than the width of the third opening 61, reducing the requirements for the accuracy of the lithography machine and improving the redundancy of overlay.

[0072] Combined with Figure 8 As shown, a gate dielectric layer 21 is formed on the inner walls of the first trench 11 and the third trench 13.

[0073] On the inner walls of the first trench 11 and the third trench 13, the gate dielectric layer 21 is grown by thermal oxidation. Those skilled in the art can set the thickness of the gate dielectric layer 21 according to the threshold voltage requirements of the semiconductor power device. For example, a gate dielectric layer 21 with a thickness of 250 angstroms can be used.

[0074] Combined with Figure 9 As shown, the semiconductor substrate corresponding to the second opening 62 is etched to form a second trench 12 passing through the first region.

[0075] First, a photoresist 800 is coated on the first interlayer dielectric layer 600, and lithography is performed using the third mask as shown in Figure 24 to form a second photoresist pattern as shown in Figure 9 on the first interlayer dielectric layer 600. The second photoresist pattern covers all areas except the area where the second trench 12 needs to be formed. The area of the second photoresist pattern corresponding to the second opening 62 is provided with a third photoresist opening 73, and the width of the third photoresist opening 73 is greater than the width of the second opening 62. Then, using the second photoresist pattern and the first interlayer dielectric layer 600 as masks, the semiconductor substrate corresponding to the second opening 62 is etched to form a second trench 12 passing through the first region as shown in Figure 9 . After that, the photoresist is removed.

[0076] The width of the third photoresist opening 73 is greater than the width of the second opening 62, reducing the requirements for the lithography machine and improving the redundancy of overlay.

[0077] The depth of the second trench 12 is greater than the thickness of the body region 400, so that the second trench 12 passes through the body region 400 and extends into the epitaxial layer 300 of the semiconductor substrate; the depth of the second trench 12 is less than the depth of the first trench 11 or the third trench 13.

[0078] During the process of etching the second trench 12, by selecting the etching conditions, the selectivity between silicon and the photoresist 800 and the first interlayer dielectric layer 600 is ensured, and silicon etching is performed in the areas not covered by the photoresist 800 or the first interlayer dielectric layer 600, thereby achieving self-aligned etching.

[0079] As shown in Figures 10 to 14 , metal is deposited into the first trench 11, the second trench 12, and the third trench 13 respectively; through rapid thermal annealing or alloying, the metal in the second trench 12 reacts with the semiconductor substrate to form a Schottky junction 50; and the deposited metal is etched back or planarized to respectively form a first metal plug 31, a second metal plug 32, and a third metal plug 33 in the first trench 11, the second trench 12, and the third trench 13.

[0080] In Figures 10 to 14 , taking the first metal layer 41 as Ti or a Ti / TiN stack, the second metal layer 42 as TiN, and the third metal layer 43 as W as an example, the process of forming the first metal plug 31, the second metal plug 32, and the third metal plug 33 from the first metal layer 41, the second metal layer 42, and the third metal layer 43 is exemplarily described.

[0081] As shown in Figure 10 , the first metal layer 41 is formed. The first metal layer 41 covers the gate dielectric layer 21 and the inner wall of the second trench 12, and correspondingly extends into the opening of the first interlayer dielectric layer 60; wherein, the first metal layer 41 covering the gate dielectric layer 21 in the first trench 11 can define a receiving cavity in the first trench 11, the first metal layer 41 covering the inner wall of the second trench 12 can define a receiving cavity in the second trench 12, and the first metal layer 41 covering the gate dielectric layer 21 in the third trench 13 can define a receiving cavity in the third trench 13. Then, the third metal layer 43 is formed on the first metal layer 41, and the third metal layer 43 fills the receiving cavities in the first trench 11, the second trench 12, and the third trench 13.

[0082] Further, in the process of forming the first metal layer 41, the thickness of the first metal layer 41 along the groove depth direction of the first groove 11 and the third groove 13 can be 1 / 6 to 2 / 3 of the groove depth. By controlling the filling degree of the first metal layer 41 in the first groove 11 and the third groove 13, especially the thickness of the first metal layer 41 relative to the groove bottom, the wafer warpage can be effectively improved on the premise of ensuring the normal realization of the power MOSFET device function. In addition, for a single chip, since the stress problem is alleviated, the reliability of the device is actually improved to a certain extent. Specifically, equipment with strong hole filling capabilities such as SIP, IMP, and RFPVD can be selected to control the filling degree of the first metal layer 41 in the first groove 11 and the third groove 13 to achieve the above filling effect.

[0083] Perform rapid thermal annealing or alloying treatment on the bottom of the second groove 12 to cause the metal in the second groove 12 to react with the semiconductor substrate to form a Schottky junction 50 as shown in Figure ...... Figure.

[0084] Etch back the third metal layer 43 so that the upper surface of the third metal layer 43 is lower than the surface of the first interlayer dielectric layer 600 to form a structure as shown in ​ Figure.

[0085] Combined with ​ Figure, a second metal layer 42 is formed at one end of the first metal layer 41 away from the semiconductor substrate. The top of the second metal layer 42 is at least not lower than the surface of the first interlayer dielectric layer 600. The first metal layer 41 and the second metal layer 42 define a receiving cavity, and the receiving cavity is filled with the third metal layer 43.

[0086] Among them, the second metal layer 42 includes the third metal layer 43, and the second metal layer 42 can act as a barrier layer to block the diffusion of the third metal layer 43.

[0087] Here, the second metal layer 42 can be formed by PVD or CVD methods.

[0088] Combined with ​ Figure, etch back or perform CMP on the second metal layer 42 to expose the upper surface of the first interlayer dielectric layer 600. In this way, the first metal plug 31, the second metal plug 32, and the third metal plug 33 can be respectively formed by the first metal layer 41, the second metal layer 42, and the third metal layer 43. Among them, the second metal layer 42 acts as a barrier layer to prevent the diffusion of the third metal layer 43, and the third metal layer 43 serves as a filler and a conductive layer to improve the limit current capacity of the device.

[0089] Combined with ​As shown, a second interlayer dielectric layer 700 is formed on the upper surface of the first interlayer dielectric layer 600 using a known SiO2 deposition method other than thermal oxidation, and the total thickness of the first interlayer dielectric layer 600 and the second interlayer dielectric layer 700 is greater than 2000 angstroms. The thicknesses listed here are only for illustrative purposes and do not constitute a substantial limitation on the embodiments of the present application. Those skilled in the art can adjust flexibly according to the actual situation.

[0090] Combined with ​ As shown, the second interlayer dielectric layer 700 is etched to form an outlet, exposing the second metal plug 31 and the third metal plug 33.

[0091] Specifically, a photoresist 800 can be first coated on the second interlayer dielectric layer 700, and then exposed using a fourth mask as shown in ​ As shown. In this way, the photoresist 800 covers all regions except the metal plugs (the second metal plug 32 and the third metal plug 33) that are used as two electrode leads. The second interlayer dielectric layer 700 in the region not covered by the photoresist 800 is etched until the upper surfaces of the metal plugs (the second metal plug 32 and the third metal plug 33) are exposed. Appropriate over-etching is allowed to expose part of the sidewalls of the metal plugs, but the upper surface of the first metal plug 31 in the first trench 11 cannot be exposed. Under the condition that the second interlayer dielectric layer 700 exposes the upper surfaces of the second metal plug 32 and the third metal plug 33 and does not expose the first metal plug 31, the outlet formed on the second interlayer dielectric layer 700 can be larger than the upper surfaces of the second metal plug 32 and the third metal plug 33 (as long as the upper surface of the first metal plug 31 is not exposed), that is, the opening of the fourth mask can be larger than the upper surfaces of the second metal plug 32 and the third metal plug 33, reducing the requirements for the lithography machine and improving the redundancy of the overlay at the same time.

[0092] Furthermore, during the etching process of the second interlayer dielectric layer 700, the upper width of the outlet is made greater than or equal to the lower width of the outlet, that is, the longitudinal section of the opening is trapezoidal with an inverted trapezoid shape, and the upper base (the shorter side) of the trapezoid is relatively closer to the semiconductor substrate. This facilitates subsequent metal filling.

[0093] Combined with ​ As shown, a top surface metal for the front side is deposited on the upper surface of the second interlayer dielectric layer 700, and using as shown in ​The fifth mask shown lithographs and etches the front top metal, causing the front top metal to form a first front top metal and a second front top metal. Among them, the first front top metal covers the first metal plug 31 and the second metal plug 32, and the second front top metal covers the third metal plug 33. The first front top metal and the second front top metal can adopt Ti-TiN-AlCu or AlSiCu. The first front top metal can be used as the first electrode 901 of the power MOSFET device, and the second front top metal can be used as the gate 902 of the power MOSFET device.

[0094] For a MOSFET, the first electrode 901 (the first front top metal) can be used as the source electrode.

[0095] In ​ Based on the structure shown, an insulating protective layer can be deposited on the surfaces of the first front top metal and the second front top metal, and a bonding pad area is etched out of the insulating protective layer; the back surface of the semiconductor substrate is polished to metallize the back surface, forming a second electrode. For a MOSFET, this second electrode is the drain electrode.

[0096] The foregoing ​ Exemplarily provides a process for forming the first metal plug 31, the second metal plug 32, and the third metal plug 33. In addition, the first metal plug 31, the second metal plug 32, and the third metal plug 33 can also be formed through another process.

[0097] The following embodiments provide another process for forming the first metal plug 31, the second metal plug 32, and the third metal plug.

[0098] Combined with ​ and ​ Shown, taking the first metal layer 41 as Ti or a Ti / TiN stack and the second metal layer 42 as TiN as an example, exemplarily illustrate the process of forming another first metal plug 31, second metal plug 32, and third metal plug 33 from the first metal 41 and the second metal layer 42. The first metal plug 31, the second metal plug 32, and the third metal plug 33 with a hollow structure can be formed from the first metal 41 and the second metal layer 42.

[0099] Deposit metals into the first trench 11, the second trench 12, and the third trench 13 respectively to first form a first metal layer 41. The first metal layer 41 covers the gate dielectric layer 21 and the inner wall of the second trench 12, and correspondingly extends into the opening of the first interlayer dielectric layer 60. Then, form a second metal layer 42 at one end of the first metal layer 41 away from the semiconductor substrate. The top of the second metal layer 42 is at least not lower than the surface of the first interlayer dielectric layer 600. The first metal layer 41 and the second metal layer 42 define a receiving cavity. Through rapid thermal annealing or alloying, the first metal layer 41 in the second trench 12 reacts with the semiconductor substrate to form a Schottky junction 50, forming a structure as shown in ​ shown.

[0100] Then, perform etch-back or planarization on the deposited second metal layer 42 to respectively form a first metal plug 31, a second metal plug 32, and a third metal plug 33 with a hollow structure as shown in ​ shown in the first trench 11, the second trench 12, and the third trench 13.

[0101] During the above process, PVD or CVD can be used to deposit the second metal layer 42. During the process of performing etch-back or planarization on the second metal layer 42, it is necessary to control the over-polishing amount of CMP to prevent damage to the upper surface of the closed metal plug.

[0102] ​ Although the first metal plug 31, the second metal plug 32, and the third metal plug 33 with a hollow structure as shown in

[0103] ​ lose part of their ultimate current-carrying capacity, they can still ensure the basic functions of the power MOSFET device. ​ shown is the structure after forming the second interlayer dielectric layer 700 on the basis of the structure shown in ​ For the structure after forming the first front top metal and the second front top metal on the basis of the structure shown in ​ shown. In the foregoing embodiments, the processes of forming the second interlayer dielectric layer 700, the first front top metal, and the second front top metal have been introduced in detail, and will not be elaborated here one by one.

[0104] Combined with ​ is a schematic structural diagram of a mask provided by an embodiment of the present application.

[0105] ​ is a schematic structural diagram of a first mask provided by an embodiment of the present application. ​ In it, the dotted shaded area is the area without photoresist protection after lithography.

[0106] ​ is a schematic structural diagram of a second mask provided by an embodiment of the present application.​ Among them, the slant shaded area is the area protected by the photoresist, the dot shaded area is the area of the trench gates (the first trench and the third trench) in the first mask, and the colorless areas are all the first interlayer dielectric layers.

[0107] ​ It is a schematic structural diagram of a third mask provided by an embodiment of the present application. ​ Among them, the slant shaded area is the area protected by the photoresist, the dot shaded area is the second trench area in the first mask, and the colorless area is the first interlayer dielectric layer.

[0108] ​ It is a schematic structural diagram of a fourth mask provided by an embodiment of the present application. ​ Among them, the slant shaded area is the opening area of the fourth mask, and all areas except the slant shaded area are covered by the photoresist.

[0109] The gray color is the trench gate conductive plug structure covered by the SiO2 retained by the second interlayer dielectric layer.

[0110] ​ It is a schematic structural diagram of a fifth mask provided by an embodiment of the present application. ​ Among them, the slant shaded area indicates the area of two electrodes. The top layer metal on the front side of the electrode area is covered by the photoresist. All areas outside the area are not protected by the photoresist. The top layer metal on the front side will be etched away. The top layer metal on the front side will be divided into the first top layer metal on the front side ( ​ the left slant shaded part) and the second top layer metal on the front side ( ​ the right slant shaded part). Among them, the first top layer metal on the front side can be the first electrode, and the second top layer metal on the front side can be used as the gate.

[0111] It should be understood that ​ The schematic diagram of the square cell version provided in is only used to illustrate the relative position relationship of each part, and does not limit the shape and size of the Cell area. In addition, there are various design methods such as strip cells, diamond cells, hexagonal cells, etc. The embodiments of the present application do not make specific limitations on this.

[0112] In the description of the present application, the orientation or position relationship indicated by terms such as "upper", "lower", etc. is based on the orientation or position relationship shown in the drawings. It is only for the convenience of describing the present application rather than requiring the present application to be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present application.

[0113] The specific features, structures, materials or characteristics described in the present application can be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0114] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A power MOSFET device, characterized in that, Comprising: A semiconductor substrate; A body region extending from the surface of the semiconductor substrate into the semiconductor substrate, and a doped region formed in the body region; The body region includes a first region serving as a cell region, and a second region surrounding the first region; A first trench and a second trench passing through the first region, a third trench passing through the second region, the depth of the second trench being less than the depth of the first trench, and gate dielectric layers being provided on the inner walls of the first trench and the third trench; A first metal plug in the first trench, a second metal plug in the second trench, and a third metal plug in the third trench, a Schottky junction being formed between the second metal plug and the bottom of the second trench; A first interlayer dielectric layer covering the body region, openings corresponding to the first trench, the second trench, and the third trench being provided on the first interlayer dielectric layer; the first metal plug, the second metal plug, and the third metal plug respectively extend into their corresponding openings, and the tops of the first metal plug, the second metal plug, and the third metal plug are at least not lower than the surface of the first interlayer dielectric layer; A second interlayer dielectric layer on the surface of the first interlayer dielectric layer, the second interlayer dielectric layer covering the first trench, and lead-out openings being provided in the second interlayer dielectric layer to expose the second metal plug and the third metal plug respectively; The first metal plug, the second metal plug, and the third metal plug respectively independently include: A first metal layer covering the gate dielectric layer and the inner wall of the second trench and extending to the first interlayer dielectric layer; A second metal layer connected to one end of the first metal layer away from the semiconductor substrate; Wherein, The upper surface of the second metal layer is flush with the upper surface of the first interlayer dielectric layer; The first metal layer and the second metal layer define a receiving cavity, and the receiving cavity is a cavity or filled with a third metal layer.

2. The power MOSFET device according to claim 1, wherein The thickness of the first metal layer in the depth direction of the first trench and the third trench is 1 / 6 to 2 / 3 of the trench depth.

3. The power MOSFET device according to claim 1, wherein, The material forming the first metal layer is Ti or a Ti / TiN stack; the material forming the second metal layer is TiN; the material forming the third metal layer is W.

4. The power MOSFET device according to any one of claims 1 to 3, characterized in that, The bottom width of the lead-out opening is greater than or equal to the top opening width of the second metal plug and the third metal plug; The upper end width of the lead-out opening is greater than or equal to the lower end width of the lead-out opening.

5. A method for manufacturing a power MOSFET device, characterized in that, Comprising: Forming a body region in a semiconductor substrate, forming a doped region in the body region, and a first interlayer dielectric layer covering the body region, wherein the body region includes a first region serving as a cell region and a second region surrounding the first region, the first interlayer dielectric layer is provided with a first opening and a second opening corresponding to the first region, and a third opening corresponding to the second region; Etch the semiconductor substrate corresponding to the first opening and the third opening to form a first trench passing through the first region and a third trench passing through the second region; Form a gate dielectric layer on the inner walls of the first trench and the third trench; Etch the semiconductor substrate corresponding to the second opening to form a second trench passing through the first region; Deposit metal into the first trench, the second trench, and the third trench respectively; react the metal in the second trench with the semiconductor substrate to form a Schottky junction; and perform etch-back or planarization on the deposited metal to respectively form a first metal plug, a second metal plug, and a third metal plug in the first trench, the second trench, and the third trench; Form a second interlayer dielectric layer on the upper surface of the first interlayer dielectric layer; Etch the second interlayer dielectric layer to form an outlet, exposing the second metal plug and the third metal plug; Among them, forming the first metal plug, the second metal plug, and the third metal plug includes: Form a first metal layer that covers the gate dielectric layer and the inner wall of the second trench and correspondingly extends into the opening of the first interlayer dielectric layer; Form a second metal layer at one end of the first metal layer away from the semiconductor substrate, the top of the second metal layer is at least not lower than the surface of the first interlayer dielectric layer, and the first metal layer and the second metal layer define a receiving cavity.

6. The preparation method according to claim 5, characterized in that, Etching the semiconductor substrate corresponding to the first opening and the third opening to form a first trench passing through the first region and a third trench passing through the second region includes: Form a first photoresist pattern on the first interlayer dielectric layer. The first photoresist pattern is respectively provided with a first photoresist opening and a second photoresist opening corresponding to the regions of the first opening and the third opening. The width of the first photoresist opening is greater than the width of the first opening, and the width of the second photoresist opening is greater than the width of the third opening; Using the first photoresist pattern and the first interlayer dielectric layer as a mask, etch the semiconductor substrate corresponding to the first opening and the third opening to form a first trench passing through the first region and a third trench passing through the second region.

7. The preparation method according to claim 5, wherein Etching the semiconductor substrate corresponding to the second opening to form a second trench passing through the first region includes: Form a second photoresist pattern on the first interlayer dielectric layer. The second photoresist pattern is provided with a third photoresist opening corresponding to the region of the second opening. The width of the third photoresist opening is greater than the width of the second opening; Using the second photoresist pattern and the first interlayer dielectric layer as a mask, etch the semiconductor substrate corresponding to the second opening to form a second trench passing through the first region.

8. The preparation method according to claim 7, characterized in that, Before forming the second metal layer, it further includes: forming a third metal layer on the first metal layer to fill the receiving cavity.

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