A field effect transistor device structure using point defect doping to reduce energy consumption

Abstract

The present invention provides a field effect transistor device structure that uses point defect doping to reduce energy consumption, and relates to the field of semiconductor technology. The present invention uses point defect periodic doping to improve the current switching ratio, reduce the delay time and power consumption delay product and other performance of the field effect transistor device structure; the structure respectively introduces Se (S) substitution defects and tin vacancy defects to achieve n-type and p-type defects of SnS2, thereby improving the electrical properties of the material. On this basis, using the Sn4S doped with point defects 7Se Sn5S8 is used as the channel material to construct dual-gate n-type and p-type field effect transistors, respectively. By controllably adjusting the carrier type and concentration in the channel region, the gate voltage's ability to regulate the device current is improved, the delay time and subthreshold swing are reduced, and the device's performance indicators meet the technical requirements of the semiconductor technology route for high performance and low energy consumption of field effect transistors in 2028.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a field effect transistor device structure that utilizes point defect periodic doping to improve current switching ratio and reduce performance such as delay time and power consumption delay product, and specifically to a field effect transistor device structure that utilizes point defect doping to reduce energy consumption. Background Art

[0002] In the next decade, the integrated circuit industry urgently needs to reduce the channel size of field effect transistors to less than 7nm. However, due to the influence of short channel effects, traditional silicon-based field effect transistors have serious leakage currents and unnecessary energy losses, so their size has reached the physical limit. In order to solve the above problems, people are in urgent need of finding new materials to replace silicon as the next generation of channel materials. Two-dimensional semiconductors have attracted widespread research interest due to their atomically uniform thickness, excellent electrical properties, gate control capabilities, and the absence of dangling bonds on the surface. To this end, people have studied field effect transistor devices based on several two-dimensional materials, such as two-dimensional silicene, MoS2, black phosphorus, InSe, and Bi2O2Se.

[0003] In recent years, people have successfully prepared atomic-level thick two-dimensional SnS2 using mechanical exfoliation and chemical vapor deposition methods. The controllable preparation of large-scale and uniform two-dimensional SnS2 has been achieved. On this basis, people have successfully constructed high-performance field-effect transistors based on SnS2 through experimental methods. The SnS2 field-effect transistor with a lateral scale of 410μm exhibits an ultra-high current switching ratio of about 10 8 , much higher than field-effect transistors made of black phosphorus, Bi2O2Se, tellurene and other two-dimensional materials that have been studied. However, when the channel size is reduced to less than 10nm or even shorter, SnS2 field-effect transistors can no longer maintain excellent device performance, and thus cannot meet the technical indicators of high-performance and low-energy field-effect transistors that should be achieved by 2028 as proposed by the International Semiconductor Technology Roadmap in 2018.

[0004] When using SnS2 as the channel material of a field effect transistor, it is a problem that those skilled in the art expect to overcome while reducing the channel length and improving the performance of the device and reducing the energy consumption. Summary of the invention

[0005] In response to the problems existing in the prior art, the present invention provides a transistor device structure with high current switching ratio, low delay time and subthreshold swing, which has both high performance and low power consumption, so as to solve the problem that the prior art cannot meet the high performance and low power consumption target requirements of the International Semiconductor Technology Blueprint for field effect transistors in 2028 due to limitations of short channel effects and the intrinsic electrical properties of semiconductor materials.

[0006] The present invention is achieved in that:

[0007] A field effect transistor device structure that uses point defect doping to reduce energy consumption, the structure comprising a source, a drain and a channel region between the source and the drain; the channel region comprises a channel material of an intermediate layer, a top gate and a top electrode are sequentially arranged on the upper side of the channel material, a bottom gate and a bottom electrode are sequentially arranged on the lower side of the channel material, and the channel material is Sn4S 7Se Channel material: Sn4S 7Se The channel material is a Sn4S doped with n-type by replacing one sulfur atom with one selenium atom in every four SnS2 cells. 7Se Unit cell. The substitution of one selenium atom for one sulfur atom, i.e., the introduction of Se(S) substitution defects, destroys the intrinsic lattice structure of SnS2, resulting in a reduction in the band gap of the channel material in the middle layer. At the same time, a large number of electrons are injected, and the vertical Schottky barrier of electrons is reduced to a greater extent than that of holes. The electrons jump from the bottom of the conduction band to the top of the valence band, and finally achieve n-type doping.

[0008] Furthermore, in the n-type field effect transistor device, the materials of the source, drain and channel regions are all single-layer Sn4S 7Se ; The electron concentration of the source and drain is 1.0×10 18 -5.0×10 22 e / cm 3 ; In the channel region, Sn4S 7Se The upper and lower surfaces of the channel material are covered with a dielectric layer made of BN to form a double-gate structure; metal gate voltages are set on the dielectric layers on the upper and lower surfaces respectively, and the carrier type and concentration in the channel region of the field effect transistor device are regulated by the double gate voltage.

[0009] The present invention discloses a field effect transistor device structure that uses point defect doping to reduce energy consumption. The channel material is Sn5S8 channel material. The Sn5S8 channel material is doped with one tin atom in every four SnS2 crystal cells to form a p-type doped Sn5S8 crystal cell. The introduction of tin atom interstitial defects destroys the intrinsic lattice structure of SnS2, resulting in a reduction in the material band gap. At the same time, a large number of holes are injected. The vertical Schottky barrier of the holes is reduced to a greater extent than that of the electrons. The holes can more easily transition from the top of the valence band to the bottom of the conduction band, ultimately achieving p-type doping.

[0010] Furthermore, in the p-type field effect transistor device, the materials of the source, drain and channel regions are all Sn5S8 channel materials; the hole concentration of the source and drain is 1.0×10 18 -5.0×10 22 e / cm 3; In the channel region, dielectric layers made of HfO2 are respectively covered on the upper and lower surfaces of the Sn5S8 channel material to form a double gate structure; metal gate voltages are respectively set on the dielectric layers on the upper and lower surfaces, and the carrier type and concentration in the channel region of the field effect transistor device are regulated by the double gate voltage.

[0011] Furthermore, the thickness of the top gate and the bottom gate on the upper and lower surfaces is 4-100nm, and the top electrode and the bottom electrode together constitute a gate electrode, each of which has a thickness of 4-100nm; in a p-type field effect transistor, the top gate is composed of HfO2, and in an n-type field effect transistor, the top gate is composed of BN; in a p-type field effect transistor, the bottom gate is composed of HfO2, and in an n-type field effect transistor, the bottom gate is composed of BN.

[0012] Furthermore, the type of the point defect determines the electrical properties of the SnS2, thereby affecting the device performance of the field effect transistor. The substitution position of the substitution defect determines the doping type of the SnS2, and the type of the substitution atom determines the doping degree, thereby affecting the device performance of the field effect transistor.

[0013] The beneficial effects of the present invention compared with the prior art are:

[0014] The field effect transistor device structure with specific point defect periodic doping provided by the present invention realizes n-type and p-type defects of SnS2 by introducing Se(S) substitution defects and tin vacancy defects, respectively, to improve the electrical properties of the material. 7Se Sn5S8 is used as the channel material to construct dual-gate n-type and p-type field effect transistors, respectively. By controllably adjusting the carrier type and concentration in the channel region, the gate voltage's ability to regulate the device current is improved, the delay time and subthreshold swing are reduced, and the device's performance indicators meet the technical requirements of the semiconductor technology route for high performance and low energy consumption of field effect transistors in 2028. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 4 SnS2 repeating units in the embodiment of the present invention, i.e., the top view and the side view of the Sn4S8 unit cell;

[0016] Figure 2 In each Sn4S8 unit cell, one sulfur atom is replaced by a selenium atom. 7Se Top and side views of;

[0017] Figure 3 Top and side views of Sn5S8 doped with one tin interstitial defect in each Sn4S8 unit cell;

[0018] Figure 4A schematic diagram of the structure of a double-gate transistor using Sn4S8 as a channel material before point defects are introduced provided in Example 1 of the present invention;

[0019] Figure 5 A Sn4S with specific substitution defects introduced in the second embodiment of the present invention is provided. 7Se A schematic diagram of a double-gate n-type field effect transistor structure with a channel material;

[0020] Figure 6 A schematic diagram of the structure of a double-gate p-type window effect transistor using Sn5S8 as the channel material after introducing specific interstitial defects provided in the third embodiment of the present invention;

[0021] Figure 7 In Examples 1 to 3 of the present invention, the changes in the band structure of Sn4S8 before and after being doped with different types of point defects, different doping positions and different doping atoms are compared;

[0022] Figure 8 The transfer characteristic curves of the Sn4S8 n-type field effect transistor before and after being doped with different types of point defects, different doping positions and different doping atoms in Examples 1 to 3 of the present invention.

[0023] Fig. 9 The transfer characteristic curves of the Sn4S8 p-type field effect transistor before and after being doped with different types of point defects, different doping positions and different doping atoms in Examples 1 to 3 of the present invention.

[0024] Among them, 1-source, 2-drain, 3-channel region, 4-single layer Sn4S8 before point defect doping, 5-top gate, 6-bottom gate, 7-top electrode, 8-bottom electrode, 9-Sn4S 7Se Channel material, 10-Sn5S8 channel material. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and effect of the present invention clearer and more specific, the present invention is further described in detail by enumerating examples below. It should be noted that the specific implementation described here is only used to explain the present invention and is not used to limit the present invention.

[0026] A field effect transistor device structure for reducing energy consumption by point defect doping includes a source 1, a drain 2, and a channel region 3 between the source 1 and the drain 2; the channel region 3 includes a middle layer of channel material, a top gate 5 and a top electrode 7 are sequentially arranged on the upper side of the channel material, and a bottom gate 6 and a bottom electrode 8 are sequentially arranged on the lower side of the channel material. Figure 1 As shown, the unit cell of a single-layer material consisting of 2×2 SnS2 unit cells before the introduction of point defects, namely Sn4S8. Figure 2The material unit cell is formed by the substitution of Se for one S atom in each Sn4S8 monolayer unit cell, that is, Sn4S 7Se . Figure 3 A material unit cell with a Sn atomic defect is interstitially doped into each Sn4S8 monolayer unit cell, namely Sn5S8.

[0027] Embodiment 1

[0028] like Figure 4 As shown, Figure 4 The schematic diagram of the structure of a field effect transistor using a single layer of Sn4S8 before point defect doping as the channel material provided in the first embodiment of the present invention. The field effect transistor comprises: a single layer of Sn4S8 before point defect doping of intrinsic semiconductor properties, the beginning and the end of the single layer of Sn4S84 before point defect doping respectively extend to the source 1 and the drain 2, becoming the electrode materials of the source and the drain. The source 1 and the drain 2 respectively inject electrons or holes in the n-type field effect transistor or the p-type field effect transistor, and the injection concentration is 1.0×10 18 -5.0×10 22 e / cm 3 . In the middle channel region 3, the upper and lower surfaces of the single-layer Sn4S8 before point defect doping are respectively provided with a top gate 5 and a bottom gate 6, both of which have a thickness of 4-100nm. A top electrode 7 and a bottom electrode 8 with a thickness of 4-100nm are provided on the upper surface of the top gate 5 and the lower surface of the bottom gate 6. The top gate 5 and the metal electrode 7 in contact with it together constitute a top gate structure, and the bottom gate 6 and the metal electrode 8 in contact with it together constitute a bottom gate structure. In an n-type field effect transistor, the top gate 5 and the bottom gate 6 are composed of BN with a dielectric constant of about 4; in a p-type field effect transistor, the top gates 5 and 6 are composed of HfO2 with a dielectric constant of about 40. The carrier type and concentration in the channel region can be further regulated by controlling the gate voltage of the top gate and the bottom gate, thereby achieving the purpose of improving the performance of the device.

[0029] Embodiment 2

[0030] Figure 5 The Sn4S8 nanostructured ... 7Se The channel material in Example 2 is Sn4S 7Se Channel material 9: Sn4S 7Se Channel material 9 is formed by replacing one sulfur atom with one selenium atom in every four SnS2 cells to form n-type doped Sn4S 7Se The channel region of this field effect transistor is entirely made of Sn4S 7Se The entire device structure is the same as that of the first embodiment.

[0031] Embodiment 3

[0032] Figure 6 A schematic diagram of the structure of a field effect transistor with Sn5S8 as the channel material, in which a Sn interstitial defect is doped into each Sn4S8 unit cell, provided in the third embodiment of the present invention. The channel material described in the third embodiment is a Sn5S8 channel material 10, in which a tin atom is doped into every four SnS2 units to form a p-type doped Sn5S8 unit cell. The channel region of the field effect transistor is entirely composed of Sn5S8, and the entire device structure is the same as that of the first embodiment.

[0033] As shown in Table 1, Table 1 compares the changes in lattice parameters and electrical properties of Sn4S8 before and after being doped with different types of point defects, different doping positions and different doping atoms in Examples 1 to 3 of the present invention. The addition of different types of point defects in perfect Sn4S8 will affect its original lattice parameters to varying degrees. For example, the formation of Sn5S8 expands the lattice parameters of Sn4S8 by 23.39%, while the addition of an S interstitial defect in each Sn4S8 unit cell increases the buckling height by 47.47%, while the changes in lattice parameters and buckling height caused by the addition of other types of point defects, including S vacancies and interstitial defects, Sn vacancies and interstitial defects, do not exceed the above two deformation levels. The positive values ​​of the point defect formation energy of the material relative to Sn4S8 after the formation of various point defects indicate that the point defects can stably exist in the Sn4S8 lattice and can be used to prepare field effect transistor devices.

[0034] Table 1

[0035]

[0036] like Figure 7 As shown in Figure 2, the addition of different types of point defects will destroy the lattice structure of the perfect Sn4S8 crystal, resulting in a significant reduction in the band gap. The band gap of Sn3S8 is even reduced to zero, achieving a transition from semiconductor to semi-metallic properties, while Sn4S 7Se The band gap of Sn4S8 changes the least. At the same time, different types of point defects show different carrier doping effects on Sn4S8. Combining the changes in the work function in Table 1, it can be seen that the S vacancy defect adds electrons to Sn4S8, which reduces the work function and shows n-type doping; while the S interstitial defect adds holes to Sn4S8, resulting in an increase in the work function and showing p-type doping. Sn4S 7Se The work function of Sn5S8 is lower than that of Sn4S8, showing an n-type doping effect; the work function of Sn5S8 is slightly higher than that of Sn4S8, showing a weak p-type doping effect.

[0037] Figure 8Sn4S8 was used as the channel material before and after doping with different types of point defects. The gate length was 5.5 nm, the dielectric layer thickness was 0.41 nm, and the electron doping concentration in the source and drain regions was 1.0×10 19 e / cm 3 The transfer characteristic curve of the manufactured n-type field effect transistor is within the gate voltage range of -0.4-1.0V when the gate voltage is 0.64V. Compared with Sn4S8 before doping, only Sn4S 7Se It can enhance the controllability of gate voltage on device drain current, while other point defect doping will weaken the controllability of gate voltage on device drain current, even in Sn4S9, Sn3S8 and Sn 3Pb In field effect transistors with S8 as the channel material, the gate voltage loses its ability to regulate the drain current because the band gap is reduced too significantly and the conductivity is too strong.

[0038] Fig. 9 Sn4S8 was used as the channel material before and after doping with different types of point defects. The gate length was 5.5 nm, the dielectric layer thickness was 0.41 nm, and the hole doping concentration in the source and drain regions was 1.0×10 19 e / cm 3 The transfer characteristic curve of the fabricated p-type field effect transistor with a gate voltage of 0.64V and a gate voltage range of 0-1.4V. Compared with Sn4S8 before doping, only Sn5S8 can enhance the controllability of the gate voltage on the device drain current, while other point defect doping will weaken the controllability of the gate voltage on the device drain current. Even in field effect transistors with Sn4S9 and Sn3S8 as channel materials, the gate voltage loses its ability to control the drain current because the band gap is too obviously reduced and the conductivity is too strong. The voltage values ​​of the top electrode and the bottom electrode are the same, and the gate voltage range of the p-type field effect transistor is 0-1.4V. For example, if the voltages of the top electrode and the bottom electrode are both 0.2V, the gate voltage is considered to be 0.2V.

[0039] according to Figure 8The transfer characteristic curve of the n-type field effect transistor is directly read to read the off-state current and on-state current, and other technical performances of the device are further calculated, such as power delay product, delay time, current switching ratio, subthreshold swing and gate-drain capacitance. The results are listed in Table 2. Table 2 is a comparison of the device performance of Sn4S8 n-type field effect transistors before and after doping with different types of point defects, different doping positions and different doping atoms in Examples 1 to 3 of the present invention and the high-performance and low-energy consumption technical indicators of the semiconductor technology route in 2028. Among them, the power delay product refers to the product of the time taken to achieve the transition from the on state to the off state and the average power consumption, which is an evaluation indicator used to reduce energy consumption. The delay time can reflect the upper limit of the switching rate of the field effect transistor. The lower the value, the higher the switching rate. The gate-drain capacitance can reflect the energy consumption during the switching process of the device. The lower the gate-drain capacitance, the smaller the switching energy consumption. The ratio of the on-state current to the off-state current is the current switching ratio. The higher the current switching ratio, the higher the performance of the device. Subthreshold swing is a performance indicator that measures the rate of conversion between the on and off states of a transistor. It represents the change in gate voltage required for the source-drain current to change tenfold. The smaller the value, the faster the switch is turned on and off. When the gate voltage is changed, an inversion layer is gradually formed between the gate and the channel, and an inversion layer charge appears. This effect can be regarded as a capacitor, and its capacitance is called the gate-drain capacitance. In order to reduce the switching time of the field effect transistor, the gate-drain capacitance must be reduced. By comparing the various device technical performances of Sn4S8 n-type field effect transistors doped with different types of point defects at different locations, only Sn4S 7Se All indicators are superior to those of the intrinsic Sn4S8 field-effect transistor, and meet the technical requirements of the 2028 International Semiconductor Technology Roadmap for high-performance and low-power field-effect transistors. Therefore, the incorporation of a Se(S) substitution defect into each Sn4S8 unit cell can be used to significantly improve the device performance of the SnS2 n-type field-effect transistor and reduce its energy consumption.

[0040] according to Fig. 9The off-state current and on-state current of the p-type field effect transistor are directly read from the transfer characteristic curve, and other technical performances of the device, such as power delay product, delay time, current switching ratio, subthreshold swing and gate-drain capacitance, are further calculated. The results are listed in Table 3, which is a comparison of the device performance of the Sn4S8 p-type field effect transistor before and after being doped with different types of point defects, different doping positions and different doping atoms in Examples 1 to 3 of the present invention and the technical indicators of high performance and low energy consumption of the semiconductor technology route in 2028. By comparing the various device technical performances of the Sn4S8 p-type field effect transistor doped with different types of point defects at different positions, only the various indicators of Sn5S8 meet the technical requirements of the international semiconductor technology route in 2028 for high performance and low power consumption field effect transistors. Therefore, the incorporation of a Sn interstitial defect in each Sn4S8 unit cell can be used to improve the device performance of the SnS2 p-type field effect transistor and reduce its energy consumption.

[0041] Table 2

[0042]

[0043] Table 3

[0044]

[0045] The above description is only a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements without departing from the principle of the present invention, and these improvements should also be regarded as within the protection scope of the present invention.

Claims

1. A field effect transistor device structure that utilizes point defect doping to reduce energy consumption, characterized in that: The structure comprises a source electrode (1), a drain electrode (2) and a channel region (3) between the source electrode (1) and the drain electrode (2); the channel region (3) comprises a channel material of an intermediate layer, a top gate (5) and a top electrode (7) are sequentially arranged on the upper surface of the channel material, a bottom gate (6) and a bottom electrode (8) are sequentially arranged on the lower surface of the channel material, and the channel material is Sn4S 7Se Channel material (9); Sn4S 7Se The channel material (9) is formed by replacing one sulfur atom with one selenium atom in every four SnS2 cells to form an n-type doped Sn4S 7Se Unit cell.

2. A field effect transistor device structure for reducing energy consumption by point defect doping according to claim 1, characterized in that: In an n-type field effect transistor device, the source, drain and channel regions (3) are all made of a single layer of Sn4S 7Se ; The electron concentration of the source and drain is 1.0×10 18 -5.0×10 22 e / cm 3 ; In the channel region (3), Sn4S 7Se The upper and lower surfaces of the channel material (9) are covered with dielectric layers made of BN to form a double gate structure; metal gate voltages are set on the dielectric layers on the upper and lower surfaces respectively, and the carrier type and concentration in the channel region of the field effect transistor device are regulated by the double gate voltages.

3. A field effect transistor device structure for reducing energy consumption by point defect doping according to claim 1, characterized in that: The doping of one selenium atom replacing one sulfur atom, i.e., utilizing Se(S) to replace defective doping, destroys the intrinsic lattice structure of SnS2, resulting in a reduction in the band gap of the channel material in the middle layer. At the same time, a large number of electrons are injected, and the vertical Schottky barrier of electrons is reduced to a greater extent than that of holes. Electrons jump from the bottom of the conduction band to the top of the valence band, ultimately achieving n-type doping.

4. A field effect transistor device structure for reducing energy consumption by point defect doping as claimed in claim 1, characterized in that: The channel material is a Sn5S8 channel material (10), and one tin atom is doped into every four SnS2 crystal cells of the Sn5S8 channel material (10) to form a p-type doped Sn5S8 crystal cell.

5. A field effect transistor device structure for reducing energy consumption by point defect doping according to claim 4, characterized in that: In the p-type field effect transistor device, the materials of the source, drain and channel regions are all Sn5S8 channel material (10); the hole concentration of the source and drain is 1.0×10 18 -5.0×10 22 e / cm 3 ; In the channel region (3), dielectric layers made of HfO2 are respectively covered on the upper and lower surfaces of the Sn5S8 channel material (10) to form a double gate structure; metal gate voltages are respectively set on the dielectric layers on the upper and lower surfaces, and the carrier type and concentration in the channel region of the field effect transistor device are regulated by the double gate voltages.

6. A field effect transistor device structure for reducing energy consumption by point defect doping according to claim 4, characterized in that: The introduction of tin atom interstitial defects destroys the intrinsic lattice structure of SnS2, resulting in a decrease in the band gap of the channel material in the middle layer. At the same time, a large number of holes are injected. The vertical Schottky barrier of holes is reduced to a greater extent than that of electrons. Holes jump from the top of the valence band to the bottom of the conduction band, ultimately achieving p-type doping.

7. A field effect transistor device structure for reducing energy consumption by point defect doping according to claim 3 or 5, characterized in that: The thickness of the top gate (5) and the bottom gate (6) on the upper and lower surfaces is 4-100nm, and the top electrode (7) and the bottom electrode (8) together constitute a gate electrode, each of which has a thickness of 4-100nm; in a p-type field effect transistor, the top gate is composed of HfO2, and in an n-type field effect transistor, the top gate is composed of BN; in a p-type field effect transistor, the bottom gate is composed of HfO2, and in an n-type field effect transistor, the bottom gate is composed of BN.

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