FIR filter multiplexing system

Abstract

The present invention discloses an FIR filter multiplexing system. The FIR filter multiplexing system comprises a filter type selection module and a filter function realization module. The filter function realization module comprises a read-write control submodule, a filter calculation submodule, a data buffer and a filter coefficient memory. The FIR filter multiplexing system is compatible with both half-band filters and non-half-band filters. The selection module is used to integrate two different types of filters, half-band filters and non-half-band filters, into one system. Therefore, relevant counting parameters can be selected to realize the extraction filtering function of the corresponding type of filter on input data, so that the FIR filter multiplexing system forms a filter system with strong universality.

Description

Technical Field

[0001] The present invention relates to the technical field of digital signal processing, and in particular to an FIR filter multiplexing system based on different types of 2x decimation. Background Art

[0002] Digital down-conversion is widely used in wireless communications. It downconverts RF / analog front-end signals, or converts them into analog-to-digital signals, to generate a lower-frequency baseband signal. This baseband signal is then filtered to produce a low-sampling-rate, high-quality signal for decoding and adaptive processing in audio and other fields. A key filter used in this process is called a digital filter. This device, consisting of a digital multiplier, adder, and delay unit, is essentially a digital signal processor (DSP), a discrete-time system that processes the digital code of a discrete input signal to alter its spectrum.

[0003] Among digital filters, the FIR (Finite Impulse Response) filter is a finite-length unit pulse impulse response digital filter and the most fundamental component in digital signal processing systems. It can maintain a strictly linear phase-frequency characteristic while maintaining arbitrary amplitude-frequency characteristics. Its unit sample response is also finite in length. Therefore, FIR filters are widely used in communications, image processing, pattern recognition, and other fields. The order of an FIR filter refers to the number of harmonics filtered. The sum of the FIR filter order and the value 1 equals the number of FIR filter coefficients, which is also equal to the number of filter taps. The FIR decimation filter, a type of FIR filter, is widely used by digital designers due to its linear phase characteristic. It is primarily used for frequency conversion. During frequency conversion, FIR decimation filters with different tap counts are selected based on the decimation rate. The order of an FIR decimation filter is proportional to the ratio of its input data sampling rate to its transition bandwidth.

[0004] In some design scenarios, if it is necessary to set the stopband suppression unchanged or achieve higher data resolution and selectivity during the extraction and filtering process, and a single FIR filter is selected to achieve this, then the order of the FIR filter needs to be set very high, resulting in a significant increase in the circuit production and design costs; the existing technology will also select multiple FIR filters of the same type to cascade to achieve the same purpose, which will greatly increase the overhead of hardware resources such as multipliers and adders required, and the amount of calculation generated during the extraction and filtering process is also large, making it difficult to meet the requirements of data access speed. Summary of the Invention

[0005] In response to the above technical deficiencies, the present invention is based on the application performance requirements of FIR filters and discloses an FIR filter multiplexing system that is compatible with both half-band filters and non-half-band filters. A selection module is used to integrate two different types of filters, half-band filters and non-half-band filters, into one system, so that relevant counting parameters can be selected to implement the extraction filtering function of the corresponding type of filter on the input data, making the FIR filter multiplexing system a filter system with strong versatility. The specific technical solution is as follows:

[0006] An FIR filter multiplexing system includes a filter type selection module and a filter function implementation module; the filter function implementation module includes a read-write control submodule, a filter calculation submodule, a data buffer and a filter coefficient memory; the filter type selection module is pre-configured with the number of taps of the FIR filter to be multiplexed and its decimation rate; wherein the FIR filter to be multiplexed includes a half-band filter and a non-half-band filter, and the non-half-band filter is a type of FIR filter other than the half-band filter; the filter type selection module is used to generate the associated read addresses in the currently multiplexed FIR filter and transmit these associated read addresses to the read-write control submodule; the read-write control submodule is used to control the writing of the to-be-filtered data input into the FIR filter multiplexing system into the data buffer; the read-write control submodule is used to use the associated Read address, read out the data to be filtered from the data buffer in sequence to the filtering calculation submodule; the filtering calculation submodule is used to control the filtering calculation of the data to be filtered output by the data buffer and the filter coefficients output by the filter coefficient memory, wherein the filtering calculation is adapted to the FIR filter currently reused by the FIR filter multiplexing system, so that the filter function implementation module is reused as the currently reused FIR filter; the filter coefficient memory is also used to store the filter coefficients required by the currently reused FIR filter, wherein the filter coefficients required for each type of FIR filter have a matching starting storage address in the filter coefficient memory; the filter coefficient memory is used to output the required filter coefficients to the filtering calculation submodule in sequence after the read-write control submodule starts to read the data to be filtered from the data buffer, in accordance with the order in which the read-write control submodule reads the data to be filtered from the data buffer, starting from the starting storage address corresponding to the currently reused FIR filter.

[0007] Furthermore, the filter type selection module includes a pre-address selector and an address enable signal selector; the pre-address selector is used to select the pre-address read address corresponding to the currently multiplexed FIR filter and transmit it to the filter function implementation module after receiving the filter type selection signal, so that when the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the read-write control submodule reads the data to be filtered from the pre-address read address of the data buffer according to the read timing corresponding to the currently multiplexed FIR filter; the address enable signal selector is used to select the folding read enable signal corresponding to the currently multiplexed FIR filter and transmit it to the filter function implementation module after receiving the filter type selection signal; wherein, when the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the folding read enable signal is a high level; when the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the folding read enable signal is a low level.

[0008] Furthermore, the filter type selection module also includes a first address selector and a second address selector; the first address selector is used to select the first folding read address corresponding to the currently multiplexed FIR filter and transmit it to the filter function implementation module after receiving the filter type selection signal, so that after the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the read-write control submodule reads the data to be filtered in the first folding read address from the data buffer according to the read timing corresponding to the currently multiplexed FIR filter; the second address selector is used to select the second folding read address corresponding to the currently multiplexed FIR filter after receiving the filter type selection signal. The read address is transmitted to the filter function implementation module so that after the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the read-write control submodule reads the data to be filtered in the second folded read address from the data buffer according to the read timing corresponding to the currently multiplexed FIR filter; wherein, the address offset between the starting address sequence number of the second folded read address and the starting address sequence number of the first folded read address is equal to the sampling rate of the currently multiplexed FIR filter; the number of taps of the currently multiplexed FIR filter is configured by a special register; wherein, the associated read addresses include the pre-read address, the second folded read address and the first folded read address.

[0009] Furthermore, the FIR filter multiplexing system is also provided with a system read-write clock source for counting and generating system clock cycles; wherein, the time consumed for writing one data to be filtered is configured as one system clock cycle, and the time consumed for reading one data to be filtered is configured as one system clock cycle; wherein, the number of data to be filtered written into the data buffer is equal to the number of data to be filtered sampled from the outside by the FIR filter multiplexing system.

[0010] Furthermore, the filter function implementation module also includes a filter counter; the filter counter is used to add one count each time two data to be filtered are written to the data buffer from the outside, and then trigger the filter calculation submodule to use the data to be filtered read from the data buffer to perform filtering calculations suitable for the currently multiplexed FIR filter, and then when the filter calculation submodule calculates the corresponding filtering result, it is determined that the FIR filter multiplexing system has passed a filtering cycle, wherein a filtering cycle is greater than two system clock cycles; after each filtering cycle, the filter calculation submodule outputs a filtering result; wherein the decimation rate of the currently multiplexed FIR filter is 2 times; wherein, the bit width of each data to be filtered written into the data buffer is configured by the filter type selection module, and the bit width occupied by each data to be filtered is less than or equal to the maximum bit width allowed to be read and written by the data buffer.

[0011] Further, when the number of data to be filtered written into the data buffer is represented by the change value of the count value of the filter counter, the transpose enable count threshold of the currently multiplexed FIR filter is represented by half of the sum of the number of taps of the currently multiplexed FIR filter and the value 1; wherein, the number of taps of the currently multiplexed FIR filter is an odd number.

[0012] Furthermore, the method of sequentially reading the data to be filtered from the data buffer and feeding it to the filtering calculation submodule using the associated read address provided by the filter type selection module according to the size relationship between the number of data to be filtered written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter includes: when the read-write control submodule determines that the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the read-write control submodule reads the data to be filtered in the pre-read address from the data buffer in each filtering cycle according to the read timing corresponding to the currently multiplexed FIR filter, and transmits it to the filtering calculation submodule; wherein the transposition enable count threshold of the currently multiplexed FIR filter is equal to the transposition enable count threshold of the currently multiplexed FIR filter. the number of taps of the FIR filter; wherein, the pre-read address is obtained by counting from an initial pre-address serial number in each filtering cycle; an initial pre-address serial number in each filtering cycle is the first pre-read address serial number participating in the reading operation in the filtering cycle, so that the data to be filtered in the pre-read address corresponding to the initial pre-address serial number is transmitted to the filtering calculation submodule according to the corresponding reading timing; wherein, when the filter type selection signal is a first logic level, the currently multiplexed FIR filter is the non-half-band filter, so that the FIR filter multiplexing system is multiplexed into the non-half-band filter; when the filter type selection signal is a second logic level, the currently multiplexed FIR filter is the half-band filter, so that the FIR filter multiplexing system is multiplexed into the half-band filter.

[0013] Furthermore, when the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the read-write control submodule sets the difference between twice the change value of the count value of the filter counter in each filtering cycle relative to its initial count value and the value 2 as the initial prefix address sequence number in the corresponding filtering cycle; wherein the address offset between the initial prefix addresses obtained in two adjacent filtering cycles is equal to the decimation rate of the currently multiplexed FIR filter; and the initial count value of the filter counter is the count value set before counting begins.

[0014] Furthermore, if the currently multiplexed FIR filter is the non-half-band filter and the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the pre-address counter is used to start from the initial pre-address sequence number corresponding to the current filtering cycle and perform a self-decrement operation according to the system clock cycle, and the pre-address read address after each self-decrement operation is handed over to the pre-address selector for transmission to the filter function implementation module to trigger the read-write control submodule to read the data to be filtered in the pre-address after each self-decrement operation from the data buffer, and then transmit it to the filtering calculation submodule in sequence; wherein the filter type selection module includes a pre-address counter, which is used to operate when the filter type selection signal is a first logic level; wherein, each time the pre-address counter decrements, the corresponding count value change is a value of 1, and the count value generated after each self-decrement operation is configured as the pre-address read address sequence number; the initial count value set by the pre-address counter is the initial pre-address sequence number.

[0015] Furthermore, if the currently multiplexed FIR filter is the non-half-band filter, then in the state where the number of data to be filtered written into the data buffer is less than or equal to the transpose enable count threshold of the currently multiplexed FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address that matches the currently multiplexed FIR filter, perform a self-addition operation on the starting storage address according to the system clock cycle, and then read the corresponding stored filter coefficients to the filtering calculation submodule in sequence according to the storage address obtained by self-addition, until the address offset of the storage address obtained by self-addition relative to the starting storage address is equal to half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1, and then record the latest storage address as the intermediate calculation storage address, and then perform a self-decrement operation on the intermediate calculation storage address, and then read the corresponding stored filter coefficients according to the storage address obtained by self-decrement. The filter coefficients are read out to the filtering calculation submodule in sequence until the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the difference between the number of taps of the currently reused FIR filter and the value 1, and the process is repeated until the number of filter coefficients read from the filter coefficient memory in the current filtering cycle meets the number of data to be filtered participating in the filtering calculation in the current filtering cycle; wherein, in the process of performing a self-increment operation on the starting storage address, the address sequence number corresponding to the storage address increases by a value of 1 each time the self-increment operation is performed; in the process of performing a self-decrement operation on the intermediate calculation storage address, the address sequence number corresponding to the storage address decreases by a value of 1 each time the self-decrement operation is performed; wherein, the address sequence number corresponding to the storage address is used to indicate the address sorting of the storage address in the filter coefficient memory; and the number of taps of the currently reused FIR filter is an odd number.

[0016] Furthermore, the filtering calculation submodule is used to control the multiplication of the data to be filtered output by the data buffer and the filter coefficients of the same read order output by the filter coefficient memory when the number of data to be filtered written into the data buffer is less than or equal to the transpose enable count threshold of the currently multiplexed FIR filter, and input the results into the adder for accumulation processing to obtain the processed filtering results within each filtering cycle; wherein, the multiplication operation within each filtering cycle is implemented by a multiplier in time-sharing multiplexing; wherein, the filtering calculation submodule includes an adder and a multiplier.

[0017] Furthermore, the read-write control submodule also includes a reference address counter; the reference address counter is used to perform a self-increment operation of the count value whenever two of the to-be-filtered data are written externally to the data buffer to trigger the filtering calculation submodule to start a filtering calculation, and configure the count value obtained by the self-increment operation as the folded reference address sequence number, and transmit the folded reference address sequence number obtained after the self-increment operation to the filter type selection module, and then update the folded reference address sequence number to the first folded read address sequence number, and update the sum of the folded reference address sequence number and the value 1 to the second folded read address sequence number; wherein, the change value of the count value generated by the reference address counter in a self-increment operation is the value 2; the transpose enable count threshold of the currently multiplexed FIR filter is equal to the number of taps of the currently multiplexed FIR filter; wherein, the folded reference address sequence number represents the order of the folded reference address in the data buffer; the second folded read address sequence number is used to represent the address order of the second folded read address in the data buffer; the first folded read address sequence number is used to represent the address order of the first folded read address in the data buffer.

[0018] Furthermore, when the count value of the reference address counter is the difference between the number of taps of the currently multiplexed FIR filter and the value 2, the read-write control submodule updates the filter starting address sequence number to the count value currently obtained by the reference address counter in the next system clock cycle, and updates the filter starting address sequence number to the folded reference address sequence number, and then transmits the updated folded reference address sequence number to the filter type selection module; when the count value of the reference address counter is the difference between the number of taps of the currently multiplexed FIR filter and the value 1, the read-write control submodule updates the sum of the filter starting address sequence number and the value 1 to the count value currently obtained by the reference address counter in the next system clock cycle, and updates the sum of the filter starting address sequence number and the value 1 to the folded reference address sequence number; wherein, the filter starting address sequence number is an address sequence number pre-configured in the data buffer, and is the address sequence number with the smallest ranking among the address sequences participating in the read operation in each filtering cycle.

[0019] Furthermore, the method of sequentially reading the data to be filtered from the data buffer to the filtering calculation submodule using the associated read address provided by the filter type selection module based on the size relationship between the number of data to be filtered written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter includes: when the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is used to perform a self-decrement operation on the first folded read address according to the read timing corresponding to the currently multiplexed FIR filter in each filtering cycle, and then transmit the first folded read address after each self-decrement operation to the read-write control submodule through the first address selector to trigger the read-write control submodule to read each folded read address from the data buffer. The data to be filtered in the first folded read address after the self-decrement operation, until the number of self-decrement operations is the first preset folded sampling number; when the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is also used to perform a self-addition operation on the second folded read address according to the read timing corresponding to the currently multiplexed FIR filter within each filtering cycle, and then transmit the second folded read address after each self-addition operation to the read-write control submodule through the second address selector to trigger the read-write control submodule to read the data to be filtered in the second folded read address after each self-addition operation from the data buffer, until the number of self-addition operations is the second preset folded sampling number; wherein, the currently multiplexed FIR filter is the non-half-band filter.

[0020] Furthermore, the number of taps of the currently multiplexed FIR filter is an odd number; the transpose enable count threshold of the FIR filter is equal to the number of taps of the FIR filter; when the second preset folding sampling number is greater than the first preset folding sampling number, the difference between half of the difference between the number of taps of the currently multiplexed FIR filter and the numerical value 1 and the numerical value 1 is equal to the first preset folding sampling number, and half of the difference between the number of taps of the currently multiplexed FIR filter and the numerical value 1 is equal to the second preset folding sampling number, so that the first folding read address stops changing in advance of the second folding read address; or, when the second preset folding sampling number is less than the first preset folding sampling number, the difference between half of the difference between the number of taps of the currently multiplexed FIR filter and the numerical value 1 and the numerical value 1 is equal to the second preset folding sampling number, and half of the difference between the number of taps of the currently multiplexed FIR filter and the numerical value 1 is equal to the first preset folding sampling number, so that the second folding read address stops changing in advance of the first folding read address.

[0021] Furthermore, the filter type selection module includes a first folding address counter and a second folding address counter, which are used to operate when the filter type selection signal is a first logic level; before the filter type selection module determines to configure the folding reference address sequence number as the starting address sequence number of the first folding read address, if the filter type selection module determines that the folding reference address sequence number is equal to the filtering starting address sequence number, the filtering target address sequence number is updated to the folding reference address sequence number, and then the updated folding reference address sequence number is updated to the starting address sequence number of the first folding read address, and then the first folding address counter is used to perform a self-decrement operation on the first folding read address sequence number starting from the starting address sequence number of the first folding read address; wherein the first folding read address sequence number represents the order of the first folding read address in the data buffer; the change value of the count value generated by the self-decrement of the first folding address counter is a value of 1, so that the change value generated by the self-decrement operation on the first folding read address sequence number is a value of 1; in the filter type selection module Before determining to configure the folding reference address sequence number as the starting address sequence number of the second folding read address, if the filter type selection module determines that the folding reference address sequence number is equal to the filtering target address sequence number, the filtering starting address sequence number is updated to the folding reference address sequence number, and then the sum of the folding reference address sequence number and the value 1 is updated as the starting address sequence number of the second folding read address; then, the second folding address counter is used to perform a self-increment operation on the second folding read address sequence number starting from the starting address sequence number of the second folding read address, wherein the change value of the count value generated by the self-increment of the second folding address counter is the value 1, so that the change value generated by the second folding read address sequence number in one self-increment operation is the value 1; wherein the filtering target address sequence number is an address sequence number pre-configured in the data buffer, as the address sequence number with the largest ranking among the addresses participating in the read operation in each filtering cycle; the difference between the filtering target address sequence number and the filtering starting address sequence number is equal to the difference between the number of taps of the currently multiplexed FIR filter and the value 1.

[0022] Furthermore, the process of the first folding address counter performing a self-decrement operation on the first folding read address sequence number includes: configuring the starting address sequence number of the first folding read address as the first folding read address sequence number, and whenever the first folding read address sequence number is decremented to the filtering starting address sequence number, updating the filtering target address sequence number to the first folding read address sequence number in the next system clock cycle, so that the first folding read address realizes address loop traversal within the address range limited by the number of taps of the currently multiplexed FIR filter; then the first folding address counter continues to perform a self-decrement operation on the first folding read address sequence number The process of the second folding address counter performing a self-increment operation on the second folding read address number includes: configuring the starting address number of the second folding read address as the second folding read address number, and whenever the second folding read address number is self-added to the filtering target address number, updating the filtering starting address number to the second folding read address number in the next system clock cycle, so that the second folding read address realizes address loop traversal within the address range limited by the number of taps of the currently multiplexed FIR filter; then the second folding address counter continues to perform a self-increment operation on the second folding read address number.

[0023] Furthermore, under the read timing corresponding to the currently multiplexed FIR filter, a self-decrement operation is performed on the first folded read address every two system clock cycles to obtain a new first folded read address, and these two system clock cycles are recorded as the counting cycle of the first folded read address; under the read timing corresponding to the currently multiplexed FIR filter, a self-increment operation is performed on the second folded read address every two system clock cycles to obtain a new second folded read address, and these two system clock cycles are recorded as the counting cycle of the second folded read address; when the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, under the control of the read-write control submodule , within the counting cycle of the first folding read address or the counting cycle of the second folding read address, read the data to be filtered in the first folding read address to the filtering calculation submodule, and read the data to be filtered in the second folding read address to the filtering calculation submodule, and repeat the reading until the number of data to be filtered read within one filtering cycle is equal to the number of taps of the currently multiplexed FIR filter; wherein, within the counting cycle of each first folding read address or the counting cycle of each second folding read address, the address offset of the first folding read address number corresponding to the read first folding read address relative to the filtering starting address number is equal to the address offset of the filtering target address number relative to the second folding read address number corresponding to the read second folding read address.

[0024] Furthermore, when the amount of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter coefficient memory is used to perform a self-increment operation on the starting storage address once every two system clock cycles, starting from the starting storage address matching the currently multiplexed FIR filter in each filtering cycle, and then read the corresponding stored filter coefficients to the filter calculation submodule in sequence according to the storage address obtained by self-increment, until the address offset of the storage address obtained by self-increment relative to the starting storage address is equal to half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1, and then the latest storage address is recorded as the intermediate calculation storage address; wherein, in the process of performing the self-increment operation on the starting storage address, the address sequence number corresponding to the storage address increases by 1 each time the self-increment is performed; the starting storage address is selected and determined by the filter type selection module to match the currently multiplexed FIR filter; wherein the address sequence number corresponding to the storage address is used to indicate the address order of the storage address in the filter coefficient memory; the number of taps of the currently multiplexed FIR filter is an odd number.

[0025] Furthermore, if the currently multiplexed FIR filter is the half-band filter and the amount of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the pre-address counter is used to start from the initial pre-address sequence number corresponding to the current filtering cycle and perform a self-decrement operation according to the system clock cycle to obtain a new pre-address read address, and the pre-address read address after each self-decrement operation is transmitted to the filter function implementation module by the pre-address selector to trigger the read-write control submodule to read the data to be filtered in the pre-address address after each self-decrement operation from the data buffer, and then transmit it to the filter calculation submodule in sequence until the latest pre-address read address sequence number is a value of 1 or a value of 0; the filter type selection module includes a pre-address counter, which is used to operate when the filter type selection signal is at a second logic level; wherein, each time the pre-address counter decrements, the corresponding count value change is a value of 2, and the count value generated after each self-decrement operation is configured as the pre-address sequence number; the initial count value set by the pre-address counter is the initial pre-address sequence number.

[0026] Furthermore, within a filtering cycle, when the difference between half of the difference between the number of taps of the half-band filter and the numerical value 1 and the numerical value 1 is equal to twice the number of times the pre-address counter performs the aforementioned decrement operation, the pre-address counter updates the difference between the currently obtained pre-read address sequence number and the numerical value 1 to the pre-read address sequence number, and allows the read-write control submodule to read the data to be filtered in the pre-read address sequence number, and marks the pre-read address sequence number as the intermediate pre-read address sequence number; the pre-address counter is used to, after obtaining the intermediate pre-read address sequence number, continue to perform the decrement operation starting from the difference between the intermediate pre-read address sequence number and the numerical value 1 to obtain a new pre-read address; wherein, the difference between the intermediate pre-read address sequence number and the numerical value 1 is allowed to be updated as the pre-read address sequence number.

[0027] Furthermore, if the currently multiplexed FIR filter is the half-band filter, then in the state where the number of data to be filtered written into the data buffer is less than or equal to the transpose enable count threshold of the currently multiplexed FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address that matches the currently multiplexed FIR filter, perform a self-addition operation on the starting storage address according to the system clock cycle, and then read out the corresponding stored filter coefficients to the filtering calculation submodule in sequence according to the storage address obtained by self-addition, until the address offset of the storage address obtained by self-addition relative to the starting storage address is equal to half of the sum of the number of taps of the currently multiplexed FIR filter and the value 1, and then record the latest storage address as the intermediate calculation storage address, and then perform a self-decrement operation on the intermediate calculation storage address, and then read the corresponding stored filter coefficients to the filtering calculation submodule according to the storage address obtained by self-decrement. The filter coefficients to be stored are read out to the filtering calculation submodule in sequence until the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the sum of the number of taps of the currently multiplexed FIR filter and the value 1, and the process is repeated until the number of filter coefficients output from the filter coefficient memory in the current filtering cycle is equal to the number of data to be filtered read in the current filtering cycle; wherein, in the process of performing a self-increment operation on the starting storage address, the address sequence number corresponding to the storage address increases by a value of 2 each time the self-increment operation is performed; in the process of performing a self-decrement operation on the starting storage address, the address sequence number corresponding to the storage address decreases by a value of 2 each time the self-decrement operation is performed; wherein, the address sequence number corresponding to the storage address represents the address order of the storage address in the filter coefficient memory; the number of taps of the currently multiplexed FIR filter is an odd number.

[0028] Furthermore, the filtering calculation submodule is used to control the multiplication of the data to be filtered output by the data buffer and the filter coefficients of the same read order output by the filter coefficient memory when the number of data to be filtered written into the data buffer is less than or equal to the transpose enable count threshold of the currently multiplexed FIR filter, and input the result into the adder for accumulation processing to obtain the processed filtering result within each filtering cycle; wherein, the number of taps of the currently multiplexed FIR filter is an odd number, and the multiplication operation within each filtering cycle is implemented by time-sharing multiplexing of a multiplier; wherein, the filtering calculation submodule includes an adder and a multiplier.

[0029] Furthermore, the method of sequentially reading the data to be filtered from the data buffer to the filtering calculation submodule using the associated read address provided by the filter type selection module based on the relationship between the amount of data to be filtered written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter includes: when the amount of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is used to perform a self-decrement operation on the first folded read address according to the read timing corresponding to the currently multiplexed FIR filter within each filtering cycle, and then transmit the first folded read address after each self-decrement operation to the read-write control submodule through the first address selector to trigger the read-write control submodule to read the data from the data buffer according to the first folded read address after each self-decrement operation. The corresponding data to be filtered is read out from the data buffer; when the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is also used to perform a self-addition operation on the second folded read address according to the read timing corresponding to the currently multiplexed FIR filter in each filtering cycle, and then transmit the second folded read address after each self-addition operation to the read-write control submodule through the second address selector to trigger the read-write control submodule to read the corresponding data to be filtered from the data buffer according to the second folded read address after each self-addition operation; wherein, the currently multiplexed FIR filter is the half-band filter; wherein, the address offset of the second folded address number in a self-addition operation is a value of 2; the address offset of the first folded address number in a self-decrement operation is a value of 2.

[0030] Further, within a filtering cycle, when it is detected that the difference between the number of taps of the currently multiplexed FIR filter and twice the number of self-decrement operations performed on the first folded read address is less than twice the number of self-decrement operations performed on the first folded read address, the aforementioned self-decrement operation on the first folded read address is stopped, and the sum of the currently obtained first folded read address sequence number and the numerical value 1 is updated to the first folded read address sequence number, and the first folded read address sequence number is kept unchanged; or, within a filtering cycle, when it is detected that the difference between the number of taps of the currently multiplexed FIR filter and twice the number of self-addition operations is less than twice the number of self-addition operations performed on the second folded read address, the self-addition operation on the second folded read address is stopped, and the difference between the currently obtained second folded read address sequence number and the numerical value 1 is updated to the second folded read address sequence number, and the second folded read address sequence number is kept unchanged.

[0031] Furthermore, the filter type selection module includes a first folding address counter, which is used to operate when the filter type selection signal is a second logic level; after the folding reference address number is updated to the starting address number of the first folding read address, the first folding address counter is used to perform a self-decrement operation on the first folding read address number starting from the starting address number of the first folding read address; if the filter type selection module determines that the first folding read address number is reduced to the filtering starting address number, the difference between the filtering target address number and the value 1 is updated to the first folding read address number; if the filter type selection module determines that the sum of the filtering starting address number and the value 1 is equal to the first folding read address number, the filtering target address number is updated to the The first folding read address sequence number; wherein, the first folding read address sequence number represents the order of the first folding read address in the data buffer; the change value of the count value generated by the first folding address counter being decremented once is a value of 2, so that the change value generated by the first folding read address sequence number in a self-increment operation is a value of 2; wherein, the filtering target address sequence number is an address sequence number pre-configured in the data buffer, and is the address sequence number with the largest order among the address sequences participating in the read operation in each filtering cycle; the difference between the filtering target address sequence number and the filtering starting address sequence number is equal to the difference between the number of taps of the currently multiplexed FIR filter and 1; wherein, the first folding read address sequence number is used to represent the address order of the first folding read address in the data buffer.

[0032] Furthermore, the filter type selection module includes a second folding address counter, which is used to work when the filter type selection signal is a second logic level; before the filter type selection module determines to configure the folding reference address number as the starting address number of the second folding read address, if the filter type selection module determines that the folding reference address number is equal to the filtering target address number, the filtering starting address number is updated to the folding reference address number, and then the sum of the folding reference address number and the value 1 is updated to the starting address number of the second folding read address number; then, the second folding address counter is used to perform a self-increment operation on the second folding read address number starting from the starting address number of the second folding read address; if the filter type selection module determines that the folding reference address number is equal to the filtering target address number, the filtering starting address number is updated to the folding reference address number, and then the sum of the folding reference address number and the value 1 is updated to the starting address number of the second folding read address number; then, the second folding address counter is used to perform a self-increment operation on the second folding read address number starting from the starting address number of the second folding read address; If the filter type selection module determines that the second folding read address number after the self-increment operation is equal to the filtering target address number, the sum of the filtering starting address number and the value 1 is updated to the second folding read address number; if the filter type selection module determines that the second folding read address number after the self-increment operation is equal to the difference between the filtering target address number and the value 1, the filtering starting address number is updated to the second folding read address number; wherein, the change value of the count value generated by the self-increment of the second folding address counter is the value 2, so that the change value of the second folding read address number generated in one self-increment operation is the value 2; wherein, the second folding read address number is used to indicate the address sorting of the second folding read address in the data buffer.

[0033] Furthermore, under the reading timing corresponding to the currently multiplexed FIR filter, a self-decrement operation is performed on the first folded read address every two system clock cycles to obtain a new first folded read address, and these two system clock cycles are recorded as the counting cycle of the first folded read address; under the reading timing corresponding to the currently multiplexed FIR filter, a self-increment operation is performed on the second folded read address every two system clock cycles to obtain a new second folded read address, and these two system clock cycles are recorded as the counting cycle of the second folded read address; in the state where the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, under the control of the read-write control submodule, the number of data to be filtered in the first folded read address is read within the counting cycle of the first folded read address or the counting cycle of the second folded read address. The data is sent to the filtering calculation submodule, and the data to be filtered in the second folding read address is read to the filtering calculation submodule, and the reading is repeated until the number of data to be filtered read in one filtering cycle is equal to half of the sum of the number of taps of the currently multiplexed FIR filter and the value 1, and then one data to be filtered is read from the intermediate calculation cache address in the next system clock cycle; wherein, the intermediate calculation cache address is the address position between the most recently obtained second folding read address and the most recently obtained first folding read address; wherein, in each counting cycle of the first folding read address or each counting cycle of the second folding read address, the address offset of the first folding read address number corresponding to the read first folding read address relative to the filtering starting address number is equal to the address offset of the filtering target address number relative to the second folding read address number corresponding to the read second folding read address.

[0034] Furthermore, when the amount of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter coefficient memory is used to perform a self-add operation on the starting storage address once every two system clock cycles, starting from the starting storage address matching the currently multiplexed FIR filter in each filtering cycle, and then read the corresponding stored filter coefficients to the filtering calculation submodule in sequence according to the storage address obtained by self-addition, until the address offset of the storage address obtained by self-addition relative to the starting storage address is equal to half of the sum of the number of taps of the currently multiplexed FIR filter and the value 1, and the latest storage address obtained is recorded as the intermediate calculation storage address; wherein, in the process of performing the self-add operation on the starting storage address, each time the self-add operation is performed, the address sequence number corresponding to the storage address increases by a value of 2; the starting storage address is selected and determined by the filter type selection module to match the currently multiplexed FIR filter; wherein, the address sequence number corresponding to the storage address is used to indicate the address sorting of the storage address in the filter coefficient memory; the number of taps of the currently multiplexed FIR filter is an odd number.

[0035] Furthermore, the filtering calculation submodule is used to, when the amount of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, first control the addition of the data to be filtered in the first folded read address output by the data buffer and the data to be filtered in the second folded read address output by the data buffer within each counting cycle of the first folded read address or each counting cycle of the second folded read address; then multiply the result of the addition with the filter coefficient of the same read order output by the filter coefficient memory; and then input the multiplication result into the adder for accumulation processing, and repeat this in each filtering cycle until When the filter coefficient memory outputs the filter coefficient in the intermediate calculation storage address, the filter coefficient in the intermediate calculation storage address is multiplied with the data to be filtered in the first folded read address output by the data buffer under the same reading order, and the multiplication result is input into the adder for accumulation processing to obtain the processed filtering result within the corresponding filtering cycle; wherein, within each filtering cycle, the multiplication operation is implemented by a multiplier in time-sharing multiplexing; wherein, the filtering calculation submodule includes an adder and a multiplier; wherein, the transpose enable count threshold of the currently multiplexed FIR filter is equal to the number of taps of the currently multiplexed FIR filter.

[0036] Furthermore, the read-write control submodule is used to control the writing of the external input data to be filtered into the data buffer according to the system clock cycle, and read out the data to be filtered written into the data buffer in sequence according to the pre-address read address selected and output by the pre-address selector, the first folded read address selected and output by the first address selector, and the second folded read address selected and output by the second address selector; wherein, if one data to be filtered is written in the current system clock cycle, then one data to be filtered is read in the next system clock cycle.

[0037] Furthermore, an incremental counter is set inside the read-write control submodule, and the read-write control submodule is used to start from the cache head address of the data buffer, and each time a data to be filtered is written, the incremental counter is controlled to add an offset to the current cache address to obtain the cache address of the next written data to be filtered, until the address offset of the currently obtained cache address relative to the cache head address is equal to the number of taps of the currently multiplexed FIR filter, the cache head address is updated to the currently obtained cache address, so that the subsequently written data to be filtered overwrites the data to be filtered originally stored at the cache head address, and determines that a round of continuous cache address traversal of the data buffer is completed; wherein, the continuous cache address is composed of address units whose number is the number of taps of the currently multiplexed FIR filter.

[0038] Furthermore, the read-write control submodule is also used to, after completing a round of continuous cache address traversal, if the new data to be filtered is continued to be written to the continuous cache address according to the system clock cycle control, then the incremental counter is set to the incremental initial value, and starting from the cache first address, each time a data to be filtered is written, the currently written data to be filtered overwrites the data to be filtered originally stored in the cache address, and controls the incremental counter to add an offset to the current cache address to obtain the cache address of the next written data to be filtered, until the address offset of the currently obtained cache address relative to the cache first address is equal to the difference between the number of taps of the currently multiplexed FIR filter and the value 1, the cache first address is updated to the currently obtained cache address, and the count value of the incremental counter is adjusted to the incremental initial value; wherein, the incremental initial value set by the incremental counter represents the address order of the cache first address in the data buffer; each count value generated by the incremental counter represents the address order of the cache address written in the corresponding system clock cycle in the data buffer.

[0039] Compared with the prior art, the present invention has the following advantages over traditional digital filter implementation methods: the present invention uses a selector and a counter to form a filter function implementation module, provides a filter type selection module for a multiplexed type of FIR filter read and write address signal, enables the filter function implementation module to perform filtering calculations corresponding to the currently multiplexed type of FIR filter on external input data based on the corresponding read and write address signal, and establishes an FIR filter system with selectable type and universal read control parameter type.

[0040] Specifically, in terms of the functions of extraction and filtering, the present invention is compatible with half-band filters and non-half-band filters. The arithmetic unit part, read-write controller part and memory part common to half-band filters and non-half-band filters are made into a filter function implementation module. At the same time, the timing logic of different functions required to be selected between half-band filters and non-half-band filters is made into a filter type selection module. However, it is not necessary to connect half-band filters and non-half-band filters in series into a single chain filter group (i.e., multiple FIR filters of different types are connected into a cascade structure). Instead, a reusable filter function implementation system is formed, allowing half-band filters and non-half-band filters to implement corresponding filtering functions by sharing a filter function implementation module. There is no need to completely separate and design two sets of filters. The selection signal is now used to determine the start and end time points of extraction and calculation under the corresponding type of filter, meeting the rate requirements of reading and calculating data of different filters. The characteristic index application is more flexible and can adapt to multiple signals with different filtering requirements. In the case of different filtering requirements, there is no need to change the structure of the entire filter system. Only by selecting the control signals for extraction and filtering such as the read enable control signal and the count control signal under the corresponding type of FIR filter, filters with different functions and performances can be reused. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is a module connection block diagram of an FIR filter multiplexing system disclosed in one embodiment of the present invention.

[0042] Figure 2 It is a schematic diagram of the circuit structure principle inside the filter type selection module disclosed in another embodiment of the present invention.

[0043] Figure 3 This is a schematic diagram of the dynamic changes in data flow after the FIR filter multiplexing system is multiplexed into a 5-tap FIR filter.

[0044] Figure 4 This is a schematic diagram of the dynamic changes in data flow after the FIR filter multiplexing system is multiplexed into a 7-tap half-band filter. DETAILED DESCRIPTION

[0045] The following describes the technical solutions in the embodiments of the present invention in detail with reference to the accompanying drawings. The present invention provides drawings to further illustrate the various embodiments. These drawings form part of the disclosure and are primarily used to illustrate the embodiments and, in conjunction with the relevant descriptions in the specification, to explain the operating principles of the embodiments.

[0046] Unless otherwise defined, the technical terms or scientific terms involved in the present invention should be understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "the" and the like involved in this application do not indicate a quantitative limitation and may represent the singular or the plural. The terms "include", "comprise", "have" and any of their variations involved in this application are intended to cover non-exclusive inclusions, such as: a process, method, system product or device that includes a series of steps or modules is not limited to the listed steps or units, but may also include steps or modules that are not listed, or may also include other steps or units inherent to these processes, methods, products or devices. The terms "first", "second", "third" and the like involved in this application are merely used to distinguish similar correspondences and do not represent a specific ordering of objects.

[0047] One embodiment of the present invention discloses an FIR filter multiplexing system that is compatible with two different types of FIR filters. The system can trigger a corresponding selection signal according to the filtering algorithm requirements of the actual application field (audio or video), select the matching type FIR filter to work in the FIR filter multiplexing system, and then perform filtering operations on the data input into the FIR filter multiplexing system. In this embodiment, the FIR filter multiplexing system includes a filter type selection module and a filter function implementation module; wherein the filter type selection module is a generator of the filter type selection signal for the FIR filter that needs to be multiplexed, forming a read address generation logic circuit for selecting the corresponding logic circuit of the currently multiplexed FIR filter and maintaining the relevant read address signal in the direction of the read address change of the currently multiplexed FIR filter. As for the logic circuit of the corresponding type of FIR filter that is not selected, it is prohibited from working to reduce power consumption. wherein the relevant enable signal and read address control signal involved in the selection operation are all configured by the filter type selection module; wherein the filter type selection signal is represented as Figure 1 sel, Figure 1 The sel can also be expressed as the selection control port of the filter type selection module; the filter function realization module is a logic circuit of the shared memory and calculation unit of each type of FIR filter that can be selected by the FIR filter multiplexing system, such as Figure 1As shown, the filter function implementation module includes a read-write control submodule, a filter calculation submodule, a data buffer and a filter coefficient memory.

[0048] The filter type selection module is pre-configured with the number of taps and the decimation rate of the FIR filter that needs to be reused. Specifically, a special parameter configuration register is set inside the filter type selection module for storing relevant performance parameters of various types of FIR filters, including but not limited to the bit width of input and output data, the bit width of the filter coefficient, the number of taps and order of the FIR filter, the number of filter coefficients, the length of the filter, the decimation rate of the filter, the filtering period required for one filtering operation, the effective time point of the chip select signal, the high time point of the enable signal, the starting address sequence number or the starting reading time point of the read address of the relevant memory in the filter function implementation module, that is, the start and end time points of the extraction and calculation of the FIR filter that may be reused, and the address range of the extraction and calculation are predetermined; these relevant performance parameters are different in different types of filters, but the number of filter coefficients is equal to the number of taps of the FIR filter, and the number of taps of the FIR filter is equal to the sum of the order of the FIR filter and the value 1.

[0049] In this embodiment, the FIR filters that need to be multiplexed in the FIR filter multiplexing system include half-band filters and non-half-band filters, wherein non-half-band filters are FIR filters of other types other than half-band filters. In some embodiments, the FIR filters that need to be multiplexed are all filters with a decimation rate, preferably, the decimation rate is a multiple of 2. In this embodiment, the filter type selection module is used to generate the associated read addresses in the currently multiplexed FIR filter and transmit these associated read addresses to the read-write control submodule to determine the start and end time of reading the data buffer. During the hardware implementation process, the read addresses are all counted by a dedicated counter under the same clock or divided by the transmission rate of the actual multiplexed filter type. It is worth noting that the starting address and starting time point of the read operation need to be determined before reading the data. Among them, the data buffer is implemented using SRAM, that is, using static random-access memory (SRAM).

[0050] It should be noted that a half-band filter is a special type of FIR filter. The order of a half-band filter can only be an even number, so the number of taps in a half-band filter is an odd number. Except for the middle value of 0.5, the filter coefficients of the other even numbers (odd items) are all 0. A half-band filter is an FIR filter with a special symmetry. It has a linear phase characteristic, so its filter coefficients are also an even-symmetric real sequence. Since the passband and stopband of this FIR filter are symmetrical about half of the Nyquist frequency point, nearly half of the filter coefficients are exactly zero. Among FIR filters, all FIR filters except half-band filters are classified as non-half-band filters. When half-band filters and non-half-band filters are configured with a number of taps, they are correspondingly set as FIR decimation filters.

[0051] The read-write control submodule is used to control the writing of the data to be filtered into the data buffer of the input FIR filter multiplexing system. Specifically, the read-write control submodule serves as the data read-write logic. It can write the input data into the data buffer at the corresponding clock cycle according to the sampling rate of the currently multiplexed FIR filter. Then, it can count and generate the read address required for the filtering calculation based on the number of taps of the currently multiplexed FIR filter and the number of data to be filtered written in real time, and then transmit the data on the generated read address to the filtering calculation submodule. However, the read address of the valid data read from the data buffer in the read-write control submodule and its enable signal are generated by the filter type selection module.

[0052] like Figure 1 As shown, port 1 of the read-write control submodule is used to transmit a clock signal to the data buffer, and is configured as a driving clock signal for reading the data in the associated read address in the data buffer; port 2 of the read-write control submodule is used to transmit a chip select signal to the data buffer, and the chip select signal is used to select the address interval in the data buffer that needs to be read or enter the working state; port 3 of the read-write control submodule is used to transmit an enable signal to the data buffer, and the enable signal is used to distinguish between read enable and write enable; port 4 of the read-write control submodule is used to transmit the associated read address generated by the filter type selection module to the data buffer; port 5 of the read-write control submodule is used to write the data to be filtered into the data buffer; port 6 of the read-write control submodule is used to receive the read data transmitted by the data buffer, and the read data transmitted by the data buffer will be transmitted to the filtering calculation submodule by other ports of the read-write control submodule, and the data transmitted to the filtering calculation submodule is as shown in FIG. Figure 1 fir_rdata is shown below.

[0053] The read-write control submodule is used to read the data to be filtered from the data buffer in sequence and give it to the filtering calculation submodule based on the size relationship between the number of data to be filtered written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter, using the associated read address provided by the filter type selection module. For one filtering calculation, the number of data to be filtered written into the data buffer is equivalent to the number of data to be filtered input to the FIR filter multiplexing system. Then, judging the size relationship between the number of data to be filtered written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter is to detect whether the number of data to be filtered input to the FIR filter multiplexing system meets a certain count threshold, and is used to decide the filtering calculation method that should be currently adopted by the currently multiplexed FIR filter. Compared with the prior art of extracting and filtering the same batch of data to be filtered, the amount of calculation and the storage amount of filter coefficients are reduced. It should be noted that the relationship between the amount of data to be filtered written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter is determined by a specific enable signal and received by the read-write control submodule. Of course, the specific enable signal can be obtained by the read-write control submodule by counting the amount of external data input into the FIR filter multiplexing system or the amount of data written into the data buffer. Optionally, the transposition enable count threshold of the FIR filter can be the number of taps of the FIR filter, or a value greater than the number of taps of the FIR filter, or a value less than the number of taps of the FIR filter.

[0054] The filtering calculation submodule is used to control the corresponding filtering calculation of the data to be filtered output by the data buffer and the filter coefficients output by the filter coefficient memory, wherein the corresponding filtering calculation is adapted to the FIR filter currently reused by the FIR filter multiplexing system, so that the filter function implementation module is reused as the currently reused FIR filter. Specifically, in the filtering calculation corresponding to the currently reused FIR filter, the calculation method under different filtering cycles is divided according to the relationship between the number of data to be filtered written into the data buffer and the transpose enable count threshold of the currently reused FIR filter. The time and resources consumed by the calculation process under different filtering cycles are different.

[0055] The filter coefficient memory is also used to store the filter coefficients required by the FIR filter that needs to be reused, wherein the filter coefficient memory can be implemented using ROM, that is, using read-only memory (ROM). Figure 1As shown, the filter coefficient memory transmits the filter coefficients to the filter calculation submodule through its port rom_out, wherein the filter coefficients required for each type of FIR filter have matching starting storage addresses in the filter coefficient memory, and these starting storage addresses are selected by the filter type selection module and configured in the filter coefficient memory, or configured in the filter calculation submodule so that the filter calculation submodule reads the required (currently multiplexed FIR filter) filter coefficients starting from the starting storage address.

[0056] In the filter coefficient memory, two types of filter coefficients can be stored simultaneously, namely, filter coefficients applicable to half-band filters and filter coefficients applicable to non-half-band filters. Optionally, the filter coefficients can also be configured using registers, which is more flexible. If the currently multiplexed FIR filter is a half-band filter, then under the control of the corresponding enable control signal and the selection signal, only the filter coefficients of the half-band filter need to be written into the filter coefficient memory; if the currently multiplexed FIR filter is the non-half-band filter, then under the control of the corresponding enable control signal and the selection signal, only the filter coefficients of the non-half-band filter need to be written into the filter coefficient memory; between the non-half-band filter and the half-band filter, the starting storage address can be used to determine whether the currently taken coefficient is for the half-band filter or the non-half-band filter.

[0057] A filter coefficient memory is used to output the required filter coefficients to the filter calculation submodule in sequence after the read-write control submodule starts to read the data to be filtered from the data buffer, starting from the starting storage address corresponding to the currently multiplexed FIR filter, in the order in which the read-write control submodule reads the data to be filtered from the data buffer. It is worth noting that the order in which the filter calculation submodule reads the storage addresses of the filter coefficients from the filter coefficient memory is the same as the order in which the read-write control submodule reads the cache addresses of the data to be filtered from the data buffer, so that the corresponding address positions of the data to be filtered output by the data buffer and the filter coefficient memory are the same. The filter coefficients at (address positions marked with odd or even numbers, which involve a base address that is pre-configured by the filter type selection module and obtained by self-addition or self-addition and subtraction on this basis) can be filtered once within the same filtering cycle. In some embodiments, when the type of the FIR filter to be multiplexed is different, the filter coefficients read from the filter coefficient memory in the same order for the data to be filtered at the same address position output by the data buffer are different, but the storage addresses read may be the same; the data to be filtered output by the data buffer and the filter coefficients output by the filter coefficient memory are not necessarily output synchronously, but it can be guaranteed that a complete filtering calculation is performed within the same filtering cycle.

[0058] Compared with the prior art, the present invention has the following beneficial effects relative to the traditional digital filter implementation method: the present invention uses a selector and a counter combination to form a filter function implementation module, and provides a filter type selection module for a read and write address signal of a type of FIR filter that can be reused, so that the filter function implementation module performs filtering calculations corresponding to the currently reused type of FIR filter on the external input data based on the corresponding read and write address signals, and establishes an FIR filter system with selectable types and universal read control parameter types.

[0059] Specifically, in terms of the functions of extraction and filtering, the present invention is compatible with half-band filters and non-half-band filters. The arithmetic unit part, read-write controller part and memory part common to half-band filters and non-half-band filters are made into a filter function implementation module. At the same time, the timing logic of different functions required to be selected between half-band filters and non-half-band filters is made into a filter type selection module. However, it is not necessary to connect half-band filters and non-half-band filters in series into a single chain filter group (i.e., multiple FIR filters of different types are connected into a cascade structure). Instead, a reusable filter function implementation system is formed, allowing half-band filters and non-half-band filters to implement corresponding filtering functions by sharing a filter function implementation module. There is no need to completely separate and design two sets of filters. The selection signal is now used to determine the start and end time points of extraction and calculation under the corresponding type of filter, meeting the rate requirements of reading and calculating data of different filters. The characteristic index application is more flexible and can adapt to multiple signals with different filtering requirements. In the case of different filtering requirements, there is no need to change the structure of the entire filter system. Only by selecting the control signals for extraction and filtering such as the read enable control signal and the count control signal under the corresponding type of FIR filter, filters with different functions and performances can be reused.

[0060] like Figure 2 As shown, the filter type selection module includes a pre-address selector and an address enable signal selector; the filter type selection module also includes a pre-address counter (belonging to the address counter) that has a data transmission relationship with the pre-address selector, and also includes a register that has an electrical connection relationship with the address enable signal selector. The pre-address selector is used to, after receiving the filter type selection signal, that is, after the selection end of the pre-address selector receives the filter type selection signal hb_sel, start selecting the pre-read address corresponding to the currently multiplexed FIR filter and transmit it to the filter function implementation module, specifically selecting the pre-read address that matches one of the FIR filters between the half-band filter and the non-half-band filter and transmitting it to the read-write control submodule in the filter function implementation module, and the pre-read address of the selected output is expressed as follows: Figure 2The signal fir_raddr_befor at the output end of the pre-address selector in the filter function implementation module is transmitted to the filter function implementation module, but the pre-address selector prohibits the pre-read address of another FIR filter matching from being transmitted to the filter function implementation module to reduce the power consumption of the related logic circuit operation. In some embodiments, the pre-address selector is used to select the pre-address read address corresponding to the currently multiplexed FIR filter and transmit it to the filter function implementation module after receiving the filter type selection signal and then after the number of data to be filtered in the write data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter. Accordingly, the pre-address selector enables the data path between the pre-address counter and the read-write control submodule or the filter function implementation module, so that the read-write control submodule reads the data to be filtered from the pre-address read address of the data buffer according to the read timing corresponding to the currently multiplexed FIR filter, wherein the number of taps of the currently multiplexed FIR filter is configured by a special register in the filter type selection module; the read timing corresponding to the currently multiplexed FIR filter is determined by the counting timing of the pre-address counter enabled by the pre-address selector, and can change according to the change of the count value of the pre-address counter.

[0061] like Figure 2 As shown, the address enable signal selector is used to select the folding read enable signal corresponding to the currently multiplexed FIR filter and transmit it to the filter function implementation module after receiving the filter type selection signal, so that after the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter calculation submodule is triggered to perform folding calculation on the data to be filtered. When the address enable signal selector selects the folding read enable signal corresponding to one FIR filter and transmits it to the filter function implementation module, the address enable signal selector prohibits the folding read enable signal corresponding to another FIR filter from being transmitted to the filter function implementation module. Corresponding to Figure 2 In the address enable signal selector, one input terminal is used to input the folded read enable signal corresponding to the non-half-band filter, which is expressed as Figure 2 The signal raddr_en of the address enable signal selector is used to input the folded read enable signal corresponding to the half-band filter, which is expressed as Figure 2 Among them, when the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the folded read enable signal output by the address enable signal selector is high, corresponding to Figure 1 and Figure 2The signal fir_raddr_en is high; when the number of data to be filtered written to the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the folded read enable signal output by the address enable signal selector is low, corresponding to Figure 1 and Figure 2 The signal fir_raddr_en is at a low level. In some embodiments, the address enable signal selector is configured to, after receiving the filter type selection signal and after the amount of to-be-filtered data written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, select and transmit the folding read enable signal corresponding to the currently multiplexed FIR filter to the filter function implementation module, wherein the folding read enable signal currently selected for transmission is at a high level, so that the read-write control submodule begins to trigger the filter calculation submodule to perform folding calculation on the to-be-filtered data.

[0062] like Figure 2 As shown, the filter type selection module also includes a first address selector and a second address selector; within the filter type selection module, the first address selector has a data transmission relationship with an address counter, and the second address selector has a data transmission relationship with another address counter, and the first address selector and the second address selector are different from the pre-address selector, and the first address selector and the second address selector are specially designed to: when the number of data to be filtered in the write data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the data path between the filter type selection module and the filter function implementation module is selected; and in some embodiments, when the number of data to be filtered in the write data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the first address selector and the second address selector are prohibited from selecting the data path between the filter type selection module and the filter function implementation module.

[0063] The first address selector is used to select the first folding read address corresponding to the currently multiplexed FIR filter and transmit it to the filter function implementation module after receiving the filter type selection signal hb_sel, but prohibit gating and outputting the first folding read address corresponding to another FIR filter, so that when the number of data to be filtered written to the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the read-write control submodule reads the data to be filtered in the first folding read address from the data buffer according to the read timing corresponding to the currently multiplexed FIR filter; corresponding to Figure 2 The first folded read address of the strobe output is expressed as Figure 2The signal fir_raddr1 at the output end of the first address selector in the filter is selected. The read timing corresponding to the currently multiplexed FIR filter is determined by the counting timing of the address counter selected by the first address selector, and can change according to the change of the count value of the address counter. In some embodiments, after receiving the filter type selection signal hb_sel, when the folding read enable signal output by the address enable signal selector is at a high level, the first folding read address corresponding to the currently multiplexed FIR filter is selected and transmitted to the filter function implementation module, so that the read-write control submodule reads the data to be filtered in the first folding read address from the data buffer according to the read timing corresponding to the currently multiplexed FIR filter.

[0064] The second address selector is used to select the second folded read address corresponding to the currently multiplexed FIR filter and transmit it to the filter function implementation module after receiving the filter type selection signal hb_sel, but prohibit gating and outputting the second folded read address corresponding to another FIR filter, so that when the number of data to be filtered written to the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the read-write control submodule reads the data to be filtered in the second folded read address from the data buffer according to the read timing corresponding to the currently multiplexed FIR filter; corresponding to Figure 2 The second folded read address of the strobe output is expressed as Figure 2 The signal fir_raddr2 at the output end of the second address selector in the filter function implementation module is selected. The read timing corresponding to the currently multiplexed FIR filter is determined by the counting timing of the address counter selected by the second address selector, which is different from the counting timing of the address counter selected by the first address selector, including the direction of change of the count value and the initial value of the count value. In some embodiments, after receiving the filter type selection signal hb_sel, when the folding read enable signal output by the address enable signal selector is at a high level, the second folding read address corresponding to the currently multiplexed FIR filter is selected and transmitted to the filter function implementation module, so that the read and write control submodule reads the data to be filtered in the second folding read address from the data buffer according to the read timing corresponding to the currently multiplexed FIR filter.

[0065] It should be added that the address offset between the starting address serial number of the second folded read address and the starting address serial number of the first folded read address is equal to the difference between the number of taps of the currently multiplexed FIR filter and the value 1, so that under the premise that the direction of traversal of the second folded read address is different from the direction of traversal of the first folded read address, each address in the same address range is traversed together, for example, by updating the first folded read address to traverse from the first address to the last address, and by updating the second folded read address to traverse from the last address to the first address, the traversal of the same address range is completed completely under the same address offset step.

[0066] It should be noted that the number of taps of the currently multiplexed FIR filter is configured by a special register, specifically in the filter type selection module; wherein, the associated read address includes the pre-read address, the second folded read address and the first folded read address, which are configured as the read address of the data buffer in this embodiment.

[0067] In this embodiment, the FIR filter multiplexing system is further provided with a system read and write clock source for counting and generating system clock cycles, corresponding to Figure 1 The clock signal output by port 1 of the read / write control submodule in this embodiment is designed as the system read / write clock source as the master clock of the FIR filter multiplexing system. The clock beats generated by the clock are counted as the system clock cycle. The time taken to write one piece of data to be filtered is configured to be equal to one system clock cycle, and the time taken to read one piece of data to be filtered is configured to be equal to one system clock cycle. In this embodiment, the FIR filter multiplexing system is configured to configure the time it takes to write a wave data input from the external input into the data buffer to be equal to one system clock cycle, that is, under the control of the read-write control submodule, excluding other delay operations, during the process of writing a wave data to be filtered into the data buffer, the system clock count length is equal to one system clock cycle, that is, one write clock cycle is equal to one system clock cycle; the FIR filter multiplexing system is also configured to configure the time it takes to read a wave data from the data buffer to be equal to one system clock cycle, that is, under the control of the read-write control submodule, excluding other delay operations, during the process of reading a wave data to be filtered from the data buffer, the system clock count length is equal to one system clock cycle; wherein, a wave data to be filtered is the information of a sampling point sampled from the external by the filter function implementation module, and in this embodiment, is also the data read from the data buffer by the read-write control submodule. The number of wave data to be filtered written into the data buffer is equal to the number of wave data to be filtered sampled from the external by the FIR filter multiplexing system, but is not necessarily the number of wave data to be filtered actually performed filtering calculations.

[0068] On the basis of the above embodiment, the filter function implementation module also includes a filter counter, which can be specifically set in the read-write control submodule as a counting logic component shared by the two types of FIR filters mentioned above; the filter counter is used to add one count once whenever the outside of the FIR filter multiplexing system or the read-write control submodule writes two of the to-be-filtered data to the data buffer and the filter calculation submodule starts a filter calculation, so as to realize that every time two system clock cycles of the write operation are passed, the filter counter counts once to meet the requirement of twice the decimation rate of the currently multiplexed FIR filter, and then triggers the filter calculation submodule to use the to-be-filtered data output by the data buffer to perform a filter calculation suitable for the currently multiplexed FIR filter, including triggering the The read-write control submodule uses the associated read address (starting from the starting address) provided by the filter type selection module to read the data to be filtered from the data buffer in sequence and give it to the filtering calculation submodule; then, when the filtering calculation submodule calculates the corresponding filtering result, that is, when the filtering calculation submodule finishes processing the data to be filtered currently read from the data buffer, it is determined that the FIR filter multiplexing system has gone through a filtering cycle since writing the two data to be filtered, including the two system clock cycles required for initially writing the two data to be filtered, the total cycle of reading the data to be filtered from the data buffer in sequence (the specific value is related to the number of data to be filtered actually read from the data buffer), and the cycle required for the multiplication and accumulation calculation included in the filtering calculation. Therefore, one filtering cycle is greater than two system clock cycles; after each filtering cycle, the filtering calculation submodule outputs a filtering result; wherein, the decimation rate of the currently multiplexed FIR filter is 2 times; it should be supplemented that the change in the count value of the filtering counter is the change in the real-time count value of the filtering counter relative to the initial count value, and the initial count value is the count value set before the filtering counter starts counting. In this embodiment, the initial count value of the filtering counter is set to a value of 1. In addition, the bit width of each data to be filtered written into the data buffer is configured by the filter type selection module, and the bit width occupied by each data to be filtered is less than or equal to the maximum bit width allowed to be read and written by the data buffer. In summary, this embodiment determines the filtering cycle and its counting rules required for a filtering calculation under the condition that the currently multiplexed FIR filter has a decimation rate of 2, which is suitable for the division of the cycles consumed by the filtering calculation of the FIR filter multiplexing system.

[0069] Preferably, when the number of data to be filtered written into the data buffer is represented by the change value of the count value of the filter counter, based on the timing rule that the filter counter adds one count every time two data to be filtered are written, the transpose enable count threshold of the currently multiplexed FIR filter is represented by half of the sum of the number of taps of the currently multiplexed FIR filter and the value 1, so that the size relationship between the transpose enable count threshold of the currently multiplexed FIR filter and the number of data to be filtered written into the data buffer is equivalent to the size relationship between half of the sum of the number of taps of the currently multiplexed FIR filter and the value 1 and the change value of the count value of the filter counter, which facilitates the statistics of the number of data to be filtered written into the data buffer. This preferred example is that in the application scenario where the number of taps of the currently multiplexed FIR filter is an odd number, it is beneficial to use the filter counter to accurately obtain the number of data to be filtered actually written into the data buffer in each filtering cycle.

[0070] Preferably, when the number of data to be filtered written into the data buffer is represented by the change value of the count value of the filter counter, based on the timing rule that the filter counter adds one count every time two data to be filtered are written, the transpose enable count threshold of the currently multiplexed FIR filter is represented by half the number of taps of the currently multiplexed FIR filter, so that the size relationship between the transpose enable count threshold of the currently multiplexed FIR filter and the number of data to be filtered written into the data buffer is equivalent to the size relationship between half the number of taps of the currently multiplexed FIR filter and the change value of the count value of the filter counter, wherein the number of taps of the currently multiplexed FIR filter is an even number.

[0071] In the above embodiment, the method of sequentially reading the data to be filtered from the data buffer and supplying it to the filtering calculation submodule using the associated read address provided by the filter type selection module according to the size relationship between the number of data to be filtered written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter includes: when the read-write control submodule determines that the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the read-write control submodule sequentially reads the data in the pre-read address from the data buffer in each filtering cycle according to the read timing corresponding to the currently multiplexed FIR filter. The data to be filtered is transmitted to the filtering calculation submodule; wherein, the transpose enable count threshold of the currently multiplexed FIR filter is equal to the number of taps of the currently multiplexed FIR filter; at this time, the read timing corresponding to the currently multiplexed FIR filter is determined by the counting timing of the filter counter or the timing of the remaining address counters indirectly triggered by the count value of the filter counter, and is related to the type of the currently multiplexed FIR filter, so that the number of taps of the currently multiplexed FIR filter is used as the maximum count value to divide the read address and the read cycle, so that the address number counted by the relevant counter does not exceed the read address range limited by the number of taps of the currently multiplexed FIR filter.

[0072] It should be noted that the pre-read address is obtained by counting from an initial pre-address sequence number in each filtering cycle, and is specifically determined by the count value of the address counter connected to the pre-address selector; wherein, an initial pre-address sequence number in each filtering cycle is the first pre-read address sequence number participating in the reading operation in the filtering cycle, so that the data to be filtered in the pre-read address corresponding to the initial pre-address sequence number is transmitted to the filtering calculation sub-module according to the corresponding reading timing.

[0073] In the aforementioned embodiment, when the filter type selection signal is at a first logic level, the currently multiplexed FIR filter is the non-half-band filter, causing the FIR filter multiplexing system to multiplex the filter into the non-half-band filter. Specifically, the filter type selection module, the read / write control submodule, and the filter calculation submodule perform the filtering effect of the corresponding type of FIR filter after determining the filter type selection signal. When the filter type selection signal is at a second logic level, the currently multiplexed FIR filter is the half-band filter, causing the FIR filter multiplexing system to multiplex the filter into the half-band filter. Furthermore, if the first logic level is high, the second logic level is low; if the second logic level is high, the first logic level is low.

[0074] As an implementation method for reading data, when the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the read-write control submodule sets the difference between twice the change value of the count value of the filter counter in each filtering cycle relative to its initial count value and the value 2 as the initial pre-address sequence number in the corresponding filtering cycle, meeting the reading requirement of twice the sampling rate, wherein the initial count value is the count value set before the filter counter starts counting. Specifically, the initial pre-address sequence number set in the data buffer in this embodiment supports configuration as 0. Since the pre-address read address is obtained by counting from an initial pre-address sequence number in each filtering cycle, the read-write control submodule can read the data to be filtered starting from the address sequence number 0 in one of the filtering cycles, thereby improving the coverage rate of the address range of the read data. In this embodiment, in each filtering cycle, two consecutive system clock cycles are used to write two data to be filtered into the data buffer in sequence, and then the data is read from the data buffer to the filtering calculation submodule according to the corresponding read timing to perform filtering calculation; preferably, when a filtering calculation is started, the filtering counter does not perform any counting operation in the same filtering cycle except adding one counting operation to the two data to be filtered written initially, but maintains the count value until new data to be filtered is written.

[0075] exist Figure 3 In an embodiment of the present invention, when the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, that is, when the number of data to be filtered written into the data buffer is less than or equal to 5 (the number of taps of the currently multiplexed FIR filter is equal to 5, and the number of taps of the currently multiplexed FIR filter is equal to the transposition enable count threshold of the currently multiplexed FIR filter), the initial prefix address sequence number corresponds to Figure 3 The initial address sequence number of the filter counter is calculated based on the difference between twice the change in the count value of the filter counter relative to its initial count value in each filter cycle and the value 2, which is set as the initial pre-address sequence number of the corresponding filter cycle. The initial pre-address sequence number of the first filter cycle is 0, where the number of data to be filtered written into the data buffer in the first filter cycle is 1; the initial pre-address sequence number of the second filter cycle is 2, and the initial pre-address sequence number of the third filter cycle is 4. At this time, 5 data to be filtered have been written, and the numbers from the most recently written to the earliest written are X5, X4, X3, X2, and X1. The count value of the filter counter can also be used to mark the sequence number of the current filter cycle.

[0076] In some embodiments, there is always a new data entry at address 0 of the data buffer. Figure 3 The window and takes the first position of the window, in particular, Figure 3 In the first filtering cycle, the outside of the FIR filter multiplexing system only writes one to-be-filtered data X1 to the data buffer. Accordingly, the initial prefix address serial number in the first filtering cycle is the value 0, which can be pre-configured by the filter type selection module; the filtering sub-calculation module uses the to-be-filtered data to perform filtering calculation and outputs the filtering result y0, which belongs to the filtering result in the first filtering cycle; therefore, in the first filtering cycle, since only one to-be-filtered data is written, the read-write control submodule sets the change value of the count value of the filter counter in each filtering cycle relative to its initial count value to the initial prefix address serial number in the corresponding filtering cycle, and the initial prefix address serial number can be the value 0 or the value 1.

[0077] As an embodiment, the read-write control submodule also includes a reference address counter; the reference address counter is used to perform a self-increment operation of the count value whenever two data to be filtered are written to the data buffer externally to trigger the filtering calculation submodule to start a filtering calculation, and configure the count value obtained by the self-increment operation as the folded reference address number, and transmit the folded reference address number obtained after the self-increment operation to the filter type selection module within each filtering cycle, and then update the folded reference address number to the first folded read address number, and update the sum of the folded reference address number and the value 1 to the second folded read address number, that is, transmit the updated first folded read address number to the address counter connected to the first address selector as the initial count value of the address counter, and at the same time transmit the updated second folded read address number to the address counter connected to the second address selector as the initial count value of the address counter. It should be noted that the second folding read address sequence number is used to indicate the address order of the second folding read address within the data buffer; the first folding read address sequence number is used to indicate the address order of the first folding read address within the data buffer; the folding base address sequence number indicates the order of the folding base address within the data buffer; the folding base address is configured in the filter type selection module as the first read address in the read operation of all first folding read addresses, and the sum of the folding base address sequence number and the value 1 is configured as the first read address in the read operation of all second folding read addresses. In this embodiment, the transpose enable count threshold of the currently multiplexed FIR filter is equal to the number of taps of the currently multiplexed FIR filter; the decimation rate of the currently multiplexed FIR filter is 2 times; in this embodiment, the reference address counter performs a self-increment operation when the read-write control submodule begins to read the data to be filtered within each filtering cycle, which is equivalent to: each time the filter calculation submodule begins to perform a filtering calculation to output a filtering result, the reference address counter performs a self-increment operation.

[0078] Compared to the aforementioned filter counter, the reference address counter disclosed in this embodiment can be used to continue to perform a self-increment operation on the count value when the number of to-be-filtered data written to the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter; and the change in the count value generated by the reference address counter in each self-increment operation is a value of 2, and the folded reference address sequence number obtained after the self-increment operation is transmitted to the filter type selection module in each filtering cycle; because each time a filtering calculation is started to output a filtering result, two to-be-filtered data need to be written continuously at a double decimation rate, the reference address counter is incremented by one twice, that is, incremented by two once in each self-increment operation. When the filter counter disclosed in the aforementioned embodiment counts that the number of to-be-filtered data written to the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter counter may still be performing a self-increment operation to record the sequence number of the current filtering cycle or the number of written to-be-filtered data, without updating the count value of the filter counter or configuring it as a related read address to be transmitted to the filter type selection module. Therefore, when the number of data to be filtered written into the data buffer exceeds the number of taps of the currently multiplexed FIR filter, the reference address counter provides a corresponding starting read address for the data to be filtered that needs to be extracted and filtered in each filtering cycle, which serves as the starting address information of the data for actual filtering calculation.

[0079] Preferably, when the count value of the reference address counter is the difference between the number of taps of the currently multiplexed FIR filter and the value 2, the read-write control submodule updates the filter starting address number to the count value currently obtained by the reference address counter in the next system clock cycle, and updates the filter starting address number to the folded reference address number, and then transmits the updated folded reference address number to the filter type selection module; wherein, the filter starting address number is an address number pre-configured in the data buffer, and is the address number with the smallest ranking among the address numbers participating in the read operation in each filtering cycle. It can be a value 0 or a value 1, and this embodiment is explained in conjunction with the drawings in the specification, and it is chosen to be set to a value 0. Among them, the reference address counter has an initial count value, which can be a value of 0 or a value of 1, and can be selected to be set to a value of 1, wherein the initial count value is the count value set before the reference address counter starts counting. Therefore, under the premise that the number of taps of the currently multiplexed FIR filter is an odd number, the count value of the reference address counter can be incremented by a value of 2 in each filtering cycle to the difference between the number of taps of the currently multiplexed FIR filter and the value 2. Then, the read-write control submodule updates the value 0 to the count value currently obtained by the reference address counter in the next system clock cycle so as to increase from the filtering starting point address number, and updates the value 0 to the folded reference address number, so that the reference address counter has sufficient counting range to cover the valid address range limited by the number of taps of the currently multiplexed FIR filter, and also avoids the phenomenon of the reference address counter overflowing in the process of increasing by a value of 2 in each filtering cycle or avoids the read-write control submodule reading data in an invalid address.

[0080] Preferably, when the count value of the reference address counter is the difference between the number of taps of the currently multiplexed FIR filter and the value 1, the read-write control submodule will update the sum of the filter starting address number and the value 1 to the count value currently obtained by the reference address counter in the next system clock cycle, and update the sum of the filter starting address number and the value 1 to the folded reference address number; wherein, the filter starting address number is an address number pre-configured in the data buffer, and is the smallest address number among the address numbers participating in the read operation in each filtering cycle. This embodiment is explained in conjunction with the accompanying drawings of the specification and chooses to set it to the value 0. The initial count value of the reference address counter is the count value set before the reference address counter starts counting, which can be a value 0 or a value 1. Under the premise that the number of taps of the currently multiplexed FIR filter is an odd number, in order to cooperate Figure 3 and Figure 4As explained, in this preferred embodiment, the initial count value is set to 0, and the count value of the reference address counter can be incremented by 2 in each filtering cycle to the difference between the number of taps of the currently multiplexed FIR filter and 1. Then, the read-write control submodule updates 1 to the count value currently obtained by the reference address counter in the next system clock cycle so as to start incrementing again from the sum of the filtering starting address number and 1, and updates 1 to the folded reference address number, so that the reference address counter has enough counting range to cover the valid address range limited by the number of taps of the currently multiplexed FIR filter, and also avoids the reference address counter from reading data in an invalid address (outside the read address range limited by the number of taps of the currently multiplexed FIR filter) in the process of incrementing by 2 in each filtering cycle.

[0081] As an embodiment, the folding reference address number corresponds to Figure 3 The initial address number of the reference address counter, in this embodiment, the count value of the reference address counter in each filtering cycle is configured as the folding reference address number in each filtering cycle as the updated folding reference address number; Figure 3 In the example, only one data to be filtered is written in one system clock cycle after power-on (understood as the first filtering cycle), so the filtering counter and the reference address counter do not count, but a filtering calculation still needs to be performed. The folded reference address sequence number of the first filtering cycle is set to the value 0, which is the initial count value of the reference address counter and the initial pre-address sequence number in the first filtering cycle. It is configured as the initial count value of the reference address counter for the first filtering calculation to meet the filtering calculation requirements matched under the condition that the number of taps of the currently multiplexed FIR filter is equal to an odd number, that is, one data to be filtered is reserved to match the even number of data to be filtered obtained at the double decimation rate to form a group of data to be filtered with an odd number; wherein, each filtering cycle except the first filtering cycle requires reading two data to be filtered to complete a filtering calculation. Therefore, the folded reference address sequence number in the first filtering cycle is the value 0, which is the initial count value of the reference address counter.

[0082] Then, each time a filtering calculation starts, it is recorded as the beginning of a filtering cycle. In subsequent filtering cycles, according to the double decimation rate, each time two new data to be filtered are written to the data buffer, a filtering calculation is started, and it is determined that the filtering counter needs to be counted once. After the first filtering calculation is completed, that is, after a filtering cycle, in the second filtering cycle, the data in the first row of boxes are shifted two coefficient positions to the right as a whole, becoming the data in the third row of boxes. Two new data are added to occupy the two leftmost grids relative to the data in the first row of boxes. At this time, the filtering calculation submodule starts a new filtering calculation, and the filtering counter counts up by one. The reference address counter counts up by two to the folding reference address number in the first filtering cycle, and the folding reference address number obtained for the second filtering cycle is the value 2. After completing the second filtering calculation and obtaining the filtering result y2, in the third filtering cycle, the data in the third row box is shifted two coefficient bits to the right as a whole and becomes the data in the fifth row box. Two new data are added to occupy the two leftmost grids relative to the data in the third row box. At this time, the filtering calculation submodule starts a new filtering calculation (the third filtering calculation), and the filtering counter counts up by one. The reference address counter counts up by two once for the folding reference address sequence number of the second filtering cycle, and the folding reference address sequence number of the third filtering cycle is obtained as 4; thereby: the address offset between the initial pre-addresses obtained under two adjacent filtering cycles is equal to the decimation rate of the currently multiplexed FIR filter, and the filtering counter can be used to count the shift operation of the data to be filtered written into the data buffer, so as to facilitate the use of the shift register to cache the newly written data to be filtered. After completing the third filtering calculation and obtaining a filtering result y4, in the fourth filtering cycle, the data in the fifth row of boxes are shifted two coefficient bits to the right as a whole and become the data in the seventh row of boxes. Two new data are added relative to the data in the fifth row of boxes to occupy the two leftmost grids. At this time, the number of data to be filtered written into the data buffer is greater than the transpose enable count threshold of the currently reused FIR filter, that is, the number of data to be filtered written into the data buffer is greater than 5 (the number of taps of the currently reused FIR filter is equal to 5, and the number of taps of the currently reused FIR filter is equal to the transpose enable count threshold of the currently reused FIR filter). At this time, the filtering calculation submodule starts a new filtering calculation (the fourth filtering calculation). At this time, a total of 5 data to be filtered are written.Since the change value of the folding reference address number of the third filtering cycle relative to the folding reference address number in the first filtering cycle is the difference between the number of taps of the currently multiplexed FIR filter and the value 1, that is, the change value of the count value of the reference address counter is the difference between the number of taps of the currently multiplexed FIR filter and the value 1, the sum of the filtering starting point address number and the value 1 is configured as the folding reference address number of the fourth filtering cycle, which is equal to the value 1, corresponding to. Figure 3 The initial address sequence number of the fourth filtering cycle in the filter; wherein the filtering starting address sequence number is a value of 0. It should be noted that the filtering starting address sequence number is an address sequence number pre-configured in the data buffer, and is the smallest address sequence number among the address sequences participating in the read operation in each filtering cycle. In this case, the filtering starting address sequence number can be a value of 0 or a value of 1, and Figure 3 Select to set the filter starting point address sequence number to the value 0 for illustration.

[0083] It is worth noting that in order to obtain the folding reference address sequence number of the fourth filtering cycle, if the reference address counter continues to perform a self-increment operation on the folding reference address sequence number of the fourth filtering cycle (the change value of the count value generated in one self-increment operation is a value of 2), the obtained folding reference address sequence number exceeds the number of taps of the currently multiplexed FIR filter, and invalid data is easily read according to the folding reference address sequence number, which is not suitable for setting Figure 3 The initial address number in , so Figure 3 The initial address sequence number of the fourth filtering cycle in is set to the value 1.

[0084] After completing the fourth filtering calculation and obtaining the filtering result y6, in the fifth filtering cycle, the data in the seventh row of the box is shifted two coefficient positions to the right as a whole, becoming the data in the ninth row of the box. Two new data are added to the data in the seventh row of the box, occupying the two leftmost grids. At this time, the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently reused FIR filter, that is, the number of data to be filtered written into the data buffer is greater than 5 (the number of taps of the currently reused FIR filter is equal to 5, and the number of taps of the currently reused FIR filter is equal to the transposition enable count threshold of the currently reused FIR filter). At this time, the filtering calculation submodule starts a new filtering calculation (the fifth filtering calculation) to obtain the filtering result y8. The reference address counter is incremented by two, and the obtained folding reference address sequence number for the fifth filtering cycle is 3. It should be noted that the aforementioned initial address sequence number is the first operation address required for the filtering calculation submodule to perform the filtering calculation, and is also the address of the first data involved in the calculation in each filtering cycle.

[0085] As an embodiment of the non-half-band filter multiplexed as a filter with a tap number equal to 5, it can be seen from the above embodiments that the filter type selection module includes a pre-address counter, which is Figure 2 The pre-address counter_N in the filter is used to work when the filter type selection signal is a first logic level; when the currently multiplexed FIR filter is the non-half-band filter and the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the pre-address counter_N is used to start from the initial pre-address sequence number corresponding to the current filtering cycle and perform a self-decrement operation according to the system clock cycle. Specifically, the pre-address sequence number corresponding to the initial pre-address sequence number converted in the read-write control submodule is used to perform a self-decrement operation in the current filtering cycle. Optionally, before performing the first self-decrement operation, a delay period is required to allow the written data to be filtered to be stably cached in the data buffer; at the same time, the pre-address counter_N after each self-decrement operation is decremented. The pre-read address is handed over to the pre-address selector and transmitted to the filter function implementation module to trigger the read-write control submodule to read the to-be-filtered data in the pre-read address after each decrement operation from the data buffer, and then transmit it to the filter calculation submodule in sequence until the latest pre-read address sequence number obtained is a value of 0 or a value of 1; the initial count value set by the pre-address counter_N in this embodiment is the initial pre-address sequence number, which can be a value of 0 or a value of 1; the pre-address counter is used as a decrement counter, and each time the pre-address counter_N is decremented, the corresponding change in the count value is a value of 1, and the count value generated after each decrement operation is configured as the pre-read address sequence number, so that after each decrement operation, a new pre-read address sequence number is obtained relative to the previous decrement operation. Therefore, the pre-address counter_N selects the data path between the filter type selection module, the read-write control submodule and the data buffer for the non-half-band filter to read data (double extraction), and transmits the pre-address sequence number obtained by each decrement operation of the pre-address counter_N to the read-write control submodule to realize reading the data in the data buffer according to the extraction rate of twice the pre-address sequence number.

[0086] On the basis of the above-mentioned embodiment 1, the currently multiplexed FIR filter is the non-half-band filter, and still in the implementation scenario where the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the filter coefficient memory is used to start from the starting storage address matched by the currently multiplexed FIR filter in each filtering cycle, under the control of the read-write control submodule or driven by the built-in counter, that is, when the filter type selection signal is at the first logic level, from the base address of the filter coefficient corresponding to the non-half-band filter pre-configured in the filter type selection module At the beginning, the starting storage address is self-added according to the system clock cycle, and then the corresponding stored filter coefficients are sequentially read out to the filtering calculation submodule according to the storage address obtained by self-addition. Specifically, the obtained storage address is added by one in each system clock cycle. In the same system clock cycle, the address offset step of the storage address is equal to the address offset step of the aforementioned pre-read address (the address sequence number subtracted from itself in each system clock cycle), and is kept changing under the same system read and write clock source, so that in one filtering cycle, the reading order of the filter coefficients required for the same filtering calculation is the same as the reading order of the data to be filtered, until The address offset of the storage address obtained by self-addition relative to the starting storage address is equal to half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1; then the filter coefficient memory records the latest storage address as the intermediate calculation storage address, and then performs a self-decrement operation on the intermediate calculation storage address, and then reads the corresponding stored filter coefficients to the filter calculation submodule in sequence according to the storage address obtained by self-decrement, until the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1, so that the self-addition before obtaining the intermediate calculation storage address The storage address obtained by the operation and the storage address obtained by the self-subtraction operation after obtaining the intermediate calculation storage address constitute the symmetrical filter coefficients of the currently reused FIR filter; then the filter coefficient memory repeats the aforementioned self-addition and self-subtraction operations under the control of the filtering calculation submodule until the number of filter coefficients read from the filter coefficient memory in the current filtering cycle meets the number of data to be filtered participating in the filtering calculation in the current filtering cycle, that is, the number of filter coefficients read from the filter coefficient memory in the current filtering cycle is equal to the number of data to be filtered participating in the filtering calculation in the current filtering cycle.It should be noted that, during the self-increment operation on the starting storage address, the address sequence number corresponding to the storage address increases by 1 each time it is self-incremented; during the self-decrement operation on the intermediate calculation storage address, the address sequence number corresponding to the storage address decreases by 1 each time it is self-decremented; the address sequence number corresponding to the storage address in the filter coefficient memory is used to indicate the address order of the storage address within the filter coefficient memory; the number of taps of the currently multiplexed FIR filter is an odd number. The intermediate calculation storage address is set in the filter coefficient memory and is used to store the address of the filter coefficient that matches the currently multiplexed FIR filter (in this embodiment, it is multiplexed as the non-half-band filter). The address with the largest order, i.e., the tail address of the address interval storing the corresponding filter coefficient, is the address.

[0087] In some embodiments, as Figure 3In the third filtering cycle, starting from the address position with the initial address number of 4, from left to right, the data in the fifth row of boxes are the data to be filtered in the pre-read address after the self-decrement operation read by the read-write control submodule from the data buffer. In the squares from left to right, the data in the squares closer to the left are read earlier, and the corresponding address position is the pre-read address number obtained by self-decrementing later; the data in the squares closer to the right are read later, and the corresponding address position is the pre-read address number obtained by self-decrementing earlier. Preferably, the data in one square is read in each system clock cycle. Similarly, the data in the sixth row of boxes are the filter coefficients in the storage addresses after the self-addition operation read from the filter coefficient memory, starting from the address position corresponding to the square h1, that is, the starting storage address matched by the currently multiplexed FIR filter. From left to right, the data in the squares closer to the left are read earlier, and the corresponding address positions are the storage addresses obtained by self-addition earlier; the data in the squares closer to the right are read later, and the corresponding address positions are the storage addresses obtained by self-addition later. When self-adding to the square h3, the address position corresponding to the square h3 relative to the address position corresponding to the square h1 has an address offset equal to 2, which is equal to half of the difference between the number of taps of the currently multiplexed FIR filter (value 5) and value 1 (equal to value 2). The filter coefficient memory configures the address position corresponding to the square h3 as the intermediate calculation storage address; then, starting from the square h3, the intermediate calculation storage address is self-decremented until it reaches the square h1. At this time, the storage address obtained by self-decrement is The address offset of the storage address relative to the intermediate calculation storage address is equal to half of the difference between the number of taps of the currently multiplexed FIR filter (value 5) and the value 1 (equal to the value 2). At this time, in the sixth row of boxes, the filter coefficients h1, h2, h3, h2 and h1 read from left to right correspond exactly to the to-be-filtered data X5, X4, X3, X2 and X1 participating in the filtering calculation in the fifth row of boxes, among which X5 is the to-be-filtered data in the pre-read address read out first, and X1 is the to-be-filtered data in the pre-read address read out last; then the number of filter coefficients read from the filter coefficient memory in the third filtering cycle meets the number of to-be-filtered data participating in the filtering calculation in the third filtering cycle, and also makes the storage address obtained by the self-addition operation before obtaining the intermediate calculation storage address and the storage address obtained by the self-subtraction operation after obtaining the intermediate calculation storage address constitute the symmetrical filter coefficients of the currently multiplexed FIR filter, that is, the filter coefficients h1 and h2 read on the left and right sides of h3 constitute a pair of symmetrical filter coefficients.It should be noted that the aforementioned self-decrement and self-increment are both performed on the address numbers of the corresponding storage addresses, and the address numbers are the address sorting of the corresponding storage addresses in the filter coefficient memory, and support being controlled by the filtering calculation submodule.

[0088] On the basis of the above embodiment, the filtering calculation submodule is used to control the multiplication of the data to be filtered output by the data buffer and the filter coefficients of the same read order output by the filter coefficient memory when the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently reused FIR filter, and input the result into the adder for accumulation processing to obtain the processed filtering result within each filtering cycle; wherein, the multiplication operation within each filtering cycle is implemented by a multiplier in time-sharing multiplexing to minimize the multiplier resources; wherein, the filtering calculation submodule includes an adder and a multiplier, and there is a method of performing multiplication first and then performing addition to achieve accumulation. Corresponding to Figure 3 , the filtering result y4 obtained in the third filtering cycle is equal to the sum of the product of X5 and h1, the product of X4 and h2, the product of X3 and h3, the product of X2 and h2, and the product of X1 and h1, then the number of multiplication operations in the third filtering cycle is equal to 5.

[0089] In a second embodiment of the non-half-band filter multiplexed with a tap number equal to 5, the currently multiplexed FIR filter is the non-half-band filter; and the tap number of the currently multiplexed FIR filter is an odd number. When the amount of data to be filtered written to the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is configured to, within each filtering cycle, perform a decrement operation on the first folded read address according to the read timing corresponding to the currently multiplexed FIR filter, and then transmit the first folded read address after each decrement operation to the read-write control submodule via the first address selector, thereby triggering the read-write control submodule to read the data to be filtered from the first folded read address after each decrement operation from the data buffer, until the number of decrement operations reaches a first preset folded sampling number.

[0090] In the above embodiment, the filter type selection module includes a first folding address counter, combined with Figure 2Specifically, the first folding address counter_N connected to the first address selector is enabled when the filter type selection signal is at a first logic level. The first folding address counter_N is configured to update the filtering target address number to the folding reference address number if the filter type selection module determines that the folding reference address number is equal to the filtering starting address number before the filter type selection module determines to configure the folding reference address number as the starting address number of the first folding read address. The updated folding reference address number is then updated as the starting address number of the first folding read address. This allows the first folding read address to be decremented by a reasonable address offset value to obtain the data to be filtered in the valid address, thereby avoiding obtaining invalid data and losing data associated with the filtering calculation in the current filtering cycle. It should be noted that the filter target address sequence number is an address sequence number pre-configured in the data buffer, and is the address sequence number of the largest address read among the addresses participating in the read operation in each filter cycle. The filter target address sequence number is greater than the filter starting address sequence number, and the difference between the filter target address sequence number and the filter starting address sequence number is equal to the difference between the number of taps of the currently multiplexed FIR filter and the value 1. When the filter starting address sequence number is set to a value of 0 or a value of 1, the filter target address sequence number is set to the difference between the number of taps of the currently multiplexed FIR filter and the value 1; or, when the filter starting address sequence number is set to a value of 1, the filter target address sequence number is set to the number of taps of the currently multiplexed FIR filter.

[0091] Then, the first folding address counter_N is used to perform a self-decrement operation on the first folding read address sequence number starting from the starting address sequence number of the first folding read address, so as to realize an orderly data reading operation based on the double sampling rate specified by the currently multiplexed non-half-band filter; wherein the aforementioned first folding read address sequence number represents the order of the first folding read address in the data buffer; the change value of the count value generated by the self-decrement of the first folding address counter is a value of 1, so that the change value generated by the self-decrement operation on the first folding read address sequence number is a value of 1; the process of the first folding address counter_N performing the self-decrement operation on the first folding read address sequence number includes: The starting address sequence number of the read address is configured as the first folded read address sequence number. Whenever the first folded read address sequence number is decremented to the filtering starting address sequence number, the filtering target address sequence number is updated to the first folded read address sequence number in the next system clock cycle, so that the first folded read address can realize address loop traversal within the address range limited by the number of taps of the currently multiplexed FIR filter, which can not only traverse to the latest written data to be filtered, but also reduce the allocation amount of cache addresses. It is worth noting that because the previously cached data can be read into the filtering calculation submodule in a timely manner, the newly written data can overwrite the address unit where the previously cached data is located. Then, after excluding the above-mentioned extreme cases of self-decrementing to the filtering starting address sequence number or the filtering target address sequence number, the first folded address counter continues to perform self-decrement operations on the first folded read address sequence number.

[0092] It should be noted that, under the read timing corresponding to the currently multiplexed FIR filter, a self-decrement operation is performed on the first folded read address every two consecutive system clock cycles to obtain a new first folded read address, and these two consecutive system clock cycles are recorded as the counting cycle of the first folded read address; under the read timing corresponding to the currently multiplexed FIR filter, a self-increment operation is performed on the second folded read address every two consecutive system clock cycles to obtain a new second folded read address, and these two consecutive system clock cycles are recorded as the counting cycle of the second folded read address; when the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, under the control of the read-write control submodule, within the counting cycle of the first folded read address, the data to be filtered in the first folded read address is read to the filter calculation submodule, and the data to be filtered in the second folded read address is read to the filter calculation submodule; the reading is repeated until the data to be filtered of the first folded read address and the data to be filtered of the second folded read address limited in the current filtering cycle are read.

[0093] On the other hand, when the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is also used to perform a self-addition operation on the second folded read address according to the read timing corresponding to the currently multiplexed FIR filter within each filtering cycle, and then transmit the second folded read address after each self-addition operation to the read-write control sub-module through the second address selector to trigger the read-write control sub-module to read the data to be filtered in the second folded read address after each self-addition operation from the data buffer, until the number of self-addition operations is the second preset folded sampling number.

[0094] In the above embodiment, the filter type selection module includes a second folding address counter, combined with Figure 2It can be seen that the second folding address counter_N connected to the second address selector is specifically enabled to operate when the filter type selection signal is at the first logic level. Before the filter type selection module determines to configure the folding reference address sequence number as the starting address sequence number of the second folding read address, if the filter type selection module determines that the folding reference address sequence number is equal to the filtering target address sequence number, the second folding address counter_N updates the filtering starting address sequence number to the folding reference address sequence number, and then updates the sum of the folding reference address sequence number and the value 1 as the starting address sequence number of the second folding read address, so as to avoid overlap with the starting address sequence number of the first folding read address and avoid reading the same data to be filtered; then, the second folding address counter_N is used to perform a self-increment operation on the second folding read address sequence number starting from the starting address sequence number of the second folding read address, wherein the change value of the count value generated by the self-increment of the second folding address counter_N is the value 1, so that the change value of the second folding read address sequence number generated in the self-increment operation is the value 1, so as to realize the data reading operation in an orderly manner based on the double sampling rate specified by the currently multiplexed non-half-band filter in the direction of the address offset different from the first folding read address; In the embodiment, the second folding read address sequence number represents the order of the second folding read address in the data buffer; the change value of the count value generated by the second folding address counter when it is self-incremented once is a value of 1, so that the change value generated by the second folding read address sequence number in one self-increment operation is a value of 1; then the process in which the second folding address counter _N performs a self-increment operation on the second folding read address sequence number includes: configuring the starting address sequence number of the second folding read address as the second folding read address sequence number, and whenever the second folding read address sequence number is self-incremented to the filtering target address sequence number, updating the filtering starting address sequence number to the second folding read address sequence number in the next system clock cycle, so that the second folding read address realizes address loop traversal within the address range limited by the number of taps of the currently multiplexed FIR filter, which can traverse to the latest written data to be filtered and reduce the allocation amount of the cache address, and then cooperate with the loop traversal of the first folding read address to completely traverse the address range limited by the number of taps of the currently multiplexed FIR filter without overlap within the same filtering cycle.

[0095] It should be noted that, under the read timing corresponding to the currently multiplexed FIR filter, a self-addition operation is performed on the second folded read address every two consecutive system clock cycles to obtain a new second folded read address, and these two consecutive system clock cycles are recorded as the counting cycle of the second folded read address; when the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, under the control of the read-write control submodule, within the counting cycle of the first folded read address or the counting cycle of the second folded read address (equivalent to two consecutive system clock cycles), the data to be filtered in the first folded read address is read to the filter calculation submodule, and the data to be filtered in the second folded read address is read to the filter calculation submodule, and the reading is repeated until the number of data to be filtered read within a filtering cycle is equal to the number of taps of the currently multiplexed FIR filter, and equal to the number of data to be filtered of the first folded read address and the number of data to be filtered of the second folded read address defined within the current filtering cycle. In this embodiment, within the counting cycle of each first folding read address or the counting cycle of each second folding read address, the address offset of the first folding read address serial number corresponding to the read first folding read address relative to the filtering starting address serial number is equal to the address offset of the filtering target address serial number relative to the second folding read address serial number corresponding to the read second folding read address, so as to realize folding calculation of the data to be filtered at the second folding read address input into the filtering calculation submodule within one filtering cycle and the data to be filtered at the first folding read address symmetrical in address position.

[0096] In the above embodiment, within the counting cycle of each first folding read address or the counting cycle of each second folding read address, the address offset of the first folding read address number corresponding to the read first folding read address relative to the filtering starting address number is equal to the address offset of the filtering target address number relative to the second folding read address number corresponding to the read second folding read address, forming an end-to-end symmetrical FIR filter structure centered on an intermediate address position.

[0097] Corresponding to Figure 3In the window of extracted data, in the 4th filtering cycle, when the number of taps is 5, according to the first folding read address and the second folding read address transmitted by the filter type selection module, the read-write control submodule first reads the 7th input data X7 (data at the first folding read address) and the 3rd input data X3 (data at the second folding read address) to form the first pair of added parameters and sends them to the filtering calculation submodule; then reads the 6th input data X6 (data at the first folding read address) and the 4th input data X4 (data at the second folding read address) to form the second pair of added parameters. The parameters are sent to the filtering calculation submodule; finally, the fifth input data X5 (the data at the first folding read address or the data at the second folding read address) is read and sent to the filtering calculation submodule, and after reading the data to be filtered of the first folding read address and the data to be filtered of the second folding read address limited in the current filtering cycle, the filtering calculation submodule is also triggered to complete the folding calculation of the data, so that the filter function implementation module completes the filtering calculation under the state that the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter.

[0098] It is worth noting that the number of taps of the currently multiplexed FIR filter is an odd number; when the second preset folding sampling number is greater than the first preset folding sampling number, the difference between half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1 and the value 1 is equal to the first preset folding sampling number, and half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1 is equal to the second preset folding sampling number, so that the first folding read address stops changing in advance of the second folding read address, that is, the first folding read address is first decremented to obtain the middle address position within the current filtering cycle, and the middle address position is the last value of the first folding address counter _N for the first folding read address. The address position obtained by subtracting one at a time; or, when the second preset folding sampling number is less than the first preset folding sampling number, the difference between half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1 and the value 1 is equal to the second preset folding sampling number, and half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1 is equal to the first preset folding sampling number, so that the second folding read address stops changing in advance of the first folding read address, that is, the second folding read address is first self-added to obtain the intermediate address position within the current filtering cycle, and the intermediate address position is the address position obtained by the second folding address counter _N adding one to the second folding read address for the last time.

[0099] As an example, Figure 3In the fourth filtering cycle, starting from the initial address number 1, the first folded read address is decremented according to the system clock cycle limited by the number of taps of the currently multiplexed FIR filter, including the maximum read time length supported by the number of taps and the system clock cycle for reading a single data, and the first folded read address after each decrement operation is transmitted to the read-write control submodule through the first address selector. Then, each time the read-write control submodule receives the first folded read address obtained by a decrement operation from the filter type selection module, the data to be filtered in the corresponding first folded read address is read from the data buffer, which are X7, X6 and X5 in the seventh row box, respectively. At this time, the number of decrement operations is 2, which is equal to half of the difference between the number of taps of the currently multiplexed FIR filter (value 5) and the value 1, and the data to be filtered in the three first folded read addresses are obtained. At the same time, each time the read-write control submodule receives a second folded read address obtained by a self-add operation from the filter type selection module, the data to be filtered in the corresponding second folded read address is read from the data buffer, which are X3 and X4 in the seventh row box, respectively. At this time, the number of self-add operations is 1, which is equal to the difference between half of the difference between the number of taps of the currently multiplexed FIR filter (value 5) and the value 1 and the value 1, and then the data to be filtered in the two second folded read addresses is obtained, and the data reading is stopped. Therefore, in the fourth filtering cycle, the data to be filtered read in sequence are X7, X3, X6, X4 and X5, among which X7 is the first data to be filtered read and X5 is the last data to be filtered read. At this time, the data to be filtered in the first folded read address and the data to be filtered in the second folded read address have satisfied the filtering calculation of the number of taps matching the currently multiplexed FIR filter.

[0100] Furthermore, in the fifth filtering cycle, starting from the initial address sequence number 3, the first folding read address is decremented according to the system clock cycle limited by the number of taps of the currently multiplexed FIR filter. Each time the read-write control submodule receives the first folding read address obtained by the decrement operation from the filter type selection module, the data to be filtered in the corresponding first folding read address is read from the data buffer, which are X9, X8 and X7 in the ninth row box, respectively. At this time, the data in the seventh row box is shifted two squares to the right, but the number of decrement operations occurring in the fifth filtering cycle is 2, which is equal to half the difference between the number of taps of the currently multiplexed FIR filter (value 5) and the value 1, and the data to be filtered in the three first folding read addresses is obtained. Therefore, in the fifth filtering cycle, the data to be filtered read in sequence are X9, X5, X8, X6 and X7, where X9 is the first data to be filtered read and X7 is the last data to be filtered read.

[0101] It is worth noting that Figure 3 In the fourth filtering cycle and the fifth filtering cycle, the arrangement order of the squares in the seventh row and the ninth row of the box corresponding to each square only represents the order in which the filtered data are read, and does not represent the actual storage order in the data buffer; similarly, Figure 3 The arrangement order of the squares in the even-numbered rows does not represent the storage order of the internal filter coefficients in the filter coefficient memory, but only represents the reading order of the filter coefficients and corresponds to the reading order of the data to be filtered in the previous row.

[0102] As a third embodiment of the non-half-band filter multiplexed with a tap number equal to 5, when the number of data to be filtered written into the data buffer is greater than the transpose enable count threshold of the currently multiplexed FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address that matches the currently multiplexed FIR filter, under the control of the read-write control submodule or driven by the built-in counter, perform a self-add operation on the starting storage address once every two system clock cycles, and then read the corresponding stored filter coefficients to the filtering calculation submodule in sequence according to the storage address obtained by self-addition, until the address offset of the storage address obtained by self-addition relative to the starting storage address is equal to half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1, and then record the latest obtained storage address as the intermediate calculation storage address, at which time the filter coefficients have been read. The data to be filtered and the filter coefficients to be processed within the cycle; specifically, the address counter set inside the filter coefficient memory or the address counter designed inside the read-write control submodule, the address serial number corresponding to the starting storage address is counted once every two system clock cycles and the corresponding address serial number is generated, and is configured as a storage address that changes simultaneously with the first folding read address and the second folding read address read out within the counting cycle of a first folding read address or the counting cycle of each second folding read address, the filter coefficient in the storage address and the data to be filtered in the first folding read address and the second folding read address within the counting cycle of the first folding read address are read into the filtering calculation submodule within the same counting cycle of the first folding read address, forming a group of calculation items that are first added and then multiplied, that is, the sum of the data to be filtered in the first folding read address and the second folding read address is multiplied by the filter coefficient. Among them, in the process of performing a self-increment operation on the starting storage address, the address number corresponding to the storage address increases by 1 each time it is self-incremented; in this embodiment, there is no need to perform a self-decrement operation on the starting storage address. Compared with the case where the number of data to be filtered in the written data buffer is less than or equal to the transpose enable count threshold of the currently multiplexed FIR filter, there is no need to loop back on the storage address, thereby saving the amount of reading operations.

[0103] It should be added that the starting storage address is selected and determined by the filter type selection module to match the currently reused FIR filter; wherein, the address sequence number corresponding to the storage address is used to indicate the address sorting of the storage address in the filter coefficient memory; in the above-mentioned embodiment three, relative to the embodiment one of the non-half-band filter with a tap number equal to 5, in the filter coefficient memory, except for the intermediate calculation storage address, half of the addresses are not read repeatedly. In this embodiment, the filter coefficients are not written at the corresponding addresses, thereby reducing the storage capacity of the filter coefficients. The number of taps of the currently reused FIR filter is an odd number.

[0104] The filtering calculation submodule is used to, when the number of to-be-filtered data written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, first control the to-be-filtered data in the first folding read address output by the data buffer to be added with the to-be-filtered data in the second folding read address output by the data buffer within each counting cycle of the first folding read address or each counting cycle of the second folding read address; then multiply the result of the addition with the filter coefficient of the same read order output by the filter coefficient memory; then input the multiplication result into the adder for accumulation processing, repeating this process within each filtering cycle until the filter coefficient memory outputs the filter coefficient in the intermediate calculation storage address, then multiply the filter coefficient in the intermediate calculation storage address with the to-be-filtered data in the first folding read address output by the data buffer under the same read order, and then input the multiplication result into the adder for accumulation processing, so as to obtain the processed filtering result within the corresponding filtering cycle, thereby completing one filtering calculation, i.e., completing the filtering calculation within one filtering cycle. Wherein, within each filtering cycle, the number of multiplication operations is equal to half of the sum of the number of taps of the currently reused FIR filter and the value 1, and is implemented by time-sharing multiplexing of a multiplier; wherein, the filtering calculation submodule includes an adder and a multiplier, and the number of taps of the currently reused FIR filter; wherein, the transposition enable count threshold of the currently reused FIR filter is equal to the number of taps of the currently reused FIR filter. This embodiment uses the same multiplier resources in the filtering calculation submodule to implement the multiplication operation of the newly input to-be-filtered data under different filtering cycles and the same set of filter coefficients, thereby improving the reuse rate of the multiplier resources under the condition that different types of filters read data.

[0105] Corresponding to Figure 3 In the fourth filtering cycle, X7 (the data to be filtered in the first folding read address read for the first time, i.e., the data to be filtered read for the first time) and X3 (the data to be filtered in the second folding read address read for the first time, i.e., the data to be filtered read for the second time) are a set of folding data, which are added together to obtain a first folding value. At the same time, the filter coefficient h1 is read from the filter coefficient memory;

[0106] Then, X6 (the data to be filtered in the first folding read address read for the second time, that is, the data to be filtered read for the third time) and X4 (the data to be filtered in the second folding read address read for the second time, that is, the data to be filtered read for the fourth time) are another set of folding data, which are added to obtain the second folding value. At the same time, the filter coefficient h2 is read from the filter coefficient memory; then, the filter coefficient h3 in the intermediate calculation storage address is read from the filter coefficient memory. Generally, the filter coefficient in the intermediate calculation storage address is set to a fixed parameter, which is applicable to any FIR filter with an odd number of taps. For these folded data, the filtering calculation submodule outputs the filter coefficients at the corresponding positions from the filter coefficient memory for multiplication to perform folding calculation. Specifically, the filtering result y6 obtained by the folding calculation is equal to: the product of the sum of X7 (the data to be filtered in the first folding read address read for the first time, that is, the data to be filtered read for the first time) and X3 (the data to be filtered in the second folding read address read for the first time, that is, the data to be filtered read for the second time) and the filter coefficient h1 read for the first time, the product of the sum of X6 (the data to be filtered in the first folding read address read for the second time, that is, the data to be filtered read for the third time) and X4 (the data to be filtered in the second folding read address read for the second time, that is, the data to be filtered read for the fourth time) and the filter coefficient h2 read for the second time, and the sum of X5 (the data to be filtered in the first folding read address read for the third time, that is, the data to be filtered read for the fifth time) and the filter coefficient h3 read for the third time.

[0107] As an embodiment, the number of taps of the currently multiplexed FIR filter is equal to 7, and the currently multiplexed FIR filter is a half-band filter, and the folding reference address sequence number corresponds to Figure 4 The initial address number of the reference address counter, in this embodiment, is configured so that the count value of the reference address counter in each filtering cycle is the folded reference address number in each filtering cycle as the updated folded reference address number; the folded reference address number in the first filtering cycle is 0, which is configured as the initial count value of the reference address counter for the purpose of performing the first filtering calculation, so as to meet the filtering calculation requirements matched under the condition that the number of taps of the currently multiplexed FIR filter is an odd number, that is, one data to be filtered is reserved to match the even number of data to be filtered obtained at a double decimation rate to form a group of data to be filtered with an odd number; wherein, in each filtering cycle except the first filtering cycle, the read-write control submodule needs to read two data to be filtered in order to complete a filtering calculation.

[0108] exist Figure 4In the example, after the first filtering calculation is completed and the filtering result y1 is obtained, that is, after one filtering cycle, in the second filtering cycle, the data in the first row of blocks are shifted rightward by two coefficients, becoming the data in the third row of blocks. Two new data are added to the data in the first row of blocks, occupying the two leftmost cells. At this time, the filtering calculation submodule begins a new filtering calculation. The reference address counter increments the folding reference address sequence number of the first filtering cycle by two, and the obtained folding reference address sequence number for the second filtering cycle is 2. After the second filtering calculation is completed and the filtering result y3 is obtained, in the third filtering cycle, the data in the third row of blocks are shifted rightward by two coefficients, becoming the data in the fifth row of blocks. Two new data are added to the data in the third row of blocks, occupying the two leftmost cells. At this time, the filtering calculation submodule begins a new filtering calculation (the third filtering calculation). The reference address counter increments the folding reference address sequence number of the second filtering cycle by two, and the obtained folding reference address sequence number for the third filtering cycle is 4. After completing the third filtering calculation and obtaining the filtering result y5, in the fourth filtering cycle, the data in the fifth row box is shifted two coefficient bits to the right as a whole and becomes the data in the seventh row box. Compared with the data in the fifth row box, two new data are added to occupy the two leftmost grids. At this time, the filtering calculation submodule starts a new filtering calculation (the fourth filtering calculation), and the reference address counter counts the folding reference address number of the third filtering cycle plus two once, and the folding reference address number of the fourth filtering cycle is 6.After completing the fourth filtering calculation and obtaining the filtering result y7, in the fifth filtering cycle, the data in the seventh row box is shifted two coefficient bits to the right as a whole and becomes the data in the ninth row box. Two new data are added relative to the data in the seventh row box to occupy the two leftmost grids. At this time, the number of data to be filtered written into the data buffer is greater than the transpose enable count threshold of the currently multiplexed FIR filter, that is, the number of data to be filtered written into the data buffer is greater than 7 (the number of taps of the currently multiplexed FIR filter is equal to 7, and the number of taps of the currently multiplexed FIR filter is equal to the transpose enable count threshold of the currently multiplexed FIR filter). At this time The filtering calculation submodule starts a new filtering calculation (the fifth filtering calculation) to obtain the filtering result y9. At this time, the data buffer has stored 9 data to be filtered; since the address offset of the folding reference address number (value 6) of the fourth filtering cycle relative to the folding reference address number (value 0) in the first filtering cycle is the difference (value 6) between the number of taps of the currently multiplexed FIR filter and the value 1, that is, the change value of the count value of the reference address counter is the difference between the number of taps of the currently multiplexed FIR filter and the value 1, the sum of the filtering starting point address number and the value 1 is configured as the folding reference address number of the fifth filtering cycle, which is equal to the value 1, corresponding to. Figure 4 The initial address number of the fifth filtering cycle in Figure 4 The boxes only display the extracted data, corresponding to X9, X3, X7, X5 and X6 in the ninth row of boxes of the fifth filtering cycle.

[0109] It should be noted that the filter starting address number is an address number pre-configured in the data buffer, and is the smallest address number among the address numbers participating in the read operation in each filter cycle. At this time, the filter starting address number is a value of 0 or a value of 1. It is worth noting that in order to obtain the folding reference address number in the fifth filter cycle, if the reference address counter uses the folding reference address number of the fourth filter cycle as the folding reference address number for self-increment operation (the change in the count value generated in one self-increment operation is a value of 2), instead of being configured as a value of 1, the obtained folding reference address number exceeds the number of taps of the currently multiplexed FIR filter, and invalid data is easily read according to the folding reference address number, so it is not suitable to be set as Figure 4 The initial address number in , so Figure 4 The initial address sequence number of the fourth filtering cycle in is set to the value 1.

[0110] As an embodiment of the half-band filter multiplexed as a tap number equal to 7, in combination with the above embodiments, in addition to the embodiment of the non-half-band filter, it can be seen that the filter type selection module includes a pre-address counter, which is Figure 2 The pre-address counter _HB in the filter type selection signal is used to work when the filter type selection signal is at the second logic level; if the currently multiplexed FIR filter is the half-band filter, and the number of to-be-filtered data written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the pre-address counter _HB is used to start from the initial pre-address sequence number corresponding to the current filtering cycle, and perform a self-decrement operation according to the system clock cycle to obtain a new pre-address read address, and transmit the pre-address read address after each self-decrement operation to the filter function implementation module by the pre-address selector to trigger the read-write control submodule. The module reads the data to be filtered from the pre-read address after each decrement operation from the data buffer and transmits it sequentially to the filter calculation submodule until the latest pre-read address sequence number is 1 or 0. In this embodiment, the initial count value set by the pre-address counter _HB is the initial pre-address sequence number, which can be 0 or 1. The pre-address counter acts as a decrementing counter. Each time the pre-address counter _HB decrements, the corresponding count value changes by 2 to meet the requirement of reading one data calculation every two addresses in the half-band filter. The count value generated after each decrement operation is configured as the pre-read address sequence number. Therefore, the pre-address counter _HB selects the data path between the filter type selection module, the read-write control submodule, and the data buffer for the half-band filter to read data (double decimation). The pre-address counter _HB transmits the pre-address sequence number obtained by each decrement operation of the pre-address counter _HB to the read-write control submodule to achieve reading half of the data in the data buffer at a decimation rate twice that of the pre-address sequence number.

[0111] As an embodiment, within a filtering cycle, when the difference between half of the difference between the number of taps of the half-band filter and the value 1 and the value 1 is equal to twice the number of times the pre-address counter _HB performs the aforementioned decrement operation, that is, the change value of the count value generated by the pre-address counter _HB performing the aforementioned decrement operation (relative to the change value generated by the initial pre-address sequence number corresponding to the current filtering cycle) is equal to the difference between half of the difference between the number of taps of the half-band filter (the number of taps is equal to the value 7) and the value 1 and the value 1, the pre-address counter _HB updates the difference between the currently obtained pre-read address sequence number and the value 1 to the pre-read address sequence number, and allows the read-write control submodule to read the data to be filtered in the pre-read address sequence number, thereby allowing the pre-address counter _HB to generate the pre-read address in the process of the pre-address counter's decrement operation. The difference between the currently obtained preamble read address number and the value 1 is updated as a new preamble read address number (the counter sets the count value) and is given the opportunity to participate in the filtering calculation of the half-band filter. In this embodiment, the preamble read address number is also marked as an intermediate preamble read address number. Then, the preamble address counter _HB is used to decrement the intermediate preamble read address number after obtaining the intermediate preamble read address number to obtain the difference between the intermediate preamble read address number and the value 1. The difference between the intermediate preamble read address number and the value 1 is allowed to be updated as the preamble read address number, that is, the difference between the intermediate preamble read address number and the value 1 is allowed to be used as the new preamble read address number to participate in the filtering calculation of the half-band filter. Then, starting from the difference between the intermediate preamble read address number and the value 1, the aforementioned self-decrement operation is continued to be performed to obtain a new preamble read address. The decrement operation here means that the count value of the leading address counter _HB is reduced by 2 in one decrement operation, resulting in an address offset of 2 in the leading read address sequence number in one decrement operation. The currently obtained leading read address sequence number is reduced by 2 relative to the previously obtained leading read address sequence number. The intermediate leading read address sequence number and the leading read address sequence number have the same meaning as the leading read address sequence number, both of which are used to indicate the address order of the leading read addresses in the data buffer.

[0112] Based on the first embodiment, if the currently multiplexed FIR filter is the half-band filter, correspondingly, the filter coefficients stored at the even-numbered address locations in the filter coefficient memory are all 0 and do not need to be output to the filter calculation submodule for calculation. When the number of data to be filtered written to the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address that matches the currently multiplexed FIR filter, that is, when the filter type selection signal is at the second logic level, under the control of the read-write control submodule or driven by the built-in counter, perform a self-increment operation on the starting storage address according to the system clock cycle, and then read the corresponding stored filter coefficients to the filter calculation submodule in sequence according to the storage address obtained by self-increment, until the address offset of the storage address obtained by self-increment relative to the starting storage address is equal to half of the sum of the number of taps of the currently multiplexed FIR filter and the value 1, and then record the latest storage address as the intermediate calculation storage address. At this time, the intermediate calculation storage address is synchronized with the data output by the intermediate pre-read address sequence number in the data buffer, so that The data stored in the two are involved in the multiplication operation; then the intermediate calculation storage address is decremented, and the corresponding stored filter coefficients are read out in sequence to the filtering calculation submodule according to the storage address obtained by self-decrement. Specifically, the value 2 is added to the obtained storage address in each self-addition operation. Then, in the same system clock cycle, the address offset step of the storage address is equal to the address offset step of the aforementioned pre-read address, and is kept changing under the same system read-write clock source, so that in one filtering cycle, the reading order of the filter coefficients required to participate in the same filtering calculation is the same as the reading order of the data to be filtered, until the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the sum of the number of taps of the currently multiplexed FIR filter and the value 1, and the process is repeated until the number of filter coefficients output from the filter coefficient memory in the current filtering cycle is equal to the number of data to be filtered read in the current filtering cycle. In this embodiment, under the control of the filtering calculation submodule, the filter coefficient memory performs a self-addition operation starting from the starting storage address that matches the currently reused FIR filter; and then performs a self-subtraction operation starting from the intermediate calculation storage address reached by the self-addition, and repeats this process until the number of filter coefficients read from the filter coefficient memory in the current filtering cycle meets the number of data to be filtered participating in the filtering calculation in the current filtering cycle, and the number of filter coefficients read from the filter coefficient memory in the current filtering cycle is equal to the number of data to be filtered participating in the filtering calculation in the current filtering cycle.It should be noted that, during the process of performing a self-increment operation on the starting storage address, the starting storage address is self-incremented once every system clock cycle, and the address number corresponding to the storage address increases by a value of 2; during the process of performing a self-decrement operation on the starting storage address, the starting storage address is self-decremented once every system clock cycle, and the address number corresponding to the storage address decreases by a value of 2; the address number corresponding to the storage address in the filter coefficient memory is used to indicate the address sorting of the storage address in the filter coefficient memory; the number of taps of the currently reused FIR filter is an odd number. Wherein, the intermediate calculation storage address is set in the filter coefficient memory, and is used to store the address of the filter coefficient matching the currently reused FIR filter, and the address with the largest sorting, that is, the tail address of the address interval storing the corresponding filter coefficient.

[0113] exist Figure 4In the fourth filtering cycle, starting from the address position with the initial address number (folded reference address number) being 6, from left to right, the data in the seventh row of boxes are sequentially the data to be filtered in the pre-read address after the self-decrement operation read by the read-write control submodule from the data buffer. In the squares from left to right, the data in the squares closer to the left are read earlier, and the corresponding address position is the pre-read address number obtained by self-decrementing earlier; the data in the squares closer to the right are read later, and the corresponding address position is the pre-read address number obtained by self-decrementing later. Preferably, the data in a square is read every two addresses, so that the address positions in odd order are read within one filtering cycle. Similarly, the data in the eighth row of boxes are the filter coefficients in the storage addresses after the self-addition operation read from the filter coefficient memory, starting from the address position corresponding to the square h1, that is, the starting storage address matched by the currently multiplexed FIR filter. From left to right, the data in the squares closer to the left are read earlier, and the corresponding address positions are the storage addresses obtained by the earlier self-addition; the data in the squares closer to the right are read later, and the corresponding address positions are the storage addresses obtained by the later self-addition, until the square h5 is read. At this time, the address offset of the address position corresponding to the square h5 relative to the address position corresponding to the square h1 is equal to the value 4, which is equal to half of the sum of the number of taps of the currently multiplexed FIR filter (value 7) and the value 1 (equal to the value 4), and then the address position of the square h5 is configured as the intermediate calculation storage address; then the intermediate calculation storage address (the intermediate calculation storage address corresponds to the address sequence number used to represent its address in the filter coefficient memory) is calculated. The difference between the first and second values ​​(sorted) and the value 1 is decremented until it reaches the square of h1. At this time, the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the sum of the number of taps of the currently multiplexed FIR filter (value 7) and the value 1 (equal to the value 4), completing a loop traversal of the filter coefficient memory. At this time, in the eighth row of boxes, the filter coefficients h1, h3, h5, h3 and h1 are read from left to right, and correspond to the to-be-filtered data X7, X5, X4, X3 and X1 participating in the filtering calculation in the fifth row of boxes, wherein h1 and X7 are read in the same system clock cycle, h3 and X5 are read in the same system clock cycle, h5 and X4 are read in the same system clock cycle, h3 and X3 are read in the same system clock cycle, and h1 and X1 are read in the same system clock cycle; then the number of filter coefficients read from the filter coefficient memory in the fourth filtering cycle meets the number of to-be-filtered data participating in the filtering calculation in the fourth filtering cycle.

[0114] It should be noted that the address offset between the pre-read address at X7 and the pre-read address at X5 is equal to the value 2 (the change in the count value generated by each self-decrement operation (minus two count) of the pre-read address counter_HB), the address offset between the pre-read address at X5 and the pre-read address at X4 is equal to the value 1 (the change in the count value generated by the subtracting one count operation of the pre-read address counter_HB), the address offset between the pre-read address at X4 and the pre-read address at X3 is equal to the value 1 (the change in the count value generated by the subtracting one count operation of the pre-read address counter_HB), and the address offset between the pre-read address at X3 and the pre-read address at X1 is equal to the value 2 (the change in the count value generated by each self-decrement operation (minus two count) of the pre-read address counter_HB), wherein the order of the pre-read address at X4 is the middle pre-read address sequence number; i in Xi represents the pre-read address sequence number, and i is an integer.

[0115] Corresponding to Figure 4 In a 7-tap half-band filter, in the fourth filtering cycle, the number of to-be-filtered data written into the data buffer is not greater than the transposition enable count threshold of the currently multiplexed FIR filter, and the pre-address counter _HB starts to perform a decrement operation (minus two counts) on the pre-address read address from the pre-address read address where the data X7 is located (i.e., the initial pre-address sequence number 6), until the difference between half of the difference between the number of taps of the half-band filter and the value 1 and the value 1 is equal to twice the number of times the pre-address counter _HB performs the aforementioned decrement operation, that is, the change in the count value generated by the pre-address counter _HB performing the aforementioned decrement operation is equal to the value 2, and the pre-address counter _HB performs The number of the aforementioned self-decrement operations is 1. The pre-address counter _HB corresponds the currently obtained pre-read address number 4 to the pre-read address at X5, and then updates the difference between the currently obtained pre-read address number and the value 1 to the pre-read address number, that is, the value 3, corresponding to the pre-read address at X4, marked as the intermediate pre-read address number; then the intermediate pre-read address number is decremented by one to obtain the difference between the intermediate pre-read address number and the value 1, and the pre-read address at X3 is obtained. Then, the self-decrement operation (minus two counts) is started on the pre-read address at X3 to obtain the pre-read address at X1, completing a loop traversal of the data buffer.

[0116] On the basis of the above embodiment, the filtering calculation submodule is used to control the multiplication of the data to be filtered output by the data buffer and the filter coefficients of the same read order output by the filter coefficient memory when the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently reused FIR filter, and input the multiplication result into the adder for accumulation processing to obtain the processed filtering result within each filtering cycle; wherein, the multiplication operation within each filtering cycle is realized by time-sharing multiplexing of only one multiplier, thereby reducing the multiplier resources; wherein, the filtering calculation submodule includes an adder and a multiplier, and there is a method of performing multiplication first and then performing addition to achieve accumulation. Corresponding to Figure 4 , the filtering result y7 obtained in the fourth filtering cycle is equal to the sum of the product of X7 and h1, the product of X5 and h3, the product of X4 and h5, the product of X3 and h3, and the product of X1 and h1, then the number of multiplication operations in the fourth filtering cycle is equal to 5.

[0117] As a second embodiment of the half-band filter multiplexed as a half-band filter with a tap number equal to 7, the currently multiplexed FIR filter is the half-band filter; the tap number of the currently multiplexed FIR filter is an odd number. When the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is used to perform a self-decrement operation on the first folded read address according to the read timing corresponding to the currently multiplexed FIR filter in each filtering cycle, and then transmit the first folded read address after each self-decrement operation to the read-write control submodule through the first address selector to trigger the read-write control submodule to read the corresponding data to be filtered from the data buffer according to the first folded read address after each self-decrement operation. In this second embodiment, the filter type selection module includes a first folded address counter, combined with Figure 2It can be seen that, specifically, the first folding address counter _HB connected to the first address selector is enabled to operate when the filter type selection signal is at the second logic level. When the amount of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module updates the folding reference address sequence number to the starting address sequence number of the first folding read address, and the first folding address counter is used to perform a self-decrement operation on the first folding read address sequence number starting from the starting address sequence number of the first folding read address; if the filter type selection module determines that the first folding read address sequence number is decremented to the filtering starting address sequence number, the difference between the filtering target address sequence number and the value 1 is updated as the first folding read address sequence number; if the filter type selection module determines that the sum of the filtering starting address sequence number and the value 1 is equal to the first folding read address sequence number, the filtering target address sequence number is updated to the first folding read address sequence number; so that the first folding read address can be offset to a valid address interval in the new self-decrement operation, and obtain the data to be filtered within the address interval corresponding to the number of taps for the half-band filter, so that the first folding read address can achieve address loop traversal within the address range limited by the number of taps of the currently multiplexed FIR filter (the number of storage layers provided in the data buffer). The first folding read address sequence number represents the order of the first folding read address within the data buffer; the change in the count value generated by one decrement of the first folding address counter is 2, so that the change in the first folding read address sequence number generated by one self-increment operation is 2. It should be noted that the filtering target address sequence number is an address sequence number pre-configured within the data buffer, serving as the address sequence number of the address with the largest order among the addresses participating in the read operation within each filtering cycle. The filtering target address sequence number is greater than the filtering starting address sequence number, and the difference between the filtering target address sequence number and the filtering starting address sequence number is equal to the difference between the number of taps of the currently multiplexed FIR filter and the value 1. When the filtering starting address sequence number is set to 0, the filtering target address sequence number is set to the difference between the number of taps of the currently multiplexed FIR filter and the value 1; alternatively, when the filtering starting address sequence number is set to 1, the filtering target address sequence number is set to the number of taps of the currently multiplexed FIR filter. The first folding read address sequence number is used to represent the address order of the first folding read address within the data buffer.

[0118] It should be noted that, under the reading timing corresponding to the currently multiplexed FIR filter, a self-decrement operation is performed on the first folded read address every two consecutive system clock cycles to obtain a new first folded read address, and these two consecutive system clock cycles are recorded as the counting cycle of the first folded read address; when the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, under the control of the read-write control submodule, within the counting cycle of the first folded read address, the data to be filtered in the first folded read address is read to the filter calculation submodule, and the data to be filtered in the second folded read address is read to the filter calculation submodule; the reading is repeated until the data to be filtered of the first folded read address and the data to be filtered of the second folded read address limited in the current filtering cycle are read.

[0119] When the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is also used to perform a self-addition operation on the second folded read address according to the read timing corresponding to the currently multiplexed FIR filter within each filtering cycle, and then transmit the second folded read address after each self-addition operation to the read-write control sub-module through the second address selector to trigger the read-write control sub-module to read the corresponding data to be filtered from the data buffer according to the second folded read address after each self-addition operation.

[0120] In the above embodiment, the filter type selection module includes a second folding address counter, combined with Figure 2It can be seen that the second folding address counter _HB connected to the second address selector is specifically enabled to operate when the filter type selection signal is at the second logic level. The second folding address counter_HB is used to update the filtering starting address number to the folding reference address number before the filter type selection module determines that the folding reference address number is configured as the starting address number of the second folding read address. If the filter type selection module determines that the folding reference address number is equal to the filtering target address number, the filtering starting address number is updated to the folding reference address number, and then the sum of the folding reference address number and the value 1 is updated to the starting address number of the second folding read address, so as to avoid overlap with the starting address number of the first folding read address and avoid reading the same data to be filtered; then, the second folding address counter_HB is used to perform a self-increment operation on the second folding read address number starting from the starting address number of the second folding read address; wherein, the change value of the count value generated by the self-increment of the second folding address counter_HB is a value of 2, so that the change value generated by the second folding read address number in one self-increment operation is a value of 2, so as to achieve orderly shifting in the direction of the address offset different from the first folding read address. The data reading operation is performed on the basis of twice the sampling rate specified by the currently multiplexed half-band filter; if the filter type selection module determines that the second folded read address number after the self-increment operation is equal to the filter target address number, the sum of the filter starting address number and the value 1 is updated to the second folded read address number; if the filter type selection module determines that the second folded read address number after the self-increment operation is equal to the difference between the filter target address number and the value 1, the filter starting address number is updated to the second folded read address number; so that the second folded read address realizes address loop traversal within the address range limited by the number of taps of the currently multiplexed FIR filter; wherein, the change value of the count value generated by the self-increment of the second folded address counter is the value 2, so that the change value of the second folded read address number generated in one self-increment operation is the value 2; wherein, the second folded read address number is used to represent the address sorting of the second folded read address in the data buffer.

[0121] It should be noted that, under the reading timing corresponding to the currently multiplexed FIR filter, a self-decrement operation is performed on the first folded read address every two consecutive system clock cycles to obtain a new first folded read address, and these two consecutive system clock cycles are recorded as the counting cycle of the first folded read address; under the reading timing corresponding to the currently multiplexed FIR filter, a self-increment operation is performed on the second folded read address every two consecutive system clock cycles to obtain a new second folded read address, and these two consecutive system clock cycles are recorded as the counting cycle of the second folded read address; in the state where the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, under the control of the read-write control submodule, in the counting cycle of the first folded read address or Within a counting cycle of the second folding read address (equal to the sum of the cycle lengths of two system clock cycles), the data to be filtered at the first folding read address is read to the filter calculation submodule. Specifically, within the first system clock cycle, one data to be filtered at the first folding read address is read, and then the data to be filtered at the second folding read address is read to the filter calculation submodule. Specifically, within the second system clock cycle, one data to be filtered at the first folding read address is read, and this reading is repeated until the number of data to be filtered read within one filtering cycle is equal to the sum of half the sum of the number of taps of the currently multiplexed FIR filter and the value 1, and the value 1, which is equal to the sum of the number of data to be filtered at the first folding read address and the number of data to be filtered at the second folding read address that the half-band filter needs to read within the current filtering cycle. Then, within the next system clock cycle, one data to be filtered is read from the intermediate calculation cache address; wherein the intermediate calculation cache address is an address position between the most recently obtained second folding read address and the most recently obtained first folding read address. Therefore, within each counting cycle of the first folding read address or each counting cycle of the second folding read address, the address offset of the first folding read address sequence number corresponding to the read first folding read address relative to the filtering start address sequence number is equal to the address offset of the filtering target address sequence number relative to the second folding read address sequence number corresponding to the read second folding read address, so as to implement folding calculation for the to-be-filtered data at half of the second folding read addresses input into the filtering calculation submodule within a filtering cycle and the to-be-filtered data at the other half of the first folding read addresses, whose address positions are symmetrical. In some embodiments, the intermediate calculation cache address can be obtained by continuing to perform a self-increment operation to obtain the second folding read address, or by continuing to perform a self-decrement operation to obtain the first folding read address.In this embodiment, within the counting cycle of each first folding read address or the counting cycle of each second folding read address, the address offset of the first folding read address number corresponding to the read first folding read address relative to the filtering starting address number is equal to the address offset of the filtering target address number relative to the second folding read address number corresponding to the read second folding read address, forming an end-to-end symmetrical FIR filter structure centered on an intermediate address position, corresponding to. Figure 4 In the fifth filtering cycle, the number of taps is 7. According to the first folding read address and the second folding read address transmitted by the filter type selection module, the read-write control submodule first reads the ninth input data X9 (data at the first folding read address) and the third input data X3 (data at the second folding read address) to form a first pair of added parameters and send them to the filtering calculation submodule, wherein the address offset between the filtering target address sequence number and the address sequence number of the address where the ninth input data X9 is located (which may be an updated address sequence number with data already stored) is equal to the address offset between the address sequence number of the address where the third input data X3 is located and the filtering starting address sequence number; finally, the sixth input data X6 is read and sent to the filtering calculation submodule, triggering the filtering calculation submodule to complete the folding calculation of the data, so that the filter function implementation module completes the filtering calculation under the state that the number of the data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter.

[0122] It is worth noting that the number of taps of the currently multiplexed FIR filter is an odd number; within a filtering cycle, when the difference between the number of taps of the currently multiplexed FIR filter and twice the number of self-decrement operations performed on the first folded read address is less than twice the number of self-decrement operations performed on the first folded read address, the aforementioned self-decrement operation on the first folded read address is stopped; it is worth noting that the self-decrement operation here is that the count value reduced by the first folding address counter _HB in a self-decrement operation is a value of 2, resulting in the first folding address sequence number having an address offset of 2 in a self-decrement operation, and the currently obtained first folding address sequence number is relative to the last obtained first folding address sequence number. The folding address sequence number is decreased by a value of 2. Since, within a counting cycle of the first folding read address or a counting cycle of the second folding read address, the data to be filtered at the first folding read address and the data to be filtered at the second folding read address may be read sequentially, the difference between the number of taps of the currently multiplexed FIR filter and twice the number of self-addition operations is already greater than twice the number of self-addition operations performed on the second folding read address. To avoid repeatedly reading data from the same address without writing new data to be filtered, the self-addition operation on the second folding read address is stopped, causing the second folding read address to stop changing before the first folding read address. The sum of the currently obtained first folding read address sequence number and the value 1 is then updated to the first folding read address sequence number. The first folding read address sequence number is then maintained unchanged and used as the intermediate calculation cache address within the current filtering cycle, which is also the intermediate address position required for performing a filtering calculation.

[0123] Alternatively, within a filtering cycle, when the difference between the number of taps of the currently multiplexed FIR filter and twice the number of self-decrement operations performed on the first folded read address is greater than twice the number of self-decrement operations performed on the first folded read address, the self-decrement operation on the first folded read address is stopped; it is worth noting that the self-increment operation here is that the count value reduced by the second folding address counter _HB in a self-increment operation is a value of 2, resulting in the second folding address number having an address offset of 2 in a self-increment operation, and the currently obtained first folding address number is increased by a value of 2 relative to the first folding address number obtained last time. Because the data to be filtered at the first folding read address and the data to be filtered at the second folding read address may be read sequentially or simultaneously within a counting cycle of the first folding read address or a counting cycle of the second folding read address, the difference between the number of taps of the currently multiplexed FIR filter and twice the number of self-increment operations is already greater than twice the number of self-increment operations performed on the second folding read address. To avoid repeatedly reading data from the same address without writing new data to be filtered, the self-decrement operation on the first folding read address is stopped, causing the first folding read address to stop changing before the second folding read address. The difference between the currently obtained second folding read address sequence number and the value 1 is then updated as the second folding read address sequence number, which is then maintained unchanged and used as the intermediate calculation cache address within the current filtering cycle, also being the intermediate address position required for performing a filtering calculation.

[0124] As an example, Figure 4In the fifth filtering cycle, starting from the initial address sequence number 1, according to the system clock cycle limited by the number of taps of the currently multiplexed FIR filter, including the maximum reading time length supported by the number of taps, and reading one data to be filtered every other address, the first folded read address is decremented, and then the first folded read address after each decrement operation is transmitted to the read-write control submodule through the first address selector. Then, every time the read-write control submodule receives the first folded read address obtained by a decrement operation from the filter type selection module, the data to be filtered in the corresponding first folded read address is read from the data buffer, which are X9 and X7 in the ninth row box respectively. At this time, the number of decrement operations is 1, and the data to be filtered in the two first folded read addresses are obtained, which belong to the data to be filtered in the two addresses separated by one address; at the same time, the Each time the read-write control submodule receives a second folded read address obtained by a self-addition operation from the filter type selection module, the data to be filtered in the corresponding second folded read address is read from the data buffer, which is X3 and X5 in the ninth row box. At this time, the number of self-addition operations is 1, and the data to be filtered in the two second folded read addresses are obtained; then the address number of X7 is subtracted by 1, or the address number of X5 is added by 1 to obtain the address number corresponding to the sixth input data X6, and then the data reading is stopped. The address number corresponding to the data X6 is used as the intermediate calculation cache address in the current filtering cycle and is sorted in the address of the data buffer. At this time, the data to be filtered in the first folded read address and the data to be filtered in the second folded read address have met the filtering calculation matching the number of taps of the currently multiplexed FIR filter.

[0125] As a third embodiment of the half-band filter multiplexed with a tap number equal to 7, when the amount of to-be-filtered data written into the data buffer is greater than the transpose enable count threshold of the currently multiplexed FIR filter, the filter coefficient memory is used to, within each filtering cycle, start from the starting storage address matching the currently multiplexed FIR filter and perform a self-increment operation on the starting storage address once every two system clock cycles, so that the address sequence number corresponding to the starting storage address is incremented by two every two system clock cycles, and then read the corresponding stored filter coefficients sequentially to the filter calculation submodule according to the storage address obtained by self-increment until the address offset of the storage address obtained by self-increment relative to the starting storage address is equal to half of the sum of the tap number of the currently multiplexed FIR filter and the value 1, and then the latest obtained storage address is recorded as the intermediate calculation storage address; in this embodiment, the intermediate calculation storage address is set in the filter coefficient memory, and is used to store the address of the filter coefficient matching the currently multiplexed FIR filter, the address with the largest sort order, that is, the tail address of the address interval storing the corresponding filter coefficient. Among them, in the process of performing a self-increment operation on the starting storage address, each time the self-increment operation is performed, the address serial number corresponding to the storage address increases by a value of 2. Then, in the filter coefficient memory, except for the intermediate calculation storage address, there are even-numbered addresses that are not read and participate in the filtering calculation. In this embodiment, the filter coefficient is not written at the corresponding even-numbered addresses. Compared with the prior art, the even-numbered addresses except the intermediate calculation storage address do not need to store data, saving some storage space.

[0126] In this third embodiment, the starting storage address is selected and determined by the filter type selection module to match the currently multiplexed FIR filter; wherein the address sequence number corresponding to the storage address is used to indicate the address order of the storage address in the filter coefficient memory; and the number of taps of the currently multiplexed FIR filter is an odd number. Specifically, the address counter provided within the filter coefficient memory or the address counter designed within the read / write control submodule counts the address sequence number corresponding to the starting storage address by adding two every two system clock cycles and generates a corresponding address sequence number, and is configured as a storage address that changes simultaneously with the first folding read address and the second folding read address read within a counting cycle of a first folding read address or a counting cycle of each second folding read address. The filter coefficient in the storage address and the data to be filtered in the first folding read address and the second folding read address within the counting cycle of the first folding read address are read into the filter calculation submodule within the same counting cycle of the first folding read address, forming a set of calculation items that are first added and then multiplied, that is, the sum of the data to be filtered in the first folding read address and the second folding read address is multiplied by the filter coefficient. In this embodiment, there is no need to perform a self-decrement operation on the starting storage address. In the case where the number of data to be filtered written into the data buffer is less than or equal to the transpose enable count threshold of the currently multiplexed FIR filter, there is no need to loop back on the storage address, thereby saving the amount of reading operations.

[0127] The filtering calculation submodule is used to, when the amount of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, first control the data to be filtered in the first folding read address output by the data buffer to be added with the data to be filtered in the second folding read address output by the data buffer in each counting cycle of the first folding read address or each counting cycle of the second folding read address; then multiply the result of the addition with the filter coefficient of the same read order output by the filter coefficient memory; then input the multiplication result into the adder for accumulation processing, and repeat this process in each filtering cycle until, in a corresponding filtering cycle, when the filter coefficient memory outputs the filter coefficient in the intermediate calculation storage address, multiply the filter coefficient in the intermediate calculation storage address with the data to be filtered in the first folding read address output by the data buffer under the same read order, and then input the multiplication result into the adder for accumulation processing to obtain the processed filtering result in the corresponding filtering cycle, thereby completing one filtering calculation, that is, completing the filtering calculation in one filtering cycle. In each filtering cycle, the number of multiplication operations is equal to half of the difference between the number of taps of the currently reused FIR filter and the value 1, and is implemented by a multiplier in time-sharing multiplexing. In the filtering calculation submodule, the adder and the multiplier are included; the transposition enable count threshold of the currently reused FIR filter is equal to the number of taps of the currently reused FIR filter. Corresponding to Figure 4In the fifth filtering cycle, X9 (the data to be filtered in the first folding read address read for the first time, i.e., the data to be filtered read for the first time) and X3 (the data to be filtered in the second folding read address read for the first time, i.e., the data to be filtered read for the second time) are a set of folding data, which are added together to obtain a first folding value. At the same time, the filter coefficient h1 is read from the filter coefficient memory; then, X7 (the data to be filtered in the first folding read address read for the second time, i.e., the data to be filtered read for the third time) and X5 (the data to be filtered in the second folding read address read for the second time, i.e., the data to be filtered read for the fourth time) are another set of folding data, which are added together to obtain a second folding value. At the same time, the filter coefficient h3 is read from the filter coefficient memory; then, the filter coefficient h5 in the intermediate calculation storage address is read from the filter coefficient memory. Generally, the filter coefficient in the intermediate calculation storage address is set to a fixed parameter, which is applicable to any FIR filter with an odd number of taps, and is read from the intermediate calculation of the data buffer. X6 (the data to be filtered read for the fifth time) is read out from the cache address; for these folded data, the filtering calculation submodule outputs the filter coefficients at the corresponding positions from the filter coefficient memory for multiplication to perform folding calculation. Specifically, the filtering result y9 obtained by the folding calculation is equal to: the product of the sum of X9 (the data to be filtered in the first folding read address read for the first time, that is, the data to be filtered read for the first time) and X3 (the data to be filtered in the second folding read address read for the first time, that is, the data to be filtered read for the second time) and the filter coefficient h1 read for the first time, the product of the sum of X7 (the data to be filtered in the first folding read address read for the second time, that is, the data to be filtered read for the third time) and X5 (the data to be filtered in the second folding read address read for the second time, that is, the data to be filtered read for the fourth time) and the filter coefficient h3 read for the second time, and the sum of X6 (the data to be filtered in the first folding read address read for the third time, that is, the data to be filtered read for the fifth time) and the filter coefficient h5 read for the third time. Therefore, compared with the aforementioned embodiment in which a non-half-band filter with 5 taps is multiplexed, after being multiplexed into a half-band filter with 7 taps, the filtering calculation submodule uses fewer multipliers and adders, has a smaller amount of calculation, and can use the same amount of multiplication operations to complete more data to be filtered.

[0128] It should be noted that, in view of the implementation process of the above modules of the present invention, an overall system structure is formed in a specific application, such as; Figure 3 and Figure 4 The 5-tap FIR filter is taken as an example. By analogy, the designs of filters with other odd taps are the same and all fall within the scope of protection of the present invention.

[0129] In summary, the present invention can pre-configure filter coefficients that meet design indicators, and design an FIR filter with M-order symmetrical coefficients in combination with the filter type selection module and the filter function implementation module, which can ensure that its phase characteristics are linear within the filter response passband, and its output under a specific filtering cycle is related to the latest M+1 input values, wherein the bit width and number of the filter coefficients, and the bit width and number of the signals to be filtered can be selected accordingly according to the hardware resource capabilities. Compared with the traditional digital filter implementation method, the filtering accuracy of the present invention is adjustable. Wherein, M is an even number; the present invention stores the M-order symmetric coefficients of the half-band filter and the non-half-band filter in a memory. When performing filtering calculations, it is only necessary to read the filter coefficients in the memory according to the address mapping, and to multiply and accumulate the input data to be filtered and the filter coefficients to complete filtering and output a signal. In particular, when the amount of input data to be filtered is large enough, a folding calculation can be performed on the input data to be filtered for an FIR filter with an M-order symmetric coefficient (pre-addition processing is performed according to the principle of coefficient symmetry to realize a transposed filter calculation structure of adding first and then multiplying). Except for the filter coefficients at the intermediate calculation storage address, the amount of calculation is relatively reduced by half;

[0130] In addition, the filter coefficients that meet the design indicators can be determined in advance by using Matlab tools or through register configuration. When the filtering requirements are different, there is no need to change the structure of the entire filter to adapt to the filter logic with different functions and performances selected by the filter type selection module.

[0131] Moreover, the present invention uses the same multiplier resources in the filtering calculation submodule to realize the multiplication operation of the newly input to-be-filtered data under different filtering cycles and the same set of filter coefficients, thereby improving the reuse rate of the multiplier resources under the condition of different types of filters reading data.

[0132] It should be noted that the self-increment operation of the counter disclosed in the present invention is an addition counting operation of the counter, including but not limited to adding one or adding two. Each time the counter performs a self-increment operation, its count value increases by a certain value, and the count values ​​before and after the change are configured as addresses; the self-decrement operation of the counter is a subtraction counting operation of the counter. Each time the counter performs a self-decrement operation, its count value decreases by a certain value; therefore, the self-increment operation and the self-decrement operation of a counter generate addresses along different directions respectively.

[0133] On the basis of the above embodiment, an embodiment of writing the data to be filtered into the data buffer is also disclosed, wherein the read-write control submodule is used to control the writing of the external input data to be filtered into the data buffer according to the system clock cycle, specifically writing one data to be filtered into the data buffer in each system clock cycle, so that the above embodiment has an implementation condition for judging the relationship between the number of data to be filtered written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter. In this embodiment, the read-write control submodule is configured to write one data to be filtered in the current system clock cycle and read one data to be filtered in the next system clock cycle. Therefore, the read-write control submodule reads the data to be filtered written into the data buffer in sequence according to the pre-address read address selected and output by the pre-address selector, the first folded read address selected and output by the first address selector, and the second folded read address selected and output by the second address selector.

[0134] It should be noted that no matter what the type of the currently multiplexed FIR filter is, the write content controlled by the read / write control submodule is the same, and shares a set of write addresses, write data, and write enable.

[0135] Furthermore, an incremental counter is provided inside the read-write control submodule, and the read-write control submodule is used to control the incremental counter to add an offset to the current cache address each time a data to be filtered is written, so as to obtain the cache address of the next data to be filtered to be written, that is, the address sequence number of the cache address is counted by one from the cache head address according to the system clock cycle until the address offset of the currently obtained cache address relative to the cache head address is equal to the difference between the number of taps of the currently multiplexed FIR filter and the value 1, and the cache head address is updated to the currently obtained Cache address, so that the subsequently written data to be filtered overwrites the data to be filtered originally stored in the cache first address, and determines that a round of continuous cache address traversal of the data cache is completed, that is, a loop traversal is completed. At this time, it is determined that the number of system clock cycles that have passed since writing a data to be filtered to the cache first address is equal to the number of taps of the currently multiplexed FIR filter; wherein, the continuous cache address is composed of address units whose number is the number of taps of the currently multiplexed FIR filter, so as to meet the calculation quantity requirement of the input data required by the number of taps of the currently multiplexed FIR filter. It is worth noting that the cache address mentioned in this embodiment is not necessarily read by the read-write control submodule in the aforementioned embodiment, especially when the currently multiplexed FIR filter is a half-band filter, data reading is only performed by spacing one address every time a system clock cycle passes.

[0136] Specifically, the read-write control submodule is further configured to, after completing a round of traversal of continuous cache addresses, set the incremental counter to an incremental initial value if new data to be filtered is continued to be written to the continuous cache addresses according to the system clock cycle control, and start from the cache first address, each time a data to be filtered is written, overwrite the data to be filtered originally stored in the cache address with the currently written data to be filtered, and control the incremental counter to add an offset to the current cache address, that is, the incremental counter counts by one and configures the obtained count value as a new cache address, thereby obtaining the cache address of the next data to be filtered to be written. Thus, the cache address of the next data to be written to be filtered is obtained, until the address offset of the currently obtained cache address relative to the cache first address is equal to the difference between the number of taps of the currently multiplexed FIR filter and the value 1, the cache first address is updated to the currently obtained cache address, and the count value of the incremental counter is adjusted to the incremental initial value; wherein, the incremental initial value set by the incremental counter represents the address sorting of the cache first address in the data buffer; each count value generated by the incremental counter represents the address sorting of the cache address written in the corresponding system clock cycle in the data buffer.

[0137] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any equivalent changes or modifications made based on the spirit and essence of the present invention are intended to be covered by the scope of protection of the present invention.

Claims

1. FIR filter multiplexing system, characterized in that, The FIR filter multiplexing system includes a filter type selection module and a filter function implementation module; the filter function implementation module includes a read-write control submodule, a filter calculation submodule, a data buffer and a filter coefficient memory; The filter type selection module is pre-configured with the number of taps and decimation rate of the FIR filter to be reused, and is also used to generate the associated read addresses in the currently reused FIR filter and transmit these associated read addresses to the read-write control submodule; wherein the FIR filter to be reused includes a half-band filter and a non-half-band filter, and the non-half-band filter is a type of FIR filter other than the half-band filter; a read / write control submodule, configured to control the writing of the to-be-filtered data input into the FIR filter multiplexing system into the data buffer, and, based on the relationship between the amount of to-be-filtered data written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter, to sequentially read the to-be-filtered data from the data buffer and provide it to the filter calculation submodule using the associated read addresses provided by the filter type selection module; a filter calculation submodule, configured to control the filtering calculation of the to-be-filtered data output by the data buffer and the filter coefficients output by the filter coefficient memory, wherein the filtering calculation is adapted to the FIR filter currently reused by the FIR filter reuse system, so that the filter function realization module is reused as the currently reused FIR filter; a filter coefficient memory for storing filter coefficients required by the currently multiplexed FIR filter, and after the read-write control submodule starts reading the to-be-filtered data from the data buffer, sequentially outputting the required filter coefficients to the filter calculation submodule starting from the starting storage address corresponding to the currently multiplexed FIR filter in the order in which the read-write control submodule reads the to-be-filtered data from the data buffer, wherein the filter coefficients required by each type of FIR filter have matching starting storage addresses in the filter coefficient memory; The filter type selection module includes a pre-address selector and an address enable signal selector; a pre-address selector for selecting, after receiving a filter type selection signal, a pre-address read address corresponding to the currently multiplexed FIR filter and transmitting it to the filter function implementation module, so that when the amount of data to be filtered written into the data buffer is less than or equal to a transposition enable count threshold of the currently multiplexed FIR filter, the read / write control submodule reads the data to be filtered from the pre-address read address of the data buffer according to a read timing corresponding to the currently multiplexed FIR filter; An address enable signal selector is used to select a folding read enable signal corresponding to the currently multiplexed FIR filter and transmit it to the filter function implementation module after receiving a filter type selection signal; Among them, when the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the folding read enable signal is a high level; when the number of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the folding read enable signal is a low level.

2. The FIR filter multiplexing system according to claim 1, characterized in that: The filter type selection module further includes a first address selector and a second address selector; a first address selector, configured to, after receiving a filter type selection signal, select a first folding read address corresponding to the currently multiplexed FIR filter and transmit it to the filter function implementation module, so that after the amount of to-be-filtered data written into the data buffer is greater than a transposition enable count threshold of the currently multiplexed FIR filter, the read / write control submodule reads the to-be-filtered data in the first folding read address from the data buffer according to a read timing corresponding to the currently multiplexed FIR filter; a second address selector, configured to, after receiving a filter type selection signal, select a second folding read address corresponding to the currently multiplexed FIR filter and transmit it to the filter function implementation module, so that after the amount of to-be-filtered data written into the data buffer is greater than a transposition enable count threshold of the currently multiplexed FIR filter, the read / write control submodule reads the to-be-filtered data in the second folding read address from the data buffer according to a read timing corresponding to the currently multiplexed FIR filter; The address offset between the starting address serial number of the second folded read address and the starting address serial number of the first folded read address is equal to the decimation rate of the currently multiplexed FIR filter; the number of taps of the currently multiplexed FIR filter is configured by a dedicated register; The associated read addresses include a pre-read address, a second folded read address, and a first folded read address.

3. The FIR filter multiplexing system according to claim 2, characterized in that: The FIR filter multiplexing system is also provided with a system read and write clock source for counting and generating system clock cycles; The time taken to write one piece of data to be filtered is configured as one system clock cycle, and the time taken to read one piece of data to be filtered is configured as one system clock cycle; The amount of the to-be-filtered data written into the data buffer is equal to the amount of the to-be-filtered data sampled from the outside by the FIR filter multiplexing system.

4. The FIR filter multiplexing system according to claim 3, characterized in that: The filter function implementation module also includes a filter counter; a filter counter, configured to increment the counter by one each time two pieces of to-be-filtered data are written externally into the data buffer, thereby triggering the filter calculation submodule to perform a filter calculation adapted to the currently multiplexed FIR filter using the to-be-filtered data read from the data buffer, and determining, when the filter calculation submodule calculates a corresponding filter result, that the FIR filter multiplexing system has passed a filter cycle, wherein a filter cycle is greater than two system clock cycles; and outputting a filter result each time a filter cycle has passed; Wherein, the decimation rate of the currently multiplexed FIR filter is 2 times; The bit width of each to-be-filtered data written into the data buffer is configured by the filter type selection module, and the bit width occupied by each to-be-filtered data is less than or equal to the maximum bit width allowed to be read and written by the data buffer.

5. The FIR filter multiplexing system according to claim 4, characterized in that: When the amount of to-be-filtered data written into the data buffer is represented by a change in the count value of the filter counter, the transposition enable count threshold of the currently multiplexed FIR filter is represented by half the sum of the number of taps of the currently multiplexed FIR filter and a value of 1; The number of taps of the currently multiplexed FIR filter is an odd number.

6. The FIR filter multiplexing system according to claim 4, characterized in that: The method of sequentially reading the data to be filtered from the data buffer and providing it to the filter calculation submodule using the associated read addresses provided by the filter type selection module according to the relationship between the amount of the data to be filtered written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter includes: In a state where the read-write control submodule determines that the amount of data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the read-write control submodule sequentially reads the data to be filtered in the pre-read address from the data buffer in each filtering cycle according to the read timing corresponding to the currently multiplexed FIR filter, and transmits the data to be filtered to the filter calculation submodule; wherein the transposition enable count threshold of the currently multiplexed FIR filter is equal to the number of taps of the currently multiplexed FIR filter; The pre-read address is obtained by counting from an initial pre-address sequence number in each filtering cycle; an initial pre-address sequence number in each filtering cycle is a pre-read address sequence number that first participates in a reading operation in the filtering cycle, so that the data to be filtered in the pre-read address corresponding to the initial pre-address sequence number is transmitted to the filtering calculation submodule according to the corresponding reading timing; Wherein, when the filter type selection signal is at a first logic level, the currently multiplexed FIR filter is the non-half-band filter, so that the FIR filter multiplexing system multiplexes the non-half-band filter; When the filter type selection signal is at the second logic level, the currently multiplexed FIR filter is the half-band filter, so that the FIR filter multiplexing system multiplexes into the half-band filter.

7. The FIR filter multiplexing system according to claim 6, characterized in that: In a state where the amount of to-be-filtered data written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the read-write control submodule sets the difference between twice the change value of the count value of the filter counter in each filtering cycle relative to its initial count value and the value 2 as the initial pre-address sequence number in the corresponding filtering cycle; The address offset between the initial pre-addresses obtained in two adjacent filtering cycles is equal to the decimation rate of the currently multiplexed FIR filter; and the initial count value of the filter counter is a count value set before counting begins.

8. The FIR filter multiplexing system according to claim 6, characterized in that: If the currently multiplexed FIR filter is the non-half-band filter, and the number of to-be-filtered data written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the pre-address counter is used to perform a self-decrement operation according to the system clock cycle starting from the initial pre-address sequence number corresponding to the current filtering cycle, and transmit the pre-address after each self-decrement operation to the filter function implementation module through the pre-address selector, so as to trigger the read-write control submodule to read the to-be-filtered data in the pre-address after each self-decrement operation from the data buffer, and then transmit the data to the filter calculation submodule in sequence; Wherein, the filter type selection module includes a pre-address counter, which is used to operate when the filter type selection signal is at a first logic level; Among them, each time the pre-address counter decrements once, the corresponding count value change is 1, and the count value generated after each decrement operation is configured as the pre-address read address number; the initial count value set by the pre-address counter is the initial pre-address number.

9. The FIR filter multiplexing system according to claim 8, characterized in that: If the currently multiplexed FIR filter is the non-half-band filter, then in the state where the number of to-be-filtered data written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address that matches the currently multiplexed FIR filter, perform a self-add operation on the starting storage address according to the system clock cycle, and then read the corresponding stored filter coefficients to the filtering calculation submodule in sequence according to the storage address obtained by self-addition, until the address offset of the storage address obtained by self-addition relative to the starting storage address is equal to the address of the currently multiplexed FIR filter. half of the difference between the number of taps of the filter and the value 1, then record the latest storage address as the intermediate calculation storage address, perform a self-decrement operation on the intermediate calculation storage address, and then read the corresponding stored filter coefficients to the filtering calculation submodule in sequence according to the storage address obtained by self-decrement, until the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1, and repeat in sequence until the number of filter coefficients read from the filter coefficient memory in the current filtering cycle meets the number of data to be filtered participating in the filtering calculation in the current filtering cycle; In the process of performing the self-increment operation on the starting storage address, the address sequence number corresponding to the storage address increases by 1 each time the self-increment operation is performed; in the process of performing the self-decrement operation on the intermediate calculation storage address, the address sequence number corresponding to the storage address decreases by 1 each time the self-decrement operation is performed; The address serial number corresponding to the storage address is used to indicate the address order of the storage address in the filter coefficient memory; and the number of taps of the currently multiplexed FIR filter is an odd number.

10. The FIR filter multiplexing system according to claim 9, characterized in that: The filtering calculation submodule is used to control the multiplication of the data to be filtered output by the data buffer and the filter coefficients of the same read order output by the filter coefficient memory when the number of the data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, and input the result into the adder for accumulation processing to obtain the processed filtering result within each filtering cycle; Among them, the multiplication operation in each filtering cycle is realized by time-sharing multiplexing of a multiplier; Wherein, the filtering calculation submodule includes an adder and a multiplier.

11. The FIR filter multiplexing system according to claim 4, characterized in that: The read-write control submodule further includes a reference address counter; the reference address counter is configured to perform a self-increment operation on a count value whenever two pieces of to-be-filtered data are externally written into the data buffer to trigger the filtering calculation submodule to start performing a filtering calculation, configure the count value obtained by the self-increment operation as a folding reference address sequence number, transmit the folding reference address sequence number obtained after the self-increment operation to the filter type selection module, update the folding reference address sequence number to a first folding read address sequence number, and update the sum of the folding reference address sequence number and a value of 1 to a second folding read address sequence number; The change in the count value generated by the reference address counter in one self-increment operation is 2; the transposition enable count threshold of the currently multiplexed FIR filter is equal to the number of taps of the currently multiplexed FIR filter; Among them, the folding base address serial number represents the order of the folding base address in the data buffer; the second folding read address serial number is used to represent the address order of the second folding read address in the data buffer; the first folding read address serial number is used to represent the address order of the first folding read address in the data buffer.

12. The FIR filter multiplexing system according to claim 11, characterized in that: When the count value of the reference address counter is the difference between the number of taps of the currently multiplexed FIR filter and the value 2, the read-write control submodule updates the filter starting address sequence number to the count value currently obtained by the reference address counter in the next system clock cycle, and updates the filter starting address sequence number to the folding reference address sequence number, and then transmits the updated folding reference address sequence number to the filter type selection module; When the count value of the reference address counter is the difference between the number of taps of the currently multiplexed FIR filter and the value 1, the read-write control submodule updates the sum of the filter starting address sequence number and the value 1 to the count value currently obtained by the reference address counter in the next system clock cycle, and updates the sum of the filter starting address sequence number and the value 1 to the folded reference address sequence number; The filtering starting point address number is an address number pre-configured in the data buffer, and serves as the smallest address number among the address numbers participating in the reading operation in each filtering cycle.

13. The FIR filter multiplexing system according to claim 12, characterized in that: The method of sequentially reading the data to be filtered from the data buffer and providing it to the filter calculation submodule using the associated read addresses provided by the filter type selection module according to the relationship between the amount of the data to be filtered written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter includes: In a state where the amount of to-be-filtered data written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is configured to, within each filtering cycle, perform a decrement operation on the first folding read address according to a read timing corresponding to the currently multiplexed FIR filter, and then transmit the first folding read address after each decrement operation to the read-write control submodule through the first address selector, so as to trigger the read-write control submodule to read the to-be-filtered data in the first folding read address after each decrement operation from the data buffer, until the number of decrement operations reaches a first preset folding sampling number; In a state where the amount of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is further configured to perform a self-addition operation on the second folded read address according to a read timing corresponding to the currently multiplexed FIR filter within each filtering cycle, and then transmit the second folded read address after each self-addition operation to the read-write control submodule through the second address selector to trigger the read-write control submodule to read the data to be filtered in the second folded read address after each self-addition operation from the data buffer until the number of self-addition operations reaches a second preset folded sampling number; The currently multiplexed FIR filter is the non-half-band filter.

14. The FIR filter multiplexing system according to claim 13, characterized in that: The number of taps of the currently multiplexed FIR filter is an odd number; the transposition enable count threshold of the FIR filter is equal to the number of taps of the FIR filter; When the second preset folding sampling number is greater than the first preset folding sampling number, the difference between half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1 and the value 1 is equal to the first preset folding sampling number, and half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1 is equal to the second preset folding sampling number, so that the first folding read address stops changing in advance of the second folding read address; or, when the second preset folding sampling number is less than the first preset folding sampling number, the difference between half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1 and the value 1 is equal to the second preset folding sampling number, and half of the difference between the number of taps of the currently multiplexed FIR filter and the value 1 is equal to the first preset folding sampling number, so that the second folding read address stops changing in advance of the first folding read address.

15. The FIR filter multiplexing system according to claim 14, characterized in that: The filter type selection module includes a first folding address counter and a second folding address counter, configured to operate when the filter type selection signal is at a first logic level; Before the filter type selection module determines to configure the folding reference address sequence number as the starting address sequence number of the first folding read address, if the filter type selection module determines that the folding reference address sequence number is equal to the filtering starting address sequence number, the filtering target address sequence number is updated to the folding reference address sequence number, and then the updated folding reference address sequence number is updated to the starting address sequence number of the first folding read address, and then the first folding address counter is used to perform a self-decrement operation on the first folding read address sequence number starting from the starting address sequence number of the first folding read address; wherein the first folding read address sequence number represents the order of the first folding read address in the data buffer; the change value of the count value generated by the first folding address counter being decremented once is a value of 1, so that the change value of the first folding read address sequence number generated in the self-decrement operation is a value of 1; Before the filter type selection module determines to configure the folding reference address sequence number as the starting address sequence number of the second folding read address, if the filter type selection module determines that the folding reference address sequence number is equal to the filtering target address sequence number, the filtering starting address sequence number is updated to the folding reference address sequence number, and then the sum of the folding reference address sequence number and the value 1 is updated as the starting address sequence number of the second folding read address; then, the second folding address counter is used to perform a self-increment operation on the second folding read address sequence number starting from the starting address sequence number of the second folding read address, wherein the change value of the count value generated by the self-increment of the second folding address counter once is the value 1, so that the change value of the second folding read address sequence number generated in the self-increment operation is the value 1; Among them, the filtering target address sequence number is an address sequence number pre-configured in the data buffer, which is the address sequence number with the largest ranking among the addresses participating in the read operation in each filtering cycle; the difference between the filtering target address sequence number and the filtering starting address sequence number is equal to the difference between the number of taps of the currently multiplexed FIR filter and the value 1.

16. The FIR filter multiplexing system according to claim 15, characterized in that: The process of the first folding address counter performing a self-decrement operation on the first folding read address sequence number includes: configuring the starting address sequence number of the first folding read address as the first folding read address sequence number, and whenever the first folding read address sequence number is decremented to the filtering starting address sequence number, updating the filtering target address sequence number to the first folding read address sequence number in the next system clock cycle, so that the first folding read address implements address loop traversal within the address range limited by the number of taps of the currently multiplexed FIR filter; and then the first folding address counter continues to perform a self-decrement operation on the first folding read address sequence number; The process of the second folding address counter performing a self-increment operation on the second folding read address sequence number includes: configuring the starting address sequence number of the second folding read address as the second folding read address sequence number, and whenever the second folding read address sequence number is self-added to the filtering target address sequence number, updating the filtering starting address sequence number to the second folding read address sequence number within the next system clock cycle, so that the second folding read address realizes address loop traversal within the address range limited by the number of taps of the currently multiplexed FIR filter; then the second folding address counter continues to perform a self-increment operation on the second folding read address sequence number.

17. The FIR filter multiplexing system according to claim 16, characterized in that: Under the read timing corresponding to the currently multiplexed FIR filter, a decrement operation is performed on the first folding read address every two system clock cycles to obtain a new first folding read address, and these two system clock cycles are recorded as a counting period of the first folding read address; Under the read timing corresponding to the currently multiplexed FIR filter, a self-increment operation is performed on the second folded read address every two system clock cycles to obtain a new second folded read address, and these two system clock cycles are recorded as a counting period of the second folded read address; In a state where the amount of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, under the control of the read-write control submodule, within a counting cycle of the first folded read address or a counting cycle of the second folded read address, the data to be filtered in the first folded read address is read to the filter calculation submodule, and the data to be filtered in the second folded read address is read to the filter calculation submodule, and the reading is repeated until the amount of data to be filtered read within one filtering cycle is equal to the number of taps of the currently multiplexed FIR filter; Among them, within the counting cycle of each first folding read address or the counting cycle of each second folding read address, the address offset of the first folding read address serial number corresponding to the read first folding read address relative to the filtering starting point address serial number is equal to the address offset of the filtering target address serial number relative to the second folding read address serial number corresponding to the read second folding read address.

18. The FIR filter multiplexing system according to claim 17, characterized in that: In a state where the amount of to-be-filtered data written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter coefficient memory is used to, within each filtering cycle, start from a starting storage address that matches the currently multiplexed FIR filter, and perform a self-addition operation on the starting storage address once every two system clock cycles, and then read the corresponding stored filter coefficients to the filtering calculation submodule in sequence according to the storage address obtained by self-addition, until the address offset of the storage address obtained by self-addition relative to the starting storage address is equal to half of the difference between the number of taps of the currently multiplexed FIR filter and a value of 1, and then record the latest obtained storage address as the intermediate calculation storage address; Wherein, in the process of performing the self-increment operation on the starting storage address, the address sequence number corresponding to the storage address increases by 1 each time the self-increment is performed; the starting storage address is selected and determined by the filter type selection module to match the currently multiplexed FIR filter; The address serial number corresponding to the storage address is used to indicate the address order of the storage address in the filter coefficient memory; and the number of taps of the currently multiplexed FIR filter is an odd number.

19. The FIR filter multiplexing system according to claim 6, characterized in that: If the currently multiplexed FIR filter is the half-band filter, and the number of to-be-filtered data written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, the pre-address counter is used to start from the initial pre-address sequence number corresponding to the current filtering cycle, and perform a self-decrement operation according to the system clock cycle to obtain a new pre-address read address, and the pre-address read address after each self-decrement operation is handed over to the pre-address selector for transmission to the filter function implementation module, so as to trigger the read-write control submodule to read the to-be-filtered data in the pre-address after each self-decrement operation from the data buffer, and then transmit it to the filter calculation submodule in sequence until the latest pre-address read address sequence number obtained is a value of 1 or a value of 0; The filter type selection module includes a pre-address counter, configured to operate when the filter type selection signal is at a second logic level; Among them, each time the pre-address counter decrements once, the corresponding count value change is 2, and the count value generated after each decrement operation is configured as the pre-address read address number; the initial count value set by the pre-address counter is the initial pre-address number.

20. The FIR filter multiplexing system according to claim 19, characterized in that: In one filtering cycle, when the difference between half of the difference between the number of taps of the half-band filter and the value 1 and the value 1 is equal to twice the number of times the pre-address counter performs the aforementioned decrement operation, the pre-address counter updates the difference between the currently obtained pre-address read address sequence number and the value 1 as the pre-address read address sequence number, allows the read-write control submodule to read the data to be filtered in the pre-address read address sequence number, and marks the pre-address read address sequence number as the intermediate pre-address read address sequence number; The pre-address counter is used to, after obtaining the intermediate pre-read address sequence number, continue to perform a self-decrement operation starting from the difference between the intermediate pre-read address sequence number and the value 1 to obtain a new pre-read address; wherein, the difference between the intermediate pre-read address sequence number and the value 1 is allowed to be updated as the pre-read address sequence number.

21. The FIR filter multiplexing system according to claim 20, characterized in that: If the currently reused FIR filter is the half-band filter, then in the state where the number of to-be-filtered data written into the data buffer is less than or equal to the transposition enable count threshold of the currently reused FIR filter, the filter coefficient memory is used to, in each filtering cycle, start from the starting storage address that matches the currently reused FIR filter, perform a self-add operation on the starting storage address according to the system clock cycle, and then read the corresponding stored filter coefficients to the filtering calculation submodule in sequence according to the storage address obtained by self-addition, until the address offset of the storage address obtained by self-addition relative to the starting storage address is equal to the address of the currently reused FIR filter. half of the sum of the number of taps of the filter and the value 1, then record the latest storage address as the intermediate calculation storage address, then perform a self-decrement operation on the intermediate calculation storage address, and then read the corresponding stored filter coefficients to the filter calculation submodule in sequence according to the storage address obtained by self-decrement, until the address offset of the storage address obtained by self-decrement relative to the intermediate calculation storage address is equal to half of the sum of the number of taps of the currently multiplexed FIR filter and the value 1, and repeat in sequence until the number of filter coefficients output from the filter coefficient memory in the current filtering cycle is equal to the number of data to be filtered read in the current filtering cycle; Wherein, in the process of performing the self-increment operation on the starting storage address, each time the self-increment operation is performed, the address sequence number corresponding to the storage address increases by 2; in the process of performing the self-decrement operation on the starting storage address, each time the self-decrement operation is performed, the address sequence number corresponding to the storage address decreases by 2; The address sequence number corresponding to the storage address represents the address order of the storage address in the filter coefficient memory; and the number of taps of the currently multiplexed FIR filter is an odd number.

22. The FIR filter multiplexing system according to claim 21, characterized in that: The filtering calculation submodule is used to control the multiplication of the data to be filtered output by the data buffer and the filter coefficients of the same read order output by the filter coefficient memory when the number of the data to be filtered written into the data buffer is less than or equal to the transposition enable count threshold of the currently multiplexed FIR filter, and input the result into the adder for accumulation processing to obtain the processed filtering result within each filtering cycle; The number of taps of the currently multiplexed FIR filter is an odd number, and the multiplication operation in each filtering cycle is implemented by a multiplier in time-sharing multiplexing; Wherein, the filtering calculation submodule includes an adder and a multiplier.

23. The FIR filter multiplexing system according to claim 12, characterized in that: The method of sequentially reading the data to be filtered from the data buffer and providing it to the filter calculation submodule using the associated read addresses provided by the filter type selection module according to the relationship between the amount of the data to be filtered written into the data buffer and the transposition enable count threshold of the currently multiplexed FIR filter includes: When the amount of the to-be-filtered data written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is configured to, within each filtering cycle, perform a self-decrement operation on the first folded read address according to the read timing corresponding to the currently multiplexed FIR filter, and then transmit the first folded read address after each self-decrement operation to the read-write control submodule through the first address selector, so as to trigger the read-write control submodule to read the corresponding to-be-filtered data from the data buffer according to the first folded read address after each self-decrement operation; When the amount of the to-be-filtered data written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter type selection module is further configured to, within each filtering cycle, perform a self-addition operation on the second folded read address according to the read timing corresponding to the currently multiplexed FIR filter, and then transmit the second folded read address after each self-addition operation to the read-write control submodule through the second address selector, so as to trigger the read-write control submodule to read the corresponding to-be-filtered data from the data buffer according to the second folded read address after each self-addition operation; Wherein, the currently multiplexed FIR filter is the half-band filter; The address offset of the second folding address number in a self-increment operation is 2; the address offset of the first folding address number in a self-decrement operation is 2.

24. The FIR filter multiplexing system according to claim 23, characterized in that: Within one filtering cycle, when it is detected that the difference between the number of taps of the currently multiplexed FIR filter and twice the number of times the decrement operation is performed on the first folding read address is less than twice the number of times the decrement operation is performed on the first folding read address, the decrement operation on the first folding read address is stopped, and the sum of the currently obtained first folding read address sequence number and the value 1 is updated as the first folding read address sequence number, and the first folding read address sequence number is kept unchanged; Alternatively, within a filtering cycle, when it is detected that the difference between the number of taps of the currently multiplexed FIR filter and twice the number of self-addition operations is less than twice the number of self-addition operations performed on the second folded read address, the self-addition operation on the second folded read address is stopped, and the difference between the currently obtained second folded read address number and the value 1 is updated to the second folded read address number, and the second folded read address number is kept unchanged.

25. The FIR filter multiplexing system according to claim 24, characterized in that: The filter type selection module includes a first folding address counter, configured to operate when the filter type selection signal is at a second logic level; After the folding reference address sequence number is updated to the starting address sequence number of the first folding read address, the first folding address counter is used to perform a self-decrement operation on the first folding read address sequence number starting from the starting address sequence number of the first folding read address; if the filter type selection module determines that the first folding read address sequence number is decremented to the filtering starting address sequence number, the difference between the filtering target address sequence number and the value 1 is updated as the first folding read address sequence number; if the filter type selection module determines that the sum of the filtering starting address sequence number and the value 1 is equal to the first folding read address sequence number, the filtering target address sequence number is updated to the first folding read address sequence number; The first folding read address sequence number represents the order of the first folding read address in the data buffer; the change in the count value generated by the first folding address counter when it is decremented once is a value of 2, so that the change in the first folding read address sequence number generated by the self-increment operation is a value of 2; The filtering target address sequence number is an address sequence number pre-configured in the data buffer and is the largest address sequence number among the address sequences participating in the read operation in each filtering cycle; the difference between the filtering target address sequence number and the filtering starting address sequence number is equal to the difference between the number of taps of the currently multiplexed FIR filter and 1; The first folding read address sequence number is used to indicate the address order of the first folding read address in the data buffer.

26. The FIR filter multiplexing system according to claim 25, characterized in that: The filter type selection module includes a second folding address counter, configured to operate when the filter type selection signal is at a second logic level; Before the filter type selection module determines to configure the folding reference address sequence number as the starting address sequence number of the second folding read address, if the filter type selection module determines that the folding reference address sequence number is equal to the filtering target address sequence number, the filtering starting address sequence number is updated to the folding reference address sequence number, and then the sum of the folding reference address sequence number and the value 1 is updated as the starting address sequence number of the second folding read address sequence number; then, the second folding address counter is used to perform a self-increment operation on the second folding read address sequence number starting from the starting address sequence number of the second folding read address; If the filter type selection module determines that the second folding read address sequence number after the self-increment operation is equal to the filtering target address sequence number, then the sum of the filtering starting address sequence number and the value 1 is updated as the second folding read address sequence number; if the filter type selection module determines that the second folding read address sequence number after the self-increment operation is equal to the difference between the filtering target address sequence number and the value 1, then the filtering starting address sequence number is updated as the second folding read address sequence number; The change value of the count value generated by the self-increment of the second folding address counter is 2, so that the change value of the second folding read address sequence number generated by the self-increment operation is 2; The second folding read address sequence number is used to indicate the address order of the second folding read address in the data buffer.

27. The FIR filter multiplexing system according to claim 26, characterized in that: Under the read timing corresponding to the currently multiplexed FIR filter, performing a decrement operation on the first folding read address once every two system clock cycles to obtain a new first folding read address, and recording these two system clock cycles as a counting period of the first folding read address; Under the read timing corresponding to the currently multiplexed FIR filter, a self-increment operation is performed on the second folded read address every two system clock cycles to obtain a new second folded read address, and these two system clock cycles are recorded as a counting period of the second folded read address; In a state where the number of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, under the control of the read-write control submodule, within the counting cycle of the first folded read address or the counting cycle of the second folded read address, the data to be filtered in the first folded read address is read to the filter calculation submodule, and the data to be filtered in the second folded read address is read to the filter calculation submodule, and the reading is repeated until the number of data to be filtered read within one filtering cycle is equal to half of the sum of the number of taps of the currently multiplexed FIR filter and the value 1, and then one data to be filtered is read from the intermediate calculation cache address within the next system clock cycle; wherein the intermediate calculation cache address is an address position between the most recently obtained second folded read address and the most recently obtained first folded read address; Among them, within the counting cycle of each first folding read address or the counting cycle of each second folding read address, the address offset of the first folding read address serial number corresponding to the read first folding read address relative to the filtering starting point address serial number is equal to the address offset of the filtering target address serial number relative to the second folding read address serial number corresponding to the read second folding read address.

28. The FIR filter multiplexing system according to claim 27, characterized in that: In a state where the amount of to-be-filtered data written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, the filter coefficient memory is used to, within each filtering cycle, start from a starting storage address that matches the currently multiplexed FIR filter, and perform a self-addition operation on the starting storage address once every two system clock cycles, and then read the corresponding stored filter coefficients to the filter calculation submodule in sequence according to the storage address obtained by self-addition, until the address offset of the storage address obtained by self-addition relative to the starting storage address is equal to half of the sum of the number of taps of the currently multiplexed FIR filter and a value of 1, and the most recently obtained storage address is recorded as the intermediate calculation storage address; Wherein, in the process of performing the self-increment operation on the starting storage address, each time the self-increment operation is performed, the address sequence number corresponding to the storage address increases by a value of 2; the starting storage address is selected and determined by the filter type selection module to match the currently multiplexed FIR filter; The address serial number corresponding to the storage address is used to indicate the address order of the storage address in the filter coefficient memory; and the number of taps of the currently multiplexed FIR filter is an odd number.

29. The FIR filter multiplexing system according to claim 18 or 28, characterized in that: The filtering calculation submodule is used to, when the amount of data to be filtered written into the data buffer is greater than the transposition enable count threshold of the currently multiplexed FIR filter, first control the data to be filtered in the first folding read address output by the data buffer and the data to be filtered in the second folding read address output by the data buffer in each counting cycle of the first folding read address or each counting cycle of the second folding read address, and then multiply the result of the addition with the filter coefficients of the same read order output by the filter coefficient memory; and then input the multiplication result into the adder for accumulation processing, and repeat this process in each filtering cycle until the filter coefficient memory outputs the filter coefficients in the intermediate calculation storage address, then multiply the filter coefficients in the intermediate calculation storage address with the data to be filtered in the first folding read address output by the data buffer under the same read order, and then input the multiplication result into the adder for accumulation processing to obtain the processed filtering result in the corresponding filtering cycle; Among them, in each filtering cycle, the multiplication operation is realized by a multiplier in time-sharing multiplexing; Wherein, the filtering calculation submodule includes an adder and a multiplier; The transposition enable count threshold of the currently multiplexed FIR filter is equal to the number of taps of the currently multiplexed FIR filter.

30. The FIR filter multiplexing system according to claim 4, characterized in that: The read / write control submodule is configured to control the writing of the external input data to be filtered into the data buffer according to the system clock cycle, and sequentially read the data to be filtered written into the data buffer according to the pre-read address selected and output by the pre-address selector, the first folded read address selected and output by the first address selector, and the second folded read address selected and output by the second address selector; Wherein, a piece of data to be filtered is written in a current system clock cycle, and a piece of data to be filtered is read in a next system clock cycle.

31. The FIR filter multiplexing system according to claim 30, characterized in that: An incremental counter is set inside the read-write control submodule, and the read-write control submodule is used to start from the cache head address of the data buffer. Each time a data to be filtered is written, the incremental counter is controlled to add an offset to the current cache address to obtain the cache address of the next written data to be filtered, until the address offset of the currently obtained cache address relative to the cache head address is equal to the number of taps of the currently multiplexed FIR filter, the cache head address is updated to the currently obtained cache address, so that the subsequently written data to be filtered overwrites the data to be filtered originally stored at the cache head address, and determines that a round of continuous cache address traversal of the data buffer is completed; wherein, the continuous cache address is composed of address units whose number is the number of taps of the currently multiplexed FIR filter.

32. The FIR filter multiplexing system according to claim 31, characterized in that: The read-write control submodule is further configured to, after completing a round of traversal of continuous cache addresses, set the incremental counter to an incremental initial value if new data to be filtered is continued to be written to the continuous cache addresses according to the system clock cycle control, and starting from the cache first address, each time a data to be filtered is written, overwrite the data to be filtered originally stored in the cache address with the currently written data to be filtered, and control the incremental counter to add an offset to the current cache address to obtain the cache address of the next written data to be filtered, until the address offset of the currently obtained cache address relative to the cache first address is equal to the difference between the number of taps of the currently multiplexed FIR filter and the value 1, update the cache first address to the currently obtained cache address, and adjust the count value of the incremental counter to the incremental initial value; Among them, the incremental initial value set by the incremental counter represents the address order of the cache first address in the data buffer; each count value generated by the incremental counter represents the address order of the cache address written in the corresponding system clock cycle in the data buffer.

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