A multi-channel adc testing method

Abstract

The application discloses a kind of multi-channel ADC test methods, comprising the following steps: S1, carry out several sample bottom test;S2, single channel qualification rate is counted;S3, measure the remaining chip of same batch;S4, different batch chip cycle test.The application can more scientifically and efficiently measure multi-channel ADC by bottoming-out-statistics-cycle test method, reduce the repeated work in test, improve test efficiency, save test cost, increase the accuracy, reliability and stability of test, timely summarize and troubleshoot problems, improve research and development production efficiency.The test results of bottoming-out-statistics-cycle test method can play its significance in each stage of chip research and development production.Similar chips can also be compared by bottoming-out-statistics-cycle test results, troubleshoot problems, improve design, and improve efficiency.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit testing, and in particular relates to a multi-channel ADC testing method. Background Art

[0002] Multichannel ADCs typically operate simultaneously, but testing typically involves testing each channel sequentially. Because each channel requires a signal source to provide input signals and ensure signal quality, simultaneous measurement of multiple channels is difficult. There are two common testing methods: testing channels sequentially without changing the chip, or testing the chip sequentially without changing channels. Different testing methods are used depending on the test objectives and chip conditions.

[0003] Each test method has its advantages. Testing channels sequentially without changing the chip ensures that different channels on the same chip are tested under the same environment. All channels are tested with the chip powered on, minimizing the impact of overall chip issues, such as fixture contact and register configuration, on channel function. Testing the chip sequentially without changing channels ensures that all channels are tested under the same environment, minimizing the impact of issues with input signals or test procedures on channel function.

[0004] Regardless of the traditional testing method used, every channel of every chip must be measured, resulting in a repetitive, lengthy, and data-intensive process. Not only can the testing environment fluctuate during the test, but tester manipulation can also contribute to test errors. During the R&D testing phase, where the overall pass rate is low, different channels within the same batch of circuits often have significantly different pass rates due to design and process factors, resulting in some channels having high pass rates and others having low pass rates. Therefore, a preliminary test of samples can be performed to determine which channel or channels within the batch have low pass rates, and then the pass rates of the different channels can be calculated. Summary of the Invention

[0005] The purpose of the present invention is to propose a new multi-channel ADC testing method based on the above problems and phenomena, which adopts the segmented operation and timely summary of the test method of investigation-statistics-loop testing. It can not only improve the test efficiency and reduce the test error, but also promptly discover the problems in the design and process and conduct timely investigation.

[0006] The technical solution of the present invention is:

[0007] A multi-channel ADC testing method comprises the following steps:

[0008] S1. Conduct a few sample tests:

[0009] First, select several samples of multi-channel ADCs from the same batch and perform a basic test on the function of each channel of each sample;

[0010] S2. Statistics of the pass rate of a single channel:

[0011] According to the preliminary test results of several samples in step S1, the qualified rate of each single channel is calculated respectively;

[0012] S3. Measure the remaining chips in the same batch:

[0013] Using the baseline test results, the remaining multi-channel ADC chips in the same batch are tested sequentially according to the principle of prioritizing the measurement of channels with low pass rates. If a channel fails, the chip will no longer be tested for the next channel.

[0014] S4. Cyclic testing of chips from different batches:

[0015] After recording the test results of steps S2-S3, improve the chip based on the test results. Repeat steps S1-S3 after the next tape-out and record the results of the new batch of chips until the overall product qualification rate meets the conditions for mass production.

[0016] Preferably, the bottom test in step S1 adopts a method of testing in sequence by changing channels without changing the chip, and sampling is performed by changing channels without powering off when the chip is in working state.

[0017] Preferably, in the baseline test of step S1, if a channel A(a) of a chip A cannot work normally, it is replaced with chip B for comparison while ensuring that the input signal and sampling program remain unchanged. If the corresponding channel B(a) of chip B can work normally, chip A is retested. If A still cannot work normally, it is determined that channel A(a) is abnormal; if B(a) also cannot work normally, after checking for problems such as loose fixture and contact misalignment, the above test experiment is repeated for troubleshooting until channel A(a) is determined to be abnormal or qualified.

[0018] Preferably, in the basic test of step S1, the functional status of each channel of each sample is recorded, and the overall qualified rate of the chip of the sample is observed:

[0019] If the overall pass rate is lower than the set value, the process proceeds to step S2 to calculate the pass rate of a single channel;

[0020] If the overall pass rate is higher than the set value, the screening test phase will be carried out directly according to the test purpose:

[0021] If the purpose is to screen, complete acceptance, and sell, there is no need to test all channels. Instead, use the baseline test results to prioritize testing channels with lower pass rates. If an unqualified channel is encountered, the entire chip is judged unqualified and there is no need to test other channels. If this test needs to be compared with other batches of chips, steps S2 and S3 are still required.

[0022] The advantages of the present invention are:

[0023] The present invention uses a thorough investigation-statistics-loop test method to measure multi-channel ADCs in a more scientific and efficient manner, reducing duplication of work during testing, improving test efficiency, saving test costs, increasing test accuracy, reliability, and stability, and timely summarizing and troubleshooting problems to improve R&D and production efficiency. The test results of the thorough investigation-statistics-loop test method can be used at every stage of chip R&D and production. Chips with similar principles can also be compared using the thorough investigation-statistics-loop test results to troubleshoot and improve design, thereby increasing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0025] Figure 1 Flowchart of the multi-channel ADC testing method of the present invention. DETAILED DESCRIPTION

[0026] like Figure 1 As shown, a multi-channel ADC testing method of the present invention includes the following steps:

[0027] S1. Conduct a few sample tests:

[0028] First, select several samples from the same batch of multi-channel ADCs and perform a baseline test on the functionality of each channel. During this baseline test, the chip is replaced with a separate channel, with sampling performed while the chip is operating and power is turned off. This ensures that the test data represents the performance of different channels on the same chip under the same conditions, minimizing the risk of differences caused by contact issues and other unstable factors due to varying test environments.

[0029] If a channel A(a) of a chip A fails to work properly, replace it with chip B for comparison while ensuring that the input signal and sampling program remain unchanged. If the corresponding channel B(a) of chip B works properly, retest chip A. If A still fails to work properly, channel A(a) is determined to be abnormal. If B(a) also fails to work properly, check for problems such as loose fixtures and contact misalignment, and repeat the above test experiments until channel A(a) is determined to be abnormal or qualified.

[0030] In the basic test of step S1, the functional status of each channel of each sample is recorded, and the overall chip qualification rate of the sample is observed:

[0031] If the overall pass rate is lower than the set value, the process proceeds to step S2 to calculate the pass rate of a single channel;

[0032] If the overall pass rate is higher than the set value, the screening test phase will be carried out directly according to the test purpose:

[0033] If the purpose is to screen, complete acceptance, and sell, there is no need to test all channels. Instead, use the baseline test results to prioritize testing channels with lower pass rates. If an unqualified channel is encountered, the entire chip is judged unqualified and there is no need to test other channels. If this test needs to be compared with other batches of chips, steps S2 and S3 are still required.

[0034] S2. Statistics of the pass rate of a single channel:

[0035] Based on the preliminary test results of several samples in step S1, the pass rate of each individual channel is calculated; the performance of each channel is recorded and calculated, and the chip test data is organized into channel test data records for storage. By analyzing the pass rate of each channel in a batch of chips, test design and process processing can be guided, and the causes of channel malfunctions can be identified, thereby improving product pass rates and reducing costs. By comparing the pass rates of the same channel across different batches of chips, it can be determined whether design and process improvements made during product development have been effective and whether they have introduced new problems.

[0036] S3. Measure the remaining chips in the same batch:

[0037] Using the baseline test results, the remaining multi-channel ADC chips in the same batch are tested sequentially according to the principle of prioritizing the measurement of channels with low pass rates. If a channel fails, the chip will no longer be tested for the next channel.

[0038] S4. Cyclic testing of chips from different batches:

[0039] After recording the test results of steps S2-S3, improve the chip based on the test results. Repeat steps S1-S3 after the next tape-out and record the results of the new batch of chips until the overall product qualification rate meets the conditions for mass production.

[0040] Example 1

[0041] Suppose we want to test a total of I batches of ADCs with m channels. The total number of chips in batch i is n. i , the number of samples is r i The total qualified rate of samples in batch i is α i , the pass rate of channel j in batch i is β ij .

[0042] but:

[0043] The traditional test method measures all test quantities T in sequence all The times are as follows:

[0044]

[0045] Use the method of survey-statistics-cycle test to test the quantity T s The times are as follows:

[0046]

[0047] The test volume reduction rates are as follows:

[0048]

[0049] The total qualified rate of samples in batch i is as follows:

[0050]

[0051] The pass rate of channel j in batch i is as follows:

[0052]

[0053] To demonstrate the feasibility of the baseline-statistics-loop test method, assume that there are three batches of 8-channel ADCs to be tested, as follows:

[0054] Batch 1, 50 8-channel ADCs, assuming the pass rate for channel 1 is 70%, the pass rate for channel 2 is 80%, and all other channels are qualified. 10 units are randomly sampled.

[0055] Batch 2, 50 8-channel ADCs, assuming the pass rate for channel 1 is 80%, the pass rate for channel 2 is 90%, and all other channels are qualified. 10 units were randomly sampled.

[0056] Batch 3, 100 8-channel ADCs, assuming the pass rate of channel 1 is 90%, the pass rate of channel 2 is 90%, and the remaining channels are all qualified. 20 units are randomly sampled, namely:

[0057] m=8,I=3,n1=50,r1=10,n2=50,r2=10,n3=100,r3=20

[0058] Using traditional testing methods:

[0059] All measured in order T all =1600.

[0060] Adopting the method of survey-statistics-cycle testing:

[0061] 1. Batch 1:

[0062] 1.1 Sampling test:

[0063] Assume the test results are as follows: 7 of the 1st channel are qualified and 3 are unqualified, 8 of the 2nd channel are qualified and 2 are unqualified, and the remaining channels are qualified, of which 1 is unqualified in both 1st and 2 channels. Test quantity T11 =10×8=80, and the overall qualified rate is α1=60%. All chips are in the R&D stage and the overall qualified rate is low, so they enter the second stage.

[0064] 1.2 Statistics of the pass rate of a single channel:

[0065] β 11 =70%, β 12 =80%, β 13 =β 14 =β 15 =β 16 =β 17 =β 18 =100%.

[0066] 1.3 Use the baseline test results to measure the remaining chips:

[0067] According to the principle of prioritizing the measurement of channels with low pass rates, the remaining chips after sampling are tested sequentially. Assume that the test results are as follows: Testing all chips with one channel requires 40 tests, 12 unqualified chips are screened out, and 28 qualified chips with one channel proceed to the next step. Testing 2 channels of the 28 qualified chips with one channel requires 28 tests, 4 unqualified chips are measured, and the remaining 24 proceed to the next step. Testing the remaining channels requires 24×6=144 tests. Test quantity T 12 =212.

[0068] 2. Batch 2:

[0069] 2.1 Sampling test:

[0070] Assume the test results are as follows: 8 pieces of channel 1 are qualified and 2 pieces are unqualified, 9 pieces of channel 2 are qualified and 1 piece is unqualified, and the rest of the channels are qualified, and there are 0 pieces of channels 1 and 2 that are unqualified. Test quantity T 21 =10×8=80, and the overall qualified rate is α2=70%. All chips are in the R&D stage and the overall qualified rate is low, so they enter the second stage.

[0071] 2.2 Statistics of the pass rate of a single channel:

[0072] β 21 =80%, β 22 =90%, β 13 =β 14 =β 15 =β 16 =β 17 =β 18 =100%.

[0073] 2.3 Use the baseline test results to measure the remaining chips:

[0074] According to the principle of prioritizing the measurement of channels with low pass rates, the remaining chips after sampling are tested sequentially. Assume that the test results are as follows: Testing all chips with one channel requires 40 tests, 8 unqualified chips are screened out, and 32 chips with one channel pass proceed to the next step. Testing 2 channels of the 32 chips with one channel pass requires 32 tests, and 4 unqualified chips are measured, leaving 28 for the next step. Testing the remaining channels requires 28 × 6 = 168 tests. Test quantity T 22 =240.

[0075] 3. Batch 3:

[0076] 3.1 Sampling test:

[0077] Assume the test results are as follows: 18 pieces of test paper in channel 1 are qualified and 2 pieces are unqualified; 18 pieces of test paper in channel 2 are qualified and 2 pieces are unqualified; the remaining channels are qualified, and there are 0 pieces of test paper that are unqualified in both channels 1 and 2. Test quantity T 31 =20×8=160, the overall pass rate is α3=80%. All chips are in the R&D stage and the overall pass rate is low, so they enter the second stage.

[0078] 3.2 Statistics of the pass rate of a single channel:

[0079] β 31 =90%, β 32 =90%, β 13 =β 14 =β 15 =β 16 =β 17 =β 18 =100%.

[0080] 3.3 Use the baseline test results to measure the remaining chips:

[0081] According to the principle of prioritizing the measurement of channels with low pass rates, the remaining chips after sampling are tested sequentially. Assume that the test results are as follows: Testing all chips with one channel requires 80 tests, 8 unqualified chips are screened out, and 72 chips with one channel pass proceed to the next step. Testing 72 channels of the 72 chips with one channel pass requires 72 tests, 8 unqualified chips are measured, and the remaining 64 proceed to the next step. Testing the remaining channels requires 64×6=384 tests. Test quantity T 32 =536.

[0082] By adopting the method of survey-statistics-cycle test, all test quantities T s =T 11 +T 12 +T 21 +T 22 +T 31 +T 32 =1308.

[0083]

[0084] Therefore, the test volume of the baseline-statistics-cycle test method is reduced by 18.25% compared with the traditional test method, which greatly reduces the test volume and improves the test efficiency.

[0085] The above embodiments are intended only to illustrate the technical concepts and features of the present invention. Their purpose is to enable those skilled in the art to understand the contents of the present invention and implement them accordingly. They are not intended to limit the scope of protection of the present invention. Any modifications made based on the spirit of the main technical solution of the present invention shall be included in the scope of protection of the present invention.

Claims

1. A multi-channel ADC testing method, characterized in that: The following steps are involved: S1. Conduct a few sample tests: First, select several samples of multi-channel ADCs from the same batch and perform a basic test on the function of each channel of each sample; S2. Statistics of the pass rate of a single channel: According to the preliminary test results of several samples in step S1, the qualified rate of each single channel is calculated respectively; S3. Measure the remaining chips in the same batch: Using the baseline test results, the remaining multi-channel ADC chips in the same batch are tested sequentially, with priority given to channels with low pass rates. If a channel fails, the chip will not be tested for the next channel. S4. Cyclic testing of chips from different batches: After recording the test results of steps S2-S3, improve the chip based on the test results. Repeat steps S1-S3 after the next tape-out, recording the results of the new batch of chips until the overall product qualification rate meets the requirements for mass production. The bottom test in step S1 adopts the method of changing channels in sequence without changing the chip, and sampling is performed by changing channels without powering off when the chip is in working state.

2. The multi-channel ADC testing method according to claim 1, wherein: In the baseline test of step S1, if a channel A(a) of a chip A cannot work normally, replace it with chip B for comparison while ensuring that the input signal and sampling program remain unchanged. If the corresponding channel B(a) of chip B can work normally, retest chip A. If A still cannot work normally, it is determined that channel A(a) is abnormal; if B(a) also cannot work normally, after checking for problems such as loose fixture and contact misalignment, repeat the above test experiment until channel A(a) is determined to be abnormal or qualified.

3. The multi-channel ADC testing method according to claim 2, wherein: In the basic test of step S1, the functional status of each channel of each sample is recorded, and the overall chip qualification rate of the sample is observed: If the overall pass rate is lower than the set value, the process proceeds to step S2 to calculate the pass rate of a single channel; If the overall pass rate is higher than the set value, the screening test phase will be carried out directly according to the test purpose: If the purpose is screening, acceptance, or sales, it is not necessary to test all channels. Instead, the channels with lower pass rates are tested first based on the baseline test results. If an unqualified channel is encountered, the entire chip is deemed unqualified, and no further testing of other channels is required. If this test needs to be compared with chips from other batches, it is still necessary to proceed to steps S2 and S3.

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