Precision Plasma Control System

Abstract

Some embodiments include a plasma system that includes: a plasma chamber, an RF plasma generator, a bias generator, and a controller. The RF plasma generator can be electrically coupled to the plasma chamber and can generate a plurality of RF bursts, each of the plurality of RF bursts including an RF waveform, each of the plurality of RF bursts having an RF burst on-time and an RF burst off-time. The bias generator can be electrically coupled to the plasma chamber and can generate a plurality of bias bursts, each of the plurality of bias bursts including a bias pulse, each of the plurality of bias bursts having a bias burst on-time and a bias burst off-time. In some embodiments, the controller communicates with the RF plasma generator and the bias generator, and the controller controls the timing of the various bursts or waveforms.

Description

Background Art

[0001] The application of RF-excited gas discharge in thin film manufacturing technology has become standard. The simplest geometry most commonly used is that of two planar electrodes with a voltage applied between the two planar electrodes.

[0002] Positive ions generated in the plasma volume are accelerated across the plasma sheath and arrive at the electrode or wafer with an ion energy distribution function (IEDF) determined by the magnitude and waveform of the time-dependent potential difference across the sheath, the gas pressure, the physical geometry of the reactor, and / or other factors. This ion bombardment energy distribution can determine the degree of anisotropy of thin film etching, the amount of surface damage caused by ion impact, etc. Summary of the Invention

[0003] Some embodiments include a plasma system comprising: a plasma chamber; an RF plasma generator electrically coupled to the plasma chamber; a bias generator electrically coupled to the plasma chamber; and / or a controller electrically coupled to the plasma chamber and communicating with the RF plasma generator and / or the bias generator.

[0004] Some embodiments include a plasma system comprising: a plasma chamber, an RF plasma generator, a bias generator, and a controller. The RF plasma generator may be electrically coupled to the plasma chamber and may generate a plurality of RF bursts, each of the plurality of RF bursts including an RF waveform, and each of the plurality of RF bursts having an RF burst on-time and an RF burst off-time. The bias generator may be electrically coupled to the plasma chamber and may generate a plurality of bias bursts, each of the plurality of bias bursts including a bias pulse, and each of the plurality of bias bursts having a bias burst on-time and a bias burst off-time. In some embodiments, the controller communicates with the RF plasma generator and the bias generator, and the controller controls the timing of the various bursts or waveforms according to the following method:

[0005] Drive the plasma chamber with the RF plasma generator having a frequency greater than 10 MHz;

[0006] Pause for a first period of time;

[0007] Pulse the plasma chamber with pulses having a first voltage at a pulse repetition frequency greater than 1 kHz through the bias generator;

[0008] Pause for a second period of time;

[0009] Stop driving the RF plasma generator;

[0010] Pause for a third time period; and

[0011] Stop the bias generator from generating pulses.

[0012] In some embodiments, the plurality of RF bursts generate and / or drive a plasma in the plasma chamber, and the plurality of bias bursts accelerate ions within the plasma.

[0013] In some embodiments, the plasma system includes an electrode deployed in the plasma chamber, the electrode being coupled to the bias generator. In some embodiments, the plasma system includes an electrode deployed in the plasma chamber, the electrode being coupled to the RF generator. In some embodiments, the plasma system includes an inductive antenna deployed in the plasma chamber, the antenna being coupled to the RF plasma generator.

[0014] In some embodiments, the plasma system includes a wafer deployed in the plasma chamber, the wafer being coupled to the bias generator. In some embodiments, the plasma system includes a wafer deployed in the plasma chamber, the wafer being coupled to the bias generator.

[0015] In some embodiments, the RF burst turn-on time precedes the bias burst turn-on time by less than 10 ms. In some embodiments, the bias burst turn-on time precedes the RF burst turn-off time by less than 10 ms. In some embodiments, the difference between the RF burst turn-on time and the RF burst turn-off time is less than about 1 ms. In some embodiments, the difference between the bias burst turn-on time and the bias burst turn-off time is less than about 1 ms.

[0016] In some embodiments, the bias pulse has a pulse repetition frequency greater than 1 kHz. In some embodiments, the bias pulse has a voltage greater than 1 kilovolt. In some embodiments, the RF waveform has a frequency greater than 10 MHz.

[0017] The plasma system according to claim 1, wherein the plurality of RF bursts generate and / or drive a plasma in the plasma chamber, and the plurality of bias bursts accelerate ions within the plasma.

[0018] In some embodiments, the controller controls the timing of the RF burst turn-on time, the RF burst turn-off time, the bias turn-on time, and the bias turn-off time based on feedback from the plasma chamber.

[0019] In some embodiments, the bias generator includes a nanosecond pulse generator. In some embodiments, the bias generator includes a bias compensation circuit. In some embodiments, the bias generator includes an energy recovery circuit. In some embodiments, the bias generator includes an RF generator.

[0020] In some embodiments, the RF plasma generator includes a full-bridge circuit or a half-bridge circuit and a resonant circuit.

[0021] Some embodiments include a method that includes: driving an RF plasma generator; pausing for a first period of time; pulsing a nanosecond pulse generator with pulses having a first voltage; pausing for a second period of time; stopping driving the RF plasma generator; pausing for a third period of time; and stopping pulsing the nanosecond pulse generator.

[0022] In some embodiments, the method may further include: pausing for a fourth period of time; stopping driving the RF plasma generator; pausing for the first period of time; pulsing the nanosecond pulse generator with pulses having a second voltage; pausing for the second period of time; stopping driving the RF plasma generator; pausing for the third period of time; and stopping pulsing the nanosecond pulse generator.

[0023] In some embodiments, the second voltage is greater than the first voltage.

[0024] In some embodiments, the method may further include: pausing for a fourth period of time; stopping driving the RF plasma generator; pausing for a fifth period of time different from the first period of time; pulsing the nanosecond pulse generator with pulses having a second voltage; pausing for a sixth period of time different from the first period of time; stopping driving the RF plasma generator; pausing for a seventh period of time different from the first period of time; and turning off the nanosecond pulse generator.

[0025] In some embodiments, the first period of time may be less than about 10 ms; the second period of time may be less than about 10 ms; and / or the third period of time may be less than about 10 ms. In some embodiments, the first period of time is less than the second period of time. In some embodiments, the first period of time is less than the second period of time.

[0026] The mention of these illustrative embodiments is not to limit or define the disclosure, but to provide examples to assist in understanding it. Additional embodiments are discussed in the detailed description and further description is provided herein. The advantages provided by one or more of the various embodiments can be further understood by examining this specification or by practicing one or more of the embodiments presented. Description of the Drawings

[0027] Figure 1 is a block diagram of a plasma system according to some embodiments.

[0028] Figure 2 is an illustration showing example waveforms of two pulse bursts according to some embodiments.

[0029] Figure 3 is an illustration of an example RF burst and an example bias burst according to some embodiments.

[0030] Figure 4 is a block diagram of a plasma control system according to some embodiments.

[0031] Figure 5 is a process for controlling a plasma system according to some embodiments.

[0032] Figure 6 is a circuit diagram of a bias generator according to some embodiments.

[0033] Figure 7 is from Figure 6 the waveform of the shown bias generator.

[0034] Figure 8 is Figure 7 an enlarged view of the shown waveform.

[0035] Figure 9 is a circuit diagram of a bias generator according to some embodiments.

[0036] Figure 10 is a circuit diagram of a bias generator according to some embodiments.

[0037] Figure 11 is a circuit diagram of a bias generator according to some embodiments.

[0038] Figure 12 is a circuit diagram of an RF plasma generator according to some embodiments.

[0039] Figure 13 is a circuit diagram of an RF plasma generator according to some embodiments.

[0040] Figure 14A 、 Figure 14B 、 Figure 15A and Figure 15B is a circuit diagram of an example resonant circuit.

[0041] Figure 16 is a circuit diagram of a bias generator with an energy recovery circuit according to some embodiments.

[0042] Figure 17Circuit diagram of a bias generator with an active energy recovery circuit according to some embodiments.

[0043] Figure 18 Circuit diagram of a bias generator including a passive bias compensation circuit and an energy recovery circuit according to some embodiments.

[0044] Figure 19 Circuit diagram of a bias generator including an active bias compensation circuit with an energy recovery circuit according to some embodiments.

[0045] Figure 20 Circuit diagram of a bias generator including an active bias compensation circuit with an active energy recovery circuit according to some embodiments.

[0046] Figure 21 Circuit diagram of a bias generator with an energy recovery circuit according to some embodiments.

[0047] Figure 22 Circuit diagram of a bias generator with an energy recovery circuit driving a capacitive load according to some embodiments.

[0048] Figure 23 Block diagram of a high-voltage switch with isolated power according to some embodiments.

[0049] Figure 24 Circuit diagram of a bias generator including an RF source, an active bias compensation circuit, and an energy recovery circuit according to some embodiments.

[0050] Figure 25 Shows another example bias generator according to some embodiments.

[0051] Figure 26 Block diagram of a computing system according to some embodiments. Detailed Description

[0052] Some embodiments include a plasma system that includes a plasma chamber, an RF plasma generator, a bias generator, and a controller. The RF plasma generator can be electrically coupled to the plasma chamber and can generate a plurality of RF bursts, each of the plurality of RF bursts including an RF waveform, and each of the plurality of RF bursts having an RF burst on-time and an RF burst off-time. The bias generator can be electrically coupled to the plasma chamber and can generate a plurality of bias bursts, each of the plurality of bias bursts including a bias pulse, and each of the plurality of bias bursts having a bias burst on-time and a bias burst off-time. In some embodiments, the controller communicates with the RF plasma generator and the bias generator, and the controller controls the timing of the various bursts or waveforms.

[0053] As used throughout this disclosure, the term "high voltage" can include voltages greater than 500V, 1kV, 10kV, 20kV, 50kV, 100kV, etc.; the term "high frequency" can be a frequency greater than 1kHz, 10kHz, 100kHz, 200kHz, 500kHz, 1MHz, etc., the term "fast rise time" can include a rise time less than about 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc.; the term "fast fall time" can include a fall time less than about 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc.; and the term short pulse width can include a pulse width less than about 1ns, 10ns, 50ns, 100ns, 250ns, 500ns, 1,000ns, etc.

[0054] Figure 1 is a block diagram of a plasma system 100 according to some embodiments. In some embodiments, the plasma system 100 includes a plasma chamber 110, an RF plasma generator 105, a bias generator 115, and / or a controller 120. In some embodiments, the RF plasma generator 105 can be used to create a plasma within the plasma chamber. In some embodiments, the bias generator 115 can provide pulses that can be used to accelerate ions within the plasma created within the plasma chamber 110.

[0055] In some embodiments, the controller 120 can include any type of controller (e.g., such as an FPGA, a microcontroller, etc.). In some embodiments, the controller 120 can receive signals from the plasma chamber 110 (or elsewhere) and change or adapt the timing, duration, frequency, amplitude, etc. of the bursts or pulses provided by the RF plasma generator 105 and / or the bias generator 115.

[0056] In some embodiments, the controller 120 can include any type of controller (e.g., such as an FPGA, an ASIC, a complex programmable logic device, a microcontroller, a system-on-chip (SoC), a supervisory control, data acquisition (SCADA), and a programmable logic controller (PLC), or any combination thereof). In some embodiments, the controller 120 can include any or all components of a computing system 2600. In some embodiments, the controller 120 can include a standard microcontroller (e.g., such as Broadcom ArmCortex, Intel ARM Cortex, PIC32, etc.).

[0057] In some embodiments, the RF plasma generator 105 can generate plasma in the plasma chamber on a microsecond time scale (e.g., 1 to 1000 microseconds). In some embodiments, the RF plasma generator 105 can allow for plasma maintenance and / or plasma driving on a microsecond time scale relative to DC with microsecond increments that are adjustable. In some embodiments, the RF plasma generator 105 can deliver very high peak power (e.g., 1 to 10000 kW). In some embodiments, the RF plasma generator 105 can generate a variable CW power (e.g., 0.1 to 100 kW) that is delivered.

[0058] In some embodiments, the RF plasma generator 105 can include the RF plasma generator 1200 or the RF plasma generator 1300. Any RF power source can be used.

[0059] In some embodiments, the RF plasma generator 105 can induce plasma formation in the plasma chamber 110 on a small time scale (e.g., on a time scale from about 1 μs to about 1,000 μs). In some embodiments, the RF plasma generator 105 can generate waveforms having arbitrary and / or controllable pulse width, pulse repetition frequency, pulse duration, maximum voltage, etc. In some embodiments, the RF plasma generator 105 can generate waveforms having a high peak power (e.g., from about 1 kW to about 10,000 kW). In some embodiments, the RF plasma generator 105 can generate waveforms having a variable and / or continuous wave (CW) power (e.g., from about 1 kW to about 100 kW).

[0060] In some embodiments, the bias generator 115 can control the wafer bias voltage on a small time scale (e.g., from about 1 μs to about 1,000 μs). In some embodiments, the bias generator 115 can generate waveforms having arbitrary and / or controllable pulse width, pulse repetition frequency, pulse duration, maximum voltage, etc. In some embodiments, the bias generator 115 can generate waveforms having a high peak power (e.g., from about 1 kW to about 100,000 kW). In some embodiments, the bias generator 115 can generate waveforms having a variable continuous power (e.g., from about 1 kW to about 100 kW).

[0061] In some embodiments, the bias generator 115 may include bias generator 600, bias generator 900, bias generator 1000, bias generator 1100, bias generator 1600, bias generator 1700, bias generator 1800, bias generator 1900, bias generator 2000, bias generator 2100, bias generator 2200, bias generator 2400, and bias generator 2500. In some embodiments, the bias generator 115 may include RF plasma generator 1200 or RF plasma generator 1300.

[0062] In some embodiments, the controller 120 may provide timing control of the pulses from both the RF plasma generator 105 and the bias generator 115. The RF waveform 305 is an example output from the RF plasma generator 105, and the bias burst 310 is an example output from the bias generator 115.

[0063] In some embodiments, for example, the timing from the controller 120 may contribute to faster plasma etching within the plasma chamber 110, allowing less / more corrosion of various masks; straighter and deeper holes / grooves, controlling specific plasma properties (e.g., temperature and density) while there is an etching voltage, driving different chemistries / reactions, changing the reaction rate, controlling some etching parameters, and / or controlling a certain plasma generation.

[0064] Figure 2 is an illustration showing an example waveform of two pulse bursts according to some embodiments. A single burst may include multiple pulses. The burst duration is the period during which the burst is on T on and the burst is off T off The pulse width P width is the period during which the pulse is on. The pulse period P period is the period during which the pulse is on and off. The duty cycle may be represented by the on time T on divided by the burst duration: The burst repetition frequency may be represented by the reciprocal of the burst period: f burst = 1 / (T op + T off ). The pulse repetition frequency may be represented by the reciprocal of the pulse period: f pulse = 1 / P period .

[0065] In some embodiments, the burst repetition frequency may be between approximately 10 Hz and approximately 1,000 Hz. In some embodiments, the pulse repetition frequency may be greater than approximately 10 kHz.

[0066] Figure 3Illustration of an example RF burst and an example bias burst according to some embodiments.

[0067] Time t1 represents the start of RF waveform 305 (e.g., RF burst turn-on time). Time t3 represents the end of RF waveform 305 (e.g., RF burst turn-off time). Time period w1 can represent the period during which the RF waveform is driving the plasma of RF waveform 305. Time t2 represents the start of bias burst 310 (e.g., bias burst turn-on time). Time t4 represents the end of bias burst 310 (e.g., bias burst turn-off time). Time period w2 can represent the period of bias burst 310.

[0068] RF waveform 305 can be created within plasma chamber 110 and drive the plasma. For example, time period w3 can include a period with an initial ring up. Time period w4 can be the period during which plasma is formed. Time period w1 can be the time during which the plasma is driven by the RF signal within the chamber.

[0069] In some embodiments, t3 can start when the plasma has been formed in chamber 110 (e.g., such as at the end of one or both of w3 or w4). In some embodiments, controller 120 can sense the formation of the plasma, for example, by sensing the amplitude of the initial ring up in RF waveform 305 or via a sensor deployed within chamber 110 or by sensing the number of cycles of RF waveform 305. For example, controller 120 can start burst 310 based on the controller sensing the formation of the plasma or anticipating the formation of the plasma within chamber 110.

[0070] In some embodiments, t1 can precede t2 by less than about 10 ms. In some embodiments, t3 can precede t4 by less than about 10 ms.

[0071] In some embodiments, the difference between t2 and t1 can be between about 10 μs and about 10 ms. In some embodiments, the difference between t2 and t1 can be less than about 1 μs. In some embodiments, the difference between t2 and t1 can be less than about 740 ns. In some embodiments, the difference between t2 and t1 can be about 10 cycles or periods of RF waveform 305 or greater than about 10 cycles or periods.

[0072] In some embodiments, t2 and t1 can occur substantially simultaneously. In some embodiments, t2 can be triggered based on when controller 120 detects that plasma formation has occurred within plasma chamber 110.

[0073] In some embodiments, the difference between t4 and t2 (or w2) can be between approximately 10 μs and approximately 10 ms. In some embodiments, w1 can be between approximately 10 μs and approximately 10 ms. In some embodiments, w2 can be continuous.

[0074] In some embodiments, the frequency of the RF waveform 305 can be between approximately 10 kHz and approximately 10 MHz. In some embodiments, the RF waveform 305 can have a frequency of 13.56 MHz or any multiple thereof (e.g., 27.12 MHz, 40.68 MHz, etc.). In some embodiments, the frequency of the RF waveform 305 can be greater than 10 MHz.

[0075] In some embodiments, w1 can be continuous (e.g., such as greater than 10 milliseconds, 1 millisecond, 1 second, 10 seconds, etc.). In some embodiments, the frequency of the pulses in the bias burst 310 can be between approximately 10 Hz and approximately 10 kHz. In some embodiments, the frequency of the pulses in the bias burst 310 can be greater than 1 kHz. In some embodiments, the frequency of the pulses in the bias burst 310 can be greater than 10 kHz. In some embodiments, the frequency of the pulses in the bias burst 310 can be between 10 kHz and 20 MHz. In some embodiments, the frequency of the pulses in the bias burst 310 can be greater than approximately 400 kHz.

[0076] In some embodiments, w3 (e.g., t3 - w1 - t1 - w4) can be less than approximately 10 ms.

[0077] In some embodiments, the flat or sloped or other segments of the bias burst 310 can be between 10 μs and 10 ms in duration.

[0078] In some embodiments, the flat or sloped or other segments of the bias burst 310 can be between 10 μs and 10 ms in duration.

[0079] In some embodiments, t2 can precede t3 by less than approximately 10 ms.

[0080] In some embodiments, t3 can precede t2 by less than approximately 10 ms.

[0081] In some embodiments, t2 can occur at any time during w4. In some embodiments, t2 can occur at any time before the start of w1. In some embodiments, t2 can occur during plasma formation. In some embodiments, t2 can occur during or after or during the initial ringing of the RF waveform 305.

[0082] In some embodiments, t2 can lead t4 by less than about 10 ms.

[0083] In some embodiments, the controller 120 can control the RF plasma generator 105 and / or the bias generator 115 to generate a plurality of pulse bursts having an arbitrary or selectable pulse width (e.g., w1 + w3 + w4 or w2), duty cycle, pulse repetition frequency, and / or burst frequency.

[0084] In some embodiments, the controller 120 can similarly control the RF plasma generator 105 and / or the bias generator 115 to include a slow start and / or a slow DC stop capability.

[0085] In some embodiments, the controller 120 can send and / or receive external commands from an external controller (e.g., an industrial controller). These external commands can control the pulse width, duty cycle, pulse repetition frequency, and / or burst frequency of one or both of the RF plasma generator 105 and / or the bias generator 115.

[0086] In some embodiments, the controller 120 can automate the control of high voltage DC power supplies including the following operations: turning them on / off, changing voltage and amperage settings, and / or making the unit safe in an emergency.

[0087] In some embodiments, the controller 120 can have a feedback circuit for the output from the RF plasma generator 105, thus allowing it to analyze the waveform entering the plasma chamber. This allows the controller 120 to self-adjust for different loads and load conditions.

[0088] In some embodiments, the controller 120 can control the bias generator 115 based on the settings entering the RF plasma generator 105.

[0089] In some embodiments, the controller 120 can control the bias generator 115 to generate pulses having a pulse width of 40 ns - 200 ns.

[0090] In some embodiments, the controller 120 can generate bursts having a duty cycle of 1% - 100%.

[0091] In some embodiments, the controller 120 can control the bias generator 115 to generate pulses having a burst repetition frequency of 200 - 1000 Hz.

[0092] In some embodiments, the controller 120 can control the bias generator 115 to start generating pulses with a minimum pulse width (e.g., ~40 ns) and ramp up to longer pulse widths (e.g., 40 ns, 44 ns, 48 ns, 52 ns, etc.) in 4 ns increments.

[0093] In some embodiments, the controller 120 may control the bias generator 115 to generate pulses that ramp a DC voltage from a maximum voltage down to 0V in selectable steps.

[0094] In some embodiments, the controller 120 may control the bias generator 115 to generate arbitrary pulses with low jitter (e.g., jitter less than about 10 nanoseconds).

[0095] In some embodiments, the controller 120 may perform self-calibration for the load conditions.

[0096] In some embodiments, the plasma chamber 110 may include any type of plasma chamber.

[0097] In some embodiments, the plasma chamber 110 may have a load capacitance of less than 20 nF. In some embodiments, an electric potential may be established in the plasma chamber 110 to accelerate ions into the surface by the action of the bias generator 115. In some embodiments, the plasma in the plasma chamber 110 may be largely capacitive in nature. In some embodiments, the plasma in the plasma chamber 110 may include dielectric barrier discharge.

[0098] In some embodiments, the plasma chamber 110 may be modeled as a capacitor, a capacitor in series with a resistor, a capacitor in series with an inductor, a dielectric barrier discharge, a plasma load, a semiconductor wafer processing load, and any arbitrary arrangement of capacitors, inductors, resistors, and / or other active and / or passive components, etc. In some embodiments, the load in the chamber may include any such load: when a voltage is applied and charge is delivered, the charge / voltage may persist for longer than desired (e.g., longer than the designed or desired fall time). For example, this may generally occur in high voltage switching applications.

[0099] In some embodiments, the plasma chamber 110 may include a capacitive load, one or more electrodes, a plasma load, one or more dielectric barriers, semiconductor manufacturing plasma, a semiconductor load, a grid, a medical load, etc. In some embodiments, the plasma chamber 110 may include a plasma deposition system, a plasma etching system, or a plasma sputtering system.

[0100] In some embodiments, the RF plasma generator 105 may include circuitry and / or processes for driving switched power into the plasma chamber without a matching network. In some embodiments, the RF plasma generator 105 may include a full (or half) bridge circuit topology that may be used to drive a resonant circuit at or near the resonant frequency of the resonant circuit. Because the resonant circuit is being driven at its resonant frequency, the output voltage of the resonant circuit may be higher than the input voltage. In some embodiments, such a resonant condition may allow a drive voltage of a few hundred volts to generate approximately 4 kV or higher.

[0101] Figure 4 FIG. 4 is a block diagram of a plasma control system 400 having a bias generator and an RF plasma generator, according to some embodiments. In some embodiments, the plasma control system 400 may be electrically coupled to the bias generator 115 at one or more locations and / or to the RF plasma generator 105 at one or more locations. For example, the first HV signal 405A (or the second HV signal 405B) may include a voltage signal at a point of the bias generator 115 between a pulse generator and a transformer stage and a bias compensation circuit. As another example, the first HV signal 405A (or the second HV signal 405B) may include a voltage signal at a point between a load stage and a bias compensation circuit. As another example, the first HV signal 405A (or the second HV signal 405B) may include a voltage at a resistive output stage or at a point prior to an energy recovery state. As another example, the first HV signal 405A (or the second HV signal 405B) may include a voltage on a wafer, chuck, or electrode. Although two signals are shown, any number of signals may be received. As another example, the first HV signal 405A (or the second HV signal 405B) may include a voltage across a resistor in a resistive output stage or an energy recovery circuit, which may represent the ion current in the chamber. As another example, the first HV signal 405A (or the second HV signal 405B) may include a voltage in an energy recovery circuit (e.g., across an energy recovery inductor), which may represent the ion current in the chamber.

[0102] In some embodiments, the first HV signal 405A and the second HV signal 405B may include voltage or current signals on each side of a capacitor of a bias compensation circuit (e.g., capacitor C12 of bias compensation circuit 104 or bias compensation circuit 134). Any number or type of other signals may be received.

[0103] In some embodiments, the first HV signal 405A or the second HV signal 405B may include a voltage signal provided to a load. In some embodiments, the first HV signal 405A or the second HV signal 405B may include a voltage signal provided to a bias compensation circuit. In some embodiments, the first HV signal 405A or the second HV signal 405B may include a voltage signal provided to a pulse generator and the transformer stage may be a voltage signal to be measured. In some embodiments, the first HV signal 405A or the second HV signal 405B may include a voltage signal provided to a resistive output stage or an energy recovery circuit.

[0104] The first HV signal 405A and the second HV signal 405B may be collectively or individually referred to as the HV input signal 405. The HV signal 405 may provide waveforms from the bias generator 115 and / or the RF plasma generator 105.

[0105] In some embodiments, the HV input signal 405 may be divided in voltage at the voltage divider 410. For example, the voltage divider 410 may include a high-value resistor or a low-value capacitor to divide a high-voltage HV input signal (e.g., greater than 1 KV) into a low-voltage signal (e.g., less than 50 V). For example, the voltage divider 410 may divide the voltage with a ratio of 500:1, 1,000:1, 10,000:1, 100,000:1, etc. For example, the voltage divider 410 may divide the voltage of the HV input signal 405 of 0 - 10 kV into a voltage of 0 - 20 V. For example, the voltage divider 410 may divide the voltage with a minimum power loss (e.g., a power loss of less than about 5 W).

[0106] In some embodiments, the voltage divider 410 may include a low-value capacitor, a large-value capacitor, a low-value resistor, and a large-value resistor. For example, the low-value capacitor may include a capacitor having a capacitance value of about 0.1 pF, 0.5 pF, 1.0 pF, 2.5 pF, 5.0 pF, 10.0 pF, 100 pF, 1 nF, 10 nF, etc. For example, the value capacitor may include a capacitor having a capacitance value of about 500 pF. In some embodiments, the large-value capacitor may have a capacitance value greater than that of the low-value capacitor of about 50, 100, 250, 500, 1,000, 2,500, 5,000 pF, etc.

[0107] Low-value resistors can have resistance values of approximately 1.0 kΩ, 2.5 kΩ, 5.0 kΩ, 10 kΩ, 25 kΩ, 50 kΩ, 100 kΩ, etc. High-value resistors can have resistance values of approximately 0.5 MΩ, 1.0 MΩ, 2.5 MΩ, 5.0 MΩ, 10 MΩ, 25 MΩ, 50 MΩ, 100 MΩ, etc. In some embodiments, high-value resistors can have resistance values greater than those of low-value resistors, such as approximately 50 Ω, 100 Ω, 250 Ω, 500 Ω, 1,000 Ω, 2,500 Ω, 5,000 Ω, etc. In some embodiments, the ratio of low-value capacitors to high-value capacitors can be substantially the same as the ratio of low-value resistors to high-value resistors.

[0108] In some embodiments, the voltage divider 410 can receive an HV input signal and output a divided voltage signal. For example, the divided voltage signal can be 100, 250, 500, 750, 1,000, etc. times smaller than the HV input signal.

[0109] In some embodiments, a filter 415 can be included, for example, to filter any noise from the divided voltage signal. For example, the filter can include any type of low-pass filter, band-pass filter, band-stop filter, or high-pass filter.

[0110] In some embodiments, the divided voltage signal can be digitized by a first ADC 420. The first ADC 420 can include an analog-to-digital converter. Any type of analog-to-digital converter can be used. The first ADC 420 can generate a digitized waveform signal. In some embodiments, the first ADC 420 can capture data at 100, 250, 500, 1,000, 2,000, 5,000 MSPS (mega samples per second or million samples per second). In some embodiments, the digitized waveform signal can be transmitted to the controller 120 using any type of communication protocol (e.g., SPI, UART, RS-232, USB, I2C, etc.).

[0111] In some embodiments, any one of the voltage divider 410, the filter 415, or the first ADC 420 can be isolated from the bias generator 115 via galvanic isolation or via an optical fiber link.

[0112] In some embodiments, the controller 120 can send and / or receive signals or data to / from the RF plasma generator 105. For example, the controller 120 can send a timing signal to the RF plasma generator 105, which commands the RF plasma generator regarding burst repetition frequency, burst voltage, burst frequency, burst duty cycle, burst duration, etc.

[0113] In some embodiments, the controller 120 may send and / or receive signals or data to / from the bias generator 115 via output 435. For example, the controller 120 may send a timing signal to the bias generator 115, which instructs the bias generator regarding the burst repetition frequency, burst voltage, burst frequency, burst duty cycle, burst duration, etc.

[0114] In some embodiments, the controller 120 may receive a trigger signal from the trigger 430. In other embodiments, the first ADC 420 may receive a trigger signal from the trigger 430. The trigger signal may provide the timing for data acquisition at the first ADC 420. For example, the trigger signal may be a 5V TTL trigger. For example, the trigger signal may have a 50-ohm termination.

[0115] The digitized signal may then be output from the controller 120 via one or more output ports (e.g., such as the first output 435A or the second output 435B (individually or jointly, output 435)). These outputs may be coupled to one or more nanosecond pulse generators (e.g., the bias generator 115). One or both of the outputs 435 may include an electrical connector (e.g., such as an LVDS, TTL, LVTTL connector). One or both of the outputs 435 may use any type of communication protocol (e.g., such as SPI, UART, RS-232, USB, I2C, EtherCat, Ethernet, Profibus, PROFINET) to provide data to the nanosecond pulse generator controller.

[0116] In some embodiments, the plasma control system 400 may be coupled to the bias generator 115 via a 4mm Multilam container on the plasma control system 400.

[0117] In some embodiments, the plasma control system 400 may include a second ADC 445, which may receive inputs from the first sensor 450A and the second sensor 450B (individually or jointly, sensor 450) (or any number of sensors). The second ADC 445 may include an analog-to-digital converter. In some embodiments, the second ADC 445 may digitize the analog signals from the sensor 450. For example, the sensor 450 may include sensors that sense the inlet water temperature, dielectric fluid temperature, dielectric fluid pressure, chassis air temperature, voltage, fluid flow, flow leak sensors, etc. In some embodiments, the second ADC445 may include an ARM, PIC32, AVR, PSOC, or PIC32.

[0118] In some embodiments, the second ADC 445 and the first ADC 420 may include a single ADC device. In some embodiments, one or both of the second ADC 445 or the first ADC 420 may be part of the controller 120. In some embodiments, the first ADC 420 may operate at a higher acquisition rate than the second ADC.

[0119] In some embodiments, the control system may measure the full width at half maximum, peak voltage, DC bias, rise time, fall time, etc. of the pulses in the bias generator 115.

[0120] In some embodiments, the plasma control system 400 may monitor the voltage, frequency, pulse width, etc. of the pulses and, in response thereto, may adjust the voltage, pulse repetition frequency, pulse width, burst repetition frequency (where a burst includes multiple pulses), RF burst on time, RF burst off time, bias burst on time, bias burst off time, etc. of the inputs provided to the bias generator 115 and / or the RF plasma generator 105. For example, the first ADC 420 may monitor the voltage amplitude of the waveform. This voltage data may be provided to the controller 120, which may communicate with the nanosecond pulse generator or the RF plasma generator to adjust the amplitude or frequency of the signal.

[0121] In some embodiments, the plasma control system 400 may output any pulse signal to one or more bias generators 115 via the output 435. For example, the output 435 may include an optical fiber or an electrical connection. In some embodiments, the plasma control system 400 may include multiple output pulse channels (e.g., 1, 2, 5, 8, 20, 50, 100, etc.) that may be independent of each other. For example, the multiple output pulse channels may output pulses with sub-nanosecond resolution.

[0122] For example, if the pulse voltage is less than a predetermined voltage, the controller 120 may send a signal to the bias generator 115 or the RF plasma generator 105 to generate a pulse with a higher voltage. If the pulse voltage is greater than the predetermined voltage, the first ADC 420 may send a signal to the bias generator 115 or the RF plasma generator 105 to generate a pulse with a lower voltage. In some embodiments, the signal to the nanosecond pulser to increase the pulse voltage may include a low voltage pulse with a longer pulse width than the previously sent signal, and the signal to the nanosecond pulser to decrease the pulse voltage may include a low voltage pulse with a shorter pulse width than the previously sent signal.

[0123] As another example, if the pulse repetition frequency is greater than the desired pulse repetition frequency, the controller 120 may send a signal to the bias generator 115 or the RF plasma generator 105 to generate pulses with a lower frequency. If the burst repetition frequency is less than the desired burst repetition frequency, the controller 120 may send a signal to the bias generator 115 or the RF plasma generator 105 to generate bursts with a higher burst repetition frequency. If the measured full width at half maximum of the pulse is different from the desired burst repetition frequency, the controller 120 may send a signal to the bias generator 115 or the RF plasma generator 105 to generate pulses with an adjusted pulse width or pulse repetition frequency.

[0124] As another example, if the waveform pulse width is longer than the desired pulse width, the first ADC 420 may send a signal to the bias generator 115 or the RF plasma generator 105 to generate a waveform with a shorter or longer pulse width. If the waveform duty cycle is shorter than or longer than the desired duty cycle, the first ADC 420 may send a signal to the bias generator 115 or the RF plasma generator 105 to generate pulses with an appropriate duty cycle.

[0125] The plasma control system 400 may monitor other waveform characteristics and / or adjust these other characteristics.

[0126] In some embodiments, the plasma control system 400 may output any pulse signal to one or more bias generators 115 or RF plasma generators 105 via the output 435. For example, the control system may include any RF plasma generator. For example, the output 435 may include an optical fiber or an electrical connection. In some embodiments, the plasma control system 400 may include a plurality of output pulse channels (e.g., 1, 2, 5, 8, 20, 50, 100, etc.) that may be independent of each other. For example, the plurality of output pulse channels may output pulses with sub - nanosecond resolution. In some embodiments, the plasma control system 400 may output pulses with a resolution of less than about 0.1 ns. In some embodiments, the plasma control system 400 may output pulses with a jitter of less than about 100 ps.

[0127] In some embodiments, each output pulse channel of the plasma control system 400 may output a pulse to trigger the bias generator 115 to the bias generator 115. For example, the plasma control system 400 may adjust the parameters of the output pulse in real - time or between pulses. These parameters may include pulse width, pulse repetition frequency, duty cycle, burst repetition frequency, voltage, the number of pulses in a burst, the number of bursts, etc. In some embodiments, one or more parameters may be adjusted or changed based on the input to the plasma control system 400 or based on a recipe or program.

[0128] For example, the recipe can include alternating high bursts and low bursts from the bias generator 115. For example, a high burst can include a plurality of high voltage pulses. For example, a low burst can include a plurality of lower voltage pulses. For example, the high bursts and low bursts can include the same number of pulses or different numbers of pulses within each burst. For example, the low burst can have a voltage that is 10%, 20%, 30%, 40%, 50%, etc. lower than the voltage of the high burst.

[0129] The alternating high bursts and low bursts from the bias generator 115 can include a ratio of low burst to high burst (low-high ratio) of 5%, 20%, 50%, 100%, 125%, 150%, etc. For example, a 20% low-high ratio can include a sequence of 10 bursts, where each burst includes approximately 500 pulses (or any number of pulses from 1 to 10,000 pulses). In a sequence of 10 bursts with a 10% low-high ratio, 2 bursts can be low voltage bursts and 8 bursts can be high voltage bursts.

[0130] In some embodiments, the controller 120 can deliver pulses with longer low voltage pulses to the nanosecond pulse generator to generate high bursts, and deliver pulses with shorter low voltage pulses to generate low bursts, thereby generating alternating high bursts and low bursts, as described in U.S. Patent Application No. 16 / 114,195, titled "ARBITRARY WAVEFORM GENERATION USING NANOSECOND PULSES", which is incorporated herein by reference for all purposes.

[0131] In some embodiments, one of the sensors 450 can include a DC voltage sensor, which can be coupled to the DC power supply in the bias generator 115. For example, if multiple DC power supply systems are used in the bias generator 115 and, during operation, the voltage changes by more than a set percentage (e.g., 1%, 5%, 10%, 20%, etc.) or more than an absolute voltage (e.g., 5V, 10V, 50V, 100V, etc.), then the controller 120 can turn off the bias generator 115. As another example, if a power supply system is used and, during operation, the voltage output differs from the set voltage by more than a certain percentage (e.g., 1%, 5%, 10%, 20%, etc.) or differs from the set voltage by more than an absolute voltage (e.g., 5V, 10V, 50V, 100V, etc.), then the controller 120 can turn off the pulses.

[0132] In some embodiments, the controller 120 may send and / or receive communications and / or commands from an external controller 465 (e.g., an industrial controller). In some embodiments, the external controller 465 may communicate with the controller 120 via an EtherCat module. In some embodiments, the EtherCat module may include any type of communication module. In some embodiments, EtherCat may include one or more components of the computing system 2600.

[0133] In some embodiments, the control system may control the operation of the pulse generation system (e.g., such as pulse width, duty cycle, high voltage set point, on / off, return current output voltage, high voltage current set point, return current output current, enabling high voltage output, returning high voltage enabling state, emergency shutdown, etc.).

[0134] Figure 5 is a process 500 for controlling the plasma system 100 according to some embodiments. In some embodiments, the process 500 may be executed by the controller 120.

[0135] The process 500 begins at block 505. At block 505, the controller 120 may begin driving the RF plasma generator 105 to create a first RF burst. For example, the first RF burst may include a waveform similar to the RF waveform 305. The first RF burst may include RF burst parameters (e.g., such as RF frequency and / or RF voltage). The first burst from the RF plasma generator 105 may create plasma within the chamber 110.

[0136] At block 510, the process 500 may pause for a first time period. For example, the first time period may be between approximately 10 μs and approximately 10 ms. In some embodiments, the first time period may be 0 seconds. The first time period may be the time between the start of the RF waveform 305 (e.g., t1 or RF burst on time) and the start of the bias burst 310 (e.g., t2 or bias burst on time).

[0137] At block 515, the controller 120 may pulse the bias generator 115 to create a first bias burst. For example, the first bias burst may include a waveform similar to the bias burst 310. The first bias burst may include bias burst parameters (e.g., such as pulse repetition frequency and / or bias voltage).

[0138] At block 520, the process 500 may pause for a second time period. For example, the second time period may be between approximately 10 μs and approximately 10 ms. The second time period may be the time between the start of the bias burst 310 (e.g., t2 or bias burst on time) and the end of the RF waveform 305 (e.g., t3 or RF burst off time).

[0139] At block 525, the RF plasma generator can stop driving the chamber with the RF waveform. For example, the controller can send a signal to the RF plasma generator 105 to end the burst.

[0140] At block 530, process 500 can pause for a third time period. For example, the third time period can be between about 10 μs and about 10 ms. For example, the third time period can be zero seconds. The third time period can be the time between the end of the RF waveform 305 (e.g., t3 or RF burst off time) and the end of the bias burst 310 (e.g., t4 or bias burst off time). In some embodiments, the first time period, the second time period, or the third time period can be the same. In some embodiments, the first time period, the second time period, or the third time period can be different.

[0141] At block 535, the bias generator 115 can stop generating pulses. For example, the controller can send a signal to the bias generator 115 to end the burst and interrupt the generation of pulses.

[0142] At block 540, process 500 can pause for a fourth time period. For example, the fourth time period can be the time between the end of the bias burst 310 (e.g., t4 or bias burst off time) and the start of the next RF burst or the start of the next RF waveform 305 (e.g., t1 for the next RF waveform or RF burst on time for the next RF waveform). In some embodiments, the fourth time period can be greater than the first time period, the second time period, and / or the fourth time period. The fourth time period can define the duty cycle of the RF waveform and / or the duty cycle of the bias burst.

[0143] At block 545, process parameters can be changed. The process parameters can include RF parameters, bias parameters, the first time period, the second time period, the third time period, the fourth time period, etc. In some embodiments, the RF parameters and / or the bias parameters (e.g., such as RF voltage, bias voltage, RF frequency, pulse repetition frequency, temperature, pressure, etc.) can be changed based on feedback from the chamber. In some embodiments, the RF parameters and / or the bias parameters can be changed based on feedback from the chamber via the HV signal 405 or the sensor 450.

[0144] After block 545, the process can repeat.

[0145] Figure 6 is a circuit diagram of a bias generator 600 according to some embodiments.

[0146] In this example, the bias generator 600 can include an RF driver 605. For example, the RF driver 605 can be a half-bridge driver or a full-bridge driver, as Figure 6As shown. The RF driver 605 may include an input voltage source V1, which may be a DC voltage source (e.g., a capacitive source, an AC-DC converter, etc.). In some embodiments, the RF driver 605 may include four switches S1, S2, S3, and S4. In some embodiments, the RF driver 605 may include a plurality of switches S1, S2, S3, and S4 in series or in parallel. For example, the switches S1, S2, S3, and S4 may include any type of solid-state switch (e.g., such as IGBT, MOSFET, SiCMOSFET, SiC junction transistor, FET, SiC switch, GaN switch, photoconductive switch, etc.). The switches S1, S2, S3, and S4 may be switched at high frequencies and / or may generate high voltage pulses. For example, these frequencies may include frequencies such as approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0147] Each of the switches S1, S2, S3, and S4 may be coupled in parallel with a respective diode D1, D2, D3, and D4 and may include stray inductance represented by inductors L1, L2, L3, and L4. In some embodiments, the inductances of the inductors L1, L2, L3, and L4 may be equal. In some embodiments, the inductances of the inductors L1, L2, L3, and L4 may be less than approximately 50 nH, 100 nH, 150 nH, 500 nH, 1,000 nH, etc. The combination of a switch (S1, S2, S3, or S4) and the respective diode (D1, D2, D3, or D4) may be coupled in series with the respective inductor (L1, L2, L3, or L4). Inductors L3 and L4 are connected to ground. Inductor L1 is connected to switch S4 and the resonant circuit 610. Inductor L2 is connected to switch S3 and the opposite side of the resonant circuit 610.

[0148] In some embodiments, the RF driver 605 can be coupled to a resonant circuit 610. The resonant circuit 610 can include a resonant inductor L5 and / or a resonant capacitor C2 coupled to a transformer T1. The resonant circuit 610 can include a resonant resistor R5, which can include, for example, the stray resistance of any leads between the RF driver 605 and the resonant circuit 610 and / or any components within the resonant circuit 610 (such as, for example, the transformer T1, the capacitor C2, and / or the inductor L5). In some embodiments, the resonant resistor R5 includes only the stray resistance of wires, traces, or circuit elements. Although the inductance and / or capacitance of other circuit elements can affect the drive frequency, the drive frequency can be set to a large extent by selecting the resonant inductor L5 and / or the resonant capacitor C2. Given the stray inductance or stray capacitance, further refinement and / or tuning may be required to create the correct drive frequency. Additionally, the rise time across the transformer T1 can be adjusted by changing L5 and / or C2, provided that:

[0149]

[0150] These values may also affect the burst envelope. As Figure 7 shown, each burst can include transient and steady-state pulses. The transient pulses within each burst can be set by the system's L5 and / or Q until full voltage is reached during the steady-state pulses.

[0151] If the switches in the RF driver 605 switch at the resonant frequency f resonant then the output voltage at the transformer T1 will be amplified. In some embodiments, the resonant frequency can be approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0152] In some embodiments, the resonant capacitor C2 can include the stray capacitance of the transformer T1 and / or a physical capacitor. In some embodiments, the resonant capacitor C2 can have a capacitance of approximately 10 μF, 1 μF, 100 nF, 10 nF, etc. In some embodiments, the resonant inductor L5 can include the stray inductance of the transformer T1 and / or a physical inductor. In some embodiments, the resonant inductor L5 can have an inductance of approximately 50 nH, 100 nH, 150 nH, 500 nH, 1,000 nH, etc. In some embodiments, the resonant resistor R5 can have a resistance of approximately 10 ohms, 25 ohms, 50 ohms, 100 ohms, 150 ohms, 500 ohms, etc.

[0153] In some embodiments, the resonant resistor R5 may represent the stray resistance of wires, traces, and / or transformer windings within a physical circuit. In some embodiments, the resonant resistor R5 may have a resistance of approximately 10 mOhm, 50 mOhm, 100 mOhm, 200 mOhm, 500 mOhm, etc.

[0154] In some embodiments, the transformer T1 may include a transformer as disclosed in U.S. Patent Application No. 15 / 365,094 titled “High Voltage Transformer,” which is incorporated herein by reference for all purposes. In some embodiments, the output voltage of the resonant circuit 610 may be changed by varying the duty cycle of switches S1, S2, S3, and / or S4 (e.g., the “on” time of the switch or the time the switch is conducting positively). For example, the longer the duty cycle, the higher the output voltage; and the shorter the duty cycle, the lower the output voltage. In some embodiments, the output voltage of the resonant circuit 610 may be changed or tuned by adjusting the duty cycle of the switches in the RF driver 605.

[0155] For example, the duty cycle of the switches may be adjusted by: changing the duty cycle of the signal Sig1 that turns on and off the switch S1; changing the duty cycle of the signal Sig2 that turns on and off the switch S2; changing the duty cycle of the signal Sig3 that turns on and off the switch S3; and changing the duty cycle of the signal Sig4 that turns on and off the switch S4. For example, by adjusting the duty cycle of switches S1, S2, S3, or S4, the output voltage of the resonant circuit 610 may be controlled.

[0156] In some embodiments, each of the switches S1, S2, S3, or S4 in the RF driver 605 may be switched independently or in combination with one or more of the other switches. For example, the signal Sig1 may be the same signal as the signal Sig3. As another example, the signal Sig2 may be the same signal as the signal Sig4. As another example, each signal may be independent, and each of the switches S1, S2, S3, or S4 may be controlled independently or separately.

[0157] In some embodiments, the resonant circuit 610 may be coupled to a half-wave rectifier 615 that may include a choke diode D7.

[0158] In some embodiments, the half-wave rectifier 615 may be coupled to a resistive output stage 620. The resistive output stage 620 may include any resistive output stage known in the art. For example, the resistive output stage 620 may include any resistive output stage described in U.S. Patent Application No. 16 / 178,538 titled “HIGHVOLTAGE RES1STIVE OUTPUT STAGE CIRCUIT,” which is incorporated herein by reference in its entirety for all purposes.

[0159] For example, the resistive output stage 620 may include inductor L11, resistor R3, resistor R1, and capacitor C11. In some embodiments, inductor L11 may have an inductance of from about 5 μH to about 25 μH. In some embodiments, resistor R1 may have a resistance of from about 50 ohms to about 250 ohms. In some embodiments, resistor R3 may include the stray resistance in the resistive output stage 620.

[0160] In some embodiments, resistor R1 may include a plurality of resistors arranged in series and / or parallel. Capacitor C11 may represent the stray capacitance of resistor R1, which includes the capacitance of the arrangement of series and / or parallel resistors. For example, the capacitance of the stray capacitance C11 may be less than 500 pF, 250 pF, 100 pF, 50 pF, 10 pF, 1 pF, etc. For example, the capacitance of the stray capacitance C11 may be less than the load capacitance (e.g., less than the capacitance of C2, C3, and / or C9).

[0161] In some embodiments, resistor R1 may discharge a load (e.g., the plasma sheath capacitance). In some embodiments, the resistive output stage 620 may be configured to discharge at an average power of more than about 1 kilowatt during each pulse period and / or with an energy of one joule or less in each pulse period. In some embodiments, the resistance of resistor R1 in the resistive output stage may be less than 200 ohms. In some embodiments, resistor R1 may include a plurality of resistors arranged in series or parallel and having a combined capacitance (e.g., C11) of less than about 200 pF.

[0162] In some embodiments, the resistive output stage 620 may include a set of circuit elements that can be used to control the shape of the voltage waveform on the load. In some embodiments, the resistive output stage 620 may include only passive elements (e.g., resistors, capacitors, inductors, etc.). In some embodiments, the resistive output stage 620 may include active circuit elements (e.g., switches) and passive circuit elements. In some embodiments, for example, the resistive output stage 620 may be used to control the voltage rise time and / or the voltage fall time of the waveform.

[0163] In some embodiments, the resistive output stage 620 may discharge a capacitive load (e.g., a wafer and / or a plasma). For example, these capacitive loads may have a small capacitance (e.g., about 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0164] In some embodiments, a resistive output stage can be used in a circuit having pulses with a high pulse voltage (e.g., a voltage greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.) and / or a high frequency (e.g., a frequency greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.) and / or a frequency of about 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0165] In some embodiments, a resistive output stage can be selected to handle high average power, high peak power, fast rise time, and / or fast fall time. For example, the average rated power can be greater than about 0.5 kW, 1.0 kW, 10 kW, 25 kW, etc., and / or the peak rated power can be greater than about 1 kW, 10 kW, 100 kW, 1 MW, etc.

[0166] In some embodiments, the resistive output stage 620 can include a series or parallel network of passive components. For example, the resistive output stage 620 can include a series of resistors, capacitors, and inductors. As another example, the resistive output stage 620 can include a capacitor in parallel with an inductor and a capacitor - inductor combination in series with a resistor. For example, L11 can be selected to be large enough such that when there is a voltage leaving the rectifier, no significant energy is injected into the resistive output stage. The values of R3 and R1 can be selected such that the L / R time can deplete the appropriate capacitor in the load faster than the RF frequency.

[0167] In some embodiments, the resistive output stage 620 can be coupled to a bias compensation circuit 625. The bias compensation circuit 625 can include any bias and / or bias compensation circuit known in the art. For example, the bias compensation circuit 625 can include any bias and / or bias compensation circuit described in U.S. Patent Application No. 16 / 523,840 entitled “NANOSECOND PULSER BIAS COMPENSATION,” which is incorporated herein by reference in its entirety for all purposes.

[0168] In some embodiments, the bias compensation circuit 625 may include a bias capacitor C7, a choke capacitor C12, a choke diode D8, a switch S8 (e.g., a high voltage switch), a bias supply voltage V1, a resistor R2, and / or a resistor R4. In some embodiments, the switch S8 includes the high voltage switch described in U.S. Patent Application No. 62 / 717,637 entitled "HIGH VOLTAGE SWITCH FOR NANOSECOND PULSING" and / or U.S. Patent Application No. 16 / 178,565 entitled "HIGH VOLTAGE SWITCH FOR NANOSECOND PULSING", which is incorporated herein by reference in its entirety for all purposes.

[0169] In some embodiments, the offset supply voltage V5 may include a DC voltage source, which may forward bias or reverse bias the output voltage. In some embodiments, the capacitor C12 may isolate / separate the offset supply voltage V5 from the resistive output stage 620 and / or other circuit elements. In some embodiments, the bias compensation circuit 625 may allow the potential transfer of power from one part of the circuit to another part. In some embodiments, when the high voltage pulse is effective in the chamber, the bias compensation circuit 625 may be used to hold the wafer in place. The resistor R2 may protect / isolate the DC bias supply from the driver.

[0170] In some embodiments, the switch S8 may be opened while the RF driver 605 is pulsing, and closed when the RF driver 605 is not pulsing. While closed, for example, the switch S8 may short-circuit the current across the choke diode D8. Short-circuiting this current may allow the bias between the wafer and the chuck to be less than 2 kV, which may be within an acceptable tolerance.

[0171] In some embodiments, the plasma and chamber 630 may be coupled to the bias compensation circuit 625. For example, the plasma and chamber 630 may be represented by Figure 6 the various circuit elements shown.

[0172] Figure 6 do not include a conventional matching network (e.g., such as a 50 ohm matching network or an external matching network or a stand-alone matching network). In fact, the embodiments described in this document do not require a 50 ohm matching network to tune the switching power applied to the wafer chamber. Additionally, the embodiments described in this document provide a variable output impedance RF generator without a conventional matching network. This may allow for a rapid change in the power extracted by the plasma chamber. Typically, such tuning of the matching network may take at least 100 μs - 200 μs. In some embodiments, the power change may occur within one or two RF cycles (e.g., 2.5 μs - 5.0 μs at 400 kHz).

[0173] Figure 7 is a waveform of the voltage across transformer T1 (red), at the post (green), and at the wafer (blue) spanning a 600 μs time frame. Figure 8 is an enlarged view of the waveform over a 10 μs time frame.

[0174] Figure 9 is a circuit diagram of a bias generator 900 according to some embodiments. For example, bias generator 900 may include an RF driver 605, a resonant circuit 610, a bias compensation circuit 625, and a plasma and chamber 630. Bias generator 900 is similar to bias generator 600, but does not include a resistive output stage 620 and includes an energy recovery circuit 905.

[0175] In this example, energy recovery circuit 905 may be located on the secondary side of transformer T1 or be electrically coupled thereto. For example, energy recovery circuit 905 may include a diode D9 (e.g., a crowbar diode) across the secondary side of transformer T1. For example, energy recovery circuit 905 may include diode D10 and inductor L12 (arranged in series), which may allow current to flow from the secondary side of transformer T1 to charge power supply C15 and allow current to flow to plasma and chamber 630. Diode D12 and inductor L12 may be electrically connected to the secondary side of transformer T1 and coupled to power supply C15. In some embodiments, energy recovery circuit 905 may include diode D13 and / or inductor L13 electrically coupled to the secondary of transformer T1. Inductor L12 may represent the stray inductance of transformer T1 and / or may include stray inductance.

[0176] When the nanosecond pulse generator is turned on, current may charge the plasma and chamber 630 (e.g., charge capacitor C3, capacitor C2, or capacitor C9). For example, when the voltage on the secondary side of transformer T1 rises above the charging voltage on power supply C15, some current may flow through inductor L12. When the nanosecond pulse generator is turned off, current may flow from the inductor within plasma and chamber 630 through inductor L12 to charge power supply C15 until the voltage across inductor L12 is zero. Diode D9 may prevent the capacitor within plasma and chamber 630 from ringing with the inductance in plasma and chamber 630 or bias compensation circuit 625.

[0177] For example, diode D12 may prevent charge from flowing from power supply C15 to the capacitor within plasma and chamber 630.

[0178] The value of inductor L12 can be selected to control the current fall time. In some embodiments, inductor L12 can have an inductance value between 1 μH and 500 μH.

[0179] In some embodiments, energy recovery circuit 905 can include a switch that can be used to control the flow of current through inductor L12. For example, the switch can be placed in series with inductor L12. In some embodiments, the switch can be closed when switch S1 is opened and / or no longer pulsed to allow current to flow from the plasma and chamber 630 back to power supply C15.

[0180] For example, the switch in energy recovery circuit 905 can include a high-voltage switch, such as the high-voltage switch disclosed in U.S. Patent Application No. 16 / 178,565, filed on November 1, 2018, titled “HIGH-VOLTAGE SWITCH WITH ISOLATED POWER,” which claims priority to U.S. Provisional Patent Application No. 62 / 717,637, filed on August 10, 2018, both of which are incorporated herein by reference in their entirety. In some embodiments, RF driver 605 can also include a high-voltage switch that replaces or supplements the various components shown in RF driver 605. In some embodiments, using a high-voltage switch can allow at least the removal of transformer T1 and switch S1.

[0181] Figure 10 is a circuit diagram of bias generator 1000 according to some embodiments. For example, bias generator 1000 can include RF driver 605, resonant circuit 610, resistive output stage 620, and plasma and chamber 630. Thus, bias generator 1000 is similar to bias generator 600 without bias compensation circuit 625.

[0182] Figure 11 is a circuit diagram of bias generator 1000 according to some embodiments. For example, bias generator 1100 can include RF driver 605, resonant circuit 610, energy recovery circuit 905, and plasma and chamber 630. Thus, bias generator 1100 is similar to bias generator 900 without bias compensation circuit 625.

[0183] Figure 126 is a circuit diagram of an RF plasma generator 1200 according to some embodiments. For example, the RF plasma generator 1200 may include an RF driver 605, a resonant circuit 610, and an inductive discharge plasma 1205. In this example, the inductor L5 may include an antenna coupled to or disposed within the inductive discharge plasma 1205. The transformer T1 may represent how the inductive discharge plasma 1205 is coupled to the antenna represented at least in part by the inductor L5. The capacitor C2 may resonate with the inductor L5 to determine the resonant frequency. The RF driver 605 may generate pulses driven by the resonant frequency.

[0184] Figure 13 1 is a circuit diagram of an RF plasma generator 1200 according to some embodiments. For example, the RF plasma generator 1200 may include an RF driver 1305, a resonant circuit 1310 (which may include a transformer), and a chamber 630. Capacitor C1 may represent the capacitance of the discharge geometry, any stray capacitance in the circuit, or the capacitance of any capacitor in the circuit. L5 may represent the inductance of any stray inductance in the circuit or the inductance of any inductance in the circuit. The RF driver 1305 may drive the resonant circuit 1310 with a pulse frequency substantially equal to the resonant frequency of the resonant circuit.

[0185] In some embodiments, each switch S1, S2, S3, or S4 in the RF driver 1305 can be switched independently or in combination with one or more of the other switches. For example, the signal Sig1 can be the same signal as the signal Sig3. As another example, the signal Sig2 can be the same signal as the signal Sig4. As another example, each signal can be independent and can control each switch S1, S2, S3, or S4 independently or separately.

[0186] In some embodiments, the transformer T1 may or may not be included in the RF plasma generator 1200 .

[0187] Figure 14A , Figure 14B , Figure 15A and Figure 15B Can be replaced Figure 6 6. Circuit diagrams of example resonant circuits used in the resonant circuit 610 of FIG. These circuits may or may not include the transformers shown in each figure.

[0188] Figure 16 is a circuit diagram of a bias generator 1600 , which includes a nanosecond pulse generator stage 101 with an energy recovery circuit 1610 , a transformer T1 , a lead stage 103 , a DC bias circuit 104 , and a load stage 106 .

[0189] In some embodiments, the load stage 106 may represent an idealized or effective circuit for a semiconductor processing chamber (e.g., such as a plasma deposition system, a semiconductor manufacturing system, a plasma sputtering system, etc.). For example, the capacitor C2 may represent the capacitance of an electrostatic chuck on which a semiconductor process wafer may be seated. For example, the chuck may include a dielectric material (e.g., alumina or other ceramic material and a conductor housed within the dielectric material). For example, the capacitor C1 may have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0190] For example, the capacitor C3 may represent the sheath capacitance between the plasma and the wafer. For example, the resistor R6 may represent the sheath resistance between the plasma and the wafer. For example, the inductor L2 may represent the sheath inductance between the plasma and the wafer. For example, the current source I2 may represent the ion current through the sheath. For example, the capacitor C1 or the capacitor C3 may have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0191] For example, the capacitor C9 may represent the plasma sheath capacitance to the walls of the chamber. For example, the resistor R7 may represent the resistance between the plasma and the chamber walls. For example, the current source I1 may represent the ion current in the plasma. For example, the capacitor C1 or the capacitor C9 may have a small capacitance (e.g., approximately 10 pF, 100 pF, 500 pF, 1 nF, 10 nF, 100 nF, etc.).

[0192] In some embodiments, the plasma voltage may be the voltage measured from ground to circuit point 123; the wafer voltage is the voltage measured from ground to circuit point 122 and may represent the voltage at the surface of the wafer; the chuck voltage is the voltage measured from ground to circuit point 121; the electrode voltage is (e.g., on the electrode) the voltage measured from ground to the circuit point labeled 124; and the input voltage is the voltage measured from ground to circuit point 125.

[0193] In this example, the DC bias circuit 104 does not include any bias compensation. The DC bias circuit 104 includes an offset supply voltage V5, which may bias the output voltage, for example, positively or negatively. In some embodiments, the offset supply voltage V5 may be adjusted to change the potential between the wafer voltage and the chuck voltage. In some embodiments, the offset supply voltage V5 may have a voltage of approximately ±5 kV, ±4 kV, ±3 kV, ±2 kV, ±1 kV, etc.

[0194] In some embodiments, the biasing capacitor C12 can isolate (or separate) the DC bias voltage from other circuit elements. For example, the biasing capacitor C12 can allow the transfer of electrical potential from one part of the circuit to another. In some embodiments, such electrical potential transfer can ensure that the electrostatic force holding the wafer in place on the chuck remains below a voltage threshold. The resistor R2 can isolate the DC bias power supply from the high voltage pulsed output from the pulse generator stage 101.

[0195] For example, the biasing capacitor C12 can have a capacitance less than about 100 pF, 10 pF, 1 pF, 100 μF, 10 μF, 1 μF, etc. For example, the resistor R2 can have a high resistance (e.g., a resistance such as about 1 kΩ, 10 kΩ, 100 kΩ, 1 MΩ, 10 MΩ, 100 MΩ, etc.).

[0196] For example, the resistor R13 can represent the resistance of a lead or transmission line connecting the output of the high voltage power system to an electrode (e.g., the load stage 106). For example, the capacitor C1 can represent the stray capacitance in a lead or transmission line.

[0197] In some embodiments, the nanosecond pulse generator stage 101 can generate pulses having a high pulse voltage (e.g., a voltage greater than 1 kV, 10 kV, 20 kV, 50 kV, 100 kV, etc.), a high frequency (e.g., a frequency greater than 1 kHz, 10 kHz, 100 kHz, 200 kHz, 500 kHz, 1 MHz, etc.), a fast rise time (e.g., a rise time less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.), a fast fall time (e.g., a fall time less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.) and / or a short pulse width (e.g., a pulse width less than about 1,000 ns, 500 ns, 250 ns, 100 ns, 20 ns, etc.).

[0198] For example, the nanosecond pulse generator stage 101 may include all or any part of any device described in U.S. patent application serial number 14 / 542,487, titled "High Voltage Nanosecond Pulser", which is incorporated herein by reference for all purposes; or all or any part of any device described in U.S. patent application serial number 14 / 635,991, titled "Galvanically Isolated Output Variable Pulse Generator Disclosure", which is incorporated herein by reference for all purposes; or all or any part of any device described in U.S. patent application serial number 14 / 798,154, titled "High Voltage Nanosecond Pulser With Variable Pulse Width and Pulse Repetition Frequency", which is incorporated herein by reference for all purposes.

[0199] In some embodiments, the nanosecond pulse generator stage 101 may include one or more nanosecond pulse generators coupled together in various ways.

[0200] In some embodiments, the nanosecond pulse generator stage 101 may include a DC power supply that provides a consistent DC voltage, which is switched by switch S6 and supplies the switched power to transformer T1. The DC power supply may include voltage source V5 and energy storage capacitor C7. If transformer T1 has a turns ratio of 1:10, the transformer may generate 10 kV across load C1.

[0201] In some embodiments, if the load capacitance (e.g., capacitance C3 and capacitance C9) is small compared to the capacitance of energy storage capacitor C7, voltage doubling may (or may not) occur at the transformer input. For example, if energy storage capacitor C7 provides 500 V, 1 kV may be measured at the input of transformer T1.

[0202] For example, switch S1 may include one or more solid-state switches (e.g., such as IGBT, MOSFET, SiC MOSFET, SiC junction transistor, FET, SiC switch, GaN switch, photoconductive switch, etc.). Switch S6 may be switched based on signals from a controller labeled Sig6+ and Sig6-.

[0203] In some embodiments, the nanosecond pulser stage 101 may include a buffer circuit, which may include any type of buffer circuit. In some embodiments, the buffer circuit may include a capacitor. In some embodiments, the buffer circuit may include a capacitor and a resistor. In some embodiments, the buffer circuit may include a capacitor, an inductor, and a resistor.

[0204] In some embodiments, the buffer circuit may include a buffer resistor R3 and a buffer capacitor C5 in parallel with a buffer diode D4. The buffer circuit may also include stray inductance. In some embodiments, the buffer resistor R3 and / or the buffer diode D4 may be placed between the collector of the switch S6 and the primary winding of the transformer T1. The buffer diode D4 may be used to buffer any overvoltage in the switching operation. A large and / or fast capacitor C5 may be coupled to the emitter side of the switch S6. The freewheeling diode D2 may also be coupled to the emitter side of the switch S1. Various other components not shown in the figure may be included. One or more switches and / or circuits may be arranged in parallel or in series.

[0205] In some embodiments, the switch S6 may switch very quickly such that the switched voltage may never be at full voltage (e.g., the voltage of the energy storage capacitor C7 and / or the voltage source V5). In some embodiments, the gate resistor coupled to the switch S6 may be set with short turn-on pulses.

[0206] In some embodiments, the nanosecond pulse generator stage 101 may include a freewheeling diode D2. In some embodiments, the freewheeling diode D2 may be used in combination with an inductive load to ensure that the energy stored in the inductive load can be dissipated after the switch S6 is opened by allowing the current to continue flowing in the same direction through the inductor, and the energy is dissipated in the resistive elements of the circuit. If the freewheeling diode D2 is not included, this may, for example, result in a large reverse voltage across the switch S6.

[0207] In some embodiments, the nanosecond pulse generator stage 101 may include stray inductance L1 and / or stray resistance R1. For example, the stray inductance L1 may be less than about 10 nH, 100 nH, 1,000 nH, 10,000 nH, etc. For example, the stray resistance R1 may be less than about 1 ohm, 100 mΩ, 10 mΩ, etc.

[0208] In some embodiments, the energy recovery circuit 1610 can be electrically coupled to the secondary side of the transformer and / or to the energy storage capacitor C7. For example, the energy recovery circuit 1610 can include a diode 130 (e.g., a snubber diode) across the secondary side of the transformer T1. For example, the energy recovery circuit 1610 can include an energy recovery diode 1620 and an energy recovery inductor 1615 (arranged in series), which can allow current to flow from the secondary side of the transformer T1 to charge the energy storage capacitor C7. The energy recovery diode 1620 and the energy recovery inductor 1615 can be electrically connected to the secondary side of the transformer T1 and the energy storage capacitor C7. In some embodiments, the energy recovery circuit 1610 can include a diode 130 and / or an inductor 140 that is electrically coupled to the secondary of the transformer T1. The inductor 140 can represent the stray inductance of the transformer T1 and / or can include stray inductance.

[0209] In some embodiments, the energy recovery inductor 1615 can include any type of inductor (e.g., such as a ferrite core inductor or an air core inductor). In some embodiments, the energy recovery inductor 1615 can have any type of geometry (e.g., such as a solenoid winding, a toroidal winding, etc.). In some embodiments, the energy recovery inductor 1615 can have an inductance greater than about 10 μH, 50 μH, 100 μH, 500 μH, etc. In some embodiments, the energy recovery inductor 1615 can have an inductance of about 1 μH to about 100 mH.

[0210] In some embodiments, when the nanosecond pulse generator is turned on, current can charge the load stage 106 (e.g., charge capacitor C3, capacitor C2, or capacitor C9). For example, when the voltage on the secondary side of the transformer T1 rises above the charging voltage on the energy storage capacitor C7, some current can flow through the energy recovery inductor 1615. When the nanosecond pulse generator is turned off, current can flow from a capacitor within the load stage 106 (e.g., capacitor C1) through the energy recovery inductor 1615 to charge the energy storage capacitor C7 until the voltage across the energy recovery inductor 1615 is zero. The diode 130 can prevent the capacitor within the load stage 106 from ringing with the inductance in the load stage 106 or the DC bias circuit 104.

[0211] For example, the energy recovery diode 1620 can prevent charge from flowing from the energy storage capacitor C7 to the capacitor within the load stage 106.

[0212] The value of the energy recovery inductor 1615 can be selected to control the current fall time. In some embodiments, the energy recovery inductor 1615 can have an inductance value between 1 μH and 600 μH. In some embodiments, the energy recovery inductor 1615 can have an inductance value greater than 50 μH. In some embodiments, the energy recovery inductor 1615 can have an inductance less than approximately 50 μH, 100 μH, 150 μH, 200 μH, 250 μH, 300 μH, 350 μH, 350 μH, 400 μH, 400 μH, 500 μH, etc.

[0213] For example, if the energy storage capacitor C7 provides 500 V, then (e.g., as described above, due to voltage doubling) 1 kV will be measured at the input of the transformer T1. When the switch S6 is opened, the 1 kV at the transformer T1 can be distributed among the components of the energy recovery circuit 1610. If the values are appropriately selected (e.g., the inductor L3 has an inductance less than the inductance of the energy recovery inductor 1615), then the voltage across the energy recovery diode 1620 and the energy recovery inductor 1615 can be greater than 500 V. Current can then flow through the energy recovery diode 1620 and / or charge the energy storage capacitor C7. Current can also flow through the diode D3 and the inductor L6. Once the energy storage capacitor C7 is charged, current can no longer flow through the diode D3 and the energy recovery inductor 1615.

[0214] In some embodiments, the energy recovery circuit 1610 can transfer energy (or transfer charge) from the load stage 106 (e.g., on a fast time scale such as time scales of 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.). The stray resistance of the energy recovery circuit can be low to ensure that the pulse across the load stage 106 has a fast fall time t f . For example, the stray resistance of the energy recovery circuit 1610 can have a resistance less than approximately 1 ohm, 100 mΩ, 10 mΩ, etc. In some embodiments, the energy transfer efficiency from the load stage 106 can be high (e.g., greater than approximately 60%, 70%, 80%, or 90%, etc.).

[0215] Any number of the components shown (e.g., diode 135 or diode 130 or inductor 140) may or may not be required. Figure 16 Any number of the components shown (e.g., diode 135 or diode 130 or inductor 140) may or may not be required.

[0216] In some embodiments, a diode can be placed between the voltage source V1 and the point where the energy recovery circuit 1610 is connected to the voltage source V1 and / or the energy storage capacitor C7. For example, such a diode can be arranged to allow current to flow from the voltage source V1 to the energy storage capacitor C7, but can prevent current from flowing from the energy recovery circuit to the energy storage capacitor C7.

[0217] 1700 is a circuit diagram of a bias generator 1700 including a nanosecond pulse generator stage 101 and having an active energy recovery circuit 111 with an energy recovery switch S5. The switch S6 can be switched based on signals from the controller labeled Sig5+ and Sig5-.

[0218] In Figure 17 the active energy recovery circuit 111 can include an energy recovery switch S5, which can be used to control the flow of current through the energy recovery inductor 1615. In some embodiments, the energy recovery switch S5 can include a freewheeling diode arranged across the energy recovery switch. For example, the energy recovery switch S5 can be placed in series with the energy recovery inductor 1615. In some embodiments, the energy recovery switch S5 can be opened and closed based on signals from Sig5+ and / or Sig5-. In some embodiments, when the switch S1 is opened and / or no pulses are occurring, the switch input V5 can close the energy recovery switch to allow current to flow back from the load stage 106 to the high voltage load C7. In some embodiments, when the switch S1 is closed and / or pulses are occurring, the switch signals from Sig5+ and / or Sig5- can open the energy recovery switch to limit the current flow to the high voltage load C7.

[0219] Figure 17 The energy recovery switch S5 in is shown in series with the energy recovery diode 1620 and the energy recovery inductor 1615 and placed between the secondary side of the transformer T1 and both the energy recovery diode 1620 and the energy recovery inductor 1615. In some embodiments, both the energy recovery diode 1620 and the energy recovery inductor 1615 can be placed between the energy recovery switch S5 and the secondary side of the transformer T1. In some embodiments, the energy recovery switch S5 can be placed between the energy recovery diode 1620 and the energy recovery inductor 1615. The energy recovery diode 1620, the energy recovery inductor 1615, and the energy recovery switch S5 can be arranged in any order.

[0220] For example, the energy recovery switch S5 can include a high voltage switch (e.g., such as the high voltage switch 2300).

[0221] In some embodiments, when the energy recovery switch S5 is open, the load stage 106 can be charged by the nanosecond pulse generator stage 101. It may be beneficial to remove charge from the load stage 106 on a fast time scale (e.g., such as on a time scale of less than about 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 1,000 ns, etc.). To remove charge from the load stage 106, the energy recovery switch S5 can be closed.

[0222] Figure 18 is a circuit diagram of a bias generator 1800 including a passive bias compensation circuit 114 having an energy recovery circuit 1610, according to some embodiments.

[0223] In this example, the passive bias compensation circuit 114 is a passive bias compensation circuit and can include a bias compensation diode 1805 and a bias compensation capacitor 1810. The bias compensation diode 1805 can be arranged in series with the offset supply voltage V5. The bias compensation capacitor 1810 can be arranged across one or both of the offset supply voltage V5 and the resistor R2. The bias compensation capacitor 1810 can have a capacitance less than 100 nF to 100 μF (e.g., such as about 100 μF, 50 μF, 25 μF, 10 μF, 2 μF, 500 nF, 200 nF, etc.).

[0224] In some embodiments, the bias compensation diode 1805 can conduct a current between 10 A and 1 kA at a frequency between 10 Hz and 500 kHz.

[0225] In some embodiments, the bias capacitor C12 can allow a voltage offset between the output of the nanosecond pulse generator stage 101 (e.g., at the location labeled 125) and the voltage on the electrode (e.g., at the location labeled 124). In operation, for example, the electrode can be at a DC voltage of -2 kV during a burst (the burst can include multiple pulses), while the output of the nanosecond pulse generator alternates between +6 kV during the pulses and 0 kV between the pulses.

[0226] For example, the bias capacitor C12 is 100 nF, 10 nF, 1 nF, 100 μF, 10 μF, 1 μF, etc. For example, the resistor R2 can have a high resistance (e.g., such as a resistance of about 1 kΩ, 10 kΩ, 100 kΩ, 1 MΩ, 10 MΩ, 100 MΩ, etc.).

[0227] In some embodiments, the bias compensation capacitor 1810 and the bias compensation diode 1805 may allow a voltage offset between the output of the nanosecond pulse generator stage 101 (e.g., at the position marked 125) and the voltage on the electrode (e.g., at the position marked 124) to be established at the start of each burst, reaching the desired balanced state. For example, charge is transferred from the capacitor C12 to the bias compensation capacitor 1810 during the process of multiple pulses (e.g., which can be approximately 5 - 100 pulses) at the start of each burst to establish the correct voltage in the circuit.

[0228] In some embodiments, the pulse repetition frequency (e.g., the pulse frequency within a burst) may be between 200 kHz and 800 MHz (e.g., such as 2 MHz, 13.56 MHz, 27 MHz, 60 MHz, and 80 MHz, etc.). In some embodiments, the burst repetition frequency (e.g., the frequency of the burst) may be approximately 10 kHz, 50 Hz, 100 kHz, 500 kHz, 1 MHz, etc. (e.g., such as 400 kHz).

[0229] The energy recovery circuit 1610 may or may not include an energy recovery switch as Figure 17 shown.

[0230] Figure 19 is a circuit diagram of a bias generator 1900 including an active bias compensation circuit 134 having an energy recovery circuit 1610 according to some embodiments.

[0231] The active bias compensation circuit 134 may include any bias and / or bias compensation circuit known in the art. For example, the active bias compensation circuit 134 may include any bias and / or bias compensation circuit described in U.S. Patent Application No. 16 / 523,840 titled "NANOSECOND PULSER BIAS COMPENSATION", which is incorporated herein by reference in its entirety for all purposes.

[0232] In some embodiments, Figure 19 the active bias compensation circuit 134 of the bias generator 1900 shown may include a bias capacitor C6, a choke capacitor C12, a choke diode D8, a bias compensation bias compensation switch S8 (e.g., a high - voltage switch), an offset supply voltage V5, a resistor R2, and / or a resistor R4. In some embodiments, for example, the switch S8 may include a high - voltage switch (e.g., such as Figure 25 the high - voltage switch 2300 shown). The bias compensation switch S8 may be switched based on signals from the controller marked Sig8+ and Sig8-.

[0233] In some embodiments, the offset supply voltage V5 may include a DC voltage source, which may forward bias or reverse bias the output voltage. In some embodiments, the capacitor C12 may isolate / separate the offset supply voltage V5 from other circuit elements. In some embodiments, the active bias compensation circuit 134 may allow the potential transfer of power from one part of the circuit to another part. In some embodiments, the active bias compensation circuit 134 may be used to maintain a constant clamping force between the process wafer and the electrostatic chuck. For example, the resistor R2 may protect / isolate the DC bias supply and the driver. As another example, the resistor R2 may be used to ensure that the DC supply V5 does not enter an overcurrent fault.

[0234] In some embodiments, the bias compensation switch S8 may be opened while the nanosecond pulse generator stage 101 is not actively generating pulses at a rate greater than 10 kHz or is not providing a pulse burst, and may be closed when the nanosecond pulse generator stage 101 is not generating pulses. While closed, for example, the bias compensation switch S8 may allow current in the direction blocked by the choke diode D8. Shorting this current may allow the bias between the wafer and the chuck to be less than 2 kV, which may be within an acceptable tolerance.

[0235] In some embodiments, the load stage 106 may be coupled to the active bias compensation circuit 134. In some embodiments, the energy recovery circuit 1610 may or may not include an energy recovery switch as Figure 17 shown.

[0236] Figure 20 is a circuit diagram of a bias generator 2000 including an active bias compensation circuit 134 with an active energy recovery circuit 111 according to some embodiments.

[0237] Figure 21 is a circuit diagram of a bias generator 2100 with an energy recovery circuit 1610 according to some embodiments. In this example, the bias generator 2100 is similar to the bias generator 1600, where the nanosecond pulse generator stage 101 switches the other polarity of the energy storage capacitor C7. When the switch S6 is opened, the charge on the capacitor C1 flows through the energy recovery circuit 1610 to the high-voltage energy storage capacitor C7, and the high-voltage energy storage capacitor C7 can be charged. When the charge on the capacitor C1 is less than the charge on the high-voltage energy storage capacitor C7, the current stops flowing through the energy recovery circuit 1610. In some embodiments, the DC bias circuit 104 may be replaced with a passive bias compensation circuit 114 or an active bias compensation circuit 134. In some embodiments, the energy recovery circuit 1610 may be replaced with an active energy recovery circuit 111.

[0238] In some embodiments, including the ground side (see, for exampleFigure 16 ) or the positive side of power supply V1 and / or C7 (see, for example, Figure 21 or Figure 22 ) a nanosecond pulse generator (or switch) for switching. Any arrangement can be used. One arrangement can be used to replace the figure showing another arrangement.

[0239] Figure 22 is a circuit diagram of a bias generator 2200 of an energy recovery circuit 1610 that drives a capacitive load 2205 according to some embodiments. In this example, the bias generator 2200 is similar to the bias generator 1600, without the DC bias circuit 104, and drives the capacitive load positively. The capacitive load 2205 can include any type of load (e.g., such as a plasma load, multiple grids, multiple electrodes, a solid capacitor, a photoconductive switch capacitor, etc.).

[0240] Figure 23 is a block diagram of a high-voltage switch 2300 with isolated power according to some embodiments. The high-voltage switch 2300 can include a plurality of switch modules 2305 (collectively or individually 2305, and individually 2305A, 2305B, 2305C, and 2305D), which can switch the voltage from a high-voltage source 2360 with a fast rise time and / or high frequency and / or with a variable pulse width. Each switch module 2305 can include a switch 2310 (e.g., such as a solid-state switch).

[0241] In some embodiments, the switch 2310 can be electrically coupled to a gate driver circuit 2330, and the gate driver circuit 2330 can include a power supply 2340 and / or an isolated fiber optic trigger 2345 (also referred to as a gate trigger or switch trigger). For example, the switch 2310 can include a collector, an emitter, and a gate (or a drain, a source, and a gate), and the power supply 2340 can drive the gate of the switch 2310 via the gate driver circuit 2330. For example, the gate driver circuit 2330 can be isolated from other components of the high-voltage switch 2300.

[0242] In some embodiments, for example, an isolation transformer can be used to isolate the power supply 2340. The isolation transformer can include a low-capacitance transformer. For example, the low capacitance of the isolation transformer can allow the power supply 2340 to be charged on a fast time scale without significant current. For example, the isolation transformer can have a capacitance of less than about 100 pF. As another example, the isolation transformer can have a capacitance of less than about 30 - 100 pF. In some embodiments, the isolation transformer can provide voltage isolation up to 1 kV, 5 kV, 10 kV, 23 kV, 50 kV, etc.

[0243] In some embodiments, an isolation transformer can have low stray capacitance. For example, the isolation transformer can have a stray capacitance less than about 1,000 pF, 100 pF, 10 pF, etc. In some embodiments, the low capacitance can minimize the electrical coupling to low voltage components (e.g., the source of input control power), and / or can reduce EMI generation (e.g., electrical noise generation). In some embodiments, the transformer stray capacitance of the isolation transformer can include the capacitance measured between the primary winding and the secondary winding.

[0244] In some embodiments, the isolation transformer can be a DC-to-DC converter or an AC-to-DC transformer. In some embodiments, for example, the transformer can include a 110V AC transformer. In any case, the isolation transformer can provide power isolated from other components in the high voltage switch 2300. In some embodiments, the isolation can be galvanic such that the conductors on the primary side of the isolation transformer do not pass through or make contact with the secondary side of the isolation transformer.

[0245] In some embodiments, the transformer can include a primary winding that can be tightly wound or coiled around the transformer core. In some embodiments, the primary winding can include conductive sheets wound around the transformer core. In some embodiments, the primary winding can include one or more windings.

[0246] In some embodiments, the secondary winding can be wound around the core as far away from the core as possible. For example, a bundle of windings including the secondary winding can be wound through the center of an aperture in the transformer core. In some embodiments, the secondary winding can include one or more windings. In some embodiments, the bundle of wires including the secondary winding can include a circular or square cross-section, for example, to minimize stray capacitance. In some embodiments, an insulator (e.g., oil or air) can be deployed between the primary winding, the secondary winding, or the transformer core.

[0247] In some embodiments, keeping the secondary winding away from the transformer core can have some benefits. For example, it can reduce the stray capacitance between the primary side of the isolation transformer and the secondary side of the isolation transformer. As another example, it can allow for high voltage isolation between the primary side of the isolation transformer and the secondary side of the isolation transformer such that corona and / or breakdown do not form during operation.

[0248] In some embodiments, the spacing between the primary side (e.g., primary winding) of the isolation transformer and the secondary side (e.g., secondary winding) of the isolation transformer can be about 0.1 inch, 0.5 inch, 1 inch, 5 inches, or 10 inches. In some embodiments, the typical spacing between the core of the isolation transformer and the secondary side (e.g., secondary winding) of the isolation transformer can be about 0.1 inch, 0.5 inch, 1 inch, 5 inches, or 10 inches. In some embodiments, the gap between windings can be filled with the lowest possible dielectric material (e.g., such as vacuum, air, any insulating gas or liquid, or a solid material having a relative dielectric constant less than 3).

[0249] In some embodiments, the power supply 2340 can include any type of power supply that can provide high voltage isolation or has a low capacitance (e.g., less than about 1,000 pF, 100 pF, 10 pF, etc.). In some embodiments, the control voltage power supply can provide 1420 V AC or 240 V AC at 60 Hz.

[0250] In some embodiments, each power supply 2340 can be inductively electrically coupled to a single control voltage power source. For example, power supply 2340A can be electrically coupled to the power source via a first transformer; power supply 2340B can be electrically coupled to the power source via a second transformer; power supply 2340C can be electrically coupled to the power source via a third transformer; and power supply 2340D can be electrically coupled to the power source via a fourth transformer. For example, any type of transformer that can provide voltage isolation between various power supplies can be used.

[0251] In some embodiments, the first transformer, the second transformer, the third transformer, and the fourth transformer can include different secondary windings around the core of a single transformer. For example, the first transformer can include a first secondary winding, the second transformer can include a second secondary winding, the third transformer can include a third secondary winding, and the fourth transformer can include a fourth secondary winding. Each of these secondary windings can be wound around the core of a single transformer. In some embodiments, the first secondary winding, the second secondary winding, the third secondary winding, the fourth secondary winding, or the primary winding can include a single winding or multiple windings wound around the transformer core.

[0252] In some embodiments, power supply 2340A, power supply 2340B, power supply 2340C, and / or power supply 2340D may not share a return reference ground or a local ground.

[0253] For example, the isolated fiber optic trigger 2345 can also be isolated from other components of the high voltage switch 2300. The isolated fiber optic trigger 2345 can include a fiber optic receiver, which allows each switch module 2305 to float relative to other switch modules 2305 and / or other components of the high voltage switch 2300, and / or, for example, allows active control of the gates of each switch module 2305 simultaneously.

[0254] In some embodiments, for example, an isolation transformer can be used to isolate the return reference ground or local ground or common ground for each switch module 2305 from each other.

[0255] For example, the electrical isolation of each switch module 2305 from the common ground can allow multiple switches to be arranged in a series configuration for building up a high voltage switch. In some embodiments, a certain lag in the switch module timing can be allowed or designed. For example, each switch module 2305 can be configured or rated to switch 1 kV, each switch module can be electrically isolated from each other, and / or the timing of closing each switch module 2305 can be allowed to not be fully aligned for a period defined by the capacitance of the buffer capacitor and / or the rated voltage of the switch.

[0256] In some embodiments, electrical isolation can provide many advantages. For example, one possible advantage can include minimizing switch-to-switch jitter and / or allowing arbitrary switch timing. For example, each switch 2310 can have a switch transition jitter of less than approximately 500 ns, 50 ns, 20 ns, 5 ns, etc.

[0257] In some embodiments, electrical isolation between two components (or circuits) can imply an extremely high resistance between the two components and / or can imply a small capacitance between the two components.

[0258] Each switch 2310 can include any type of solid state switching device (e.g., IGBT, MOSFET, SiCMOSFET, SiC junction transistor, FET, SiC switch, GaN switch, photoconductive switch, etc.). For example, the switch 2310 can be capable of switching a high voltage (e.g., a voltage greater than approximately 1 kV) at a high frequency (e.g., greater than 1 kHz), at a high speed (e.g., with a repetition rate greater than approximately 500 kHz), and / or with a fast rise time (e.g., less than approximately 23 ns) and / or with a long pulse length (e.g., greater than approximately 10 ms). In some embodiments, each switch can be individually rated to switch 1,200 V - 1,700 V, while in a combined manner they can switch greater than 4,800 V - 6,800 V (for four switches). Switches with various other rated voltages can be used.

[0259] There can be some advantages to using a large number of lower voltage switches instead of a few higher voltage switches. For example, lower voltage switches typically have better performance: compared to higher voltage switches, lower voltage switches can switch faster, can have faster transition times, and / or can switch more efficiently. However, for example, the more switches there are, the greater the need for switch timing accuracy.

[0260] Figure 23 The high voltage switch 2300 shown includes four switch modules 2305. Although four are shown in this figure, any number of switch modules 2305 can be used (e.g., two, eight, twelve, sixteen, twenty, twenty-four, etc.). For example, if each switch in each switch module 2305 is rated at 1200V and sixteen switches are used, the high voltage switch can switch up to 19.2kV. As another example, if each switch in each switch module 2305 is rated at 1700V and sixteen switches are used, the high voltage switch can switch up to 27.2kV.

[0261] In some embodiments, the high voltage switch can switch voltages greater than 5kV, 10kV, 14kV, 20kV, 23kV, etc.

[0262] In some embodiments, the high voltage switch 2300 can include a fast capacitor 2355. For example, the fast capacitor 2355 can include one or more capacitors arranged in series and / or parallel. For example, these capacitors can include one or more polypropylene capacitors. The fast capacitor 2355 can store energy from a high voltage source 2360.

[0263] In some embodiments, the fast capacitor 2355 can have a low capacitance. In some embodiments, the fast capacitor 2355 can have a capacitance value of about 1μF, about 5μF, between about 1μF and about 5μF, between about 100nF and about 1,000nF, etc.

[0264] In some embodiments, the high voltage switch 2300 may or may not include a snubber diode 2350. The snubber diode 2350 may include a plurality of diodes arranged in series or parallel, which may be beneficial, for example, for driving inductive loads. In some embodiments, the snubber diode 2350 may include one or more Schottky diodes (e.g., such as silicon carbide Schottky diodes). For example, the snubber diode 2350 may sense whether the voltage from the switch in the high voltage switch is higher than a specific threshold. If so, the snubber diode 2350 may short the power from the switch module to ground. For example, the snubber diode may allow an alternating current path to dissipate the energy stored in the inductive load after switching. For example, this can prevent large inductive voltage spikes. In some embodiments, the snubber diode 2350 may have a low inductance (e.g., such as 1 nH, 10 nH, 100 nH, etc.). In some embodiments, the snubber diode 2350 may have a low capacitance (e.g., such as 100 pF, 1 nF, 10 nF, 100 nF, etc.).

[0265] In some embodiments, for example, such as when the load 2365 is primarily resistive, the snubber diode 2350 may not be used.

[0266] In some embodiments, each gate drive circuit 2330 may produce jitter less than about 1000 ns, 100 ns, 10.0 ns, 5.0 ns, 3.0 ns, 1.0 ns, etc. In some embodiments, each switch 2310 may have a minimum on-time (e.g., less than about 10 μs, 1 μs, 500 ns, 100 ns, 50 ns, 10, 5 ns, etc.) and a maximum on-time (e.g., greater than 23 seconds, 10 seconds, 5 seconds, 1 second, 500 milliseconds, etc.).

[0267] In some embodiments, during operation, each of the high voltage switches may turn on and / or off within 1 ns of each other.

[0268] In some embodiments, each switch module 2305 may have the same or substantially the same (±5%) stray inductance. The stray inductance may include any inductance within the switch module 2305 that is not associated with an inductor (e.g., such as the inductance in leads, diodes, resistors, switch 2310, and / or circuit board traces, etc.). The stray inductance within each switch module 2305 may include a low inductance (e.g., such as an inductance less than about 300 nH, 100 nH, 10 nH, 1 nH, etc.). The stray inductance between each switch module 2305 may include a low inductance (e.g., such as an inductance less than about 300 nH, 100 nH, 10 nH, 1 nH, etc.).

[0269] In some embodiments, each switch module 2305 may have the same or substantially the same (±5%) stray capacitance. The stray capacitance may include any capacitance within the switch module 2305 that is not associated with a capacitor (e.g., capacitance in leads, diodes, resistors, switches 2310, and / or circuit board traces, etc.). The stray capacitance within each switch module 2305 may include low capacitance (e.g., less than about 1,000 pF, 100 pF, 10 pF, etc.). The stray capacitance between each switch module 2305 may include low capacitance (e.g., less than about 1,000 pF, 100 pF, 10 pF, etc.).

[0270] For example, voltage distribution defects can be addressed with a passive buffer circuit (e.g., buffer diode 2315, buffer capacitor 2320, and / or freewheeling diode 2325). For example, small differences in timing between the turn-on or turn-off of each of the switches 2310 or differences in inductance or capacitance may result in voltage spikes. These spikes can be mitigated with various buffer circuits (e.g., buffer diode 2315, buffer capacitor 2320, and / or freewheeling diode 2325).

[0271] For example, the buffer circuit may include buffer diode 2315, buffer capacitor 2320, buffer resistor 2316, and / or freewheeling diode 2325. In some embodiments, the buffer circuit may be arranged in parallel with the switches 2310. In some embodiments, the buffer capacitor 2320 may have low capacitance (e.g., a capacitance less than about 100 pF).

[0272] In some embodiments, the high voltage switch 2300 may be electrically coupled to a load 2365 (e.g., a resistive or capacitive or inductive load) or include the load 2365. For example, the load 2365 may have a resistance ranging from 50 ohms to 500 ohms. Alternatively or additionally, the load 2365 may be an inductive load or a capacitive load.

[0273] In some embodiments, the energy recovery circuit 1610 or the active energy recovery circuit 111 can reduce the energy consumption of the high voltage bias generator and / or the voltage required to drive a given load by the same energy output performance as a system without an energy recovery circuit. For example, for the same energy output performance as a system without an energy recovery circuit, the energy consumption can be reduced by up to 10%, 15%, 20%, 23%, 30%, 40%, 45%, 50%, etc. or more.

[0274] In some embodiments, diode 130, diode 135, and / or energy recovery diode 1620 may include high voltage diodes.

[0275] Figure 24A circuit diagram of a bias generator 2400 including an RF source 2405, an active bias compensation circuit 134, and an energy recovery circuit 1610 according to some embodiments. In this example, the bias generator 2400 is similar to the bias generator 900, where the RF driver 605 and the resonant circuit 610 are replaced by the RF source 2405. Figure 9 The illustrated RF driver 605 includes a full-wave rectifier and a resonant circuit 610, and the resonant circuit 610 is replaced by the RF source 2405.

[0276] In some embodiments, the RF source 2405 may include multiple high-frequency solid-state switches, RF generators, amplifier-tube-based RF generators, or tube-based RF generators.

[0277] The bias generator 2400 may not include a conventional matching network (e.g., such as a 50-ohm matching network or an external matching network or a stand-alone matching network). In some embodiments, the bias generator 2400 does not require a 50-ohm matching network to optimize the switching power applied to the wafer chamber. An RF generator without a conventional matching network may allow for a rapid change in the power extracted by the plasma chamber. Typically, such optimization of the matching network may take at least 100 μs - 200 μs. In some embodiments, the power change may occur within one or two RF cycles (e.g., at 400 kHz, 2.5 μs - 5.0 μs).

[0278] In some embodiments, the RF source 2405 may operate at frequencies of approximately 400 kHz, 0.5 MHz, 2.0 MHz, 4.0 MHz, 13.56 MHz, 27.12 MHz, 40.68 MHz, 50 MHz, etc.

[0279] Figure 25 Another example bias generator 2500 according to some embodiments is shown. The bias generator 2500 can be generalized into five stages (these stages can be decomposed into other stages or generalized into fewer stages). The bias generator 2500 includes a nanosecond pulse generator stage 101, a resistive output stage 2507, a bias compensation circuit 134, and a load stage 106.

[0280] In this example, the load stage 106 may represent an effective circuit for a plasma deposition system, a plasma etching system, or a plasma sputtering system. The capacitor C2 may represent the capacitance of the dielectric material on which the wafer can sit. The capacitor C3 may represent the sheath capacitance of the plasma to the wafer. The capacitor C9 may represent the capacitance within the plasma between the chamber wall and the top surface of the wafer. The current sources I2 and I1 may represent the ion current through the sheath.

[0281] In this example, the resistive output stage 2507 may include one or more inductive elements represented by inductor L1 and / or inductor L5. For example, inductor L5 may represent the stray inductance of the leads in the resistive output stage 2507. Inductor L1 may be arranged to minimize the power flowing directly from the nanosecond pulse generator stage 101 into resistor R1.

[0282] In some embodiments, resistor R1 may dissipate charge from the load stage 2515, for example, on a fast time scale (e.g., time scales such as 1 ns, 10 ns, 50 ns, 100 ns, 250 ns, 500 ns, 100 ns, etc.). The resistance of resistor R1 may be low to ensure that the pulse across the load stage 2515 has a fast fall time t f 。

[0283] In some embodiments, resistor R1 may include a plurality of resistors arranged in series and / or parallel. Capacitor C11 may represent the stray capacitance of resistor R1, which includes the capacitance of the arrangement of series and / or parallel resistors. For example, the capacitance of stray capacitor C11 may be less than 500 pF, 250 pF, 100 pF, 50 pF, 10 pF, 1 pF, etc. For example, the capacitance of stray capacitor C11 may be less than the load capacitance (e.g., less than the capacitance of C2, C3, and / or C9).

[0284] In some embodiments, multiple nanosecond pulse generator stages 2506 may be aggregated in parallel and coupled to the resistive output stage 2507 across inductor L1 and / or resistor R1. Each of the multiple pulse generator and transformer stages 906 may also include diode D1 and / or diode D6.

[0285] In some embodiments, capacitor C8 may represent the stray capacitance of choke diode D1. In some embodiments, capacitor C4 may represent the stray capacitance of diode D6.

[0286] Figure 26The illustrated computing system 2600 can be used to execute any embodiment of the present invention. For example, the computing system 2600 can be used to execute process 500. As another example, the computing system 2600 can be used to perform any of the calculations, identifications, and / or determinations described herein. The computing system 2600 includes hardware elements that can be electrically coupled via bus 2605 (or, where appropriate, can communicate in other ways). The hardware elements can include: one or more processors 2610, including but not limited to one or more general-purpose processors and / or one or more special-purpose processors (e.g., digital signal processing chips, graphics acceleration chips, etc.); one or more input devices 2615, which can include but are not limited to a mouse, keyboard, etc.; and one or more output devices 2620, which can include but are not limited to a display device, printer, etc.

[0287] The computing system 2600 can also include one or more storage devices 2625 (and / or communicate therewith), which can include but are not limited to local and / or network-accessible storage, and / or can include but are not limited to disk drives, drive arrays, optical storage devices, solid-state storage devices (e.g., random access memory (“RAM”) and / or read-only memory (“ROM”)), which can be programmable, flash-updatable, etc. The computing system 2600 can also include a communication subsystem 2630, which can include but is not limited to a modem, network card (wireless or wired), infrared communication device, wireless communication device, and / or chip set (e.g., Bluetooth device, 802.6 device, Wi-Fi device, WiMax device, cellular communication facility, etc.). The communication subsystem 2630 can allow data to be exchanged with a network (e.g., the network described below, by way of example only) and / or any other device described in this document. In many embodiments, the computing system 2600 will also include a working memory 2635, which can include a RAM or ROM device as described above.

[0288] The computing system 2600 can also include software elements shown as currently residing within the working memory 2635, including an operating system 2640 and / or other code (e.g., one or more application programs 2645, which can include the computer program of the present invention, and / or can be designed to implement the methods of the present invention and / or configure the systems of the present invention), as described herein. For example, one or more of the processes described with respect to the methods discussed above can be implemented as code and / or instructions executable by a computer (and / or a processor within the computer). This set of instructions and / or code can be stored on a computer-readable storage medium (e.g., the storage device 2625 described above).

[0289] In some cases, the storage medium may be incorporated within or communicate with the computing system 2600. In other embodiments, the storage medium may be separate from the computing system 2600 (e.g., a removable medium (e.g., a compact disc, etc.)), and / or provided in an installation package such that the storage medium can be used to program a general purpose computer with instructions / code stored thereon. These instructions may take the form of executable code executable by the computing system 2600, and / or may take the form of source code and / or installable code that takes the form of executable code upon compilation and / or installation on the computing system 2600 (e.g., using any one of a variety of commonly available compilers, installers, compression / decompression utilities, etc.).

[0290] Unless otherwise specified, the term "substantially" means within 5% or 10% of the value referred to or within the manufacturing tolerance. Unless otherwise specified, the term "about" means within 5% or 10% of the value referred to or within the manufacturing tolerance.

[0291] The term "or" is inclusive.

[0292] Numerous specific details are set forth herein to provide a thorough understanding of the claimed subject matter. However, those skilled in the art will understand that the claimed subject matter may be practiced without these specific details. In other instances, well-known methods, devices, or systems have not been described in detail so as not to obscure the claimed subject matter.

[0293] Algorithmic or symbolic representations of operations on data bits or binary digital signals stored within a computing system memory (e.g., computer memory) are presented in some portions. These algorithmic descriptions or representations are examples of techniques that a person of ordinary skill in the data processing art uses to convey the substance of their work to others skilled in the art. An algorithm is a self-consistent sequence of operations or similar processing that leads to a desired result. In this case, the operations or processing involve the physical manipulation of physical quantities. Typically, but not necessarily, these quantities may take the form of electrical or magnetic signals capable of being stored, transmitted, combined, compared, or otherwise manipulated. For general reasons, it has sometimes proven convenient to refer to these signals as bits, data, values, elements, symbols, characters, terms, numbers, numerical values, etc. However, it should be understood that all of these and similar terms are to be associated with appropriate physical quantities and are merely convenient labels. Unless otherwise specifically stated, it should be understood that throughout this specification discussion, terms such as "processing," "computing," "operating," "determining," and "identifying" refer to the actions or processes of a computing device (e.g., one or more computers or one or more similar electronic computing devices) that manipulate or transform data represented as physical electronic or magnetic quantities within a memory, register, or other information storage device, transmission device, or display device of a computing platform.

[0294] The one or more systems discussed herein are not limited to any particular hardware architecture or configuration. A computing device may include any suitable arrangement of components that provide a result conditioned on one or more inputs. Suitable computing devices include multi-purpose microprocessor-based computer systems that access stored software that programs or configures the computing system from a general-purpose computing device to a dedicated computing device that implements one or more embodiments of the present subject matter. Any suitable programming, scripting, or other type of language or combination of languages may be used to implement the teachings contained herein in software to be used in programming or configuring a computing device.

[0295] Embodiments of the methods disclosed herein may be performed in the operation of these computing devices. The order of the blocks presented in the above examples may be changed, for example, the blocks may be reordered, combined and / or decomposed into sub-blocks. Certain blocks or processes may be performed in parallel.

[0296] The use of "suitable for" or "configured to" herein is intended to be open and inclusive language that does not exclude devices that are suitable for or configured to perform additional tasks or steps. In addition, the use of "based on" is intended to be open and inclusive in that a process, step, calculation, or other action that is "based on" one or more stated conditions or values may actually be based on additional conditions or values beyond the stated conditions or values. The headings, lists, and numbering included herein are for ease of explanation only and are not intended to be limiting.

[0297] Although the subject matter has been described in detail with respect to specific embodiments of the subject matter, it should be understood that those skilled in the art can easily generate changes, modifications and equivalents to these embodiments when realizing the understanding of the foregoing. Accordingly, it should be understood that the present disclosure has been presented for the purpose of illustration and not limitation, and does not exclude the inclusion of such modifications, modifications and / or additions to the subject matter, as will be readily apparent to those of ordinary skill in the art.

Claims

1. A plasma system, comprising: a plasma chamber; an RF plasma generator electrically coupled to the plasma chamber, the RF plasma generator generating a plurality of RF bursts, each of the plurality of RF bursts including an RF waveform, each of the plurality of RF bursts having an RF burst turn-on time and an RF burst turn-off time; a bias generator electrically coupled to the plasma chamber, the bias generator generating a plurality of bias bursts, each of the plurality of bias bursts including a bias pulse, each of the plurality of bias bursts having a bias burst turn-on time and a bias burst turn-off time; and a controller in communication with the RF plasma generator and the bias generator, the controller controlling the timing of the RF burst turn-on time, the RF burst turn-off time, the bias burst turn-on time, and the bias burst turn-off time according to the following method: driving the plasma chamber with the RF plasma generator having a frequency greater than 10 MHz; pausing for a first period of time; pulsing the plasma chamber with pulses having a first voltage at a pulse repetition frequency greater than 1 kHz through the bias generator; pausing for a second period of time; stopping driving the RF plasma generator; pausing for a third period of time; and stopping the bias generator from pulsing.

2. The plasma system according to claim 1, wherein The plurality of RF bursts generate and / or drive plasma in the plasma chamber, and the plurality of bias bursts accelerate ions within the plasma.

3. The plasma system according to claim 1, further comprising an electrode disposed within the plasma chamber, the electrode being coupled to the RF plasma generator.

4. The plasma system according to claim 1, further comprising an inductive antenna disposed within the plasma chamber, the antenna being coupled to the RF plasma generator.

5. The plasma system according to claim 1, further comprising an electrode disposed within the plasma chamber, the electrode being coupled to the bias generator.

6. The plasma system according to claim 1, wherein The RF burst turn-on time precedes the bias burst turn-on time by less than 10 ms.

7. The plasma system according to claim 1, wherein, The bias burst turn-on time occurs within 10 cycles of the RF waveform after the RF burst turn-on time.

8. The plasma system according to claim 1, wherein The bias burst turn-on time precedes the RF burst turn-off time by less than 10 ms.

9. The plasma system according to claim 1, wherein The difference between the RF burst turn-on time and the RF burst turn-off time is less than 1 ms.

10. The plasma system according to claim 1, wherein, The difference between the bias burst turn-on time and the bias burst turn-off time is less than 10 ms.

11. The plasma system according to claim 1, wherein, The RF waveform has a frequency between 10 kHz and 100 MHz.

12. The plasma system according to claim 1, wherein, The RF waveform has a frequency of 13.56 MHz.

13. The plasma system according to claim 1, wherein, The bias generator includes a bias compensation circuit.

14. The plasma system according to claim 1, wherein, The bias generator includes an energy recovery circuit.

15. The plasma system according to claim 1, wherein, The RF plasma generator includes a full-bridge circuit or a half-bridge circuit and a resonant circuit.

16. The plasma system according to claim 1, wherein The bias generator includes a nanosecond pulse generator.

17. The plasma system according to claim 1, wherein The bias generator includes an RF generator.

18. A method, comprising: driving a plasma chamber with an RF plasma generator having a frequency greater than 10 MHz; Pause for a first time period; Pulse the plasma chamber with pulses having a first voltage at a pulse repetition frequency greater than 1 kHz through a bias generator; Pause for a second time period; Stop driving the RF plasma generator; Pause for a third time period; and Stop the bias generator from pulsing.

19. The method according to claim 18, further comprising: Pause for a fourth time period; Drive the RF plasma generator; Pause for the first time period; Pulse the bias generator with pulses having a second voltage; Pause for the second time period; Stop driving the RF plasma generator; Pause for the third time period; and Stop the bias generator from pulsing.

20. The method of claim 19, wherein, The second voltage is greater than the first voltage.

21. The method of claim 18, further comprising: Pause for a fourth time period; Drive the RF plasma generator; Pause for a fifth time period different from the first time period; Pulse the bias generator with pulses having a second voltage; Pause for a sixth time period different from the first time period; Stop driving the RF plasma generator; Pause for a seventh time period different from the first time period; and Stop the bias generator from pulsing.

22. The method of claim 18, wherein: The first time period is less than 10 ms; The second time period is less than 10 ms; and The third time period is less than 10 ms.

23. The method of claim 18, wherein, The first time period is less than the second time period.

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