Semiconductor device and method of manufacturing the same

Abstract

Provided is a semiconductor device including a transistor portion and a diode portion, and including: a drift region of a first conductivity type provided in a semiconductor substrate; an accumulation region of the first conductivity type provided at a position closer to a front surface side of the semiconductor substrate than the drift region in the transistor portion and the diode portion; and a first lifetime control region provided at the front surface side of the semiconductor substrate in the transistor portion and the diode portion.

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods for manufacturing the same. Background Technology

[0002] Previously, semiconductor devices having transistor sections and diode sections were known (for example, see Patent Documents 1-4).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2015-138801

[0004] Patent Document 2: Japanese Patent Application Publication No. 2017-11000

[0005] Patent Document 3: International Publication No. 2018 / 030440

[0006] Patent Document 4: International Publication No. 2019 / 142706

[0007] Technical issues

[0008] In conventional semiconductor devices, it is preferable to improve the balance of charge carriers between the transistor section and the diode section. Summary of the Invention

[0009] In a first aspect of the present invention, a semiconductor device is provided, the semiconductor device comprising a transistor portion and a diode portion, and comprising: a drift region of a first conductivity type disposed on a semiconductor substrate; an accumulation region of the first conductivity type disposed in the transistor portion and the diode portion at a position closer to the front side of the semiconductor substrate than the drift region; and a first lifetime control region disposed in the transistor portion and the diode portion on the front side of the semiconductor substrate.

[0010] The first lifetime control area can be set on the entire surface of the semiconductor substrate.

[0011] The semiconductor device may have a second lifetime control area disposed on the entire back side of the semiconductor substrate.

[0012] The semiconductor device may have multiple trenches disposed on the front side of the semiconductor substrate. The depth of the first lifetime control region may be deeper than the depth of the multiple trenches.

[0013] The depth of the accumulation zone can be within the trench depth of multiple trench sections.

[0014] The depth of the first lifetime control zone can be twice the depth of the boundary between the accumulation zone and the drift zone.

[0015] The depth of the first lifetime control region can be greater than 5 μm and less than 20 μm.

[0016] The dose of lifespan inhibitor in the first lifespan control region can be 0.5E10cm.-2 Above and 1E13cm -2 the following.

[0017] The first lifetime control region can be implanted from the back side of the semiconductor substrate.

[0018] The accumulation zone may have a first accumulation zone located on the front side of the drift zone and a second accumulation zone located below the first accumulation zone.

[0019] The ion implantation dose in the accumulation region can be 1E12cm. -2 Above and 1E13cm -2 the following.

[0020] The depth of the accumulation zone can be above 1 μm and below 5 μm.

[0021] The transistor section may have an emitter region of a first conductivity type with a doping concentration higher than that of the drift region. The accumulation region, when viewed from above, may be located over a larger area than the region where the emitter region is located.

[0022] The transistor section may have a boundary section adjacent to the diode section and a dummy trench section electrically connected to the emitter electrode. The trench section of the boundary section may be a dummy trench section.

[0023] The boundary portion may have: an accumulation region; a base region of a second conductivity type disposed on the front side; a contact region disposed on the front side of the base region and having a doping concentration higher than that of the base region; and a plug region of a second conductivity type disposed on the front side of the contact region and having a doping concentration higher than that of the contact region.

[0024] The boundary section may not have a launch zone.

[0025] In a second aspect of the present invention, a manufacturing method is provided, which is a method for manufacturing a semiconductor device having a transistor section and a diode section, comprising: a stage of providing a drift region of a first conductivity type on a semiconductor substrate; a stage of providing an accumulation region of the first conductivity type in the transistor section and the diode section at a position closer to the front side of the semiconductor substrate than the drift region; and a stage of providing a first lifetime control region in the transistor section and the diode section on the front side of the semiconductor substrate.

[0026] The stage of setting the first lifetime control region may include a stage of irradiating impurities from the back side of the semiconductor substrate.

[0027] The stage of setting the first lifetime control zone may include 0.5E10cm -2 Above and 1E12cm -2 The following dosage is injected during the impurity stage.

[0028] The stage of setting up the accumulation zone may include 3E12cm -2 Above and 6E12cm -2 The following dosages are used for the ion implantation phase.

[0029] It should be noted that the above description of the invention does not list all the features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0030] Figure 1A An example of a top view of a semiconductor device 100 according to an embodiment.

[0031] Figure 1B It means Figure 1A A diagram of an example of section a-a' in the figure.

[0032] Figure 1C It means Figure 1A A diagram of an example of section b-b' in the figure.

[0033] Figure 2A An example of a top view of a semiconductor device 100 according to an embodiment.

[0034] Figure 2B It means Figure 2A A diagram of an example of the c-c' section.

[0035] Figure 2C It means Figure 2A A diagram of an example of the d-d' section.

[0036] Figure 2D This is a diagram used to illustrate the differences in characteristics caused by the series of accumulation zone 16.

[0037] Figure 3 This is an example of a cross-sectional view obtained by magnifying the vicinity of the stage 71.

[0038] Figure 4 This is an example of a top view showing the chip end of the semiconductor device 100.

[0039] Figure 5 This is an example of a cross-sectional view of a comparative semiconductor device 500.

[0040] Symbol Explanation

[0041] 10…Semiconductor substrate, 12…Emitter region, 14…Base region, 15…Contact region, 16…Accumulation region, 17…Well region, 18…Drift region, 19…Plug region, 20…Buffer zone, 21…Front side, 22…Collector region, 23…Back side, 24…Collector electrode, 25…Connection portion, 30…Dummy trench portion, 31…Extension portion, 32…Dummy insulating film, 33…Connection portion, 34…Dummy conductive portion, 38…Interlayer insulating film, 40…Gate trench portion, 41…Extension portion, 42…Gate insulating film, 43…Connection portion, 44…Gate conductive portion, 45… …Gate channel, 50…Gate metal layer, 52…Emitter electrode, 54…Contact hole, 55…Contact hole, 56…Contact hole, 70…Transistor section, 71…Mesa section, 80…Diode section, 81…Mesa section, 82…Cathode region, 90…Boundary section, 91…Mesa section, 100…Semiconductor device, 101…Curve, 102…Curve, 150…Lifetime control region, 160…Lifetime control region, 500…Semiconductor device, 516…Accumulation region, 550…Lifetime control region, 560…Lifetime control region, 570…Transistor section, 580…Diode section Detailed Implementation

[0042] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are essential to the technical solution of the invention.

[0043] In this specification, one side parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions "upper," "lower," "front," and "back" are not limited to the direction of gravity or the actual mounting direction towards the substrate when mounting a semiconductor device.

[0044] In this specification, rectangular coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. In this specification, the plane parallel to the upper surface of the semiconductor substrate is designated as the XY plane, and the depth direction of the semiconductor substrate is designated as the Z-axis. It should be noted that in this specification, the view of the semiconductor substrate along the Z-axis is referred to as a top view.

[0045] In each embodiment, although an example is shown where the first conductivity type is N-type and the second conductivity type is P-type, it is also possible to set the first conductivity type to P-type and the second conductivity type to N-type. In this case, the conductivity types of the substrate, layer, region, etc., in each embodiment are of opposite polarities.

[0046] In this specification, in layers and / or regions marked with n or p, electrons or holes are respectively designated as majority carriers. Furthermore, a "+" sign for n or p indicates a higher doping concentration than layers and / or regions without the "+" sign, a "-" sign indicates a lower doping concentration than layers and / or regions without the "-" sign, "++" indicates a higher doping concentration than "+", and "--" indicates a lower doping concentration than "-".

[0047] In this specification, doping concentration refers to the concentration of donor or acceptor dopant. Therefore, its unit is / cm². 3 In this specification, the concentration difference between donors and acceptors (i.e., net doping concentration) is sometimes used as the doping concentration. In this case, the doping concentration can be determined using the SR method. Alternatively, the chemical concentrations of donors and acceptors can also be used as the doping concentration. In this case, the doping concentration can be determined using the SIMS method. Unless otherwise specified, any of the above-mentioned doping concentrations can be used as the doping concentration. Unless otherwise specified, the peak value of the doping concentration distribution in the doped region can be used as the doping concentration of that doped region.

[0048] Furthermore, in this specification, dosage refers to the number of ions implanted per unit area of ​​the wafer during ion implantation. Therefore, its unit is / cm². 2 It should be noted that the dose in the semiconductor region can be set as the integrated concentration obtained by integrating the doping concentration along the depth direction of the semiconductor region. The unit of this integrated concentration is / cm. 2 Therefore, the dose and integrated concentration can be considered the same. The integrated concentration can be the integral value up to the half-width, which can be derived by excluding the influence of other semiconductor regions when their spectra overlap with those of other semiconductor regions.

[0049] Therefore, in this specification, the level of doping concentration can be referred to as the level of dose. That is, when the doping concentration in one region is higher than the doping concentration in other regions, it can be understood that the dose in that region is higher than the dose in other regions.

[0050] Figure 1A This is an example of a top view of a semiconductor device 100 according to an embodiment. The semiconductor device 100 in this example is a semiconductor chip including a transistor section 70 and a diode section 80. For example, the semiconductor device 100 is a reverse-conducting IGBT (RC-IGBT).

[0051] The transistor section 70 is a region obtained by projecting the collector region 22, which is disposed on the back side of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The collector region 22 has a second conductivity type. As an example, the collector region 22 in this example is P+ type. The transistor section 70 includes transistors such as IGBTs. The transistor section 70 includes a boundary section 90 located at the boundary between the transistor section 70 and the diode section 80.

[0052] The diode section 80 is a region obtained by projecting the cathode region 82, which is disposed on the back side of the semiconductor substrate 10, onto the upper surface of the semiconductor substrate 10. The cathode region 82 has a first conductivity type. As an example, the cathode region 82 in this example is of the N+ type. The diode section 80 includes diodes such as freewheel diodes disposed adjacent to the transistor section 70 on the upper surface of the semiconductor substrate 10.

[0053] exist Figure 1A The diagram shows the edge side of the semiconductor device 100, i.e., the area surrounding the chip end; other areas are omitted. For example, in this example, an edge termination structure may be provided in the negative Y-axis region of the semiconductor device 100. The edge termination structure mitigates the electric field concentration on the upper surface of the semiconductor substrate 10. The edge termination structure may include, for example, a protective ring, a field plate, a surface electric field reducing component, and a structure combining these components. It should be noted that, for convenience, only the negative Y-axis edge is described in this example, but the same applies to the other edges of the semiconductor device 100.

[0054] The semiconductor substrate 10 can be a silicon substrate, a silicon carbide substrate, or a gallium nitride or other nitride semiconductor substrate. In this example, the semiconductor substrate 10 is a silicon substrate.

[0055] The semiconductor device 100 in this example has a gate trench 40, a dummy trench 30, an emitter region 12, a base region 14, a contact region 15, and a well region 17 on the front side of the semiconductor substrate 10. In addition, the semiconductor device 100 in this example has an emitter electrode 52 and a gate metal layer 50 disposed on the upper part of the front side of the semiconductor substrate 10.

[0056] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, and the well region 17. Additionally, the gate metal layer 50 is disposed above the gate trench portion 40 and the well region 17.

[0057] The emitter electrode 52 and the gate metal layer 50 are formed of a metal-containing material. For example, at least a portion of the emitter electrode 52 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. At least a portion of the gate metal layer 50 may be formed of aluminum, an aluminum-silicon alloy, or an aluminum-silicon-copper alloy. The emitter electrode 52 and the gate metal layer 50 may have a barrier metal formed of titanium, titanium compounds, or the like beneath the regions formed of aluminum, etc. The emitter electrode 52 and the gate metal layer 50 are disposed separately from each other.

[0058] The emitter electrode 52 and the gate metal layer 50 are disposed above the semiconductor substrate 10, separated by an interlayer insulating film 38. Figure 1A The interlayer insulating film 38 is omitted. Contact holes 54, 55 and 56 are provided through the interlayer insulating film 38.

[0059] The contact hole 55 connects the gate metal layer 50 to the gate conductive portion within the transistor section 70. A plug made of tungsten or the like may be formed inside the contact hole 55.

[0060] The contact hole 56 connects the emitter electrode 52 to the dummy conductive part within the dummy trench portion 30. A plug made of tungsten or the like can be formed inside the contact hole 56.

[0061] The connection portion 25 electrically connects the front-side electrode, such as the emitter electrode 52 or the gate metal layer 50, to the semiconductor substrate 10. In one example, the connection portion 25 is disposed between the gate metal layer 50 and the gate conductive portion. The connection portion 25 is also disposed between the emitter electrode 52 and the dummy conductive portion. The connection portion 25 is made of a conductive material such as polysilicon doped with impurities. Here, the connection portion 25 is polysilicon (N+) doped with N-type impurities. The connection portion 25 is disposed above the front side of the semiconductor substrate 10 through an insulating film such as an oxide film.

[0062] The gate trench portions 40 are arranged at predetermined intervals along a predetermined arrangement direction (X-axis direction in this example). In this example, the gate trench portions 40 may have two extension portions 41 extending along an extension direction (Y-axis direction in this example) that is parallel to the front surface of the semiconductor substrate 10 and perpendicular to the arrangement direction. The connection portion 43 connects the two extension portions 41.

[0063] The connection portion 43 is preferably at least partially formed in a curved shape. By connecting the ends of the two extension portions 41 of the gate trench portion 40, the electric field concentration at the ends of the extension portions 41 can be mitigated. At the connection portion 43 of the gate trench portion 40, the gate metal layer 50 can be connected to the gate conductive portion.

[0064] The dummy trench portion 30 is a trench portion electrically connected to the emitter electrode 52. Like the gate trench portion 40, the dummy trench portions 30 are arranged at predetermined intervals along a predetermined arrangement direction (the X-axis direction in this example). Similar to the gate trench portion 40, the dummy trench portion 30 in this example can have a U-shape on the front side of the semiconductor substrate 10. That is, the dummy trench portion 30 can have two extension portions 31 extending along the extension direction and a connecting portion 33 connecting the two extension portions 31.

[0065] The transistor section 70 in this example has a structure in which two gate trench sections 40 and three dummy trench sections 30 are repeatedly arranged. That is, the transistor section 70 in this example has gate trench sections 40 and dummy trench sections 30 in a 2:3 ratio. For example, the transistor section 70 has an extension section 31 between two extension sections 41. In addition, the transistor section 70 has two extension sections 31 adjacent to the gate trench sections 40.

[0066] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 to the dummy trench portion 30 can be 1:1 or 2:4. Alternatively, it can be configured as a so-called all-gate structure in which the transistor portion 70 does not have dummy trench portions 30 and is entirely composed of gate trench portions 40.

[0067] Well region 17 is a second conductivity type region located further on the front side of the semiconductor substrate 10 than drift region 18, which will be described later. Well region 17 is an example of a well region located on the edge side of the semiconductor device 100. As an example, well region 17 is P+ type. Well region 17 is formed within a predetermined range from the end of the active region on the side where the gate metal layer 50 is located. The diffusion depth of well region 17 can be deeper than the depth of gate trench portion 40 and dummy trench portion 30. A portion of the gate trench portion 40 and dummy trench portion 30 on the gate metal layer 50 side is formed in well region 17. The bottom of the ends of the gate trench portion 40 and dummy trench portion 30 in the extending direction can be covered by well region 17.

[0068] Contact holes 54 are formed in the transistor section 70 above each region of the emitter region 12 and the contact region 15. Additionally, contact holes 54 are provided above the base region 14 in the diode section 80. Contact holes 54 are provided above the contact region 15 in the boundary section 90. Contact holes 54 are provided above the base region 14 in the diode section 80. None of the contact holes 54 are provided above the well regions 17 located at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 can extend along the extension direction. It should be noted that a plug region 19 can be provided below the contact hole 54. The plug region 19 will be described later.

[0069] The boundary portion 90 is a region disposed on the transistor portion 70 and adjacent to the diode portion 80. The boundary portion 90 includes a contact region 15. In this example, the boundary portion 90 does not include the emitter region 12. In one example, the trench portion of the boundary portion 90 is a dummy trench portion 30. In this example, the boundary portion 90 is configured such that both ends in the X-axis direction are dummy trench portions 30.

[0070] Mesa-faces 71, 91, and 81 are mesa-faces provided adjacent to the trench portions in a plane parallel to the front surface of the semiconductor substrate 10. A mesa-face refers to the portion of the semiconductor substrate 10 sandwiched between two adjacent trench portions, and can be the portion extending from the front surface of the semiconductor substrate 10 to the deepest bottom of each trench portion. Each trench portion can be defined as an extension portion of a single trench portion. In other words, the area sandwiched between two extension portions can be considered a mesa-face.

[0071] The mesa portion 71 is disposed adjacent to at least one of the dummy trench portion 30 or the gate trench portion 40 in the transistor portion 70. The mesa portion 71 includes a well region 17, an emitter region 12, a base region 14, and a contact region 15 on the front side of the semiconductor substrate 10. In the mesa portion 71, the emitter region 12 and the contact region 15 are disposed alternately in the extending direction.

[0072] A mesa 91 is provided on the boundary portion 90. The mesa 91 has a contact area 15 and a well area 17 on the front side of the semiconductor substrate 10.

[0073] The mesa portion 81 is disposed in the diode portion 80 in the region sandwiched by the adjacent dummy trench portion 30. The mesa portion 81 has a base region 14, a contact region 15, and a well region 17 on the front side of the semiconductor substrate 10.

[0074] The base region 14 is a region of a second conductivity type disposed on the front side of the semiconductor substrate 10 in the transistor section 70 and the diode section 80. As an example, the base region 14 is P-type. The base region 14 can be disposed at both ends of the mesa 71 and mesa 91 in the Y-axis direction on the front side of the semiconductor substrate 10. It should be noted that... Figure 1A Only one end of the base region 14 in the Y-axis direction is shown.

[0075] Emitter region 12 is a region of the first conductivity type with a doping concentration higher than that of drift region 18. As an example, emitter region 12 in this example is N+ type. An example of the dopant for emitter region 12 is arsenic (As). Emitter region 12 is disposed on the front side of mesa 71 in contact with gate trench portion 40. Emitter region 12 can extend from one of the two trench portions sandwiching mesa 71 along the X-axis to the other trench portion. Emitter region 12 is also disposed below contact hole 54.

[0076] Furthermore, the emission area 12 may or may not contact the dummy groove portion 30. In this example, the emission area 12 contacts the dummy groove portion 30. The emission area 12 may not be provided on the platform surface 91 of the boundary portion 90.

[0077] Contact region 15 is a region of the second conductivity type with a higher doping concentration than the base region 14. As an example, contact region 15 in this example is P+ type. In this example, contact region 15 is disposed on the front side of mesa 71 and mesa 91. Contact region 15 can be disposed in the X-axis direction from one of the two trench portions sandwiching mesa 71 or mesa 91 to the other. Contact region 15 may or may not contact the gate trench portion 40. Additionally, contact region 15 may or may not contact the dummy trench portion 30. In this example, contact region 15 contacts both the dummy trench portion 30 and the gate trench portion 40. Contact region 15 is also disposed below contact hole 54. It should be noted that contact region 15 may also be disposed on mesa 81.

[0078] Figure 1B It means Figure 1A The figure shows an example of the a-a' cross-section. The a-a' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in the a-a' cross-section. The emitter electrode 52 is formed above the semiconductor substrate 10 and the interlayer insulating film 38.

[0079] Drift region 18 is a region of a first conductivity type disposed on semiconductor substrate 10. As an example, drift region 18 in this example is N-type. Drift region 18 can be a region remaining in semiconductor substrate 10 where no other doped regions are formed. That is, the doping concentration of drift region 18 can be the doping concentration of semiconductor substrate 10.

[0080] Buffer 20 is a region of the first conductivity type disposed below drift region 18. As an example, buffer 20 in this example is N-type. The doping concentration of buffer 20 is higher than that of drift region 18. Buffer 20 can function as a field blocking layer to prevent the depletion layer extending from the lower surface side of base region 14 from reaching the collector region 22 of the second conductivity type and the cathode region 82 of the first conductivity type.

[0081] The collector region 22 is disposed below the buffer zone 20 in the transistor section 70. The cathode region 82 is disposed below the buffer zone 20 in the diode section 80. The boundary between the collector region 22 and the cathode region 82 is the boundary between the transistor section 70 and the diode section 80.

[0082] Collector electrode 24 is formed on the back side 23 of semiconductor substrate 10. Collector electrode 24 is formed of conductive material such as metal.

[0083] The base region 14 is a second conductivity type region disposed above the drift region 18 in the mesa 71, mesa 91, and mesa 81. The base region 14 is disposed in contact with the gate trench portion 40. The base region 14 may be disposed in contact with the dummy trench portion 30.

[0084] The emitter region 12 is disposed in the mesa 91 between the base region 14 and the front surface 21. The emitter region 12 is disposed in contact with the gate trench portion 40. The emitter region 12 may or may not be in contact with the dummy trench portion 30. It should be noted that the emitter region 12 may not be disposed in the mesa 91.

[0085] The contact area 15 is disposed above the base region 14 in the mesa 91. The contact area 15 is disposed in contact with the gate trench portion 40 in the mesa 91. In other cross-sections, the contact area 15 may be disposed on the front surface 21 of the mesa 71.

[0086] The plug region 19 is a region of a second conductivity type with a higher doping concentration than the contact region 15. As an example, the plug region 19 in this example is of the P++ type. In this example, the plug region 19 is located on the front side 21. In the mesa 91, the plug region 19 is located above the contact region 15. In the mesa 81, the plug region 19 is located above the base region 14. The plug region 19 can be provided on the mesa 91 and mesa 81 in a manner that extends along the contact hole 54 in the Y-axis direction.

[0087] The accumulation region 16 is a first conductivity type region located further on the front side 21 of the semiconductor substrate 10 than the drift region 18. As an example, the accumulation region 16 in this example is N+ type. The accumulation region 16 is provided in the transistor section 70 and the diode section 80. In this example, the accumulation region 16 is also provided in the boundary section 90. Therefore, the semiconductor device 100 can prevent mask deviation of the accumulation region 16.

[0088] Additionally, the accumulation region 16 is disposed in contact with the gate trench portion 40. The accumulation region 16 may or may not be in contact with the dummy trench portion 30. The doping concentration of the accumulation region 16 is higher than that of the drift region 18. The ion implantation dose of the accumulation region 16 can be 1E12cm⁻¹. -2 Above and 1E13cm -2 The following is an explanation. Additionally, the ion implantation dose in accumulation region 16 can be 3E12cm. -2 Above and 6E12cm -2 The following describes how, by setting the accumulation region 16, the carrier injection enhancement effect (IE effect) can be improved, thereby reducing the turn-on voltage of the transistor section 70. It should be noted that E refers to a power of 10, for example, 1E12cm. -2 It refers to 1×10 12 cm-2 .

[0089] One or more gate trench portions 40 and one or more dummy trench portions 30 are disposed on the front side 21. Each trench portion extends from the front side 21 to the drift region 18. In regions where at least one of the emitter region 12, base region 14, contact region 15, and accumulation region 16 is disposed, each trench portion also extends through these regions to reach the drift region 18. The trench portion extending through the doped region is not limited to the case where the trench portions are formed after the doped regions are formed. The case where doped regions are formed between the trench portions after the trench portions are formed is also included in the case where the trench portions extend through the doped regions.

[0090] The gate trench portion 40 has a gate trench formed on the front side 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed by covering the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate trench at a position closer to the inner side of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered on the front side 21 by an interlayer insulating film 38.

[0091] The gate conductive portion 44 includes a region in the depth direction of the semiconductor substrate 10 that faces the base region 14 adjacent to the mesa 71 side separated by the gate insulating film 42. If a predetermined voltage is applied to the gate conductive portion 44, an electron-based inversion layer channel is formed on the surface layer of the interface in the base region 14 that contacts the gate trench.

[0092] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front side 21. The dummy insulating film 32 is formed by covering the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is located further inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy trench portion 30 is covered on the front side 21 by an interlayer insulating film 38.

[0093] An interlayer insulating film 38 is disposed on the front side 21. An emitter electrode 52 is disposed above the interlayer insulating film 38. One or more contact holes 54 are provided on the interlayer insulating film 38 for electrically connecting the emitter electrode 52 to the semiconductor substrate 10. Contact holes 55 and 56 may also be provided through the interlayer insulating film 38.

[0094] The lifetime control region 150 is a region intentionally formed with lifetime inhibitors by injecting impurities or the like into the interior of the semiconductor substrate 10. A lifetime inhibitor is a recombination center for charge carriers. A lifetime inhibitor can be a crystal defect. For example, a lifetime inhibitor can be a vacancy, multiple vacancyes, a recombination defect between these vacancyes and elements constituting the semiconductor substrate 10, or a dislocation. Alternatively, a lifetime inhibitor can also be a rare gas element such as helium or neon, or a metallic element such as platinum. The lifetime control region 150 can be formed by injecting helium or the like into the semiconductor substrate 10.

[0095] A lifetime control region 150 is disposed on the front side 21 of the semiconductor substrate 10. The lifetime control region 150 is disposed on both the transistor section 70 and the diode section 80. The lifetime control region 150 can be formed by implanting impurities from the front side 21 or by implanting impurities from the back side 23. The lifetime control region 150 is an example of a first lifetime control region disposed on the front side 21.

[0096] In this example, the lifetime control region 150 is disposed on the entire surface of the semiconductor substrate 10. Therefore, the lifetime control region 150 can be formed without using a mask. The dosage of impurities used to form the lifetime control region 150 can be 0.5E10cm⁻¹. -2 Above and 1E13cm -2 The following applies. Additionally, the dosage of impurities used to form the lifetime control region 150 can be 5E10cm⁻¹. -2 Above and 5E11cm -2 the following.

[0097] Furthermore, in this example, the lifetime control region 150 is formed by implantation from the back side 23. For example, the lifetime control region 150 is formed by irradiating helium from the back side 23. This avoids impacting the front side 21 of the semiconductor device 100. Whether the lifetime control region 150 is formed by implantation from the front side 21 or from the back side 23 can be determined by measuring the state of the front side 21 using the SR method or leakage current measurement.

[0098] A lifetime control region 160 is disposed on the back side 23 of the semiconductor substrate 10. The lifetime control region 160 is disposed on both the transistor section 70 and the diode section 80. The lifetime control region 160 is disposed at a position closer to the front side 21 than the buffer zone 20. The lifetime control region 160 can be disposed within the buffer zone 20.

[0099] Furthermore, the lifetime control region 160 is disposed on the entire surface of the back side 23 of the semiconductor substrate 10. That is, the lifetime control region 160 can be formed without using a mask. The lifetime control region 160 can be formed using any of the methods for forming the lifetime control region 150. It can be formed by implanting impurities from the back side 23 of the semiconductor substrate 10. The lifetime control region 160 is an example of a second lifetime control region disposed on the back side 23 of the semiconductor substrate 10.

[0100] Figure 1C It means Figure 1A The figure shows an example of the b-b' section. The b-b' section is the XZ plane passing through the contact area 15 in the transistor section 70.

[0101] The platform 71 has a base region 14, a contact region 15, a storage region 16, and a plug region 19. The plug region 19 improves the RBSOA (Reverse Bias Safe Operating Area) tolerance. The platform 91 has the same base region 14, contact region 15, storage region 16, and plug region 19 as in the a-a' section. In the b-b' section, the platform 71 has the same structure as the platform 91. The platform 81 has the same base region 14, storage region 16, and plug region 19 as in the a-a' section.

[0102] Lifetime control regions 150 and 160 are provided on both sides of transistor section 70 and diode section 80 in the same manner as in the case of section a-a'.

[0103] In this example, the semiconductor device 100 has lifetime control regions 150 on both the transistor section 70 and the diode section 80. Therefore, the extraction of holes during turn-off becomes more uniform, and the carrier balance between the transistor section 70 and the diode section 80 is improved. Furthermore, the RBSOA withstand capability and short-circuit withstand capability are improved, and the latch-up withstand capability is also enhanced.

[0104] Figure 2A This is an example of a top view of a semiconductor device 100 according to an embodiment. In this example of the semiconductor device 100, the arrangement of the dummy trench portion 30 and the gate trench portion 40 is similar to... Figure 1A The semiconductor device 100 is different. In this example, it is different from the semiconductor device 100. Figure 1A The differences in the embodiments will be specifically explained. In this example, the ratio of the dummy groove portion 30 is greater than... Figure 1A The ratio of the cases in the embodiments.

[0105] The transistor section 70 has gate trench sections 40 and dummy trench sections 30 arranged repeatedly in a ratio of 2:4 between gate trench sections 40 and dummy trench sections 30. A set of dummy trench sections 30 connected by the connecting portion 33 is provided inside a set of gate trench sections 40 connected by the connecting portion 43.

[0106] Figure 2B It means Figure 2A The diagram shows an example of a c-c' cross-section. The c-c' cross-section is the XZ plane passing through the emitter region 12 in the transistor section 70. The semiconductor device 100 in this example is similar to [the previous example] in that it has a two-stage accumulation region 16 consisting of accumulation regions 16a and 16b. Figure 1B The semiconductor device 100 is different. In this example, it is different from the semiconductor device 100. Figure 1B The differences between the embodiments are specifically explained.

[0107] Accumulation regions 16a and 16b are disposed on both sides of the transistor section 70 and the diode section 80. The doping concentrations of accumulation regions 16a and 16b can be the same or different. The doping concentration of accumulation region 16a can be greater than or less than the doping concentration of accumulation region 16b. It should be noted that the doping concentration of accumulation region 16 can refer to the peak value of the doping concentration of each accumulation region 16.

[0108] Accumulation region 16a is a first accumulation region located further to the front side 21 than drift region 18. Accumulation region 16a is located below base region 14. In one example, the ion implantation dose of accumulation region 16a is 1E12cm. -2 Above and 1E13cm -2 Below. For example, accumulation zone 16a with a diameter of 3E12cm. -2 The dosage and 2.6 MeV accelerated energy formation.

[0109] Accumulation region 16b is a second accumulation region located below accumulation region 16a. In one example, the ion implantation dose in accumulation region 16b is 1E12cm. -2 Above and 1E13cm -2 Below. For example, accumulation zone 16b with 3E12cm -2 The dose and 3.9 MeV acceleration energy are formed. The accumulation region 16a and the accumulation region 16b may be a drift region 18. It should be noted that the semiconductor device 100 in this example has two levels of accumulation regions 16, but it may also have three or more levels of accumulation regions 16.

[0110] Figure 2C It means Figure 2A A diagram showing an example of the d-d' cross-section. The d-d' cross-section is the XZ plane passing through the contact region 15 in the transistor section 70. The semiconductor device 100 in this example is similar to [the example shown] in having accumulation regions 16a and 16b. Figure 1C The semiconductor device 100 is different. In this example, it is different from the semiconductor device 100. Figure 1C The differences between the embodiments are specifically explained.

[0111] Accumulation regions 16a and 16b are disposed on both sides of the transistor section 70 and the diode section 80 in the same manner as the c-c' section. Accumulation regions 16a and 16b can be disposed under the same conditions as the c-c' section.

[0112] The semiconductor device 100 improves the inductance performance by having two-stage accumulation regions 16, thereby easily reducing the on-resistance of the transistor section 70. Furthermore, by providing the lifetime control region 150 across the entire surface, the semiconductor device 100 can suppress capacity degradation. Therefore, the semiconductor device 100 in this example can both reduce on-resistance and suppress capacity degradation.

[0113] Figure 2D This is a graph used to illustrate the differences in characteristics caused by the number of stages in the accumulation region 16. The vertical axis represents the turn-off loss Eoff (mJ), and the horizontal axis represents the collector-emitter saturation voltage Vce (sat) (V).

[0114] Curve 101 represents the characteristics when accumulation zone 16 is at level 1. In other words, curve 101 corresponds to... Figures 1A to 1C The semiconductor device 100. Curve 102 represents the characteristics when the accumulation region 16 is at level 2. Curve 102 corresponds to Figures 2A to 2C Semiconductor device 100.

[0115] The combined doping concentration of accumulation regions 16a and 16b, with doping concentration set to level 2, is equal to the doping concentration of accumulation region 16 in the level 1 case. Furthermore, the doping concentration of accumulation region 16a is the same as that of accumulation region 16b. For example, the doping concentration of level 1 accumulation region 16 is 1E12cm⁻¹. -3 In this case, the corresponding doping concentrations for the second stage are 0.5E12cm. -3 The figure shows the doping concentration corresponding to each curve. In this example, the curves represent the doping concentration of accumulation region 16 as 1E12cm⁻¹. -3 3E12cm -3 6E12cm -3 1E13cm -3 and 1.2E13cm -3 The situation.

[0116] The collector-emitter saturation voltage Vce(sat) tends to be smaller as the doping concentration in the accumulation region 16 increases. However, in the region with a high doping concentration in the accumulation region 16, the turn-off loss Eoff tends to increase due to the IE effect.

[0117] In the region where the collector-emitter saturation voltage Vce(sat) is relatively large, curves 101 and 102 overlap, and the difference in characteristics becomes smaller. On the other hand, in the region where the collector-emitter saturation voltage Vce(sat) is relatively small, curve 102 has a smaller turn-off loss Eoff compared to curve 101.

[0118] Therefore, in the semiconductor device 100, setting the accumulation region 16 to a two-stage structure makes it easier to suppress the collector-emitter saturation voltage Vce(sat) and reduce the turn-off loss Eoff. Furthermore, in the semiconductor device 100, setting the accumulation region 16 to a two-stage structure allows for an increase in the doping concentration of the accumulation region 16 without increasing the turn-off loss Eoff.

[0119] Figure 3 This is an example of a cross-sectional view obtained by magnifying the vicinity of the mesa 71. In this example, the mesa 71, which is sandwiched between the dummy trench portion 30 and the gate trench portion 40, is shown.

[0120] Depth D1 is the depth of the trench in the dummy trench portion 30 or the gate trench portion 40. Depth D1 can be the depth of the lower end of the dummy insulating film 32 or the gate insulating film 42. Depth D1 is appropriately set according to the characteristics of the semiconductor device 100, etc.

[0121] Depth D2 is the depth of the lifetime control region 150 measured from the front side 21. In this example, depth D2 is deeper than depth D1. That is, the lifetime control region 150 is located below the dummy trench portion 30 and the gate trench portion 40. For example, depth D2 is 5 μm or more and 20 μm or less.

[0122] Depth D3 is the depth of the accumulation region 16 measured from the front side 21. In one example, depth D3 is the depth of the lower end of the accumulation region 16. When the accumulation region 16 has multiple levels, depth D3 can be the depth of the lower end of the lowest accumulation region 16. The depth of the lower end of the accumulation region 16 refers to the depth of the boundary between the accumulation region 16 and the drift region 18. That is, the lower end of the accumulation region 16 is the position where the doping concentration of the accumulation region 16 becomes the doping concentration of the drift region 18. Alternatively, depth D3 can also be the depth of the peak position of the doping concentration of the accumulation region 16. For example, depth D3 is 1 μm or more and 5 μm or less. In one example, depth D3 is 3 μm.

[0123] It should be noted that depth D2 is deeper than depth D1. Depth D2 can be twice as deep as depth D3. In this case, a gap of depth D3 or greater is provided between the life control region 150 and the accumulation region 16. Thus, by providing a gap between the life control region 150 and the accumulation region 16, the tolerance can be increased through the life control region 150 without sacrificing the effect of reducing the on-resistance brought about by the accumulation region 16.

[0124] The lifetime control region 150 has a depth of less than 20 μm, measured from the front side 21. In one example, the lifetime control region 150 has a depth of 10 μm, measured from the front side 21.

[0125] Depth D3 is within the trench depth of the trench section. "Within the trench depth" includes both cases where the depth is the same as the trench depth and cases where it is shallower than the trench depth. The accumulation zone 16 may not be located deeper than the trench section. That is, depth D3 ≤ depth D1 holds true.

[0126] Figure 4 This is an example of a top view showing the chip end of the semiconductor device 100. In this example, a top view is shown at the negative end of the emitter electrode 52 in the X-axis and Y-axis directions.

[0127] The emitter electrode 52 is provided to cover the dummy trench portion 30 and the gate trench portion 40. In this example, the gate trench portion 40 is electrically connected to the gate metal layer 50 via the gate flow channel 45.

[0128] The gate channel 45 electrically connects the gate metal layer 50 to the gate trench portion 40 via contact holes provided in the interlayer insulating film 38. In this example, the gate channel 45 is electrically connected to the gate conductive portion 44 on the front side 21. The gate channel 45 is not connected to the dummy conductive portion within the dummy trench portion 30. For example, the gate channel 45 is formed of polysilicon or the like, which is doped with impurities.

[0129] Region R12 represents the area where emitter region 12 and contact region 15 are repeatedly disposed. That is, it is not necessary to provide emitter region 12 on the entire surface of region R12. The outer periphery of region R12 is defined by the emitter region 12 located on the outermost side when viewed from above. For example, region R12 functions as an active region for the main current to flow through the transistor section 70.

[0130] Region R16 is the region where the accumulation area 16 is provided. The accumulation area 16 can be provided across the entire surface of region R16. However, even within region R16, the accumulation area 16 may not be provided in areas where the dummy trench portion 30 and the gate trench portion 40 are provided. In this example, region R16 is located in an area larger than region R12 when viewed from above.

[0131] Region R15 is a region where contact area 15 is provided. Region R15, like region R12, may include areas where emission area 12 and contact area 15 are repeatedly provided. Insertion area 19 may be repeatedly provided in region R15.

[0132] In the semiconductor device 100 of this example, region R16 is provided to cover region R12. Therefore, the active region of the transistor section 70 is less susceptible to the influence of mask deviation of the accumulation region 16. Furthermore, in the semiconductor device 100, region R15 is provided to cover region R16. Moreover, the lifetime control region 150 is provided to cover region R15, thereby avoiding the influence of mask deviation of the lifetime control region 150. It should be noted that when the lifetime control region 150 is provided over the entire surface of the semiconductor substrate 10, the influence of mask deviation of the lifetime control region 150 does not occur.

[0133] Figure 5 This is an example of a cross-sectional view of a comparative semiconductor device 500. In this example, a cross-sectional view of the boundary between the transistor section 570 and the diode section 580 included in the semiconductor device 500 is shown.

[0134] The semiconductor device 500 has an accumulation region 516 in the transistor section 570. The semiconductor device 500 does not have an accumulation region 516 in the diode section 580, and may sometimes be affected by mask deviation of the accumulation region 516.

[0135] Additionally, the semiconductor device 500 includes a lifetime control region 550 disposed on the front side 21 of the semiconductor substrate 10. The semiconductor device 500 also includes a lifetime control region 560 disposed on the back side 23 of the semiconductor substrate 10.

[0136] The lifetime control region 550 is located in the diode section 580, but not in the transistor section 570. That is, the lifetime control region 550 is formed by partial irradiation, not by irradiation of the entire surface of the impurity. For partial irradiation of the lifetime control region 550, a mask such as a resist mask or a metal mask is required. Therefore, the semiconductor device 500 may sometimes be affected by mask deviation of the lifetime control region 550.

[0137] In contrast, the semiconductor device 100 of this embodiment has lifetime control regions 150 in the transistor section 70 and the diode section 80, thus preventing mask misalignment. Furthermore, since it is not necessary to form a mask for the lifetime control regions 150, the process steps are simplified. In the semiconductor device 100, hole extraction during turn-off becomes more uniform, and the carrier balance between the transistor section 70 and the diode section 80 is improved.

[0138] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As can be seen from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0139] It should be noted that the execution order of actions, processes, steps, and stages in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order, unless specifically stated as "earlier than" or "before," and the results of previous processes are not used in subsequent processes. Even if the flow of actions in the claims, specification, and drawings is described using terms such as "firstly" or "next" for convenience, it does not mean that they must be implemented in that order.

Claims

1. A semiconductor device, characterized in that, It has a transistor section and a diode section, and also has: A drift region of the first conductivity type is disposed on a semiconductor substrate; The first conductivity type accumulation region is disposed in the transistor portion and the diode portion at a position closer to the front side of the semiconductor substrate than the drift region; as well as A first lifetime control region is disposed on the front side of the semiconductor substrate in the transistor portion and the diode portion. The accumulation zone has: A first accumulation zone is located further along the front side than the drift zone; and The second accumulation zone is disposed below the first accumulation zone, separated from the drift zone. The dose in the first accumulation zone is the same as that in the second accumulation zone, and the total dose in the first accumulation zone and the second accumulation zone is 1E12cm. -2 Above and 1E13cm -2 the following.

2. The semiconductor device according to claim 1, characterized in that, The first lifetime control region is disposed on the entire surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, characterized in that, It has a second lifetime control area disposed on the entire back side of the semiconductor substrate.

4. The semiconductor device according to claim 2, characterized in that, It has a second lifetime control area disposed on the entire back side of the semiconductor substrate.

5. The semiconductor device according to claim 1, characterized in that, It has multiple trench portions disposed on the front side of the semiconductor substrate. The depth of the first lifetime control zone is deeper than the depth of the plurality of trenches.

6. The semiconductor device according to claim 2, characterized in that, It has multiple trench portions disposed on the front side of the semiconductor substrate. The depth of the first lifetime control zone is deeper than the depth of the plurality of trenches.

7. The semiconductor device according to claim 3, characterized in that, It has multiple trench portions disposed on the front side of the semiconductor substrate. The depth of the first lifetime control zone is deeper than the depth of the plurality of trenches.

8. The semiconductor device according to claim 4, characterized in that, It has multiple trench portions disposed on the front side of the semiconductor substrate. The depth of the first lifetime control zone is deeper than the depth of the plurality of trenches.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, The depth of the accumulation zone is within the groove depth of the multiple trench sections.

10. The semiconductor device according to any one of claims 1 to 8, characterized in that, The depth of the first lifetime control zone is twice the depth of the boundary between the accumulation zone and the drift zone.

11. The semiconductor device according to any one of claims 1 to 8, characterized in that, The depth of the first lifetime control region is greater than 5 μm and less than 20 μm.

12. The semiconductor device according to any one of claims 1 to 8, characterized in that, The dose of the lifetime inhibitor in the first lifetime control region is 0.5E10cm. -2 Above and 1E13cm -2 the following.

13. The semiconductor device according to claim 12, characterized in that, The first lifetime control region is implanted from the back side of the semiconductor substrate.

14. The semiconductor device according to any one of claims 1 to 8, characterized in that, The depth of the accumulation zone is above 1 μm and below 5 μm.

15. The semiconductor device according to any one of claims 1 to 8, characterized in that, The transistor section has an emitter region of a first conductivity type with a doping concentration higher than that of the drift region. The accumulation area, when viewed from above, is located over a larger area than the area where the launch area is located.

16. The semiconductor device according to any one of claims 1 to 8, characterized in that, The transistor section has: The boundary portion, which is adjacent to the diode portion; and A dummy groove is provided, which is electrically connected to the emitter electrode. The groove portion of the boundary portion is the dummy groove portion.

17. The semiconductor device according to claim 16, characterized in that, The boundary portion has: The accumulation area; The base region of the second conductivity type is disposed on the front side; A contact region, located further to the front side than the base region, and having a higher doping concentration than the base region; and The second conductivity type plug region is disposed on the front side of the contact region and has a higher doping concentration than the contact region.

18. The semiconductor device according to claim 16, characterized in that, The boundary portion does not have a launch zone.

19. The semiconductor device according to claim 17, characterized in that, The boundary portion does not have a launch zone.

20. A manufacturing method, characterized in that, This is a method for manufacturing a semiconductor device having a transistor section and a diode section, the method comprising: The stage of setting a drift region of the first conductivity type on the semiconductor substrate; In the transistor section and the diode section, a stage is performed where an accumulation region of a first conductivity type is formed at a position closer to the front side of the semiconductor substrate than the drift region; and In the stage where a first lifetime control region is formed on the front side of the semiconductor substrate in both the transistor section and the diode section, The accumulation zone has: A first accumulation zone is located further along the front side than the drift zone; and The second accumulation zone is disposed below the first accumulation zone, separated from the drift zone. The dose in the first accumulation zone is the same as that in the second accumulation zone, and the total dose in the first accumulation zone and the second accumulation zone is 1E12cm. -2 Above and 1E13cm -2 the following.

21. The manufacturing method according to claim 20, characterized in that, The stage of setting the first lifetime control region includes the stage of irradiating impurities from the back side of the semiconductor substrate.

22. The manufacturing method according to claim 20, characterized in that, The stage of setting the first lifetime control zone includes 0.5E10cm -2 Above and 1E12cm -2 The following dosage is injected during the impurity stage.

23. The manufacturing method according to claim 21, characterized in that, The stage of setting the first lifetime control zone includes 0.5E10cm -2 Above and 1E12cm -2 The following dosage is injected during the impurity stage.

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