A multi-port register file based on a single-ended voltage sense amplifier structure

Abstract

The application relates to a multi-port register file based on a single-ended voltage sensitive amplifier structure, which comprises a storage unit array, a read address decoder, a write address decoder, a read data path and a write data path; the storage unit array is composed of a cross-coupled inverter pair to form a storage node, and is provided with multiple write ports and multiple read ports; the read address decoder and the write address decoder are both realized by full static logic; the read data path is realized by a single-ended voltage sensitive amplifier and an RS latch structure to realize a read operation; and the write data path adopts a segmented write bit line mode to perform block driving on write data. The application improves performance while reducing dynamic power consumption.

Description

Technical Field

[0001] This invention relates to the field of multi-port register file technology for microprocessors, and in particular to a multi-port register file based on a single-ended voltage-sensitive amplifier structure. Background Technology

[0002] In superscalar microprocessors, the register file (RF) requires multiple ports for simultaneous read and write operations. To meet performance requirements, a custom-built bitcell with multiple read and write ports is typically used, employing a dynamic domino structure to improve read performance. However, with further improvements in processor architecture, the demands on the number of register file ports and entries have increased. While this meets system requirements, it limits the performance and physical feasibility of the register file itself. Therefore, to improve processor performance, a superior register file design approach is needed to address the challenges of multiple ports and entries.

[0003] As the number of ports increases, the area of ​​the bitcell grows larger, further impacting the line load of the wordline. Advanced manufacturing processes worsen the underlying line resistance, increasing the complexity of layout design. With the increase in the number of entries, the read bitline load becomes increasingly heavy, and the two-level dynamic line-OR structure can no longer meet design requirements. To address these issues, the industry typically uses multiplexing arrays to split ports, reducing the design complexity of a single array, but this incurs higher array area costs and increases the complexity of upper-level designs. Another approach is time-division multiplexing to compress the number of ports, completing multiple reads and writes within a single clock cycle, but this introduces more complex control designs, impacting the performance of the register file and causing reliability issues, resulting in limited benefits. Therefore, more efficient design methods are needed to meet application requirements. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a multi-port register file implementation method based on a single-ended voltage sensitive amplifier structure, which meets the requirements of simultaneous reading and writing of multiple ports and the requirement of realizing read and write operations within one clock cycle, realizes a multi-port high-performance register file design, improves performance and reduces dynamic power consumption.

[0005] The technical solution adopted by this invention to solve its technical problem is as follows: A multi-port register file based on a single-ended voltage-sensitive amplifier structure is provided, including: a memory cell array, a read address decoder, a write address decoder, a read data path, and a write data path; the memory cell array consists of cross-coupled inverter pairs forming memory nodes, and simultaneously has multiple write ports and multiple read ports; both the read address decoder and the write address decoder are implemented using fully static logic; the read data path uses a single-ended voltage-sensitive amplifier and RS latch structure to implement the read operation, achieving the purpose of quickly reading valid data by amplifying the swing signal; the write data path uses a segmented write bit line method for block-driven write data.

[0006] Each write port of the memory cell array is a single-ended write port consisting of 3 transistors, used to ensure strong '0' writing to the positive and negative points of the memory node to realize write '0' and write '1' operations.

[0007] Each read port of the memory cell array is a single-ended read port with a pull-down structure consisting of two transistors. It is structurally isolated from the memory node, and multiple read ports are evenly connected to the positive and negative points of the memory node.

[0008] The read address decoder includes: a dynamic differential read address generation module, a dynamic read enable narrow pulse width generation module, a static logic full decoding module, and a precharge clock and amplifier enable generation module. The dynamic differential read address generation module generates a differential dynamic address signal through a positive edge clock-gated latch for subsequent read address decoding. The dynamic read enable narrow pulse width generation module generates a dynamic read enable through a positive edge clock-gated latch and generates a narrow pulse width read enable through a pulse signal generator, which participates in subsequent read address decoding. The static logic full decoding module performs full decoding of the differential dynamic address signal and the narrow pulse width read enable through static logic, ultimately generating a narrow pulse width read word line to enable any entry for read operations on the memory array. The precharge clock and amplifier enable generation module generates a precharge signal from the input read enable through a positive edge clock-gated latch, and the precharge signal generates a sensitive amplifier enable signal through a delay gating unit.

[0009] The read data path includes a single-ended voltage sensitive amplifier and an RS latch; the single-ended voltage sensitive amplifier is composed of a reference voltage generator and a high-resolution voltage latch type voltage sensitive amplifier. One end of the differential input signal of the high-resolution voltage latch type voltage sensitive amplifier is connected to the read port bit line, and the other end is connected to the reference voltage generator; the RS latch is constructed by a static NOR gate, which, in conjunction with the single-ended voltage sensitive amplifier, extends and holds the read pulse signal until the next read operation.

[0010] The single-ended voltage sensitive amplifier uses a shared charge method to achieve a fixed reference voltage. Combined with the discharge situation on the bitline, the voltage swing difference is amplified and output by the single-ended voltage sensitive amplifier to complete the read 0 or read 1 operation.

[0011] The write address decoder includes a dynamic differential write address generation module, a dynamic write enable narrow pulse width generation module, and a static logic full decoding module. The dynamic differential write address generation module latches the input write address for one clock cycle using a register, and then generates a differential dynamic address signal through a negative edge clock-gated latch for subsequent write address decoding. The dynamic write enable narrow pulse width generation module latches the input write enable for one clock cycle using a register, then generates a dynamic write enable through a negative edge clock-gated latch, and generates a narrow pulse width write enable through a pulse signal generator, which participates in subsequent write address decoding. The static logic full decoding module completes the full decoding of the differential dynamic address signal and the narrow pulse width write enable through static logic, and finally generates a write word line to enable any entry for write operations on the memory array.

[0012] Beneficial effects

[0013] Due to the adoption of the above technical solution, this invention has the following advantages and positive effects compared with the prior art: The storage cell (bitcell) array of this invention is composed of customized bitcells with n read ports and n write ports. The isolation between the read tube and the storage node enables simultaneous reading from multiple ports. The read address decoder uses a gated latch to latch the static address and convert it into a dynamic signal. After static logic decoding, a read address signal is generated. The read enable signal is generated after passing through the gated latch and the narrow pulse generation module, which generates a narrow pulse width enable signal and a narrow pulse width read wordline, controlling the storage array to complete the read operation in the first half of the clock cycle. Compared with the traditional method, the narrow pulse width method can save the clock power consumption caused by the dynamic buffer and more effectively avoid the problem of read-write conflicts in the same clock cycle. At the same time, the narrow pulse width combined with the low swing signal amplification achieved by the sensitive amplifier can effectively reduce the bitline discharge power consumption. The read data path uses a single-ended voltage latch type voltage sensitive amplifier to replace the original dynamic domino line or logic, which effectively improves the read speed. The read data is latched by the RS latch and then sent out to complete the read operation of the multi-port register file. The write address decoder uses a negative-edge-gated latch to latch the static address and convert it into a dynamic signal. This signal is then decoded by static logic to generate the write address signal. The write enable signal is also decoded by a negative-edge-gated latch to generate the final write wordline, controlling the memory array to complete the write operation within the second half of the clock cycle. The write data path employs single-ended write data and bit-line splitting. Single-ended write data effectively reduces the number of wires in the register file. Bit-line splitting reduces long-line resistance, ensuring data is more easily written to memory cells. The multi-port register file implemented using these methods features high performance, low power consumption, simultaneous multi-port read / write, and read / write completion within a single clock cycle, making it suitable for high-performance microprocessor applications. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of an embodiment of the present invention;

[0015] Figure 2 This is a schematic diagram of the structure of the storage unit in an embodiment of the present invention;

[0016] Figure 3 This is a circuit diagram of the address decoder in an embodiment of the present invention;

[0017] Figure 4 This is a circuit diagram of the data reading path in an embodiment of the present invention;

[0018] Figure 5 This is a circuit diagram of the write address decoder in an embodiment of the present invention;

[0019] Figure 6 This is a circuit diagram of the data writing path in an embodiment of the present invention;

[0020] Figure 7 This is a schematic diagram of the structure of a single-ended voltage-sensitive amplifier in an embodiment of the present invention;

[0021] Figure 8 This is a read / write timing diagram of an embodiment of the present invention. Detailed Implementation

[0022] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0023] The present invention relates to a multi-port register file based on a single-ended voltage-sensitive amplifier structure, comprising: a memory cell array, a read address decoder, a write address decoder, a read data path, and a write data path; the memory cell array consists of cross-coupled inverter pairs forming memory nodes, and simultaneously has multiple write ports and multiple read ports; both the read address decoder and the write address decoder are implemented using fully static logic; the read data path uses a single-ended voltage-sensitive amplifier and an RS latch structure to implement read operations; the write data path uses a segmented write bit line method to drive the write data in blocks.

[0024] Specifically, such as Figure 1 As shown, the multi-port register file consists of a 6R6W bitcell array, a read address decoder, a read data path, a write address decoder, and a write data path. The bitcell array is divided into four arrears (top, bottom, left, and right) to allow both the wordline and bitline to be driven from the center, reducing the impact of line resistance on timing. The horizontal center contains the read and write address decoders, with six sets each for read and write operations, based on the number of ports. The vertical center contains the read and write data paths, also with one set for each port. The write address decoder generates the write wordline through multi-stage decoding, and the write data is transmitted to the write bitline through hierarchical inversion and written to the memory cell. The read address decoder generates a narrow pulse width read wordline through multi-stage decoding, controls the read pull-down transistor to discharge the read bitline, and the low-swing signal is latched and amplified to a full-swing signal by a voltage-sensitive amplifier, then latched and output by an RS latch.

[0025] In this embodiment, each write port of the memory cell array is a single-ended write port composed of 3 transistors, used to ensure strong '0' writing to the positive and negative points of the memory node to realize write '0' and write '1' operations; each read port of the memory cell array is a pull-down structure single-ended read port composed of 2 transistors, which is structurally isolated from the memory node, and multiple read ports are evenly connected to the positive and negative points of the memory node.

[0026] like Figure 2 As shown, this bitcell is a cross-coupled inverter pair structure with 6 read and 6 write ports. The read and write operations are separated, allowing simultaneous reading from multiple ports of the same address bitcell and simultaneous writing to multiple ports of different address bitcells, as well as simultaneous read and write operations within a single clock cycle. Each write port consists of 3 transistors in a single-ended, non-differential structure, including 2 transmission transistors and 1 pull-down transistor. This structure can reliably complete write 0 and write 1 operations by writing a strong '0' to the storage's positive and negative points. Each read port consists of 2 transistors in a single-ended, non-differential structure, including 1 transmission transistor and 1 pull-down transistor. The read transistors are isolated from the storage node to avoid interference with the stored data during read operations. Read operations are completed by placing a point on the read bitline. The read ports are evenly connected to the storage's positive and negative points to ensure consistent load on both nodes, maintain bitcell symmetry, and improve noise margin.

[0027] The read address decoder includes: a dynamic differential read address generation module, a dynamic read enable narrow pulse width generation module, a static logic full decoding module, and a precharge clock and amplifier enable generation module. The dynamic differential read address generation module generates a differential dynamic address signal through a positive-edge clock-gated latch for subsequent read address decoding. The dynamic read enable narrow pulse width generation module generates a dynamic read enable through a positive-edge clock-gated latch and then generates a narrow pulse width read enable through a pulse signal generator, which participates in subsequent read address decoding. The static logic full decoding module performs full decoding of the differential dynamic address signal and the narrow pulse width read enable through static logic, ultimately generating a narrow pulse width read word line to enable any entry for read operations on the memory array. The precharge clock and amplifier enable generation module generates a precharge signal from the input read enable through a positive-edge clock-gated latch, and the precharge signal generates a sensitive amplifier enable signal through a delay-gated unit. The pulse signal generator inverts the input signal after passing it through a delay unit and then performs a logical AND operation with the input signal to generate the narrow pulse width signal. The logic used by this pulse signal generator to generate narrow pulses employs static logic, and the narrow pulse width is achieved through logic delay, resulting in a fixed pulse width. The design must consider the bitline discharge rate and the voltage difference resolution of the voltage-sensitive amplifier, taking into account process variations to ensure design reliability under all conditions. The delay gating unit performs a multi-stage logical AND operation on the pre-charge signal and clock signal, and then generates the enable signal for the sensitive amplifier via the delay unit.

[0028] like Figure 3 As shown, this circuit structure is built from gated latches and all static logic units. The read enable signal, generated by a pulse generator, produces a narrow pulse width enable signal to participate in the full address decoding to generate the narrow pulse width read wordline. The advantage of full address decoding is that it can strictly control the consistency of the wordline signal, improving read reliability. Compared with traditional dynamic circuit structures, the narrow pulse width read wordline technology significantly saves clock power consumption and effectively avoids the conflict problem of reading and writing within a single clock cycle. The self-timed precharge clock generated by the read enable controls the precharge reset of the entire array read bitline and the sensitive amplifier. The read enable signal, generated by the sensitive amplifier enable generator, produces the enable (fire) signal to turn on the sensitive amplifier.

[0029] The data read path includes a single-ended voltage-sensitive amplifier and an RS latch; such as Figure 7As shown, the single-ended voltage sensitive amplifier consists of a reference voltage generator and a high-resolution voltage latch type voltage sensitive amplifier. One end of the differential input signal of the high-resolution voltage latch type voltage sensitive amplifier is connected to the read port bit line, and the other end is connected to the reference voltage generator. The voltage latch type voltage sensitive amplifier has a traditional structure, which matches the size and load according to the actual design to generate a stable reference voltage, ensuring that the sensitive amplifier correctly completes the read '0' and read '1' operations. The RS latch is constructed using static NOR gates, which, in conjunction with the single-ended voltage sensitive amplifier, extend and hold the read pulse signal until the next read operation. The single-ended voltage sensitive amplifier uses a shared charge method to achieve a fixed reference voltage. Combined with the discharge situation on the bit line, the voltage swing difference is amplified and output by the single-ended voltage sensitive amplifier to complete the read 0 or read 1 operation.

[0030] like Figure 4 As shown, this circuit structure uses a single-ended voltage-sensitive amplifier + RS structure, replacing the traditional multi-stage dynamic domino line or +Catcher1 structure. By amplifying the low-swing signal, it achieves the goal of quickly reading valid data, fundamentally solving the problem of heavy bitline read load caused by the increase in the number of ports and entries, and significantly improving the performance of the register file. Furthermore, it can further simplify the logic and reduce the layout area in the implementation.

[0031] In this implementation, both the address and read enable signals in the read address decoder are converted into dynamic signals by a positive edge clock (CK) gated latch. The read enable signal then passes through a pulse signal generator to generate a narrow pulse width enable signal, which, along with the address signal, undergoes static logic decoding to ultimately generate a narrow pulse width read wordline signal. Combined with a voltage-sensitive amplifier, this completes the read operation in the first half of the clock cycle. The narrow pulse width wordline signal is period-independent and has a fixed pulse width, effectively controlling and preventing conflicts between read and write operations within a single clock cycle. The read address decoder employs fully static logic, which, compared to designs using dynamic circuits, saves significant clock and dynamic power consumption and improves reliability.

[0032] The write address decoder includes a dynamic differential write address generation module, a dynamic write enable narrow pulse width generation module, and a static logic full decoding module. The dynamic differential write address generation module latches the input write address for one clock cycle using a register, and then generates a differential dynamic address signal through a negative edge clock-gated latch for subsequent write address decoding. The dynamic write enable narrow pulse width generation module latches the input write enable for one clock cycle using a register, then generates a dynamic write enable through a negative edge clock-gated latch, and generates a narrow pulse width write enable through a pulse signal generator, which participates in subsequent write address decoding. The static logic full decoding module completes the full decoding of the differential dynamic address signal and the narrow pulse width write enable through static logic, and finally generates a write word line to enable any entry for write operations on the memory array.

[0033] like Figure 5 As shown, the write address decoder is constructed using a DFF (Device Filter), a gated latch, and all static logic units. The write enable signal is generated by a write enable pulse generator and participates in the full address decoding to generate the write wordline. The advantage of full address decoding is that it allows for strict control over the consistency of the wordline signal, improving write reliability. In the write address decoder, both the address and write enable are converted into dynamic signals by a negative-edge clock (NCK) gated latch. The write enable signal then passes through a pulse signal generator to generate a narrow-pulse enable signal, which, along with the address, undergoes static logic decoding to finally generate a narrow-pulse write wordline signal. The read operation is completed in the second half of the clock cycle. The narrow-pulse wordline is period-dependent, and its pulse width varies with frequency. The write address decoder also employs fully static logic, which, compared to a dynamic circuit design, saves significant clock power consumption and improves reliability.

[0034] like Figure 6 As shown, the circuit structure of the write data path adopts a segmented write bitline approach, forming a local-bitline and a global-bitline. This hierarchical, block-based driving method effectively reduces the impact of line resistance on the write operation, significantly lowering the requirements for write data setup and hold. Furthermore, the use of a half-cycle write structure provides the data path with 1.5 cycles of time for data preprocessing, allowing the data station to be placed within an external module.

[0035] Figure 8 The following is a timing diagram for reading and writing multi-port register files in this implementation: In the simulation, it is necessary to ensure that the precharge clock covers the read wordline, and the read and write wordlines should not overlap to avoid read and write conflicts. The focus should be on the setup and hold requirements for writing data.

[0036] It is easy to see that the multi-port register file implemented using the above method has the characteristics of high performance, low power consumption, simultaneous reading and writing of multiple ports, and reading and writing completed in one clock cycle, making it suitable for high-performance microprocessor applications.

Claims

1. A multi-port register file based on a single-ended voltage sense amplifier structure, characterized by, include: The system comprises a memory cell array, a read address decoder, a write address decoder, a read data path, and a write data path. The memory cell array consists of cross-coupled inverter pairs forming memory nodes, and has multiple write ports and multiple read ports. Both the read address decoder and the write address decoder are implemented using fully static logic. The read data path uses a single-ended voltage-sensitive amplifier and an RS latch structure to implement the read operation, and amplifies the swing signal to achieve the purpose of quickly reading valid data. The write data path uses a segmented write bit line method to drive the write data in blocks. The read address decoder includes: a dynamic differential read address generation module, a dynamic read enable narrow pulse width generation module, a static logic full decoding module, and a precharge clock and amplifier enable generation module. The dynamic differential read address generation module generates a differential dynamic address signal through a positive edge clock-gated latch for subsequent read address decoding. The dynamic read enable narrow pulse width generation module generates a dynamic read enable through a positive edge clock-gated latch and generates a narrow pulse width read enable through a pulse signal generator, which participates in subsequent read address decoding. The static logic full decoding module performs full decoding of the differential dynamic address signal and the narrow pulse width read enable through static logic, ultimately generating a narrow pulse width read word line to enable any entry for read operations on the memory array. The precharge clock and amplifier enable generation module generates a precharge signal from the input read enable through a positive edge clock-gated latch, and the precharge signal generates a sensitive amplifier enable signal through a delay gating unit.

2. The single-ended voltage sense amplifier based multi-ported register file of claim 1, wherein, Each write port of the memory cell array is a single-ended write port consisting of 3 transistors, used to ensure strong '0' writing to the positive and negative points of the memory node to realize write '0' and write '1' operations.

3. The single-ended voltage sense amplifier based multi-ported register file of claim 1, wherein, Each read port of the memory cell array is a single-ended read port with a pull-down structure consisting of two transistors. It is structurally isolated from the memory node, and multiple read ports are evenly connected to the positive and negative points of the memory node.

4. The single-ended voltage sense amplifier based multi-ported register file of claim 1, wherein, The read data path includes a single-ended voltage sensitive amplifier and an RS latch; the single-ended voltage sensitive amplifier is composed of a reference voltage generator and a high-resolution voltage latch type voltage sensitive amplifier. One end of the differential input signal of the high-resolution voltage latch type voltage sensitive amplifier is connected to the read port bit line, and the other end is connected to the reference voltage generator; the RS latch is constructed by a static NOR gate, which, in conjunction with the single-ended voltage sensitive amplifier, extends and holds the read pulse signal until the next read operation.

5. The single-ended voltage sense amplifier based multi-ported register file of claim 1, wherein, The single-ended voltage sensitive amplifier uses a shared charge method to achieve a fixed reference voltage. Combined with the discharge situation on the bitline, the voltage swing difference is amplified and output by the single-ended voltage sensitive amplifier to complete the read 0 or read 1 operation.

6. The single-ended voltage sense amplifier based multi-ported register file of claim 1, wherein, The write address decoder includes a dynamic differential write address generation module, a dynamic write enable narrow pulse width generation module, and a static logic full decoding module. The dynamic differential write address generation module latches the input write address for one clock cycle using a register, and then generates a differential dynamic address signal through a negative edge clock-gated latch for subsequent write address decoding. The dynamic write enable narrow pulse width generation module latches the input write enable for one clock cycle using a register, then generates a dynamic write enable through a negative edge clock-gated latch, and generates a narrow pulse width write enable through a pulse signal generator, which participates in subsequent write address decoding. The static logic full decoding module completes the full decoding of the differential dynamic address signal and the narrow pulse width write enable through static logic, and finally generates a write word line to enable any entry for write operations on the memory array.

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