A method, device, equipment and readable medium for FPGA secure boot

Abstract

The application provides a FPGA secure starting method, device and equipment and readable medium, the method comprises the following steps: calculating the digest value of the data bit stream to be delivered, and encrypting the digest value using a unique private key to obtain a verification identifier; storing the verification identifier, data bit stream and public key into the memory of the FPGA; in response to the power-on of the FPGA device, obtaining the data bit stream in the FPGA and calculating the digest value of the obtained data bit stream; decrypting the verification identifier using the public key in the memory of the FPGA to obtain the decrypted digest value; judging whether the decrypted digest value is same as the digest value of the obtained data bit stream; in response to the decrypted digest value being same as the digest value of the obtained data bit stream, determining that the version of the data bit stream obtained from the FPGA is correct and outputting a FPGA starting signal. Through the use of the scheme of the application, it can be ensured that the data logic bit stream called in the FPGA device starting is safe and reliable, and the security performance of the device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of computers, and more particularly to a method, device, equipment and readable medium for secure start of FPGA. BACKGROUND

[0002] In FPGA development projects, logic data bit streams need to be generated and written to FPGAs for project testing and verification, and thus various versions of logic data bit streams often appear. However, when the project is completed and delivered, the formal version of the logic data bit stream needs to be provided to the customer, and the provided logic data bit stream may be maliciously tampered with by others, resulting in the FPGA device being unable to work normally or even being damaged. SUMMARY

[0003] Therefore, the purpose of the embodiments of the present application is to provide a method, device, equipment and readable medium for secure start of FPGA, which can ensure that the data logic bit stream called in the start of the FPGA device is safe and reliable, and can improve the security performance of the device.

[0004] Based on the above purpose, one aspect of an embodiment of the present application provides a method for secure start of FPGA, comprising the following steps:

[0005] calculating the digest value of the data bit stream to be delivered, and encrypting the digest value using a unique private key to obtain a verification identifier;

[0006] storing the verification identifier, the data bit stream and the public key into the memory of the FPGA;

[0007] in response to power-on of the FPGA device, obtaining the data bit stream in the FPGA and calculating the digest value of the obtained data bit stream;

[0008] decrypting the verification identifier using the public key in the memory of the FPGA to obtain a decrypted digest value;

[0009] judging whether the decrypted digest value is the same as the digest value of the obtained data bit stream;

[0010] in response to the decrypted digest value being the same as the digest value of the obtained data bit stream, determining that the version of the data bit stream obtained from the FPGA is correct and outputting an FPGA start signal.

[0011] According to one embodiment of the present application, calculating the digest value of the data bit stream to be delivered and encrypting the digest value using a unique private key to obtain a verification identifier comprises:

[0012] calculating the digest value of the data bit stream to be delivered to the customer using the SHA algorithm;

[0013] The digest value is encrypted using a unique RSA private key to obtain a verification mark.

[0014] According to one embodiment of the present application, further comprising:

[0015] In response to the decrypted digest value being different from the digest value of the obtained data bit stream, determining that the version of the data bit stream obtained from the FPGA is incorrect, issuing a version error warning to the user, and stopping the FPGA from starting.

[0016] According to one embodiment of the present application, the memory storing the public key is an OTP storage unit, and a plurality of public key and private key pairs are also stored in the OTP storage unit, and the OTP storage unit is obtained by programming the OTP using a plurality of preset instructions.

[0017] Another aspect of the embodiment of the present application also provides a device for secure starting of an FPGA, the device comprising:

[0018] The encryption module is configured to calculate a digest value of the data bit stream to be delivered, and encrypt the digest value using a unique private key to obtain a verification mark;

[0019] The storage module is configured to store the verification mark, the data bit stream, and the public key into the memory of the FPGA;

[0020] The calculation module is configured to obtain the data bit stream in the FPGA and calculate a digest value of the obtained data bit stream in response to the FPGA being powered on;

[0021] The decryption module is configured to decrypt the verification mark using the public key in the memory of the FPGA to obtain a decrypted digest value;

[0022] The judgment module is configured to judge whether the decrypted digest value is the same as the digest value of the obtained data bit stream;

[0023] The starting module is configured to determine that the version of the data bit stream obtained from the FPGA is correct in response to the decrypted digest value being the same as the digest value of the obtained data bit stream, and output an FPGA starting signal.

[0024] According to one embodiment of the present application, the encryption module is further configured to:

[0025] Calculate a digest value of the data bit stream to be delivered to the customer using a SHA algorithm;

[0026] Encrypt the digest value using a unique RSA private key to obtain a verification mark.

[0027] According to one embodiment of the present application, further comprising a warning module configured to:

[0028] In response to the decrypted digest value being different from the digest value of the obtained data bit stream, it is determined that the version of the data bit stream obtained from the FPGA is incorrect, a version error warning is issued to the user, and the FPGA is stopped from being started.

[0029] According to one embodiment of the present application, the memory storing the public key is an OTP storage unit, a plurality of public key and private key pairs are also stored in the OTP storage unit, and the OTP storage unit is obtained by burning and writing the OTP in a preset multi-instruction manner.

[0030] Another aspect of the embodiments of the present application also provides a computer device, which comprises:

[0031] at least one processor; and

[0032] a memory storing computer instructions executable on the processor, the instructions being executed by the processor to implement the steps of any of the above methods.

[0033] Another aspect of the embodiments of the present application also provides a computer readable storage medium storing a computer program, the computer program being executed by a processor to implement the steps of any of the above methods.

[0034] The FPGA secure starting method provided by the embodiments of the present application has the following beneficial technical effects: the digest value of the data bit stream to be delivered is calculated, and the digest value is encrypted using a unique private key to obtain a verification identifier; the verification identifier, the data bit stream and the public key are stored in the memory of the FPGA; in response to the FPGA device being powered on, the data bit stream in the FPGA is obtained and the digest value of the obtained data bit stream is calculated; the verification identifier is decrypted using the public key in the memory of the FPGA to obtain a decrypted digest value; it is determined whether the decrypted digest value is the same as the digest value of the obtained data bit stream; in response to the decrypted digest value being the same as the digest value of the obtained data bit stream, it is determined that the version of the data bit stream obtained from the FPGA is correct, and a FPGA starting signal is output, which can ensure that the data logic bit stream called in the FPGA device starting is safe and reliable, and can improve the security performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other embodiments according to these drawings without creative labor.

[0036] Figure 1 a schematic flow chart of a method for FPGA secure boot according to an embodiment of the present application;

[0037] Figure 2 a schematic diagram of a software part structure according to an embodiment of the present application;

[0038] Figure 3 a schematic diagram of a hardware part structure according to an embodiment of the present application;

[0039] Figure 4 a schematic diagram of an apparatus for FPGA secure boot according to an embodiment of the present application;

[0040] Figure 5 a schematic diagram of a computer device according to an embodiment of the present application;

[0041] Figure 6 a schematic diagram of a computer readable storage medium according to an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the objects, technical solutions and advantages of the present application clearer, the embodiments of the present application are further described in detail below with reference to the drawings.

[0043] Based on the above purpose, in a first aspect, an embodiment of a method for FPGA secure boot is provided. Figure 1 A schematic flow chart of the method is shown.

[0044] As shown in the method shown in the Figure 1 The method can include the following steps:

[0045] S1, calculating a digest value of a data bit stream to be delivered, and encrypting the digest value using a unique private key to obtain a verification identifier.

[0046] S2, storing the verification identifier, the data bit stream and the public key into a memory of the FPGA.

[0047] When providing a formal version of the bit stream to the customer, the manufacturer needs to generate a verification identifier using software at the same time. The formal version of the bit stream is first calculated by the SHA algorithm to obtain a digest value, and then the manufacturer uses the unique RSA private key in hand to encrypt the digest value to obtain the verification identifier of this version. Then the manufacturer provides the identifier and the bit stream to the customer to store in the Flash of the FPGA device.

[0048] S3, in response to power-on of the FPGA device, obtaining the data bit stream in the FPGA and calculating a digest value of the obtained data bit stream.

[0049] After the FPGA device is powered on, the bit stream to be started is obtained from the started Flash through the interface unit, and the digest value of the bit stream is calculated using the SHA algorithm.

[0050] S4 decrypts the authentication mark using the public key in the memory of the FPGA to obtain the decrypted digest value.

[0051] Then, the public key of RSA is obtained from the internal OTP memory, and the authentication mark stored in the Flash is decrypted using the public key to obtain the correct digest value of the bit stream provided by the manufacturer.

[0052] S5 judges whether the decrypted digest value is the same as the digest value of the obtained data bit stream.

[0053] S6, in response to the decrypted digest value being the same as the digest value of the obtained data bit stream, determines that the version of the data bit stream obtained from the FPGA is correct and outputs the FPGA start signal.

[0054] The decrypted digest value and the calculated digest value are compared. If they match, it means that the bit stream in the Flash is the correct version provided by the manufacturer, and the FPGA product can be normally started. If the comparison result does not match, no start signal is output, and a warning of version error is sent to the user.

[0055] The technical scheme of the present application can ensure that the data logic bit stream called in the FPGA device startup is safe and reliable, and can improve the security performance of the device.

[0056] The above method can be implemented using the structure shown in Figure 2 and Figure 3 As shown in Figure 2 , the software part includes:

[0057] SHA calculation unit: call SHA algorithm to operate on bit stream, output unique digest value.

[0058] RSA calculation unit: continue to encrypt and operate on the digest value of the bit stream using the private key, and output the authentication mark.

[0059] Interface unit: write the bit stream to be started and the authentication mark into the internal Flash of the FPGA device.

[0060] As shown in Figure 3 , the hardware part includes:

[0061] SHA calculation unit: obtains the bit stream to be started from the starting Flash by the interface unit, and calls the SHA hardware accelerator to calculate the digest value.

[0062] RSA decryption unit: decrypts the authentication tag in the starting Flash by using the public key.

[0063] OTP storage unit: internal storage unit for storing the RSA public key, which is not secret and has the characteristic of unmodifiable data after programming.

[0064] OTP programming unit: a functional unit for programming the OTP by using the password programming mode and fixed password instruction operation.

[0065] Verification unit: verifies the digest value output by the SHA calculation unit and the authentication tag output by the RSA decryption unit, and if they are consistent, it is determined that the bit stream is safe and reliable and can be normally started, otherwise, it is determined that the starting condition is not met.

[0066] Starting control unit: if the verification unit passes the verification, a starting control signal is output so that the FPGA can be normally started, otherwise, the starting control signal is output.

[0067] Interface unit: data transmission unit linking the starting Flash and the internal operation control unit.

[0068] In a preferred embodiment of the present application, the digest value of the data bit stream to be delivered is calculated, and the digest value is encrypted by using a unique private key to obtain the verification identification, which comprises:

[0069] The digest value of the data bit stream to be delivered to the customer is calculated by using the SHA algorithm;

[0070] The digest value is encrypted by using a unique RSA private key to obtain the verification identification.

[0071] In a preferred embodiment of the present application, it further comprises:

[0072] In response to the decrypted digest value being different from the obtained digest value of the data bit stream, it is determined that the version of the data bit stream obtained from the FPGA is incorrect, a version error warning is issued to the user, and the FPGA is stopped.

[0073] In a preferred embodiment of the present application, the memory storing the public key is an OTP storage unit, a plurality of public key and private key pairs are also stored in the OTP storage unit, and the OTP is programmed by using a preset multiple instruction mode to obtain the OTP storage unit. The RSA unique private key is in the hands of the manufacturer, and the manufacturer uses the private key to encrypt the digest value of the bit stream to ensure the correctness of the bit stream. When the private key is illegally obtained by others, the secure boot device will lose the protection function. Therefore, the present application adds an OTP storage unit, which can burn a plurality of RSA public keys and cannot be modified after successful burning. Each public key corresponds to a private key. When one of the private keys is leaked, the manufacturer can rewrite the OTP configuration area to start a new public and private key pair and prohibit the leaked public and private key pair, thereby continuing to achieve the purpose of secure boot. The OTP storage unit cannot be modified at will, so the present application designs an OTP encryption programming unit, which programs the OTP by using a predetermined multiple instruction mode. For example, the programming instruction is to input 0xFACDEFAS three times. After the programming unit recognizes the programming instruction, the user needs to continue to input a 128-bit programming password, and the programming unit will execute the OTP programming operation. The programming password is also managed by the manufacturer and cannot be easily leaked.

[0074] The technical solution of the present application can ensure that the data logic bit stream called in the FPGA device startup is safe and reliable, and even if the logic data bit stream in the startup Flash is maliciously tampered with, the startup can be aborted to prevent unnecessary losses caused by abnormal device after startup. The structure of the present application can be divided into two parts of software and hardware cooperating with each other. For the logic bit stream provider who masters the RSA private key, as long as the private key is not leaked, the software can be used to update the new version of the logic bit stream in real time and provide it to the customer. Even if the private key is leaked, a new public and private key pair can be started by programming the OTP with a password, and the leaked public and private key pair is discarded. Moreover, the OTP programming adopts a password programming mode, which further improves the security performance, thereby ensuring the safe startup performance of the device.

[0075] It should be noted that those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by a computer program to instruct related hardware to complete. The above-mentioned program can be stored in a computer readable storage medium, and when the program is executed, it can include the processes of the above-mentioned embodiments. The storage medium can be a magnetic disc, an optical disc, a read-only memory (ROM) or a random access memory (RAM), etc. The above-mentioned computer program embodiments can achieve the same or similar effect as any of the above-mentioned method embodiments.

[0076] In addition, the method disclosed by the embodiment of the present application can also be implemented as a computer program executed by a CPU, which can be stored in a computer readable storage medium. When the computer program is executed by the CPU, the above-mentioned functions defined in the method disclosed by the embodiment of the present application are performed.

[0077] Based on the above-mentioned purpose, a second aspect of the embodiment of the present application provides a device for secure starting of FPGA, as shown in Figure 4 The device 200 comprises:

[0078] An encryption module, configured to calculate a digest value of the data bit stream to be delivered, and encrypt the digest value using a unique private key to obtain a verification identifier;

[0079] A storage module, configured to store the verification identifier, the data bit stream and the public key into a memory of the FPGA;

[0080] A calculation module, configured to, in response to power-on of the FPGA device, acquire the data bit stream in the FPGA and calculate a digest value of the acquired data bit stream;

[0081] A decryption module, configured to decrypt the verification identifier using the public key in the memory of the FPGA to obtain a decrypted digest value;

[0082] A judgment module, configured to judge whether the decrypted digest value is same as the digest value of the acquired data bit stream;

[0083] A starting module, configured to, in response to the decrypted digest value being same as the digest value of the acquired data bit stream, determine that the version of the data bit stream acquired from the FPGA is correct and output a FPGA starting signal.

[0084] In a preferred embodiment of the present application, the encryption module is further configured to:

[0085] Calculate the digest value of the data bit stream to be delivered to the customer using SHA algorithm;

[0086] Encrypt the digest value using a unique RSA private key to obtain the verification identifier.

[0087] In a preferred embodiment of the present application, further comprising a warning module, configured to:

[0088] In response to the decrypted digest value being not same as the digest value of the acquired data bit stream, determine that the version of the data bit stream acquired from the FPGA is incorrect, issue a version error warning to the user and stop starting the FPGA.

[0089] In a preferred embodiment of the present application, the memory storing the public key is an OTP memory unit, a plurality of public key and private key pairs are also stored in the OTP memory unit, and the OTP is programmed to obtain the OTP memory unit by using a plurality of preset instructions.

[0090] Based on the above purpose, a third aspect of the embodiments of the present application provides a computer device. Figure 5 The figure shows a schematic diagram of an embodiment of the computer device provided by the present application. As shown in the figure, Figure 5 The embodiment of the present application includes the following devices: at least one processor 21; and a memory 22, the memory 22 storing computer instructions 23 executable on the processor, the instructions being executed by the processor to implement the following method:

[0091] Calculate the digest value of the data bit stream to be delivered, and encrypt the digest value using a unique private key to obtain a verification identifier;

[0092] Store the verification identifier, data bit stream and public key in the memory of the FPGA;

[0093] In response to the power-on of the FPGA device, obtain the data bit stream in the FPGA and calculate the digest value of the obtained data bit stream;

[0094] Decrypt the verification identifier using the public key in the memory of the FPGA to obtain a decrypted digest value;

[0095] Determine whether the decrypted digest value is the same as the digest value of the obtained data bit stream;

[0096] In response to the decrypted digest value being the same as the digest value of the obtained data bit stream, determine that the version of the data bit stream obtained from the FPGA is correct and output an FPGA start signal.

[0097] In a preferred embodiment of the present application, calculating the digest value of the data bit stream to be delivered and encrypting the digest value using a unique private key to obtain a verification identifier includes:

[0098] Using the SHA algorithm to calculate the digest value of the data bit stream to be delivered to the customer;

[0099] Encrypting the digest value using a unique RSA private key to obtain a verification identifier.

[0100] In a preferred embodiment of the present application, it further includes:

[0101] In response to the decrypted digest value being different from the digest value of the obtained data bit stream, determining that the version of the data bit stream obtained from the FPGA is incorrect and issuing a version error warning to the user and stopping the FPGA from starting.

[0102] In a preferred embodiment of the present application, the memory storing the public key is an OTP memory unit, and a plurality of public key and private key pairs are also stored in the OTP memory unit, and the OTP is programmed to obtain the OTP memory unit by using a plurality of preset instructions.

[0103] To achieve the above object, a fourth aspect of the embodiments of the present application provides a computer readable storage medium. Figure 6 An embodiment of the computer readable storage medium provided by the present application is shown in the schematic diagram. As shown in the diagram, Figure 6 The computer readable storage medium 31 stores a computer program 32 which, when executed by a processor, performs the following method:

[0104] calculating a digest value of the data bit stream to be delivered, and encrypting the digest value using a unique private key to obtain a verification identifier;

[0105] storing the verification identifier, the data bit stream and the public key into the memory of the FPGA;

[0106] in response to the power-on of the FPGA device, obtaining the data bit stream in the FPGA and calculating a digest value of the obtained data bit stream;

[0107] decrypting the verification identifier using the public key in the memory of the FPGA to obtain a decrypted digest value;

[0108] judging whether the decrypted digest value is the same as the digest value of the obtained data bit stream;

[0109] in response to the decrypted digest value being the same as the digest value of the obtained data bit stream, determining that the version of the data bit stream obtained from the FPGA is correct and outputting an FPGA start signal.

[0110] In a preferred embodiment of the present application, calculating a digest value of the data bit stream to be delivered, and encrypting the digest value using a unique private key to obtain a verification identifier comprises:

[0111] calculating a digest value of the data bit stream to be delivered to the customer using the SHA algorithm;

[0112] encrypting the digest value using a unique RSA private key to obtain a verification identifier.

[0113] In a preferred embodiment of the present application, it further comprises:

[0114] in response to the decrypted digest value being different from the digest value of the obtained data bit stream, determining that the version of the data bit stream obtained from the FPGA is incorrect, issuing a version error warning to the user and stopping the start of the FPGA.

[0115] In a preferred embodiment of the present application, the memory storing the public key is an OTP memory unit, and a plurality of public key and private key pairs are also stored in the OTP memory unit, and the OTP is programmed with a plurality of preset instructions to obtain the OTP memory unit.

[0116] Furthermore, the method disclosed by the embodiments of the present application can also be implemented as a computer program executed by a processor, and the computer program can be stored in a computer readable storage medium. When the computer program is executed by the processor, the above-mentioned functions defined in the method disclosed by the embodiments of the present application are performed.

[0117] Furthermore, the above-mentioned method steps and system units can also be implemented by using a controller and a computer readable storage medium for storing a computer program enabling the controller to implement the above-mentioned steps or unit functions.

[0118] Those skilled in the art will further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein can be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present embodiments.

[0119] In one or more exemplary designs, the functions described can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media can be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code means in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or other wire-based, fiber-based, or wireless technologies, then the coaxial cable, fiber optic cable, twisted pair, DSL, or other wire-based, fiber-based, or wireless technologies are included in the definition of medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0120] The foregoing is a summary of the example embodiments disclosed herein, but it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the claims. The functions, steps and / or actions of the method claims described herein need not be performed in any particular order. Furthermore, although elements of the embodiments disclosed herein can be described or claimed in individual form, other embodiments can also include a plurality of those elements in combination.

[0121] It should be understood that, as used herein, "a" or "an" can mean one or more things unless context clearly indicates otherwise. It should also be understood that "and / or" as used herein means any and all possible combinations of one or more of the associated listed items.

[0122] The above-mentioned example embodiment numbers of the embodiments disclosed herein are merely for description, and do not represent the advantages or disadvantages of the embodiments.

[0123] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware to complete, and the program can be stored in a computer readable storage medium. The storage medium mentioned above can be a read-only memory, a magnetic disk or an optical disk, etc.

[0124] Those skilled in the art shall understand that the above discussion of any embodiment is only exemplary, and is not intended to imply that the scope (including claims) of the embodiments of the present application is limited to these examples; the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes of different aspects of the embodiments of the present application as above. In order to be brief, they are not provided in details. Therefore, any omission, modification, equivalent replacement, improvement, etc. made in the spirit and principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A method for secure booting an FPGA, characterized in that, Includes the following steps: Calculate the digest value of the data bitstream to be delivered, and encrypt the digest value using a unique private key to obtain a verification identifier; The verification identifier, the data bit stream, and the public key are stored in the FPGA's memory; In response to the power-on of the FPGA device, the data bit stream in the FPGA is acquired and the digest value of the acquired data bit stream is calculated; The verification identifier is decrypted using the public key stored in the FPGA's memory to obtain the decrypted digest value; Determine whether the decrypted digest value is the same as the digest value of the acquired data bit stream; If the decrypted digest value is the same as the digest value of the acquired data bit stream, the version of the data bit stream acquired from the FPGA is determined to be correct and an FPGA start signal is output. The storage unit for the public key is an OTP storage unit. The OTP storage unit also stores multiple public and private key pairs. If the unique private key is leaked, the configuration area of ​​the OTP storage unit is rewritten, a new public and private key pair is started, and the leaked unique private key and its corresponding public key are disabled.

2. The method according to claim 1, characterized in that, Calculate the digest value of the data bitstream to be delivered, and encrypt the digest value using a unique private key to obtain a verification identifier, including: The SHA algorithm is used to calculate the digest value of the data bit stream to be delivered to the customer; The digest value is encrypted using a unique RSA private key to obtain a verification identifier.

3. The method according to claim 1, characterized in that, Also includes: If the decrypted digest value is different from the digest value of the acquired data bit stream, it is determined that the version of the data bit stream acquired from the FPGA is incorrect, a version error warning is issued to the user, and the FPGA startup is stopped.

4. The method according to claim 1, characterized in that, The OTP storage unit is obtained by programming the OTP using a pre-defined multi-instruction method.

5. A device for secure booting an FPGA, characterized in that, The device includes: An encryption module is configured to calculate a digest value of the data bit stream to be delivered and encrypt the digest value using a unique private key to obtain a verification identifier; A storage module configured to store the verification identifier, the data bit stream, and the public key into the FPGA's memory; A computing module, configured to, in response to power-on of the FPGA device, acquire a data bit stream in the FPGA and calculate a digest value of the acquired data bit stream; A decryption module is configured to use a public key stored in the FPGA's memory to decrypt the verification identifier to obtain a decrypted digest value. The judgment module is configured to determine whether the decrypted digest value is the same as the digest value of the acquired data bit stream; A startup module is configured to determine that the version of the data bit stream obtained from the FPGA is correct and output an FPGA startup signal in response to the fact that the decrypted digest value is the same as the digest value of the acquired data bit stream. The storage unit for the public key is an OTP storage unit. The OTP storage unit also stores multiple public and private key pairs. If the unique private key is leaked, the configuration area of ​​the OTP storage unit is rewritten, a new public and private key pair is started, and the leaked unique private key and its corresponding public key are disabled.

6. The apparatus according to claim 5, characterized in that, The encryption module is also configured to: The SHA algorithm is used to calculate the digest value of the data bit stream to be delivered to the customer; The digest value is encrypted using a unique RSA private key to obtain a verification identifier.

7. The apparatus according to claim 5, characterized in that, It also includes a warning module, which is configured as follows: If the decrypted digest value is different from the digest value of the acquired data bit stream, it is determined that the version of the data bit stream acquired from the FPGA is incorrect, a version error warning is issued to the user, and the FPGA startup is stopped.

8. The apparatus according to claim 7, characterized in that, The OTP storage unit is obtained by programming the OTP using a pre-defined multi-instruction method.

9. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-4.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-4.

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