A method and device for automatic layout based on Euler path algorithm

Abstract

In the automatic layout method, device and storage medium based on the Euler path algorithm proposed in the present application, the MOS tubes to be placed can be classified according to their characteristic parameters to obtain multiple MOS tube groups, and then the gate sequence of the MOS tubes in each group of MOS tubes is respectively determined, with the drain and source levels of the MOS tubes as the nodes of the graph theory, to determine whether the nodes of the graph theory constitute an Euler path. If the nodes of the graph theory do not constitute an Euler path, the nodes with odd degrees are added with preset components in the graph theory to convert the nodes that do not constitute an Euler path into nodes that constitute an Euler path, and then the MOS tubes are placed according to the arrangement order in the constituted Euler path to form a sequence of multiple MOS tube groups after placement. The method proposed in the present application realizes the automatic layout of MOS tubes, thereby reducing the time required for manual consideration of the layout of MOS tubes in integrated circuit design, while ensuring that the active area of ​​the MOS tubes is correctly shared, reducing the area occupied by the layout, and shortening the integrated circuit design cycle.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an automatic layout method, device and storage medium based on the Euler path algorithm. Background Art

[0002] MOS tubes are key components of current integrated circuits. MOS tubes also need to be laid out, and when laying out MOS tubes, attention needs to be paid to the sharing of active areas.

[0003] In the related art, the layout of MOS tubes requires integrated circuit engineers to check whether the source and gate of the MOS tubes are consistent and then manually arrange them, which makes the efficiency of integrated circuit design low. Summary of the invention

[0004] The present application provides an automatic layout method, device and storage medium based on the Euler path algorithm, so as to at least solve the technical problem of low efficiency of integrated circuit design in the related art.

[0005] The first embodiment of the present application proposes an automatic layout method based on the Euler path algorithm, including:

[0006] Obtaining the MOS tube to be placed, and obtaining characteristic parameters of the MOS tube to be placed;

[0007] Classifying the MOS transistors to be placed according to the characteristic parameters to obtain a plurality of MOS transistor groups, wherein the MOS transistors in each of the MOS transistor groups have the same width;

[0008] For each gate sequence of the MOS tubes in the MOS tube group, the drain and source of the MOS tubes are used as nodes of a graph theory, and it is determined whether the nodes of the graph theory form an Euler path, wherein the nodes forming the Euler path are characterized by active areas of the MOS tubes being interconnected;

[0009] If the nodes of the graph theory do not constitute an Euler path, adding preset components to nodes with odd degrees in the graph theory to convert the nodes that do not constitute an Euler path into nodes that constitute an Euler path;

[0010] According to the nodes constituting the Euler path, the gate sequence constituting the Euler path is spliced ​​to complete the target path, and the connected MOS transistor sequence in the plurality of MOS transistor groups is generated according to the spliced ​​target path;

[0011] The MOS transistors in the MOS transistor sequence are arranged according to the arrangement order of the Euler path to form a plurality of arranged MOS transistor grouping sequences.

[0012] The second aspect of the present application provides an automatic layout device based on the Euler path algorithm, including:

[0013] An acquisition module, used for acquiring the MOS tube to be placed, and acquiring characteristic parameters of the MOS tube to be placed;

[0014] A classification module, used for classifying the MOS transistors to be placed according to the characteristic parameters to obtain a plurality of MOS transistor groups, wherein the MOS transistors in each of the MOS transistor groups have the same width;

[0015] A judgment module is used to respectively judge whether the nodes of the graph theory constitute an Euler path for the gate sequences of the MOS tubes in the MOS tube group, using the drain and source of the MOS tube as nodes of the graph theory, wherein the nodes constituting the Euler path are characterized by the active areas of the MOS tubes being interconnected;

[0016] A first processing module is used for adding preset components to nodes with odd degrees in the graph theory if the nodes of the graph theory do not constitute an Euler path, so as to convert the nodes that do not constitute an Euler path into nodes that constitute an Euler path;

[0017] A splicing module, used for completing the splicing of the target path of the gate sequence that has constituted the Euler path according to the nodes constituting the Euler path, and generating a MOS transistor sequence connected in the plurality of MOS transistor groups according to the spliced ​​target path;

[0018] The second processing module is used to arrange the MOS transistors in the MOS transistor sequence according to the arrangement order of the Euler path to form a plurality of arranged MOS transistor grouping sequences.

[0019] The computer storage medium proposed in the third aspect of the present application stores computer executable instructions; after the computer executable instructions are executed by the processor, the method described in the first aspect above can be implemented.

[0020] The computer device proposed in the fourth aspect of the present application includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it can implement the method described in the first aspect above.

[0021] The technical solution provided by the embodiments of the present application brings at least the following beneficial effects:

[0022] In the automatic layout method, device and storage medium based on the Euler path algorithm proposed in the present application, the MOS tubes to be placed can be classified according to their characteristic parameters to obtain multiple MOS tube groups, and then the gate sequence of the MOS tubes in each group of MOS tubes is respectively determined, with the drain and source of the MOS tubes as the nodes of the graph theory, to determine whether the nodes of the graph theory constitute an Euler path, if the nodes of the graph theory do not constitute an Euler path, then the nodes with odd degrees are added with preset components in the graph theory to convert the nodes that do not constitute an Euler path into nodes that constitute an Euler path, and then according to the splicing of the completed target path that constitutes the Euler path, the connected MOS tube sequences in the multiple MOS tube groups are generated according to the spliced ​​target path, and the MOS tubes in the MOS tube sequence are placed according to the arrangement order of the Euler path to form multiple MOS tube group sequences after placement. Among them, the method proposed in the present application realizes the automatic layout of MOS tubes, thereby reducing the time required for manual consideration of the layout of MOS tubes in integrated circuit design, while ensuring that the active area of ​​the MOS tube is correctly shared, reducing the area occupied by the layout, and shortening the integrated circuit design cycle.

[0023] Additional aspects and advantages of the present application will be given in part in the description below, and in part will become apparent from the description below, or will be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The above and / or additional aspects and advantages of the present application will become apparent and easily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0025] Figure 1 A schematic diagram of a flow chart of an automatic layout method based on the Euler path algorithm provided according to an embodiment of the present application;

[0026] Figure 2 The present invention is a schematic diagram of the structure of an automatic layout device based on the Euler path algorithm according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0028] The following describes an automatic layout method and device based on the Euler path algorithm according to an embodiment of the present application with reference to the accompanying drawings.

[0029] Embodiment 1

[0030] Figure 1FIG. 1 is a flow chart of an automatic layout method based on the Euler path algorithm according to an embodiment of the present application. Figure 1 As shown, it may include:

[0031] Step 101: Obtain the MOS tube to be placed, and obtain characteristic parameters of the MOS tube to be placed.

[0032] In the embodiment of the present application, the characteristic parameters of the MOS tube may include: the gate width of the MOS tube.

[0033] Step 102: Classify the MOS transistors to be placed according to the characteristic parameters to obtain a plurality of MOS transistor groups, wherein the MOS transistors in each MOS transistor group have the same width.

[0034] In the embodiment of the present application, the characteristic parameters of the MOS tube may further include: the finger of the MOS tube. Also, in the embodiment of the present application, before the MOS tubes to be placed are classified according to the characteristic parameters, the fingers of the MOS tubes need to be flattened to facilitate the subsequent classification of the MOS tubes.

[0035] Furthermore, in an embodiment of the present application, a method for classifying the MOS tubes to be placed according to the characteristic parameters to obtain a plurality of MOS tube groupings may include the following steps:

[0036] Step a: obtaining a one-dimensional sequence of MOS tubes to be placed, wherein the one-dimensional sequence of MOS tubes may include PMOS tubes and NMOS tubes, wherein the drain and source of the PMOS tubes and the NMOS tubes are determined by the order of the PMOS tubes and the NMOS tubes in the one-dimensional sequence of MOS tubes.

[0037] Step b: according to the one-dimensional sequence of MOS tubes, PMOS tubes and NMOS tubes of the same width in the one-dimensional sequence of MOS tubes are divided into a group, and the PMOS tubes and NMOS tubes in each group are distinguished by different gates to obtain a PMOS tube sequence and an NMOS tube sequence.

[0038] In the embodiment of the present application, after the PMOS tubes and NMOS tubes of the same width in the one-dimensional sequence of MOS tubes are divided into a group, each group contains multiple PMOS tubes and NMOS tubes. Also, in the embodiment of the present application, multiple different PMOS tube sequences can be obtained according to the different gates of the PMOS tubes in each group, and multiple different NMOS tube sequences can be obtained according to the different gates of the NMOS tubes in each group.

[0039] For example, in an embodiment of the present application, it is assumed that the MOS tubes are divided into N groups, wherein in the i-th group, according to different gates of the PMOS tubes and the NMOS tubes, the gate sequence 1, gate sequence 2, ..., gate sequence m of the PMOS tubes and the gate sequence a, gate sequence b, ..., gate sequence n of the NMOS tubes are obtained.

[0040] Step 103: for the gate sequences of the MOS tubes in the MOS tube group, respectively, the drain and source of the MOS tubes are used as nodes of the graph theory, and it is determined whether the nodes of the graph theory form an Euler path, wherein the nodes forming the Euler path are characterized by the active areas of the MOS tubes being interconnected.

[0041] Among them, in the embodiment of the present application, the gate sequence of the MOS tubes in the MOS tube group is respectively determined, and the drain and source of the MOS tube are used as the nodes of the graph theory. Judging whether the nodes of the graph theory constitute an Euler path includes judging whether the nodes in the graph theory constitute an Euler path by taking the gate sequence of the PMOS tubes in each group and the drain and source of the PMOS tube as the nodes of the graph theory and judging whether the nodes in the graph theory constitute an Euler path by taking the gate sequence of the NMOS tubes in each group and the drain and source of the NMOS tube as the nodes of the graph theory. And, in the embodiment of the present application, the Euler path composed of the PMOS tubes in each group and the Euler path composed of the NMOS tubes are two different Euler paths.

[0042] For example, in an embodiment of the present application, assuming that the MOS tubes are divided into N groups, it is necessary to determine whether the gate sequence 1, gate sequence 2, ..., gate sequence m of the PMOS tube in the i-th group can form an Euler path, and whether the gate sequence a, gate sequence b, ..., gate sequence n of the NMOS tube can form an Euler path.

[0043] Step 104: If the nodes of the graph theory do not form an Euler path, then preset components are added to the nodes with odd degrees in the graph theory to convert the nodes that do not form an Euler path into nodes that form an Euler path.

[0044] In an embodiment of the present application, if there are nodes in the graph theory that do not constitute an Euler path, a preset source device (for example, dummy) is added to the nodes with odd degrees in the graph theory so that the nodes with odd degrees can share an active area with the constructed Euler path, thereby converting the nodes that do not constitute an Euler path into nodes that constitute an Euler path.

[0045] Step 105 , according to the nodes constituting the Euler path, the gate sequence constituting the Euler path is spliced ​​to complete the target path, and a MOS transistor sequence connected in a plurality of MOS transistor groups is generated according to the spliced ​​target path.

[0046] In an embodiment of the present application, according to the nodes constituting the Euler path, a method for completing the splicing of the gate sequence constituting the Euler path into the target path may include the following steps:

[0047] Step 1: In the PMOS tube sequence and NMOS tube sequence of the same width, the gate sequence that has formed the Euler path is respectively connected by adding a preset component between each of the two paths, in which the drain of a MOS tube is the source of the last MOS tube of the previous path and the source of the MOS tube is the drain of the first MOS tube of the next path, to complete the splicing of the target path.

[0048] Step 2: Add a preset component to each of the two end points of the spliced ​​target path to obtain a PMOS tube sequence and an NMOS tube sequence connected in multiple MOS tube groups.

[0049] And, in the embodiment of the present application, the Euler path of the PMOS tube and the Euler path of the NMOS tube in each group can be obtained according to the target path after the splicing is completed. Specifically, the Euler path of the PMOS tube includes the arrangement order of all gate sequences in the PMOS tube; the Euler path of the NMOS tube includes the arrangement order of all gate sequences in the NMOS tube.

[0050] Step 106: Arrange the MOS transistors in the MOS transistor sequence according to the arrangement order of the Euler path to form a plurality of arranged MOS transistor grouping sequences.

[0051] In the automatic layout method, device and storage medium based on the Euler path algorithm proposed in the present application, the MOS tubes to be placed can be classified according to their characteristic parameters to obtain multiple MOS tube groups, and then the gate sequence of the MOS tubes in each group of MOS tubes is respectively determined, with the drain and source of the MOS tubes as the nodes of the graph theory, to determine whether the nodes of the graph theory constitute an Euler path, if the nodes of the graph theory do not constitute an Euler path, then the nodes with odd degrees are added with preset components in the graph theory to convert the nodes that do not constitute an Euler path into nodes that constitute an Euler path, and then according to the splicing of the completed target path that constitutes the Euler path, the connected MOS tube sequences in the multiple MOS tube groups are generated according to the spliced ​​target path, and the MOS tubes in the MOS tube sequence are placed according to the arrangement order of the Euler path to form multiple MOS tube group sequences after placement. Among them, the method proposed in the present application realizes the automatic layout of MOS tubes, thereby reducing the time required for manual consideration of the layout of MOS tubes in integrated circuit design, while ensuring that the active area of ​​the MOS tube is correctly shared, reducing the area occupied by the layout, and shortening the integrated circuit design cycle.

[0052] Embodiment 2

[0053] Further, Figure 2FIG. 1 is a schematic diagram of a structure of an automatic layout device based on the Euler path algorithm according to an embodiment of the present application. Figure 2 As shown, it may include:

[0054] The acquisition module 201 is used to acquire the MOS tube to be placed and acquire the characteristic parameters of the MOS tube to be placed;

[0055] A classification module 202 is used to classify the MOS transistors to be placed according to the characteristic parameters to obtain a plurality of MOS transistor groups, wherein the MOS transistors in each MOS transistor group have the same width;

[0056] The judgment module 203 is used to respectively judge whether the nodes of the graph theory form an Euler path for the gate sequences of the MOS transistors in the MOS transistor group, using the drain and source of the MOS transistors as nodes of the graph theory, wherein the nodes forming the Euler path are characterized by the active areas of the MOS transistors being interconnected;

[0057] A first processing module 204 is used for adding preset components to nodes with odd degrees in the graph theory if the nodes of the graph theory do not constitute an Euler path, so as to convert the nodes that do not constitute an Euler path into nodes that constitute an Euler path;

[0058] The splicing module 205 is used to complete the splicing of the target path by the gate sequence that has formed the Euler path according to the nodes that form the Euler path, and generate a MOS transistor sequence connected in multiple MOS transistor groups according to the spliced ​​target path;

[0059] The second processing module 206 is used to arrange the MOS transistors in the MOS transistor sequence according to the arrangement order of the Euler path to form a plurality of arranged MOS transistor grouping sequences.

[0060] Among them, in the embodiment of the present application, the characteristic parameter includes the gate width of the MOS tube. And, in the embodiment of the present application, the classification module is used to obtain a one-dimensional sequence of MOS tubes to be placed, the one-dimensional sequence of MOS tubes includes PMOS tubes and NMOS tubes, the drain and source levels of the PMOS tubes and NMOS tubes are determined by the order of the PMOS tubes and NMOS tubes in the one-dimensional sequence of MOS tubes, and according to the one-dimensional sequence of MOS tubes, the PMOS tubes and NMOS tubes of the same width in the one-dimensional sequence of MOS tubes are divided into a group, and the PMOS tubes and NMOS tubes of each group are distinguished by different gates to obtain a PMOS tube sequence and an NMOS tube sequence.

[0061] The computer storage medium proposed in the third aspect of the present application stores computer executable instructions; after the computer executable instructions are executed by the processor, the method described in the first aspect above can be implemented.

[0062] The computer device proposed in the fourth aspect of the present application includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it can implement the method described in the first aspect above.

[0063] In order to implement the above embodiments, the present disclosure also proposes a computer storage medium.

[0064] The computer storage medium provided in the embodiment of the present disclosure stores a computer program; when the computer program is executed by a processor, the following can be achieved: Figure 1 The automatic layout method based on the Euler path algorithm is shown.

[0065] In order to implement the above embodiments, the present disclosure also provides a computer device.

[0066] The computer device provided in the embodiment of the present disclosure includes a memory, a processor, and a computer program stored in the memory and executable on the processor; when the computer program is executed by the processor, the following can be achieved: Figure 1 The automatic layout method based on the Euler path algorithm is shown.

[0067] In the automatic layout method, device and storage medium based on the Euler path algorithm proposed in the present application, the MOS tubes to be placed can be classified according to their characteristic parameters to obtain multiple MOS tube groups, and then the gate sequence of the MOS tubes in each group of MOS tubes is respectively determined, with the drain and source of the MOS tubes as the nodes of the graph theory, to determine whether the nodes of the graph theory constitute an Euler path, if the nodes of the graph theory do not constitute an Euler path, then the nodes with odd degrees are added with preset components in the graph theory to convert the nodes that do not constitute an Euler path into nodes that constitute an Euler path, and then according to the splicing of the completed target path that constitutes the Euler path, the connected MOS tube sequences in the multiple MOS tube groups are generated according to the spliced ​​target path, and the MOS tubes in the MOS tube sequence are placed according to the arrangement order of the Euler path to form multiple MOS tube group sequences after placement. Among them, the method proposed in the present application realizes the automatic layout of MOS tubes, thereby reducing the time required for manual consideration of the layout of MOS tubes in integrated circuit design, while ensuring that the active area of ​​the MOS tube is correctly shared, reducing the area occupied by the layout, and shortening the integrated circuit design cycle.

[0068] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0069] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0070] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. An automatic layout method based on Euler path algorithm, characterized in that: include: Obtaining the MOS tube to be placed, and obtaining characteristic parameters of the MOS tube to be placed; The MOS tubes to be placed are classified according to the characteristic parameters to obtain a plurality of MOS tube groups, wherein the MOS tubes in each of the MOS tube groups have the same width, and the characteristic parameters include the gate width of the MOS tubes, and a one-dimensional sequence of MOS tubes of the MOS tubes to be placed is obtained, wherein the one-dimensional sequence of MOS tubes includes PMOS tubes and NMOS tubes, and the drain and source levels of the PMOS tubes and NMOS tubes are determined by the order of the PMOS tubes and NMOS tubes in the one-dimensional sequence of MOS tubes, and according to the one-dimensional sequence of MOS tubes, the PMOS tubes and NMOS tubes of the same width in the one-dimensional sequence of MOS tubes are divided into a group, and the PMOS tubes and NMOS tubes in each group are distinguished by different gates to obtain a PMOS tube sequence and an NMOS tube sequence; For the gate sequences of the MOS tubes in the MOS tube group, respectively, the drain and source of the MOS tubes are used as nodes of the graph theory to determine whether the nodes of the graph theory constitute an Euler path, wherein the nodes constituting the Euler path are characterized by the active regions of the MOS tubes being interconnected, and for the gate sequence of the PMOS tubes in each group, the drain and source of the PMOS tubes are used as nodes of the graph theory to determine whether the nodes in the graph theory constitute an Euler path, and for the gate sequence of the NMOS tubes in each group, the drain and source of the NMOS tubes are used as nodes of the graph theory to determine whether the nodes in the graph theory constitute an Euler path; If the nodes of the graph theory do not constitute an Euler path, adding preset components to nodes with odd degrees in the graph theory to convert the nodes that do not constitute an Euler path into nodes that constitute an Euler path; According to the nodes constituting the Euler path, the gate sequence constituting the Euler path is spliced ​​to complete the target path, and the connected MOS transistor sequence in the plurality of MOS transistor groups is generated according to the spliced ​​target path; The MOS transistors in the MOS transistor sequence are arranged according to the arrangement order of the Euler path to form a plurality of arranged MOS transistor grouping sequences.

2. The method according to claim 1, characterized in that According to the nodes constituting the Euler path, the gate sequence constituting the Euler path completes the splicing of the target path, and according to the spliced ​​target path, generates the MOS transistor sequence connected in the plurality of MOS transistor groups, including: In the PMOS tube sequence and the NMOS tube sequence of the same width, the gate sequence that has formed the Euler path is respectively connected by adding a preset component between each of the two paths, wherein the drain of a MOS tube is the source of the last MOS tube of the previous path, and the source of the MOS tube is the drain of the first MOS tube of the next path, to complete the splicing of the target path; A preset component is added to each of the two end points of the spliced ​​target path to obtain a PMOS tube sequence and an NMOS tube sequence connected in the plurality of MOS tube groups.

3. The method according to claim 1, characterized in that The characteristic parameter further includes: the finger of the MOS tube. Before classifying the MOS tubes to be placed according to the characteristic parameter, the method further includes: The fingers of the MOS tube are flattened.

4. An automatic layout device based on Euler path algorithm, characterized in that: The device comprises: An acquisition module, used for acquiring the MOS tube to be placed, and acquiring characteristic parameters of the MOS tube to be placed; a classification module, configured to classify the MOS tubes to be placed according to the characteristic parameters to obtain a plurality of MOS tube groups, wherein the MOS tubes in each of the MOS tube groups have the same width, and the characteristic parameters include the gate width of the MOS tubes, obtain a one-dimensional sequence of MOS tubes of the MOS tubes to be placed, the one-dimensional sequence of MOS tubes including PMOS tubes and NMOS tubes, the drain and source levels of the PMOS tubes and NMOS tubes being determined by the order of the PMOS tubes and NMOS tubes in the one-dimensional sequence of MOS tubes, and according to the one-dimensional sequence of MOS tubes, classify the PMOS tubes and NMOS tubes of the same width in the one-dimensional sequence of MOS tubes into a group, and distinguish the PMOS tubes and NMOS tubes in each group by different gates to obtain a PMOS tube sequence and an NMOS tube sequence; A judgment module is used to respectively judge whether the nodes of the graph theory constitute an Euler path for the gate sequence of the MOS tubes in the MOS tube group, using the drain and source of the MOS tube as the nodes of the graph theory, wherein the nodes constituting the Euler path are characterized by the active areas of the MOS tubes being interconnected, and to judge whether the nodes in the graph theory constitute an Euler path for the gate sequence of the PMOS tubes in each group, using the drain and source of the PMOS tube as the nodes of the graph theory, and to judge whether the nodes in the graph theory constitute an Euler path for the gate sequence of the NMOS tubes in each group, using the drain and source of the NMOS tube as the nodes of the graph theory; A first processing module is used for adding preset components to nodes with odd degrees in the graph theory if the nodes of the graph theory do not constitute an Euler path, so as to convert the nodes that do not constitute an Euler path into nodes that constitute an Euler path; A splicing module, used for completing the splicing of the target path of the gate sequence that has constituted the Euler path according to the nodes constituting the Euler path, and generating a MOS transistor sequence connected in the plurality of MOS transistor groups according to the spliced ​​target path; The second processing module is used to arrange the MOS transistors in the MOS transistor sequence according to the arrangement order of the Euler path to form a plurality of arranged MOS transistor grouping sequences.

5. A computer storage medium, wherein: The computer storage medium stores computer executable instructions; after the computer executable instructions are executed by the processor, any method described in claims 1-3 can be implemented.

6. A computer device, characterized in that: The method comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the method according to any one of claims 1 to 3 is implemented.

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