Memory device including row decoder

Abstract

The present application relates to a memory device including a row decoder. A memory device includes: a substrate defining a first cell region and a second cell region and a row decoder region between the first cell region and the second cell region; a peripheral circuit defined in the first cell region and the second cell region of the substrate; a pass transistor defined in the row decoder region of the substrate; a bottom wiring layer disposed in a first dielectric layer covering the peripheral circuit and the pass transistor; a memory cell array defined on the first dielectric layer; a second dielectric layer defined on the first dielectric layer and covering the memory cell array; a top wiring layer disposed in a third dielectric layer defined on the second dielectric layer; and a global line disposed in the row decoder region and configured to transmit an operating voltage to the pass transistor, wherein the global line is disposed only in at least one of the bottom wiring layer and the top wiring layer.

Description

Technical Field

[0001] Various embodiments relate generally to semiconductor technology and, more particularly, to memory devices including row decoders. Background Art

[0002] Volatile memory devices have high write and read speeds, but if their power supply is interrupted, the data stored therein will be lost. Non-volatile memory devices have relatively low write and read speeds, but can retain the data stored therein even if their power supply is interrupted. Therefore, in order to store data that should be retained regardless of the power supply, a non-volatile memory device can be used. Examples of non-volatile memory devices include read-only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory can be divided into NOR type memory and NAND type memory.

[0003] Among examples of nonvolatile memory devices, NAND flash memory devices are widely used as data storage devices. NAND flash memory devices can transmit operating voltages to memory cells through a row decoder. Summary of the Invention

[0004] Various embodiments relate to measures capable of reducing the size and failure of memory devices.

[0005] In one embodiment, a memory device may include: a substrate defining first and second cell regions arranged in a first direction and a row decoder region arranged between the first and second cell regions; peripheral circuits defined in the first and second cell regions of the substrate; a plurality of pass transistors defined in the row decoder region of the substrate; a plurality of bottom wiring layers provided in a first dielectric layer covering the peripheral circuits and the plurality of pass transistors; a memory cell array defined on the first dielectric layer; a second dielectric layer defined on the first dielectric layer, the second dielectric layer covering the memory cell array; a plurality of top wiring layers provided in a third dielectric layer, the third dielectric layer defined on the second dielectric layer; and a plurality of global lines provided in the row decoder region, the plurality of global lines transmitting operating voltages to the plurality of pass transistors. The plurality of global lines are provided only in the bottom wiring layers among the plurality of bottom wiring layers and the plurality of top wiring layers.

[0006] In one embodiment, a memory device may include: a substrate defining a first planar region and a second planar region arranged in a first direction, each of the first planar region and the second planar region including a cell region and a row decoder region adjacent to the cell region in the first direction; a plurality of pass transistors defined in the row decoder region of the first planar region and the second planar region of the substrate; a peripheral circuit defined in the cell region of the first planar region and the second planar region of the substrate; a plurality of bottom wiring layers disposed in a first dielectric layer covering the pass transistors and the peripheral circuit; a first-plane memory cell array and a second-plane memory cell array, the first-plane memory cell array being disposed on the first dielectric layer and disposed in the cell region of the first planar region, the second-plane memory cell array being disposed on the first dielectric layer and disposed in the cell region of the second planar region; a second dielectric layer defined on the first dielectric layer and covering the memory cell array; a plurality of top wiring layers disposed in a third dielectric layer, the third dielectric layer being defined on the second dielectric layer; and a plurality of global lines disposed in the row decoder region of the first planar region and the second planar region to transmit operating voltages to the plurality of pass transistors. The plurality of global lines may be provided only in at least one bottom wiring layer among the plurality of bottom wiring layers and the plurality of top wiring layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram illustrating a representation of a memory device according to an embodiment of the present disclosure.

[0008] Figure 2 It is an example Figure 1 A circuit diagram showing a representation of the memory cell array and row decoder is shown.

[0009] Figure 3 is a cross-sectional view illustrating a representation of a schematic layout of a memory device according to an embodiment of the present disclosure.

[0010] Figure 4 is a top view of a representation illustrating a layout of a memory device according to an embodiment of the present disclosure.

[0011] Figure 5 and Figure 6 is a cross-sectional view illustrating a representation of a memory device according to an embodiment of the present disclosure.

[0012] 7A to 7E is a top view illustrating a representation of the main components of a memory device according to an embodiment of the present disclosure.

[0013] Figure 8is a block diagram schematically illustrating a representation of a memory system including a memory device according to an embodiment of the present disclosure.

[0014] Figure 9 is a block diagram schematically illustrating a representation of a computing system including a memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] From the description of the exemplary embodiments described below and with reference to the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving them will become apparent. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.

[0016] Because the figures, sizes, ratios, angles, and quantities of the elements shown in the drawings describing the embodiments of the present disclosure are only exemplary, the present disclosure is not limited to what is shown. Throughout the specification, similar figure numerals refer to similar components. When describing the present disclosure, when it is determined that the detailed description of the related art may obscure the gist or clarity of the present disclosure, its detailed description will be omitted. It should be understood that the terms "including", "having", "comprising" and the like used in the specification and claims should not be interpreted as being limited to the means listed thereafter, unless otherwise expressly set forth. When an indefinite article or definite article (for example, "one", "a kind of" or "the") is used when referring to a singular noun, the article may include the plural form of the noun unless otherwise expressly set forth.

[0017] When explaining the elements in the embodiments of the present disclosure, they should be interpreted as including an error tolerance even in the case where there is no explicit mention.

[0018] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a) and (b) may be used. These terms are only used to distinguish one component from another component, and do not limit the material, order, sequence or quantity of the components. In addition, the components in the embodiments of the present disclosure are not limited by these terms. These terms are only used to distinguish one component from another component. Therefore, as used herein, within the technical spirit of the present disclosure, a first component may be a second component.

[0019] If a component is described as being “connected,” “coupled,” or “linked” to another component, it may mean that the component is not only directly “connected,” “coupled,” or “linked” but may also be indirectly “connected,” “coupled,” or “linked” via a third component. When describing a positional relationship, for example, “element A on element B,” “element A above element B,” “element A below element B,” and “element A next to element B,” one or more other elements may be disposed between elements A and B unless the term “directly” or “immediately thereafter” is explicitly used.

[0020] The features of the various exemplary embodiments of the present disclosure may be partially or completely connected, combined, or separated. Technically, various interactions and operations are also feasible. The various exemplary embodiments may be practiced individually or in combination.

[0021] Hereinafter, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0022] Figure 1 is a block diagram illustrating a representation of a memory device according to an embodiment of the present disclosure.

[0023] Reference Figure 1 , the memory device 10 according to the embodiment of the present disclosure may include a plurality of planes PLANE1 to PLANE4 and a peripheral circuit (PERI circuit) 200. The memory device 10 may have a four-plane structure. Figure 1 The embodiment illustrates the memory device 10 having four planes, but it is noted that the number of planes included in the memory device 10 is not limited thereto.

[0024] Each of the planes PLANE1 to PLANE4 may be substantially identical and may include a memory cell array 110 , a row decoder (X-DEC) 120 , and a page buffer circuit (page buffer) 130 .

[0025] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz (where z is a natural number of 2 or greater). Each of the memory blocks BLK1 to BLKz may be coupled to the row decoder 120 via at least one drain select line DSL, a plurality of word lines WL, and at least one source select line SSL. The memory blocks BLK1 to BLKz may be coupled to the page buffer circuit 130 via a plurality of bit lines BL. A drain select line DSL, a word line WL, and a source select line SSL may be provided for each of the memory blocks BLK1 to BLKz, and a bit line BL may be provided in common for the memory blocks BLK1 to BLKz.

[0026] Each of the memory blocks BLK1 to BLKz may include a plurality of cell strings. Although not shown, each cell string may include at least one drain select transistor, a plurality of memory cells, and at least one source select transistor coupled in series.

[0027] In response to a row address X_A provided from the peripheral circuit 200, the row decoder 120 may select any one memory block from among the memory blocks BLK1 to BLKz included in the memory cell array 110. The row decoder 120 may transmit an operating voltage X_V provided from the peripheral circuit 200 to a drain select line DSL, a word line WL, and a source select line SSL coupled to the selected memory block.

[0028] The page buffer circuit 130 may include a plurality of page buffers (not shown) respectively coupled to a plurality of bit lines BL. The page buffers may receive a page buffer control signal PB_C from the peripheral circuit 200 and may transmit a data signal DATA to the peripheral circuit 200 and receive a data signal DATA from the peripheral circuit 200. The page buffers may control the bit lines BL in response to the page buffer control signal PB_C. For example, the page buffers may detect data stored in memory cells of the memory cell array 110 by sensing signals of the bit lines BL in response to the page buffer control signal PB_C, and may transmit data signals DATA to the peripheral circuit 200 based on the detected data. The page buffers may apply signals to the bit lines BL based on the data signals DATA received from the peripheral circuit 200 in response to the page buffer control signal PB_C, thereby writing data to the memory cells of the memory cell array 110. The page buffers may write data to the memory cells coupled to the activated word lines WL or read data from the memory cells coupled to the activated word lines WL.

[0029] The peripheral circuit 200 can receive a command signal CMD, an address signal ADD, and a control signal CTRL from outside the memory device 10, and can transmit data DATA to a device outside the memory device 10 (e.g., a memory controller) and receive data DATA from a device outside the memory device 10 (e.g., a memory controller). The peripheral circuit 200 can output signals for writing data to or reading data from the memory cell array 110 based on the command signal CMD, the address signal ADD, and the control signal CTRL, such as a row address X_A and a page buffer control signal PB_C. The peripheral circuit 200 can generate various voltages required in the memory device 10, including the operating voltage X_V.

[0030] Although the present specification describes the case where the memory device 10 is a flash memory as an example, in other embodiments, the type of memory is not limited thereto, and the present disclosure can also be applied to memories other than flash memory. For example, the memory can be any one of dynamic random access memory (DRAM), phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0031] Figure 2 It is an example Figure 1 A circuit diagram showing a representation of the memory cell array and row decoder is shown.

[0032] Reference Figure 2 , the memory cell array 110 included in each of the plurality of planes PLANE1 to PLANE4 may include a plurality of memory blocks BLK1 to BLKz. When the memory device performs an erase operation, each of the memory blocks BLK1 to BLKz may correspond to an erase unit.

[0033] Each of the memory blocks BLK1 to BLKz may include a plurality of cell strings CSTR coupled between a plurality of bit lines BL and a common source line CSL. Figure 2 As shown, in the memory block BLKi, each cell string CSTR may include a drain select transistor DST coupled to a bit line BL, a source select transistor SST coupled to a common source line CSL, and a plurality of memory cells MC coupled in series between the drain select transistor DST and the source select transistor SST.

[0034] A plurality of cell strings CSTR included in each of the memory blocks BLK1 to BLKz may be commonly coupled to a common source line CSL, and each of the cell strings CSTR may be coupled to a corresponding bit line BL.

[0035] The gate of the drain select transistor DST can be coupled to a drain select line DSL. The gate of each memory cell MC can be coupled to a corresponding word line WL. The gate of the source select transistor SST can be coupled to a source select line SSL. The drain select line DSL, the word line WL, and the source select line SSL can each be coupled to a local line LWL.

[0036] The row decoder 120 may include a plurality of pass transistor groups PTG1 to PTGz corresponding to the memory blocks BLK1 to BLKz, respectively. Each of the plurality of pass transistor groups PTG1 to PTGz may include a plurality of pass transistors TR coupled between a global line GWL and a local line LWL. The pass transistors TR may transmit an operating voltage applied to the global line GWL to the corresponding memory block via the local line LWL in response to a block select signal BLKSW. A local line LWL may be provided for each of the pass transistor groups PTG1 to PTGz, and a global line GWL may be provided in common for the pass transistor groups PTG1 to PTGz. Thus, the pass transistor groups PTG1 to PTGz may share the global line GWL.

[0037] In the accompanying drawings, two directions parallel to the top surface of the substrate and intersecting each other are defined as a first direction FD and a second direction SD, respectively, and a direction perpendicular to the top surface of the substrate is defined as a vertical direction VD. For example, the first direction FD may correspond to the direction in which a word line extends, and the second direction SD may correspond to the direction in which a bit line extends. The first direction FD and the second direction SD may intersect substantially perpendicularly with each other. In the accompanying drawings, a direction indicated by an arrow and a direction opposite thereto represent the same direction.

[0038] Figure 3 is a cross-sectional view illustrating a representation of a schematic layout of a memory device according to an embodiment of the present disclosure.

[0039] Reference Figure 3 The memory device 10 according to an embodiment of the present disclosure may have a PUC (Peripheral Under Cell) structure. The memory device 10 may include a substrate 1, a logic structure 2 disposed on the substrate 1, a source plate 3 disposed on the logic structure 2, and a memory structure 4 disposed on the logic structure 2 and the source plate 3.

[0040] The substrate 1 of the memory device 10 may include first and second planar regions R1 and R2 arranged in a first direction FD. Each of the first and second planar regions R1 and R2 may include a cell region CR and a row decoder region XR adjacent to the cell region CR in the first direction FD.

[0041] As will be described later, the logic structure 2 may include a row decoder, a page buffer circuit, and peripheral circuits. In addition, the logic structure 2 may include a plurality of bottom wiring layers located at different height levels.

[0042] The source plate 3 may be disposed in the cell region CR of the first planar region R1 and the cell region CR of the second planar region R2 , respectively.

[0043] As will be described later, the memory structure 4 may include memory cell arrays respectively provided on the source plates 3 and a plurality of top wiring layers at different height levels. Figure 3 A structure including two planes is illustrated: a memory cell array disposed in a first plane region R1 may configure a first plane, and a memory cell array disposed in a second plane region R2 may configure a second plane.

[0044] Figure 4 is a top view of a representation illustrating a layout of a memory device according to an embodiment of the present disclosure.

[0045] Reference Figure 4 , the memory device 10 may include a plurality of plane regions R1 to R4. For example, Figure 4 The example includes four plane regions arranged in a row in the first direction FD. For ease of explanation, the plane regions R1 to R4 will be defined as first to fourth plane regions R1 to R4. Each of the first to fourth plane regions R1 to R4 may include a cell region CR and a row decoder region XR adjacent to the cell region CR in the first direction FD.

[0046] The memory cell array 110, the row decoder 120, and the page buffer circuit 130 may be provided in each of the first to fourth plane regions R1 to R4. The memory cell array 110, the row decoder 120, and the page buffer circuit 130 included in each of the first to fourth plane regions R1 to R4 may constitute one plane.

[0047] The memory cell array 110 may be provided in the cell region CR. The row decoder 120 may be provided in the row decoder region XR. The page buffer circuit 130 may be provided in the cell region CR to overlap with the memory cell array 110 in the vertical direction VD.

[0048] As mentioned above Figure 2 As described above, the operation voltage can be transmitted to the word line of the memory cell array 110 through the pass transistor of the row decoder 120. In order to reduce the delay time caused in the process of transmitting the operation voltage, the row decoder 120 can be configured to have a shape extending in the second direction SD, which is the arrangement direction of the word line, and can be configured to have a length in the second direction SD that is substantially the same as or similar to the length of the memory cell array 110.

[0049] In each of the first to fourth planar regions R1 to R4, the page buffer circuit 130 may be provided by being divided into a first page buffer region (first PB) 131 and a second page buffer region (second PB) 132. The first and second page buffer regions 131 and 132 may be arranged in the second direction SD.

[0050] In order to reduce the delay time of the signal applied to the bit line by the page buffer circuit 130 or provided to the page buffer circuit 130 through the bit line, the first page buffer area 131 and the second page buffer area 132 can each have a length that is substantially the same as or similar to the length of the memory cell array 110 in the first direction FD which is the arrangement direction of the bit line.

[0051] The peripheral circuit may be provided by being divided into a plurality of peripheral regions 210 and 220. The peripheral regions 210 and 220 may include a plurality of first peripheral regions (top PERIs) 210 and a plurality of second peripheral regions (middle PERIs) 220. One first peripheral region 210 and one second peripheral region 220 may be provided in the cell region CR of each of the first to fourth planar regions R1 to R4 to overlap with the memory cell array 110 in the vertical direction VD.

[0052] In the single cell region CR, the second peripheral region 220 may be disposed between the first page buffer region 131 and the second page buffer region 132. The first peripheral region 210 may be disposed on a side of the first page buffer region 131 opposite to a side adjacent to the second peripheral region 220. Therefore, the first peripheral region 210 and the second peripheral region 220 disposed in the single cell region CR may be respectively located on both sides of the first page buffer region 131 having a length substantially the same as or similar to that of the memory cell array 110 in the first direction FD.

[0053] The first peripheral region 210 of the first plane region R1 and the first peripheral region 210 of the second plane region R2 may be arranged on opposite sides of the pair of row decoders 120 of the first plane region R1 and the second plane region R2 in the first direction FD. The row decoders 120 of the first plane region R1 and the row decoders 120 of the second plane region R2 may each have a length in the second direction SD that is substantially the same as or similar to the length of the memory cell array 110. The second peripheral region 220 of the first plane region R1 and the second peripheral region 220 of the second plane region R2 may also be located on both sides of the pair of row decoders 120 of the first plane region R1 and the second plane region R2 in the first direction FD.

[0054] The first peripheral region 210 of the third plane region R3 and the first peripheral region 210 of the fourth plane region R4 may be arranged on opposite sides of the pair of row decoders 120 of the third plane region R3 and the row decoders 120 of the fourth plane region R4 in the first direction FD. The row decoders 120 of the third plane region R3 and the row decoders 120 of the fourth plane region R4 may each have a length substantially the same as or similar to the length of the memory cell array 110 in the second direction SD. The second peripheral region 220 of the third plane region R3 and the second peripheral region 220 of the fourth plane region R4 may also be located on both sides of the pair of row decoders 120 of the third plane region R3 and the row decoders 120 of the fourth plane region R4 in the first direction FD.

[0055] Although not shown, the elements configuring the peripheral circuit may be connected to each other through connection lines. The connection lines may include power lines for transmitting power such as power supply voltage and ground voltage, analog signal lines for transmitting analog signals, and logic signal lines for transmitting logic signals such as data, commands, and addresses.

[0056] In order to connect elements of the peripheral circuits provided in the plurality of peripheral regions 210 and 220 , some of the connection lines may have a shape extending in the second direction SD, and some of the connection lines may have a shape extending in the first direction FD.

[0057] As mentioned above Figure 2 As described, each of the row decoders 120 may include a plurality of pass transistors. The pass transistors may be used to transmit the power applied to the global line ( Figure 2 Although not shown, the global line may extend in the second direction SD and may be disposed to overlap with the transfer transistor of the row decoder 120 in the vertical direction VD.

[0058] As described above, since the global line extending in the second direction SD is disposed above the transfer transistor of the row decoder 120 , it becomes more difficult or complicated to dispose the connection line to avoid the global line.

[0059] For example, if the plane area is increased or a wiring layer is added in order to arrange the connection line, the connection line can be arranged independently of the position of the global line. However, if the plane area is increased or a wiring layer is added, the size of the memory device 10 will increase.

[0060] The embodiments of the present disclosure can achieve provision of connection lines without increasing the size of a memory device.

[0061] Figure 5 and Figure 6is a cross-sectional view illustrating a representation of a memory device according to an embodiment of the present disclosure.

[0062] Figure 5 is a cross-sectional view illustrating a cell region CR, and Figure 6 is a cross-sectional view illustrating a row decoder region XR. Figure 6 The components indicated by dotted lines are illustrated for ease of understanding and are not actually provided in the Figure 6 on the cross section.

[0063] Reference Figure 5 and Figure 6 , the substrate 1 may include at least one selected from the group consisting of: a single crystal silicon layer, an SOI (silicon on insulator), a silicon layer formed on a silicon germanium (SiGe) layer, a single crystal silicon layer formed on a dielectric layer, and a polycrystalline silicon layer formed on a dielectric layer.

[0064] The logic structure 2 may include a plurality of transistors TR defined in an active region of the substrate 1 defined by the isolation layer 1A, a plurality of bottom wiring layers UM1 to UM3 , and a plurality of contacts UM1C to UM3C.

[0065] The transistor TR may include a gate dielectric layer Gox defined on a substrate 1, a gate G defined on the gate dielectric layer Gox, and junction regions formed by implanting impurity ions into active regions on both sides of the gate G. One of the junction regions may serve as a source region S of the transistor TR, and the other may serve as a drain region D of the transistor TR. The transistor TR may configure any one of a row decoder, a page buffer circuit, and a peripheral circuit.

[0066] A dielectric layer 21 may be defined on the substrate 1 to cover the transistor TR. The dielectric layer 21 may include silicon oxide, for example, HDP (High Density Plasma) oxide or TEOS (Tetraethyl Orthosilicate) oxide.

[0067] A plurality of bottom wiring layers UM1 to UM3 may be provided in the dielectric layer 21. For example, the bottom wiring layers UM1 to UM3 may include a first bottom wiring layer UM1, a second bottom wiring layer UM2 above the first bottom wiring layer UM1, and a third bottom wiring layer UM3 above the second bottom wiring layer UM2. Figure 5 and Figure 6 Three bottom wiring layers UM1 to UM3 are illustrated, but it should be noted that the present disclosure is not limited thereto. The number of bottom wiring layers may be four or more.

[0068] A plurality of wiring patterns may be provided in each of the bottom wiring layers UM1 to UM3. The wiring patterns of the bottom wiring layers UM1 to UM3 may be configured to have characteristics that do not exhibit process failures (e.g., small hills) at the highest temperature (hereinafter referred to as the "process critical temperature") during the process of forming the memory cell array. In other words, as a material for the wiring patterns of the bottom wiring layers UM1 to UM3, a conductive material having heat-resistant characteristics at the process critical temperature may be used. For example, the wiring patterns of the bottom wiring layers UM1 to UM3 may include a material having a melting point higher than the process critical temperature, such as tungsten (W). Because the wiring patterns of the bottom wiring layers UM1 to UM3 are formed before the memory cell array is formed, the wiring patterns are formed of a conductive material having a high resistivity and a high melting point.

[0069] The wiring pattern of the second bottom wiring layer UM2 may include a plurality of first local lines LWL1, a plurality of global lines GWL, and a plurality of first connection lines CL1. The wiring pattern of the third bottom wiring layer UM3 may include a plurality of first local pads LP1 and a plurality of second connection lines CL2 (not illustrated in detail). The plurality of first local lines LWL1, the plurality of global lines GWL, the plurality of first connection lines CL1, and the plurality of first local pads LP1 may be arranged in the row decoder region XR. Although not illustrated in detail, the plurality of second connection lines CL2 may traverse the row decoder region XR in the first direction FD, and an end portion of each of the plurality of second connection lines CL2 may be arranged in the cell region CR.

[0070] A contact UM1C may be defined between the first bottom wiring layer UM1 and the transistor TR, and may couple the wiring pattern of the first bottom wiring layer UM1 and the transistor TR. A contact UM2C may be defined between the second bottom wiring layer UM2 and the first bottom wiring layer UM1, and may couple the wiring pattern of the second bottom wiring layer UM2 and the wiring pattern of the first bottom wiring layer UM1. A contact UM3C may be defined between the third bottom wiring layer UM3 and the second bottom wiring layer UM2, and may couple the wiring pattern of the third bottom wiring layer UM3 and the wiring pattern of the second bottom wiring layer UM2.

[0071] The source plate 3 may be configured to be disposed on the dielectric layer 21 of the cell region CR and to expose the dielectric layer 21 of the row decoder region XR. The source plate 3 may be formed as a polysilicon layer. Unlike the substrate 1, which may use a single crystal silicon layer, the source plate 3 may be formed as a polysilicon layer on the dielectric layer 21 of the logic structure 2.

[0072] The memory structure 4 may include multiple electrode layers 41 and multiple interlayer dielectric layers 42 alternately stacked on the source plate 3, multiple vertical channels CH passing through the multiple electrode layers 41 and the multiple interlayer dielectric layers 42, multiple top wiring layers M1 and M2, and contacts M0C, M1C and M2C.

[0073] The electrode layer 41 may include a conductive material. For example, the electrode layer 41 may include at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum). Among the electrode layers 41, at least one electrode layer 41 starting from the bottommost electrode layer 41 may be configured as a source select line SSL. Among the electrode layers 41, at least one electrode layer 41 starting from the topmost electrode layer 41 may be configured as a drain select line DSL. The electrode layer 41 between the source select line SSL and the drain select line DSL may be configured as a word line WL.

[0074] Each of the vertical channels CH may include a channel layer and a gate dielectric layer. The channel layer may include polycrystalline silicon or single crystal silicon, and may include p-type impurities such as boron (B) in some regions thereof. The channel layer may have the shape of a column completely filled to its center or the shape of a solid cylinder. Although not illustrated, the channel layer may have the shape of a tube with its central region open. In this case, a buried dielectric layer may be formed in the open central region of the channel layer. The gate dielectric layer may have the shape of a stem tube or a cylindrical shell surrounding the outer wall of the channel layer. Although not illustrated, the gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a blocking layer stacked in sequence from the outer wall of the channel layer. The gate dielectric layer may have an ONO (oxide-nitride-oxide) stacked structure in which an oxide layer, a nitride layer, and an oxide layer are stacked in sequence.

[0075] The source select transistor may be formed in a region where the source select line SSL surrounds the vertical channel CH. The drain select transistor may be formed in a region where the drain select line DSL surrounds the vertical channel CH. The memory cell may be formed in a region where the word line WL surrounds the vertical channel CH.

[0076] A dielectric layer 43 may be defined on the logic structure 2 to cover the top and side surfaces of the source plate 3, the alternately stacked plurality of electrode layers 41 and the plurality of interlayer dielectric layers 42, and the side surfaces of the plurality of vertical channels CH. In the row decoder region XR, a plurality of contacts M0C pass through the dielectric layer 43 in the vertical direction VD and may be respectively connected to the plurality of first local pads LP1 and the at least one second connection line CL2.

[0077] A dielectric layer 44 may be defined on the dielectric layer 43. A plurality of top wiring layers M1 and M2 may be provided in the dielectric layer 44. For example, the top wiring layers M1 and M2 may include a first top wiring layer M1 and a second top wiring layer M2 above the first top wiring layer M1. Each of the top wiring layers M1 and M2 may include a plurality of wiring patterns.

[0078] The wiring patterns of the top wiring layers M1 and M2 may be formed of a conductive material having a lower resistivity than the wiring patterns of the bottom wiring layers UM1 to UM3. For example, the wiring patterns of the top wiring layers M1 and M2 may include at least one of aluminum (Al) and copper (Cu). Because the wiring patterns of the top wiring layers M1 and M2 are formed after the memory cell array is formed, they may be formed of a material having a low resistivity that may cause process failure at a critical process temperature due to its low melting point.

[0079] Contacts M1C may be defined on the contacts M0C and the vertical channels CH. The wiring pattern of the first top wiring layer M1 may include bit lines BL, second local lines LWL2, and connection pads CP1. The bit lines BL may be disposed in the cell region CR, extending in the second direction SD, and arranged in the first direction FD. Each of the bit lines BL may be coupled to a corresponding vertical channel CH via a contact M1C.

[0080] The second local line LWL2 and the coupling pad CP1 may be disposed in the row decoder region XR. Each of the second local line LWL2 and the coupling pad CP1 may be coupled to a corresponding contact M0C through a contact M1C.

[0081] A plurality of contacts M2C may be defined between the first top wiring layer M1 and the second top wiring layer M2. Each of the plurality of contacts M2C may couple a wiring pattern of the first top wiring layer M1 to a corresponding wiring pattern of the second top wiring layer M2. The second top wiring layer M2 may include a third coupling wire CL3. The third coupling wire CL3 may be coupled to the coupling pad CP1 via the contact M2C.

[0082] 7A to 7E is a top view illustrating a representation of main components of a memory device according to an embodiment of the present disclosure, and illustrates a row decoder region XR.

[0083] In detail, Figure 7A is a top view illustrating a transfer transistor TR of a row decoder; Figure 7B is a top view illustrating the transfer transistor TR and the second bottom wiring layer UM2; Figure 7C is a top view illustrating the second bottom wiring layer UM2, the third bottom wiring layer UM3, and the contact UM3C; Figure 7Dis a top view illustrating the third bottom wiring layer UM3, the first top wiring layer M1, and the contact M0C; and Figure 7E is a top view illustrating the first top wiring layer M1 , the second top wiring layer M2 , and the contact M2C.

[0084] Reference Figure 6 and Figure 7A , a plurality of active areas ACT may be formed in the row decoder region XR of the substrate 1. In each active area ACT, a drain region D and two source regions S doped to a first conductivity type, and two channel regions (not shown) doped to a second conductivity type located between the drain region D and the source region S may be defined. The drain region D may be disposed at the center portion of the active area ACT in the second direction SD. The two source regions S may be disposed at the two ends of the active area ACT in the second direction SD, respectively. Each of the channel regions may be disposed between the drain region D and the adjacent source region S. A gate G may be formed above each channel region, and a gate dielectric layer Gox may be interposed between the gate and the channel region. The gate G may include a conductive material such as polysilicon. Two transfer transistors TR sharing a drain region D may be configured in each active area ACT. The two transfer transistors TR sharing a drain region D may be respectively connected to different memory blocks BLK. The transfer transistors TR in different active areas ACT connected to one memory block BLK may be arranged in two rows adjacent to each other in the second direction SD.

[0085] Although the present embodiment illustrates two transfer transistors TR in one active region ACT, it should be noted that the present disclosure is not limited thereto. For example, one transfer transistor TR may be configured in one active region ACT.

[0086] Although the present embodiment illustrates that the pass transistors TR coupled to one memory block BLK are arranged in two rows, it should be noted that the present disclosure is not limited thereto. For example, the pass transistors TR coupled to one memory block BLK may be arranged in one row or at least three rows.

[0087] Reference Figure 6 and Figure 7B , a plurality of first local lines LWL1 , a plurality of global lines GWL, and a plurality of first link lines CL1 may be provided in the second bottom wiring layer UM2 of the row decoder region XR.

[0088] A plurality of wiring traces T extending in the second direction SD and arranged at regular intervals in the first direction FD may be defined in the second bottom wiring layer UM2. The plurality of wiring traces T may be lines used as a reference in setting the first local line LWL1, the global line GWL, and the first link line CL1. The first local line LWL1, the global line GWL, and the first link line CL1 may be aligned with the wiring traces T, and the center line of each of the first local line LWL1, the global line GWL, and the first link line CL1 may overlap with the corresponding wiring trace T.

[0089] The global lines GWL may extend in the second direction SD and may each overlap with a corresponding transfer transistor TR in the vertical direction VD. Each of the plurality of global lines GWL may be connected to the second direction SD via a contact UM2C (see FIG. Figure 6 ), the first bottom wiring layer UM1 (see Figure 6 ) of the wiring pattern and contact UM1C (see Figure 6 ) is connected to the drain region D of the corresponding transfer transistor TR (see Figure 7A The second bottom wiring layer UM2 may correspond to the uppermost wiring layer used in setting global lines. Although this embodiment illustrates that global lines are set in one bottom wiring layer, it should be noted that the present disclosure is not limited thereto. The global lines may be set in at least one of the remaining bottom wiring layers except the third bottom wiring layer UM3.

[0090] The first local lines LWL1 may extend in the second direction SD and may each overlap the source region S of the corresponding transfer transistor TR in the vertical direction VD. Each of the plurality of first local lines LWL1 may be connected to the source region S of the transfer transistor TR through the contact UM2C (see FIG. Figure 6 ), the first bottom wiring layer UM1 (see Figure 6 ) of the wiring pattern and contact UM1C (see Figure 6 ) is connected to the source region S of the corresponding transfer transistor TR (see Figure 6 ).

[0091] Each of the plurality of first local lines LWL1 may be disposed within a width of a corresponding memory block BLK in the second direction SD. The plurality of first local lines LWL1 corresponding to different memory blocks BLK may be disposed in one wiring trace T. That is, the plurality of first local lines LWL1 corresponding to different memory blocks BLK may share one wiring trace T.

[0092] In the second bottom wiring layer UM2 , there may be a wiring trace T that is not used to arrange the global line GWL and the first local line LWL1 . Figure 7BThe area AR may correspond to an area in which a wiring trace T not used for disposing the global line GWL and the first local line LWL1 is located. The wiring trace T of the area AR may be used for the first link line CL1.

[0093] Reference Figure 6 and Figure 7C , a plurality of second connection lines CL2 and a plurality of first local pads LP1 may be provided in the third bottom wiring layer UM3. The first local pads LP1 corresponding to one memory block BLK may be arranged in a row within the width of the corresponding memory block BLK. The plurality of first local pads LP1 may be arranged in a plurality of rows corresponding to the plurality of memory blocks BLK arranged in the second direction SD in the second direction SD. The first local pads LP1 may be connected to the first local pads LP1 through the contact UM3C (see Figure 6 ) are coupled to the corresponding first local line LWL1.

[0094] A first zone ZONE1 and a second zone ZONE2 separated by a row of first partial pads LP1 may be defined. The first zone ZONE1 and the second zone ZONE2 may be arranged in the second direction SD. Although not illustrated, a plurality of first zones ZONE1 and a plurality of second zones ZONE2 may be alternately arranged in the second direction SD.

[0095] The second connection line CL2 may be disposed in the first zone ZONE1 and the second zone ZONE2 and may have a line shape extending in the first direction FD. In the second direction SD, the second connection line CL2 disposed in the first zone ZONE1 may have a width greater than that in the second zone ZONE2.

[0096] Due to the resistance component of second connection line CL2, the amplitude of the signal may decrease during transmission through second connection line CL2. Second connection line CL2 in first zone ZONE1 can be used to transmit signals that are likely to cause functional errors in the memory device when the signal amplitude is reduced, such as power signals and analog signals. Second connection line CL2 in second zone ZONE2 can be used to transmit signals that are less likely to cause functional errors in the memory device even when the signal amplitude is reduced and that require a large number of lines, such as logic signals that only need to distinguish between logic high and logic low.

[0097] Since the second bottom wiring layer UM2 is the uppermost wiring layer used when setting a global line, it is not necessary to configure a pad connected to the global line GWL in the third bottom wiring layer UM3. Therefore, there is no pad connected to the global line GWL in the third bottom wiring layer UM3.

[0098] Unlike the present embodiment, when pads connected to global lines are present in the third bottom wiring layer, the number of pads provided in the third bottom wiring layer increases, and the number of pad rows increases. Therefore, the number of second connection lines that can be provided in the third bottom wiring layer can be reduced. In contrast, according to the present embodiment, there are no pads connected to global lines GWL in the third bottom wiring layer UM3, so the number of pads provided in the third bottom wiring layer UM3 can be reduced, and the number of pad rows can be reduced. Therefore, the number of second connection lines that can be provided in the third bottom wiring layer UM3 can be increased.

[0099] Reference Figure 6 and Figure 7D , a plurality of second local lines LWL2 and coupling pads CP1 may be provided in the first top wiring layer M1.

[0100] The second local lines LWL2 may extend in the second direction SD and may each overlap the corresponding first local pad LP1 in the vertical direction VD. Figure 6 ) and the contact M0C may be disposed at an overlapping region between the second local line LWL2 and the corresponding first local pad LP1 in the vertical direction VD, thereby coupling the second local line LWL2 and the first local pad LP1.

[0101] The connection pad CP1 may overlap one of the second connection lines CL2 of the first zone ZONE1 in the vertical direction VD. Figure 6 ) and the contact member M0C may be disposed at an overlapping region between the coupling pad CP1 and the second coupling line CL2, such that the coupling pad CP1 and the second coupling line CL2 may be coupled.

[0102] Reference Figure 6 and Figure 7E , a third coupling line CL3 may be provided in the second top wiring layer M2. The third coupling line CL3 may extend in the second direction SD and may overlap the coupling pad CP1 in the vertical direction VD. A contact M2C may be defined at the overlapping region between the third coupling line CL3 and the coupling pad CP1, and the third coupling line CL3 may be coupled to the coupling pad CP1 through the contact M2C.

[0103] The third connection line CL3 may be connected to the first zone ZONE1 (see FIG. 1 ) through the contact M2C, the connection pad CP1, the contact M1C, and the contact M0C. Figure 7D ) is one of the second connection lines CL2.

[0104] Similar to ZONE 1 (see Figure 7D ) of the second connection line CL2 (see Figure 7D), the third connection line CL3 can be used to transmit signals that are likely to cause functional errors in the memory device when the signal amplitude is reduced, such as power signals and analog signals. As described above, the top wiring layer M2 is made of a conductive material with a lower resistivity than the bottom wiring layers UM1 to UM3. By using the third connection line CL3 to transmit signals such as power signals and analog signals that are likely to cause functional errors in the memory device when the signal level is reduced, functional errors in the memory device can be suppressed.

[0105] No global line is provided in the first and second top wiring layers M1 and M2. The first and second top wiring layers M1 and M2 may be defined as layers in which provision of a global line is prohibited.

[0106] According to a memory operation state, a high voltage may be loaded on the second local line LWL2. The high voltage applied to the second local line LWL2 may be higher than a voltage applied to the third link line CL3.

[0107] Because the second local line LWL2 and the third connection line CL3 have different voltage drive ranges, the memory device may malfunction due to the connection between the second local line LWL2 and the third connection line CL3. According to this embodiment, since the provision of global lines in the first and second top wiring layers M1 and M2 is prohibited, the number of top wiring layers required for provision of the second local line LWL2 can be reduced. Therefore, provision of local lines in the second top wiring layer M2, where the third connection line CL3 is provided, can be prohibited, and provision of connection lines in the first top wiring layer M1, where the second local line LWL2 is provided, can be prohibited.

[0108] Therefore, the third connection line CL3 and the second local line LWL2 can be arranged in different top wiring layers. Therefore, the coupling between the connection line and the local line can be reduced, thereby helping to suppress malfunction of the memory device caused by the coupling.

[0109] Figure 8 A block diagram schematically illustrates a representation of a memory system including a memory device according to an embodiment of the present disclosure.

[0110] Reference Figure 8 , a memory system 600 according to an embodiment may include a nonvolatile memory device (NVM device) 610 and a memory controller 620 .

[0111] The non-volatile memory device (NVM device) 610 may be composed of the aforementioned memory devices and may operate in the aforementioned manner. The memory controller 620 may be configured to control the non-volatile memory device (NVM device) 610. By combining the non-volatile memory device (NVM device) 610 and the memory controller 620, a memory card or a solid-state disk (SSD) may be provided. The SRAM 621 serves as a working memory for the processing unit (CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol for a host connected to the memory system 600.

[0112] The error correction code block (ECC) 624 detects and corrects errors included in data read from the nonvolatile memory device (NVM device) 610 .

[0113] The memory interface (memory I / F) 625 interfaces with the nonvolatile memory device (NVM device) 610 of the present embodiment. The processing unit (CPU) 622 performs general control operations for data exchange with the memory controller 620 .

[0114] Although not shown in the drawings, it is obvious to those skilled in the art that the memory system 600 according to the embodiment may be additionally provided with a ROM that stores code data for interfacing with a host. The non-volatile memory device (NVM device) 610 may be provided as a multi-chip package consisting of a plurality of flash memory chips.

[0115] As described above, the memory system 600 according to the present embodiment can be set to a high-reliability storage medium with a low probability of error. Specifically, the non-volatile memory device of the present embodiment can be included in a memory system such as a solid-state disk (SSD) that is currently being actively studied. In this case, the memory controller 620 can be configured to communicate with an external device (e.g., a host) through one of the following interface protocols: USB (Universal Serial Bus) protocol, MMC (MultiMediaCard) protocol, PCI-E (Peripheral Component Interconnect Express) protocol, SATA (Serial Advanced Technology Attachment) protocol, PATA (Parallel Advanced Technology Attachment) protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, and IDE (Integrated Drive Electronics) protocol.

[0116] Figure 9 is a block diagram schematically illustrating a representation of a computing system including a memory device according to an embodiment of the present disclosure.

[0117] Reference Figure 9The computing system 700 according to the embodiment may include a memory system 710, a microprocessor (CPU) 720, a RAM 730, a user interface 740, and a modem 750 (such as a baseband chipset) electrically connected to a system bus 760. In the case where the computing system 700 according to the embodiment is a mobile device, a battery (not shown) for supplying an operating voltage for the computing system 700 may be additionally provided. Although not shown in the drawings, it is obvious to those skilled in the art that the computing system 700 according to the embodiment may be additionally provided with an application chipset, a camera image processor (CIS), a mobile DRAM, etc. For example, the memory system 710 may be configured as an SSD (solid state drive / disk) that uses a non-volatile memory to store data. In addition, the memory system 710 may be configured as a fusion flash memory (e.g., OneNAND flash memory).

[0118] Although the exemplary embodiments of the present disclosure have been described for illustrative purposes, it will be understood by those skilled in the art that various modifications, additions, and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered only in a descriptive sense and not for the purpose of limiting the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of the present disclosure should be interpreted by the appended claims, and all equivalent forms falling within the scope of the appended claims are encompassed.

[0119] CROSS-REFERENCE TO RELATED APPLICATIONS

[0120] This application claims priority from Korean Patent Application No. 10-2020-0114973 filed on September 8, 2020, in the Korean Intellectual Property Office, which is hereby incorporated by reference in its entirety.

Claims

1. A memory device, comprising: a substrate defining a first unit region and a second unit region arranged in a first direction and a row decoder region arranged between the first unit region and the second unit region; a peripheral circuit defined in the first unit region and the second unit region of the substrate; a plurality of pass transistors defined in the row decoder region of the substrate; a plurality of bottom wiring layers disposed in a first dielectric layer covering the peripheral circuit and the plurality of pass transistors; a memory cell array defined on the first dielectric layer; a second dielectric layer, the second dielectric layer being defined on the first dielectric layer and covering the memory cell array; a plurality of top wiring layers disposed in a third dielectric layer, the third dielectric layer being defined on the second dielectric layer; as well as a plurality of global lines disposed in the row decoder region, the plurality of global lines transmitting operating voltages to the plurality of pass transistors, wherein the plurality of global lines are disposed only in the bottom wiring layer among the plurality of bottom wiring layers and the plurality of top wiring layers, and The plurality of global lines are arranged in a bottom wiring layer other than the topmost bottom wiring layer among the plurality of bottom wiring layers.

2. The memory device according to claim 1, wherein the plurality of bottom wiring layers include a first bottom wiring layer, a second bottom wiring layer above the first bottom wiring layer, and a third bottom wiring layer above the second bottom wiring layer, The third bottom wiring layer is the topmost bottom wiring layer, The plurality of top wiring layers include a first top wiring layer and a second top wiring layer above the first top wiring layer, and The plurality of global lines are disposed in the second bottom wiring layer.

3. The memory device according to claim 2, further comprising: a plurality of local lines disposed in the row decoder region and configured to transmit the operating voltage provided through the plurality of pass transistors to the memory cell array, Wherein, the plurality of local lines include: a plurality of first local lines provided in the second bottom wiring layer and electrically coupled to the plurality of transfer transistors, respectively; and A plurality of second local lines are provided in the first top wiring layer and are electrically coupled to the plurality of first local lines, respectively.

4. The memory device according to claim 3, further comprising: a plurality of first local pads, the plurality of first local pads being arranged in the row decoder region of the third bottom wiring layer and being respectively coupled to the first local lines through a plurality of first contacts, Wherein, the memory cell array includes a plurality of memory blocks, wherein the plurality of pass transistors are grouped into a plurality of pass transistor groups corresponding to the plurality of memory blocks respectively, and The first local pads coupled to the first local lines coupled to the pass transistors included in one of the plurality of pass transistor groups are arranged in a row in the first direction.

5. The memory device according to claim 4, wherein Each of the first unit area and the second unit area includes a plurality of peripheral areas arranged in a second direction, The peripheral circuit is divided into a plurality of peripheral areas, The elements included in the peripheral circuit are electrically connected to each other through a plurality of connection lines, and The plurality of connection lines include: a plurality of first connection lines, the plurality of first connection lines being arranged in the row decoder region of the second bottom wiring layer, the plurality of first connection lines extending in the second direction; a plurality of second connection lines, the plurality of second connection lines being provided in the third bottom wiring layer, the plurality of second connection lines extending in the first direction; and a third connection line provided in the row decoder region of the second top wiring layer, the third connection line extending in the second direction; The second direction is parallel to the top surface of the substrate and crosses the first direction. The memory device according to claim 5 , wherein: The second local line is provided in the first top wiring layer and is not provided in the second top wiring layer, and The third connection line is provided only in the second top wiring layer and is not provided in the first top wiring layer.

7. The memory device according to claim 5, further comprising: a connection pad provided in the row decoder region of the first top wiring layer, the connection pad being connected to the third connection line through a second contact; as well as A third contact passes through the second dielectric layer and couples the coupling pad and one of the plurality of second coupling lines.

8. The memory device according to claim 7, wherein The plurality of second connecting lines include: a first set of second coupling lines having a first width; and a second set of second coupling lines having a second width smaller than the first width, The third contact connects the connection pad to one of the first group of second connection lines.

9. The memory device according to claim 8, wherein The third bottom wiring layer includes a first area and a second area divided by a row of the first local pads arranged in the first direction, and The first group of second coupling lines is disposed in the first region, and the second group of second coupling lines is disposed in the second region.

10. The memory device according to claim 8, wherein The first group of second coupling lines includes power signal lines and analog signal lines, and the second group of second coupling lines includes logic signal lines.

11. A memory device, comprising: a substrate defining a first planar region and a second planar region arranged in a first direction, wherein each of the first planar region and the second planar region includes a cell region and a row decoder region adjacent to the cell region in the first direction; a plurality of pass transistors defined in the row decoder region of the first and second planar regions of the substrate; a peripheral circuit defined in the unit area of ​​the first planar area and the second planar area of ​​the substrate; A plurality of bottom wiring layers are provided on a surface covering the transfer transistor and the peripheral circuit. in the first dielectric layer; a first-plane memory cell array and a second-plane memory cell array, the first-plane memory cell array being disposed on the first dielectric layer and disposed in the cell region of the first-plane region, the second-plane memory cell array being disposed on the first dielectric layer and disposed in the cell region of the second-plane region; a second dielectric layer defined on the first dielectric layer and covering the memory cell array; a plurality of top wiring layers disposed in a third dielectric layer, the third dielectric layer being defined on the second dielectric layer; as well as a plurality of global lines disposed in the row decoder region of the first plane region and the second plane region and configured to transmit operating voltages to the plurality of pass transistors, wherein the plurality of global lines are disposed only in at least one bottom wiring layer among the plurality of bottom wiring layers and the plurality of top wiring layers, and The plurality of global lines are provided in at least one bottom wiring layer except an uppermost bottom wiring layer among the plurality of bottom wiring layers.

12. The memory device according to claim 11, wherein the plurality of bottom wiring layers include a first bottom wiring layer, a second bottom wiring layer above the first bottom wiring layer, and a third bottom wiring layer above the second bottom wiring layer, The third bottom wiring layer is the topmost bottom wiring layer, The plurality of top wiring layers include a first top wiring layer and a second top wiring layer above the first top wiring layer, and The plurality of global lines are disposed in the second bottom wiring layer.

13. The memory device according to claim 12, further comprising: a plurality of local lines disposed in the row decoder region of the first plane region and the second plane region and configured to transmit the operating voltage provided by the plurality of pass transistors to the memory cell array, Wherein, the plurality of local lines include: a plurality of first local lines provided in the second bottom wiring layer and electrically coupled to the plurality of pass transistors, respectively; and A plurality of second local lines are provided in the first top wiring layer and are electrically coupled to the plurality of first local lines, respectively.

14. The memory device according to claim 13, further comprising: a plurality of first local pads, the plurality of first local pads being disposed in the row decoder region of the third bottom wiring layer and being respectively coupled to the first local lines through a plurality of first contacts; Each of the memory cell arrays includes a plurality of memory blocks. wherein the plurality of pass transistors are grouped into a plurality of pass transistor groups corresponding to the plurality of memory blocks respectively, and Among the plurality of first local pads, first local pads connected to a first local line connected to a pass transistor included in one of the plurality of pass transistor groups are arranged in a row in the first direction.

15. The memory device according to claim 14, wherein Each of the unit regions of the first planar region and the second planar region includes a plurality of peripheral regions arranged in a second direction that is parallel to the top surface of the substrate and intersects the first direction, The peripheral circuit is arranged in the plurality of peripheral regions, The elements included in the peripheral circuit are electrically connected to each other through a plurality of connection lines, and The plurality of connection lines include: a plurality of first connection lines, the plurality of first connection lines being arranged in the row decoder region of the second bottom wiring layer and extending in the second direction; a plurality of second connection lines disposed in the third bottom wiring layer and extending in the first direction; and A third connection line is provided in the row decoder region of the second top wiring layer and extends in the second direction.

16. The memory device according to claim 15, further comprising: a connection pad provided in the row decoder region of the first top wiring layer and coupled to the third connection line through a second contact; as well as A third contact passes through the second dielectric layer and couples the coupling pad to one of the plurality of second coupling lines.

17. The memory device according to claim 16, wherein: The plurality of second connecting lines include: a first set of second coupling lines having a first width; and a second set of second coupling lines having a second width smaller than the first width, wherein the third contact connects the connection pad to one of the first group of second connection lines, and The first group of second connection lines includes power signal lines and analog signal lines, and the second group of second connection lines includes logic signal lines.

18. The memory device according to claim 17, wherein: The third bottom wiring layer includes a first area and a second area divided by a row of the first local pads arranged in the first direction, and The first group of second coupling lines is disposed in the first region, and the second group of second coupling lines is disposed in the second region.

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