Gallium nitride epitaxial structure for power devices

Abstract

A method for fabricating a multilayer device on an engineered substrate having a substrate coefficient of thermal expansion, comprising: growing a buffer layer on the engineered substrate; and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized as having an epitaxial coefficient of thermal expansion that is substantially the same as the substrate coefficient of thermal expansion.

Description

[0001] This application is a divisional application of Chinese Invention Patent Application No. 2018800071840, filed on January 10, 2018, with the title of "Gallium Nitride Epitaxial Structure for Power Devices".

[0002] Cross Reference to Related Applications

[0003] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 447,857, filed on January 18, 2017, U.S. Provisional Patent Application No. 62 / 591,016, filed on November 27, 2017, and U.S. Non-Provisional Patent Application No. 15 / 864,977, filed on January 8, 2018, the entire contents of which are incorporated herein by reference. BACKGROUND

[0004] Generally, gallium nitride-based power devices are epitaxially grown on sapphire substrates. Since the substrate and the epitaxial layer are composed of different materials, the growth of gallium nitride-based power devices on sapphire substrates is a heteroepitaxial growth process. Due to this heteroepitaxial growth process, the epitaxially grown material can exhibit various negative effects, including a reduction in uniformity and a reduction in metrics associated with electronic / optical properties of the epitaxial layer. Therefore, there is a need for improved methods and systems related to epitaxial growth processes and substrate structures in this field. SUMMARY

[0005] According to some embodiments of the present invention, a method for fabricating a multilayer device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate; and growing a first epitaxial layer on the buffer layer. The first epitaxial layer is characterized as having an epitaxial coefficient of thermal expansion that is substantially the same as the substrate coefficient of thermal expansion.

[0006] According to some other embodiments of the invention, a method of fabricating a multilayer device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate; and growing one or more epitaxial layers on the buffer layer. At least one of the one or more epitaxial layers is characterized by having an epitaxial coefficient of thermal expansion that is substantially the same as the substrate coefficient of thermal expansion. In some embodiments, the one or more epitaxial layers can include a superlattice of alternating undoped GaN layers and doped GaN layers. The doped GaN can include carbon-doped GaN (C-GaN) or iron-doped GaN (Fe-GaN). The method can further include growing an undoped GaN layer coupled to the superlattice; and growing a first epitaxial layer coupled to the undoped GaN layer. The first epitaxial layer can include aluminum gallium nitride (AlGaN) or indium aluminum nitride (InAlN). An interface between the undoped GaN layer and the first epitaxial layer can form a conductive channel 150 of a high electron mobility transistor (HEMT). The engineered substrate can include a polycrystalline ceramic core, a barrier layer encapsulating the polycrystalline ceramic core, a bonding layer coupled to the barrier layer, and a substantially single crystalline silicon layer coupled to the bonding layer. The buffer layer can include at least one of AlN, AlGaN, or AlN / AlGaN.

[0007] According to some other embodiments of the invention, a method for fabricating a multilayer device on an engineered substrate having a substrate coefficient of thermal expansion includes growing a buffer layer on the engineered substrate; and growing a first epitaxial layer coupled to the buffer layer. The first epitaxial layer is characterized by having an epitaxial coefficient of thermal expansion that is substantially the same as the substrate coefficient of thermal expansion. The method further includes growing an aluminum gallium nitride (AlGaN) back barrier layer coupled to the first epitaxial layer; growing an undoped gallium nitride (GaN) layer coupled to the AlGaN back barrier layer; and growing a barrier layer coupled to the undoped GaN layer.

[0008] According to some other embodiments of the invention, an epitaxial semiconductor structure includes an engineered substrate having a substrate coefficient of thermal expansion; a buffer layer formed on the engineered substrate; and a first epitaxial layer formed on the buffer layer. The first epitaxial layer is characterized by having an epitaxial coefficient of thermal expansion that is substantially the same as the substrate coefficient of thermal expansion. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 FIG. 1 is a simplified cross-sectional schematic diagram illustrating a power device formed on an engineered substrate structure according to an embodiment of the invention.

[0010] Figure 2 FIG. 2 is a simplified cross-sectional schematic diagram illustrating a power device formed on an engineered substrate structure according to another embodiment of the invention.

[0011] Figure 3 A simplified cross-sectional schematic diagram showing a power device formed on an engineered substrate structure with back-side contact according to embodiments of the present application.

[0012] Figure 4 A simplified cross-sectional schematic diagram showing a power device formed on an engineered substrate structure with front-side contact according to embodiments of the present application.

[0013] Figure 5 A simplified cross-sectional schematic diagram showing a power device formed on an engineered substrate structure according to embodiments of the present application.

[0014] Figure 6 A simplified cross-sectional schematic diagram showing a power device formed on an engineered substrate structure according to another embodiment of the present application.

[0015] Figure 7 A simplified cross-sectional schematic diagram showing a power device formed on an engineered substrate structure according to yet another embodiment of the present application.

[0016] Figure 8 A simplified cross-sectional schematic diagram showing a power device formed on an engineered substrate structure according to some other embodiments of the present application.

[0017] Figure 9A An exemplary conduction band diagram of a HEMT without an AlGaN back barrier according to some embodiments is shown.

[0018] Figure 9B An exemplary conduction band diagram of a HEMT with an AlGaN back barrier according to some other embodiments is shown.

[0019] Figure 10 A simplified cross-sectional schematic diagram showing a substrate structure suitable for use in the manufacture of power devices according to embodiments of the present application.

[0020] Figure 11 A simplified cross-sectional schematic diagram showing an engineered substrate structure according to embodiments of the present application.

[0021] Figure 12 A simplified schematic diagram showing an engineered substrate structure according to some embodiments of the present application.

[0022] Figure 13 A simplified schematic diagram showing an engineered substrate structure according to some other embodiments of the present application.

[0023] Figure 14 FIG. 1 is a simplified schematic diagram illustrating an engineered substrate structure according to some embodiments of the present application.

[0024] Figure 15 FIG. 2 is a simplified flow diagram illustrating a method of fabricating an engineered substrate according to some embodiments of the present application.

[0025] Figure 16 FIG. 3 is a simplified flow diagram illustrating a method of fabricating a multilayer device on an engineered substrate according to some embodiments of the present application.

[0026] Figure 17 FIG. 4 is a simplified flow diagram illustrating a method of fabricating a multilayer device on an engineered substrate according to some other embodiments of the present application.

[0027] Figure 18 FIG. 5 is a simplified flow diagram illustrating a method of fabricating a multilayer device on an engineered substrate according to some further embodiments of the present application. DETAILED DESCRIPTION

[0028] The present application generally relates to power devices formed on engineered substrates. More specifically, the present application relates to methods and systems suitable for fabricating power devices using epitaxial growth processes. By way of example only, the present application has been applied to methods and systems for fabricating power devices on substrates by epitaxial growth, where the substrate is characterized by a coefficient of thermal expansion (CTE) that substantially matches an epitaxial layer forming the power device. The methods and techniques can be applied in a variety of semiconductor processing operations.

[0029] Figure 1 FIG. 1 is a simplified schematic diagram illustrating an engineered substrate structure according to some embodiments of the present application. The engineered substrate structure 102 can include a ceramic substrate 110, with a thin silicon (Si) layer 120 formed on the ceramic substrate 110. The silicon layer 120 can provide a surface for subsequent epitaxial growth. The CTE of the ceramic substrate 110 can substantially match the CTE of one or more subsequent epitaxial layers.

[0030] A buffer layer 130 can be epitaxially formed on the silicon layer 120. The buffer layer 130 can include one or more layers. In some embodiments, the buffer layer 130 can be relatively thin, e.g., less than 0.5 microns thick. The buffer layer 130 can include, for example, AlN about 0.2 μm thick, AlGaN about 0.125 μm thick, GaN about 0.125 μm thick, combinations thereof, etc. The relatively thin aluminum-containing buffer layer (e.g., 0.2 μm AlN / 0.125 μm AlGaN) can provide a surface for subsequent epitaxial growth that is substantially free of defects. 0.25 Ga 0.75 N, combinations thereof, etc. The relatively thin aluminum-containing buffer layer (e.g., 0.2 μm AlN / 0.125 μm Al0.25 Ga 0.75 N) can support GaN epitaxy larger than 8 micrometers on large-diameter substrates, while GaN epitaxy larger than 8 micrometers cannot be manufactured using silicon substrates.

[0031] A GaN epitaxial layer 140 may be formed on the buffer layer 130. In some embodiments, the thickness of the GaN epitaxial layer 140 may be greater than 8 μm for high voltage withstand. For example, in power devices subsequently formed on the GaN epitaxial layer 140, a breakdown voltage greater than 500V or 600V can be obtained. Figure 1 As shown, the GaN epitaxial layer 140 may include a doped GaN epitaxial layer 142 and an undoped GaN epitaxial layer 144 below (e.g., immediately below) the conductive channel 150. The doped GaN epitaxial layer 142 may have a thickness of 5 μm or greater. In some embodiments, the doped GaN epitaxial layer 142 may include C or Fe-doped GaN to provide high resistance. As discussed more fully herein, the low conductivity layer may be formed, for example, a C-GaN layer or an Fe-GaN layer, wherein the background doping level (free carrier density) of the C-GaN layer or Fe-GaN layer is approximately 1 × 10⁻⁶. 12 cm -3 This is because carbon or iron cancels out background impurities or provides a deep center.

[0032] Although this paper discusses GaN layers, the invention is not limited to GaN and may utilize other III-V materials, including AlGaN, InGaN, InAlGaN, and combinations thereof. Many variations, modifications, and substitutions will be apparent to those skilled in the art.

[0033] An AlGaN or InAlN layer 160 can be formed as a barrier layer on the GaN epitaxial layer 140. At the AlGaN / GaN interface, a two-dimensional electron gas (2DEG) may be generated due to polarization-induced charges at the heterojunction. The 2DEG forms the conductive channel 150 of the high electron mobility transistor (HEMT) power device.

[0034] In some embodiments, an optional undoped or p-type GaN capping layer may be formed on the AlGaN or InAlN layer 160 to suit the fabrication of enhancement-mode devices.

[0035] Since the CTE of the ceramic substrate 110 can substantially match the CTE of the GaN epitaxial layer, the relatively thin buffer layer 130 (e.g., less than 0.5 μm) can support the relatively thick GaN epitaxial layer 140 (e.g., greater than 5 μm).

[0036] Figure 2A simplified cross-sectional schematic diagram illustrating a power device formed on an engineered substrate structure 202 according to an embodiment of the present invention is provided. The engineered substrate structure 202 may include a ceramic substrate 110 on which a thin silicon-germanium (SiGe) layer 220 is formed. The silicon-germanium layer 220 can provide a lattice-matched surface for subsequent epitaxial growth. The CTE of the ceramic substrate 110 can substantially match the CTE of the subsequent epitaxial layer. The silicon-germanium layer 220 may be epitaxially grown on a Si layer (not shown), or may be transferred from the donor substrate (e.g., by bonding a donor substrate (on which a SiGe layer is formed) to the ceramic substrate).

[0037] A buffer layer 130 may be epitaxially formed on the SiGe layer 220. The buffer layer 130 may comprise one or more layers. In some embodiments, the buffer layer 130 may be relatively thin, for example, less than 0.5 micrometers thick. The buffer layer 130 may comprise, for example, AlN with a thickness of about 0.2 μm, Al with a thickness of about 0.125 μm, etc. 0.25 Ga 0.75 N, their combinations, etc. Relatively thin aluminum-containing buffer layers (e.g., 0.2 μm AlN / 0.125 μm Al). 0.25 Ga 0.75 N) can support GaN epitaxy larger than 8 micrometers on large-diameter substrates, while GaN epitaxy larger than 8 micrometers cannot be manufactured using silicon substrates.

[0038] A GaN epitaxial layer 140 may be formed on the buffer layer 130. In some embodiments, the thickness of the GaN epitaxial layer 140 may be greater than 8 μm for high voltage withstand. For example, in power devices subsequently formed on the GaN epitaxial layer, a breakdown voltage greater than 500V or 600V can be obtained. Figure 2 As shown, the GaN epitaxial layer may include, for example, a 5 μm doped epitaxial layer 142 and an undoped GaN epitaxial layer 144 located below (e.g., immediately below) the conductive channel 150. In some embodiments, the doped epitaxial layer 142 may comprise C- or Fe-doped GaN. While GaN layers have been discussed herein, the invention is not limited to GaN and may utilize other III-V materials, including AlGaN, InGaN, InAlGaN, and combinations thereof. Many variations, modifications, and substitutions will be recognized by those skilled in the art.

[0039] An AlGaN or InAlN layer 160 can be formed as a barrier layer on the GaN epitaxial layer 140. At the AlGaN / GaN interface, a two-dimensional electron gas (2DEG) may be generated due to polarization-induced charges at the heterojunction. The 2DEG forms the conductive channel 150 of the high electron mobility transistor (HEMT) power device.

[0040] In some embodiments, an optional undoped or p-type GaN cap layer can be formed on the AlGaN or InAlN layer 160 to be suitable for fabricating enhancement mode devices.

[0041] Figure 3 A simplified cross-sectional schematic of a power device formed on an engineered substrate structure 102 according to embodiments of the application is shown. The engineered substrate structure 102 can include a ceramic substrate 110 on which a thin Si layer 120 is formed. The Si layer 120 can provide a surface for subsequent epitaxial growth. The CTE of the ceramic substrate 110 can be substantially matched to the CTE of the subsequent epitaxial layers.

[0042] The power device can also include a buffer layer 130 epitaxially formed on the Si layer 120, a GaN epitaxial layer 140 formed on the buffer layer 130, and an AlGaN or InAlN barrier layer 160 formed on the GaN epitaxial layer 140, substantially similar to the power device shown in Figure 1 The GaN epitaxial layer 140 can include a 5 μιη doped epitaxial layer 142 below (e.g., immediately below) the conductive channel 150 and an undoped GaN epitaxial layer 144. The GaN epitaxial layer 140 can also include one or more conductive epitaxial layers below the doped epitaxial layer (e.g., as shown in Figure 4

[0043] The power device can also include an electrical contact 310 to the Si layer 120 or the GaN epitaxial layer 140, the electrical contact 310 formed through the ceramic substrate 110. During operation of the power device, some parasitic charge can accumulate in the Si layer 120 and / or the buffer layer 130, resulting in parasitic capacitance. The electrical contact 310 can facilitate removal of the parasitic charge, resulting in faster switching of the power device.

[0044] Figure 4 A simplified cross-sectional schematic of a power device formed on an engineered substrate structure 102 according to embodiments of the application is shown. The engineered substrate structure 102 can include a ceramic substrate 110 on which a thin Si layer 120 is formed. The Si layer 120 can provide a surface for subsequent epitaxial growth. The CTE of the ceramic substrate 110 can be substantially matched to the CTE of the subsequent epitaxial layers.

[0045] A GaN epitaxial layer 140 can be formed on the buffer layer 130. In some embodiments, the thickness of the GaN epitaxial layer 140 can be greater than 8 μιη for high voltage resistance. For example, in a power device subsequently formed on the GaN epitaxial layer 140, a breakdown voltage greater than 500 V or 600 V can be obtained. As Figure 4 ​As shown, the GaN epitaxial layer 140 may include, for example, a conductive GaN epitaxial layer 420, a doped GaN epitaxial layer 142, and an undoped GaN epitaxial layer 144 located below (e.g., immediately below) the conductive channel 150. In some embodiments, the doped epitaxial layer 142 may comprise C- or Fe-doped GaN. While GaN layers have been discussed herein, the invention is not limited to GaN and may utilize other III-V materials, including AlGaN, InGaN, InAlGaN, and combinations thereof. Many variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0046] An AlGaN or InAlN layer 160 can be formed as a barrier layer on the GaN epitaxial layer 140. At the AlGaN / GaN interface, a two-dimensional electron gas (2DEG) may be generated due to polarization-induced charges at the heterojunction. The 2DEG forms the conductive channel 150 of a high electron mobility transistor (HEMT) power device.

[0047] In some embodiments, an optional undoped or p-type GaN capping layer 170 may be formed on the AlGaN or InAlN layer 160 to suit the fabrication of enhancement-mode devices.

[0048] The power device may also include electrical contacts 410 extending to the Si layer 120 or the GaN epitaxial layer 140, the electrical contacts 410 being formed across the front of the power device. Although Figure 4 The electrical contact extends through the GaN epitaxial layer 140 to the buffer layer 130, but in some embodiments, the electrical contact may extend to the Si layer 120. The electrical contact may be insulated on its sidewalls so that it is not electrically connected to the AlGaN or InAlN layer 160 and the GaN epitaxial layer 140. The electrical contact 410 may facilitate the removal of parasitic charges, thereby enabling faster switching of power devices.

[0049] Figure 5 A simplified cross-sectional schematic diagram is provided to illustrate a power device formed on an engineered substrate structure 102 according to another embodiment of the present invention. The engineered substrate 102 may include a ceramic substrate 110 on which a thin silicon (Si) layer 120 is formed. The silicon layer 120 may provide a surface for subsequent epitaxial growth and may be a single-crystal layer. The CTE of the ceramic substrate 110 may substantially match the CTE of one or more subsequent epitaxial layers.

[0050] like Figure 5 As shown, a partial monolayer 510 of SiN can be inserted to promote a reduction in dislocations during 3D growth. The use of an engineered substrate 102, due to the polycrystalline ceramic core substrate 110, can reduce compressive stress in the epitaxial layer. (As shown...) Figure 5As shown, a local monolayer 510 of SiN can provide SiN islands, which are used to reduce dislocation density and improve crystal quality during lateral overgrowth. Further description is provided in U.S. Patent No. 9,012,253, published April 21, 2015, the contents of which are incorporated herein by reference in their entirety for all purposes.

[0051] The local monolayer 510 of SiN can partially cover the buffer layer 130 and provide tensile stress for the epitaxial growth of GaN. The regrowth of GaN on the local monolayer 510 of SiN can lead to nucleation between SiN islands and lateral overgrowth on the SiN islands, thereby terminating dislocations and improving crystal quality. Although this paper discusses SiN islands, other local layers can be used, including arrays of SiN strips. Furthermore, SiN is not necessarily formed as a monolayer, but can have a thickness greater than a predetermined monolayer. Besides SiN, other materials, including SiO2, can be used during the lateral overgrowth process.

[0052] In some embodiments, multiple local monolayers are used. In these embodiments, a first local monolayer is formed, a first lateral overgrowth is performed, a second local monolayer is formed, a second lateral overgrowth is performed, and the monolayer / regrowth structure can be repeated a predetermined number of times to provide multiple sandwich layers. The thickness of the lateral overgrowth layer can vary, for example, from 0.5 μm to 2.5 μm in some embodiments. Because the lateral overgrowth layers successively become flatter and are characterized by a reduced number of defects and / or dislocations, the local monolayer 510 can provide an improved surface for subsequent lateral overgrowth layers, which can increase or decrease the thickness to suit a particular application.

[0053] In some embodiments, the conductive epitaxial layer 520 formed on the local monolayer 510 of SiN can be undoped GaN (u-GaN), characterized by an octane rating of approximately 1 × 10⁻⁶. 16 cm -3 Its low doping density provides a high-resistivity layer that serves as an integral part of the overall epitaxial structure in the design.

[0054] Figure 6 A simplified cross-sectional schematic diagram is provided to illustrate a power device formed on an engineered substrate structure 102 according to another embodiment of the present invention. The engineered substrate 102 may include a ceramic substrate 110 on which a thin silicon (Si) layer 120 is formed. The silicon layer 120 may provide a surface for subsequent epitaxial growth and may be a single-crystal layer. The CTE of the ceramic substrate 110 may substantially match the CTE of one or more subsequent epitaxial layers.

[0055] like Figure 6 As shown, Al with a preset aluminum mole fraction (x)x Ga 1-x The AlGaN and GaN epitaxial layer 640 extends from the buffer layer 130 to the undoped GaN layer 144 below the channel 150. The aluminum mole fraction can be low, for example less than 10%, to provide the desired confinement of the charge carriers. In other embodiments, the aluminum mole fraction can range from 10% to 30%. The Al x Ga 1-x The AlGaN and GaN epitaxial layer 640 can be doped with iron or carbon to further increase the resistivity of the epitaxial layer, which can be used as an insulating or barrier layer. The bandgap difference between the AlGaN and GaN can provide an additional barrier to breakdown.

[0056] Figure 7 A simplified cross-sectional schematic of a power device formed on an engineered substrate structure 102 according to another embodiment of the application is shown. The engineered substrate structure 102 can include a ceramic substrate 110 on which a thin silicon (Si) layer 120 is formed. The silicon layer 120 can provide a surface for subsequent epitaxial growth, which can be a single crystalline layer. The CTE of the ceramic substrate 110 can be substantially matched to the CTE of one or more subsequent epitaxial layers.

[0057] In Figure 7 some embodiments, the epitaxial structure 740 is formed by growing alternating C-GaN (or Fe-GaN) layers and undoped GaN (u-GaN) layers to provide high resistance and improved crystal quality. Since u-GaN is typically grown at higher temperatures than C-GaN or Fe-GaN, the presence of u-GaN in the superlattice can result in better crystal quality since higher growth temperatures are generally associated with higher quality crystals. Thus, this structure maintains the insulating properties of the epitaxial layer, which provides high breakdown performance, while improving the crystal quality. In some embodiments, even without intentional doping, the u-GaN has a background doping level of approximately 1 x 1010cm-2 due to incorporation of dopants present in the growth chamber. These layers with low conductivity can be combined with C-GaN or Fe-GaN layers in the superlattice, which have a background doping level (free carrier density) of approximately 1 x 1010cm-2 due to the carbon or iron canceling out the background impurities. Thus, the superlattice can provide high resistance and high crystal quality. 16 cm -3 12 cm -3

[0058] Figure 8 ​​A simplified cross-sectional schematic of a power device formed on an engineered substrate structure 102 according to another embodiment of the present application is shown. The engineered substrate structure 102 can include a ceramic substrate 110 on which a thin silicon (Si) layer 120 is formed. The silicon layer 120 can provide a surface for subsequent epitaxial growth, which can be a single crystalline layer. The CTE of the ceramic substrate 102 can be substantially matched to the CTE of one or more subsequent epitaxial layers. A buffer layer 130 can be formed epitaxially on the Si layer 120. A non-intentionally doped GaN (UID-GaN) epitaxial layer 840 (or alternating C-GaN (or Fe-GaN) layers and undoped GaN (uGaN) layers) can be formed on the buffer layer 130, as discussed above with reference to FIG. 1. Figure 1 and Figure 7 as discussed above.

[0059] Still referring to Figure 8 , an undoped low-composition AlGaN layer 810 can be formed on the UID-GaN layer 840 (or alternating C-GaN (or Fe-GaN) layers and uGaN layers). The undoped low-composition AlGaN layer 810 can be referred to as a back barrier layer. An undoped GaN layer 144 can be formed on the undoped low-composition AlGaN layer 810. An AlGaN (or InGaN) layer 160 can be formed on the undoped GaN layer 810. The AlGaN (or InGaN) layer 160 can be referred to as a barrier layer. At the AlGaN / GaN interface, a two-dimensional electron gas (2DEG) can be generated due to polarization-induced charges at the hetero-interface. The two-dimensional electron gas forms a conductive channel 150 of a high electron mobility transistor (HEMT) power device. The addition of the low-composition AlGaN layer 840 (i.e., the back barrier layer) can enhance the retention of electrons in the conductive channel 150 and prevent the electrons from penetrating into the UID-GaN layer 840 (or alternating C-GaN (or Fe-GaN) layers and uGaN layers) as a leakage current, as discussed below.

[0060] Figure 9A An exemplary conduction band (CB) diagram of a HEMT without a back barrier layer according to some embodiments is shown. The aluminum mole fraction of the AlGaN barrier layer 160 can range from about 10% to about 100%, and the thickness dl can range from about 1 nm to about 100 nm. The thickness d2 of the GaN layer 144 (i.e., the channel) can range from about 10 nm to about 100 nm. The thickness d3 of the UID-GaN layer 840 can be greater than about 8 pm for high voltage resistance, as discussed above. As shown, Figure 9A The conduction band of the AlGaN barrier layer 160 can form a first barrier height E F relative to the Fermi energy level (E B1First barrier height E B1 The range can be from about 1 eV to about 4 eV. The conduction band of the UID-GaN layer 840 can be relative to the Fermi level (E... F The second potential barrier height E is formed. B2 The height of the second barrier is E B2 It can be substantially lower than the height E of the first barrier. B1 In some embodiments, E B2 The range can be from about 0.2 eV to 1.5 eV. Therefore, electrons in the channel (2DEG) 150 can easily penetrate into the UID-GaN layer 840, thereby generating leakage current.

[0061] Figure 9B An exemplary conduction band (CB) diagram of a HEMT with a low-concentration AlGaN back barrier layer 810 according to another embodiment is shown. For clarity, regarding Figure 9A The components shown will not be repeated. The aluminum molar fraction of the low-concentration AlGaN back barrier layer 810 can range from about 1% to about 50%, for example from about 3% to about 15%, and the thickness d4 can range from about 0.1 μm to about 1 μm, for example from about 0.2 μm to about 0.3 μm. In some embodiments, the AlGaN back barrier layer 810 can be undoped. As shown, the low-concentration AlGaN back barrier layer 810 can be relative to the Fermi level (E F The third barrier height E is formed. B3 , and like Figure 9A The second barrier height E shown is formed by a UID-GaN layer 840 without a low-component AlGaN back barrier layer 810. B2 In comparison, the height of the third barrier is E B3 Relatively high. In some embodiments, E B3 The range is from 1 eV to 3 eV. Therefore, the addition of the low-concentration AlGaN back barrier layer 810 can prevent electrons in the channel (2DEG) from penetrating into the UID-GaN layer, thereby reducing the leakage current through the substrate.

[0062] Figure 10 A simplified cross-sectional schematic diagram is shown for a substrate structure 102 suitable for use in the manufacture of power devices according to an embodiment of the present invention. (Refer to...) Figure 10 An engineered substrate 102, including a polycrystalline ceramic core 110, may be provided (which may include...). Figure 11A single crystal layer 120 (e.g., single crystal silicon) is bonded to the polycrystalline ceramic core 110 (e.g., using a layer transfer process) to provide a single crystal growth surface. A buffer layer 130 can be grown on the single crystal layer 120, and a III-V epitaxial layer 1040 (e.g., GaN) can be grown on the buffer layer 130. The CTE of the III-V epitaxial layer 1040 can be substantially matched to the CTE of the core of the polycrystalline ceramic core 110. The III-V epitaxial layer 1040 can be single crystalline, with high quality to some extent resulting from the CTE matching.

[0063] Figure 11 A simplified schematic diagram showing an engineered substrate structure according to some embodiments of the present application. As shown, the engineered substrate structure can be suitable for various electronic and optical applications. The engineered substrate structure includes a core 1110 (e.g., an AIN substrate) that can have a coefficient of thermal expansion (CTE) that is substantially matched to the CTE of epitaxial material to be grown on the engineered substrate structure (e.g., on a released silicon (111) layer 1125). Figure 11

[0064] For applications involving growth of gallium nitride (GaN)-based materials (including epitaxial layers of GaN-based layers), the core 1110 can be a polycrystalline ceramic material, e.g., polycrystalline aluminum nitride (AIN), which can include a binder material, e.g., yttrium oxide. Other materials can also be used in the core, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium sesquioxide (Ga2O3), etc.

[0065] The core 1110 can have a thickness of about 100 μm to 1500 μm, e.g., 750 μm. The core 1110 can be encapsulated in an adhesion layer 1112, which can be referred to as a shell or encapsulation shell. In one embodiment, the adhesion layer 1112 includes a tetraethyl orthosilicate (TEOS) oxide layer having a thickness of about 1 μm to 10 μm, e.g., 5 μm. In other embodiments, the thickness of the adhesion layer 1112 varies, e.g., in the range of about 1 μm to 10 μm, e.g., 5 μm. to While TEOS oxide is used for the adhesion layer 1112 in some embodiments, other materials that provide adhesion between a subsequently deposited layer and an underlying layer or material (e.g., ceramic, in particular, polycrystalline ceramic) can also be used in accordance with embodiments of the present application. For example, silicon dioxide (SiO2) or other silicon oxides (SiOx) can be used. Other materials that provide adhesion between a subsequently deposited layer and an underlying layer or material (e.g., ceramic, in particular, polycrystalline ceramic) can also be used in accordance with embodiments of the present application. x O y ​The adhesive layer 1112 adheres well to the ceramic material and provides a suitable surface for subsequent deposition (e.g., deposition of conductive materials). In some embodiments, the adhesive layer 1112 completely surrounds the core 1110 to form a fully encapsulated core 1110, and can be formed using LPCVD (low-pressure chemical vapor deposition) or other suitable deposition processes that are compatible with semiconductor processes, particularly with polycrystalline or composite substrates and layers. The adhesive layer 1112 provides a surface on which subsequent layers adhere to form components of an engineered substrate structure.

[0066] According to embodiments of the present invention, in addition to using LPCVD processes, spin coating on glass / dielectrics, furnace-based processes, etc., to form the adhesive layer of the package, other semiconductor processes, including CVD (chemical vapor deposition) processes or similar deposition processes, can also be used. As an example, a deposition process can be used to coat a portion of core 1110, which can be flipped, and the deposition process can be repeated to coat other portions of core 1110. Therefore, although LPCVD technology is used in some embodiments to provide a fully encapsulated structure, other film formation techniques can also be used depending on the specific application.

[0067] Reference Figure 11 A conductive layer 1114 is formed around the adhesion layer 1112. In one embodiment, because polycrystalline silicon exhibits poor adhesion to ceramic materials, the conductive layer 1114 is a polycrystalline silicon shell formed around the adhesion layer 1112. In embodiments where the conductive layer 1114 is polycrystalline silicon, the thickness of the polycrystalline silicon layer can be approximately... to For example, In some embodiments, the polysilicon layer may be formed as a shell to completely surround the adhesion layer 1112 (e.g., a TEOS oxide layer), thereby forming a fully encapsulated adhesion layer 1112, which may be formed using an LPCVD process. In other embodiments, as discussed below, a conductive material may be formed on a portion of the adhesion layer 1112, for example, on the lower half of the substrate structure. In some embodiments, the conductive material may be formed as a fully encapsulated layer and subsequently removed from one side of the substrate structure.

[0068] In one embodiment, the conductive layer 1114 may be a doped polycrystalline silicon layer to provide a highly conductive material, for example, boron doping to provide a p-type polycrystalline silicon layer. In some embodiments, the boron doping is 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 To provide high conductivity, other dopants with different dopant concentrations can be used (e.g., dopant concentrations of 1 × 10⁻⁶). 16 cm -3 Up to 5×10 18 cm -3 The range of phosphorus, arsenic, bismuth, etc., is used to provide N-type or P-type semiconductor materials suitable for use in conductive layer 1114. Various variations, modifications, and substitutions will be apparent to those skilled in the art.

[0069] The presence of the conductive layer 1114 is useful during the electrostatic adsorption of the engineered substrate onto a semiconductor processing tool (e.g., a tool with an electrostatic chuck (ESC or e-chuck)). The conductive layer enables rapid desorption after processing in the semiconductor processing tool. In embodiments of the invention, the conductive layer 1114 can achieve electrical contact with the chuck or capacitive coupling with the e-chuck during subsequent processing (including bonding). Therefore, embodiments of the invention provide a substrate structure that can be processed in a manner used with conventional silicon wafers. Various variations, modifications, and substitutions will be appreciated by those skilled in the art. Furthermore, combining a substrate structure with an electrostatic chuck can provide better deposition conditions for the subsequent formation of engineered and epitaxial layers, as well as subsequent device fabrication steps. For example, it can provide the desired thermal distribution, which, through subsequent layer formation, results in lower stress, more uniform deposition thickness, and better stoichiometric control.

[0070] A second adhesion layer 1116 (e.g., with a thickness of approximately) is formed around the conductive layer 1114. (TEOS oxide layer). In some embodiments, the second adhesion layer 1116 completely surrounds the conductive layer 1114 to form a fully encapsulated structure, and the second adhesion layer 1116 can be formed using an LPCVD process, a CVD process, or any other suitable deposition process (including spin-coating deposition on a dielectric).

[0071] A barrier layer 1118, such as a silicon nitride layer, is formed around the second adhesion layer 1116. In one embodiment, the barrier layer 1118 has a thickness of approximately [missing information]. to The barrier layer 1118 completely surrounds the second adhesion layer 1116 to form a fully encapsulated structure, and the barrier layer 1118 can be formed using an LPCVD process. In addition to the silicon nitride layer, amorphous materials (including silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum nitride (AlN), silicon carbide (SiC), etc.) can also be used as the barrier layer 1118. In some embodiments, the barrier layer 1118 consists of multiple sublayers constructed to form the barrier layer 1118. Therefore, the term "barrier layer" is not intended to mean a single layer or a single material, but rather encompasses one or more materials layered in a composite manner. Various variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0072] In some embodiments, the barrier layer 1118 (e.g., a silicon nitride layer) prevents elements present in the core (e.g., yttrium, yttrium oxide, oxygen, metallic impurities, other trace elements, etc.) from diffusing and / or venting into the environment of the semiconductor processing chamber where the engineered substrate may be present, for example, during high-temperature (e.g., 1000°C) epitaxial growth processes. By using the encapsulation layer described herein, ceramic materials, including polycrystalline aluminum nitride designed for non-cleanroom environments, can be used in semiconductor process flows and cleanroom environments.

[0073] Typically, the ceramic material used to form the core is fired at temperatures in the range of 1800°C. This process is expected to remove a significant number of impurities present in the ceramic material. These impurities may include yttrium (due to the use of yttrium as a sintering agent), calcium, and other elements and compounds. Subsequently, during epitaxial growth processes at lower temperatures in the range of 800°C to 1100°C, the subsequent diffusion of these impurities is expected to be negligible. However, contrary to conventional expectations, the inventors have determined that significant diffusion of elements through layers of the engineered substrate occurs even during epitaxial growth processes at temperatures far below the firing temperature of the ceramic material. Therefore, embodiments of the present invention integrate a barrier layer 1118 into the engineered substrate structure to prevent this undesirable diffusion.

[0074] Refer again Figure 11 A bonding layer 1120 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 1118 (e.g., the top surface of the barrier layer 1118), and subsequently a bonding substantial single-crystal layer 1125 (e.g., such as...) is deposited on top of it. Figure 11The bonding layer 1120 is used during the exfoliation of a silicon (111) layer (e.g., a single crystal silicon layer) as shown in FIG. 1 1. In some embodiments, the bonding layer 1120 can have a thickness of about 1.5 pm. In some embodiments, the bonding layer 1120 has a thickness of 20 nm or more for bonding-induced void migration. In some embodiments, the bonding layer has a thickness in the range of 0.75 pm to 1.5 pm.

[0075] The substantially single crystal layer 1125 (e.g., exfoliated silicon (111)) is suitable for use as a growth layer during an epitaxial growth process to form an epitaxial material. In some embodiments, the epitaxial material can include a GaN layer having a thickness of 2 pm to 10 pm, which can be used as one of a plurality of layers used in optoelectronic, RF, and power devices. In one embodiment, the substantially single crystal layer 1125 includes a single crystal silicon layer adhered to the bonding layer 1120 using a layer transfer process.

[0076] Additional description related to engineered substrate structures is provided in U.S. Patent Application No. 15 / 621,335, filed June 13, 2017, and U.S. Patent Application No. 15 / 621,235, filed June 13, 2017, the disclosures of which are hereby incorporated by reference in their entirety for all purposes.

[0077] Figure 12 A simplified cross-sectional schematic of an engineered substrate 1200 according to embodiments of the present application is shown. Figure 12 The engineered substrate 1200 shown in FIG. 12 is suitable for a variety of electronic and optical applications. The engineered substrate 1200 includes a core 1210 that can have a coefficient of thermal expansion (CTE) that is substantially matched to the CTE of an epitaxial material to be grown on the engineered substrate 1200. The epitaxial material 1230 is shown as optional in that it is not necessarily a component of the engineered substrate 1200, but is typically grown on the engineered substrate 1200.

[0078] For applications involving growth of gallium nitride (GaN)-based materials (including epitaxial layers of GaN-based layers), the core 1210 can be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AIN), which can include a binder material such as yttrium oxide. Other materials can also be used in the core 1210, including polycrystalline gallium nitride (GaN), polycrystalline aluminum gallium nitride (AlGaN), polycrystalline silicon carbide (SiC), polycrystalline zinc oxide (ZnO), polycrystalline gallium sesquioxide (Ga2O3), and the like.

[0079] The thickness of core 1210 can be approximately 100 μm to 1500 μm, for example, 725 μm. Core 1210 can be encapsulated in an adhesive layer 1212, which can be referred to as a shell or encapsulation shell. In one embodiment, the adhesive layer 1212 comprises a tetraethyl orthosilicate (TEOS) oxide layer, the thickness of which is approximately... (Å). In other embodiments, the thickness of the adhesion layer is varied, for example in... arrive The range varies. While TEOS oxide is used for the adhesion layer in some embodiments, other materials that provide adhesion between the subsequent deposited layer and the underlying layer or material (e.g., ceramic, particularly polycrystalline ceramic) may also be used according to embodiments of the invention. For example, silicon dioxide (SiO2) or other silicon oxides (SiO2) x O y The adhesive layer 1212 adheres well to the ceramic material and provides a suitable surface for subsequent deposition (e.g., deposition of a conductive material). In some embodiments, the adhesive layer 1212 completely surrounds the core 1210 to form a fully encapsulated core. The adhesive layer 1212 can be formed using an LPCVD (low-pressure chemical vapor deposition) process. The adhesive layer 1212 provides a surface on which subsequent layers adhere to form components of the engineered substrate 1200 structure.

[0080] According to embodiments of the present invention, in addition to using LPCVD processes, furnace-based processes, etc., to form the first adhesion layer 1212 of the package, other semiconductor processes, including CVD (chemical vapor deposition) processes or similar deposition processes, can also be used. As an example, a deposition process for coating a portion of the core 1210 can be used; the core 1210 can be flipped, and the deposition process can be repeated to coat other portions of the core. Therefore, although LPCVD technology is used in some embodiments to provide a fully encapsulated structure, other film formation techniques can also be used depending on the specific application.

[0081] A conductive layer 1214 is formed around the adhesion layer 1212. In one embodiment, because polycrystalline silicon exhibits poor adhesion to ceramic materials, the conductive layer 1214 is a polycrystalline silicon shell formed around the first adhesion layer 1212. In embodiments where the conductive layer 1214 is polycrystalline silicon, the thickness of the polycrystalline silicon layer can be approximately... to For example, In some embodiments, the polysilicon layer may be formed as a shell to completely surround the first adhesion layer 1212 (e.g., a TEOS oxide layer), thereby forming a fully encapsulated first adhesion layer 1212, which may be formed using an LPCVD process. In other embodiments, as discussed below, a conductive material may be formed on a portion of the adhesion layer, for example, on the lower half of the substrate structure. In some embodiments, the conductive material may be formed as a fully encapsulated layer and subsequently removed from one side of the substrate structure.

[0082] In one embodiment, the conductive layer 1214 may be a doped polycrystalline silicon layer to provide a highly conductive material, for example, boron doping to provide a p-type polycrystalline silicon layer. In some embodiments, the boron doping is 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 To provide high conductivity, other dopants with different dopant concentrations can be used (e.g., dopant concentrations of 1 × 10⁻⁶). 16 cm -3 Up to 5×10 18 cm -3 The range of phosphorus, arsenic, bismuth, etc., is used to provide N-type or P-type semiconductor materials suitable for use in conductive layer 1214. Various variations, modifications, and substitutions will be apparent to those skilled in the art.

[0083] The presence of the conductive layer 1214 is useful during the electrostatic adsorption of the engineered substrate 1200 onto a semiconductor processing tool (e.g., a tool with an electrostatic discharge chuck (ESC)). The conductive layer 1214 enables rapid desorption after processing in the semiconductor processing tool. Therefore, embodiments of the present invention provide a substrate structure that can be processed in a manner used with conventional silicon wafers. Various variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0084] A second adhesion layer 1216 (e.g., with a thickness of approximately) is formed around the conductive layer 1214. (TEOS oxide layer). In some embodiments, the second adhesion layer 1216 completely surrounds the conductive layer 1214 to form a fully encapsulated structure. The second adhesion layer 1216 can be formed using LPCVD, CVD, or any other suitable deposition process (including spin-coating deposition on a dielectric).

[0085] A barrier layer 1218, such as a silicon nitride layer, is formed around the second adhesion layer 1216. In one embodiment, the barrier layer 1218 has a thickness of approximately [missing information]. to silicon nitride layer. In some embodiments, the barrier layer 1218 completely surrounds the second adhesion layer 1216 to form a fully encapsulated structure, and can be formed using an LPCVD process. In addition to silicon nitride layers, amorphous materials (including silicon carbon nitride (SiCN), silicon oxynitride (SiON), aluminum nitride (AIN), silicon carbide (SiC), etc.) can also be used as the barrier layer. In some embodiments, the barrier layer is composed of multiple sub-layers that are built to form the barrier layer. Thus, the term "barrier layer" is not intended to mean a single layer or a single material, but rather encompasses one or more materials layered in a composite manner. Those of ordinary skill in the art can appreciate a variety of variations, modifications, and alternatives.

[0086] In some embodiments, the barrier layer 1218 (e.g., a silicon nitride layer) prevents diffusion and / or outgassing of elements present in the core 1210 into the environment of a semiconductor processing chamber in which the engineered substrate 1200 can be present (e.g., during high temperature (e.g., 1000°C) epitaxial growth processes). The elements present in the core 1210 can include, for example, yttrium oxide, oxygen, metallic impurities, other trace elements, etc. Diffusion of elements from the core 1210 can result in unintentional doping in the engineered layers 1220 / 1222. Outgassing of elements from the core 1210 can move through the chamber and be absorbed elsewhere on the wafer, causing impurities in the engineered layers 1220 / 1222 and the epitaxial material 1230. By using the encapsulation layers described herein, ceramic materials can be used in semiconductor process flows and clean chamber environments that would otherwise include polycrystalline aluminum nitride designed for non-clean chamber environments.

[0087] A bonding layer 1220 (e.g., a silicon oxide layer) is deposited on a portion of the barrier layer 1218 (e.g., the top surface of the barrier layer) and subsequently used during the bonding single crystal layer 1222. In some embodiments, the bonding layer 1220 can have a thickness of approximately 1.5 μιη. The single crystal layer 1222 can include, for example, silicon (Si), silicon carbide (SiC), sapphire, gallium nitride (GaN), aluminum nitride (AIN), silicon germanium (SiGe), germanium (Ge), diamond, gallium trioxide (Ga2O3), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), indium nitride (InN), and / or zinc oxide (ZnO). In some embodiments, the single crystal layer 1222 can have a thickness of 0 to 0.5 μιη. The single crystal layer 1222 is suitable for use as a growth layer during an epitaxial growth process for forming an epitaxial material 1230. The crystalline layer of the epitaxial material 1230 is an extension of the underlying semiconductor lattice associated with the single crystal layer 1222. The unique CTE matching properties of the engineered substrate 1200 enable the growth of thicker epitaxial material 1230 than is possible with prior art growth. In some embodiments, the epitaxial material 1230 includes a gallium nitride layer having a thickness of 2 μιη to 10 μιη, which can be used as one of a plurality of layers used in optoelectronic devices, power devices, and the like. In other embodiments, the epitaxial material 1230 has a thickness greater than 10 μιη and can be an epitaxial structure including a plurality of epitaxial layers. In one embodiment, the bonding layer 1220 includes a single crystal silicon layer that is attached to the silicon oxide barrier layer 1218 using a layer transfer process.

[0088] Figure 13 A simplified schematic diagram of an engineered substrate structure according to embodiments of the present application is shown. Figure 13 The engineered substrate 1300 shown in FIG. 13 is suitable for a variety of electronic and optical applications. The engineered substrate includes a core 1310 having a coefficient of thermal expansion (CTE) that can be substantially matched to the CTE of an epitaxial material 1230 to be grown on the engineered substrate 1300. The epitaxial material 1230 is shown as optional in that it is not necessarily a component of the engineered substrate structure, but is typically grown on the engineered substrate structure.

[0089] For applications involving the growth of gallium nitride (GaN)-based materials (including epitaxial layers of GaN-based layers), the core 1310 can be a polycrystalline ceramic material, such as polycrystalline aluminum nitride (AlN). The thickness of the core 1010 can be approximately 100 μm to 1500 μm, for example, 725 μm. The core 1310 can be encapsulated in a first adhesive layer 1312, which can be referred to as a shell or encapsulation shell. In this embodiment, the first adhesive layer 1312 completely encapsulates the core, but this is not essential to the invention, as shown in the reference... Figure 14 That will be discussed in more detail elsewhere.

[0090] In one embodiment, the first adhesion layer 1312 includes a thickness of approximately (Å) a tetraethyl orthosilicate (TEOS) layer. In other embodiments, the thickness of the first adhesion layer 1312 is varied, for example in... arrive The range varies. While TEOS is used for the adhesion layer in some embodiments, other materials that provide adhesion between subsequent deposited layers and underlying layers or materials may also be used according to embodiments of the invention. For example, silicon dioxide (SiO2), silicon oxynitride (SiON), etc., adhere well to ceramic materials and provide a suitable surface for subsequent deposition (e.g., deposition of conductive materials). In some embodiments, the first adhesion layer 1312 completely surrounds the core 1310 to form a fully encapsulated core, and the first adhesion layer 1312 may be formed using an LPCVD process. The first adhesion layer 1312 provides a surface on which subsequent layers adhere to form components of an engineered substrate structure.

[0091] In addition to using LPCVD processes, furnace-based processes, etc., to form the adhesive layer 1312 of the package, other semiconductor processes can also be used according to embodiments of the present invention. As an example, a deposition process for coating a portion of the core 1310, such as CVD (chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), etc., can be used, wherein the core 1310 can be flipped and the deposition process can be repeated to coat other portions of the core.

[0092] A conductive layer 1314 is formed on at least a portion of the first adhesion layer 1312. In one embodiment, the conductive layer 1314 comprises polysilicon, which is formed on the lower portion (e.g., the lower half or back side) of the core / adhesion layer structure by a deposition process. In embodiments where the conductive layer 1314 is polysilicon, the thickness of the polysilicon layer can be approximately several thousand angstroms, for example... In some embodiments, the polycrystalline silicon layer may be formed using an LPCVD process.

[0093] In one embodiment, the conductive layer 1314 may be a doped polycrystalline silicon layer to provide a highly conductive material; for example, the conductive layer 1314 may be doped with boron to provide a p-type polycrystalline silicon layer. In some embodiments, boron doping is at a density of 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 The conductive layer 1314 provides a horizontal range to offer high conductivity. The presence of the conductive layer 1314 is useful during the electrostatic adsorption of the engineered substrate onto a semiconductor processing tool (e.g., a tool with an electrostatic chuck (ESC)). The conductive layer 1314 enables rapid desorption after processing. Therefore, embodiments of the present invention provide a substrate structure that can be processed in a manner used with conventional silicon wafers. Various variations, modifications, and substitutions will be appreciated by those skilled in the art.

[0094] A second adhesion layer 1316 (e.g., a second TEOS layer) is formed around the conductive layer 1314 (e.g., a polysilicon layer). The thickness of the second adhesion layer 1316 is approximately... In some embodiments, the second adhesive layer 1316 may completely surround the conductive layer 1314 and the first adhesive layer 1312 to form a fully encapsulated structure, and the second adhesive layer 1316 may be formed using an LPCVD process. In other embodiments, the second adhesive layer 1316 only partially surrounds the conductive layer 1314, for example, terminating at the location shown in plane 1317, which may be aligned with the top surface of the conductive layer 1314. In this example, the top surface of the conductive layer 1314 will contact a portion of the barrier layer 1318. Various variations, modifications, and substitutions will be apparent to those skilled in the art.

[0095] A barrier layer 1318 (e.g., a silicon nitride layer) is formed around the second adhesion layer 1316. In some embodiments, the thickness of the barrier layer 1318 is approximately to In some embodiments, the barrier layer 1318 completely surrounds the second adhesive layer 1316 to form a fully encapsulated structure, and the barrier layer 1318 can be formed using an LPCVD process.

[0096] In some embodiments, the use of the silicon nitride barrier layer prevents diffusion and / or outgassing of elements present in the core 1310 (e.g., yttrium oxide, oxygen, metal impurities, other trace elements, etc.) into the environment of a semiconductor processing chamber in which the engineered substrate can be present, for example, during high temperature (e.g., 1000°C) epitaxial growth processes. By using the encapsulation layers described herein, ceramic materials can be used in semiconductor process flows and clean chamber environments that include polycrystalline aluminum nitride (AIN) that are designed for non-clean chamber environments.

[0097] Figure 14 A simplified schematic of an engineered substrate structure showing another embodiment of the present application is shown in FIG. 14. In the embodiment shown, a first adhesion layer 1412 is formed on at least a portion of the core 1410, but does not encapsulate the core 1410. In this implementation, the first adhesion layer 1412 is formed on the lower surface of the core 1410 (the backside of the core 1410) in order to improve adhesion of a subsequently formed conductive layer 1414 (as described more fully below). Although the adhesion layer 1412 is shown in FIG. 14 only on the lower surface of the core 1410, it should be understood that deposition of adhesion layer material on other portions of the core 1410 would not adversely affect the performance of the engineered substrate structure, and such material can be present in various embodiments. Those of ordinary skill in the art will recognize a variety of variations, modifications, and alternatives. Figure 14 In the embodiment shown, the first adhesion layer 1412 is formed on at least a portion of the core 1410, but does not encapsulate the core 1410. In this implementation, the first adhesion layer 1412 is formed on the lower surface of the core 1410 (the backside of the core 1410) in order to improve adhesion of a subsequently formed conductive layer 1414 (as described more fully below). Although the adhesion layer 1412 is shown in FIG. 14 only on the lower surface of the core 1410, it should be understood that deposition of adhesion layer material on other portions of the core 1410 would not adversely affect the performance of the engineered substrate structure, and such material can be present in various embodiments. Those of ordinary skill in the art will recognize a variety of variations, modifications, and alternatives. Figure 14 In the embodiment shown, the first adhesion layer 1412 is formed on at least a portion of the core 1410, but does not encapsulate the core 1410. In this implementation, the first adhesion layer 1412 is formed on the lower surface of the core 1410 (the backside of the core 1410) in order to improve adhesion of a subsequently formed conductive layer 1414 (as described more fully below). Although the adhesion layer 1412 is shown in FIG. 14 only on the lower surface of the core 1410, it should be understood that deposition of adhesion layer material on other portions of the core 1410 would not adversely affect the performance of the engineered substrate structure, and such material can be present in various embodiments. Those of ordinary skill in the art will recognize a variety of variations, modifications, and alternatives.

[0098] The conductive layer 1414 does not encapsulate the first adhesion layer 1412 and the core 1410, but is substantially aligned with the first adhesion layer 1412. Although the conductive layer 1414 is shown as extending along the bottom or backside of the first adhesion layer 1412 and upwardly along a portion of the sides of the first adhesion layer 1412, extending along the vertical sides is not required by the present application. Thus, embodiments can use deposition on one side of the substrate structure, masking of one side of the substrate structure, etc. The conductive layer 1414 can be formed on a portion of one side (e.g., the bottom / backside) of the first adhesion layer 1412. The conductive layer 1414 provides an electrical conductor on one side of the engineered substrate structure that has advantages in radio frequency (RF) and high power applications. The conductive layer 1414 can include doped polysilicon as discussed with respect to the conductive layer 1314 in FIG. 13. Figure 13

[0099] ​To improve adhesion of the barrier layer 1418 to the underlying material, a portion of the core 1410, a portion of the first adhesion layer 1412, and the conductive layer 1414 are covered by a second adhesion layer 1416. As discussed above, the barrier layer 1418 forms an encapsulation structure to prevent diffusion from the underlying layers.

[0100] In addition to a semiconductor-based conductive layer, in other embodiments, the conductive layer 1414 is a metal layer, such as titanium, and the like.

[0101] Referring again to Figure 14 According to this embodiment, one or more layers can be removed. For example, the layer 1412 and the layer 1414 can be removed, leaving only the single adhesion shell 1416 and the barrier layer 1418. In other embodiments, only the layer 1414 can be removed. In this embodiment, the layer 1412 can also balance the stress and wafer bowing caused by the layer 1220 deposited on top of the layer 1418. The construction of a substrate structure with an insulating layer on the top side of the core 1410 (e.g., only an insulating layer between the core 1410 and the layer 1220) can provide benefits for power / RF applications where a highly insulating substrate is desired.

[0102] In another embodiment, the barrier layer 1418 can encapsulate the core 1410 directly, followed by the conductive layer 1414 and the subsequent adhesion layer 1416. In this embodiment, the layer 1220 can be deposited directly from the top side on the adhesion layer 1416. In yet another embodiment, the adhesion layer 1416 can be deposited on the core 1410, followed by the barrier layer 1418, and then followed by the conductive layer 1414 and another adhesion layer 1412.

[0103] Figure 15 A simplified flowchart of a method 1500 of fabricating an engineered substrate according to an embodiment of the present application is shown. The method 1500 can be used to fabricate a substrate whose CTE matches that of one or more epitaxial layers grown on the substrate. The method 1500 includes forming a support structure by providing a polycrystalline ceramic core (1510), encapsulating the polycrystalline ceramic core in a first adhesion layer forming a shell (e.g., a tetraethyl orthosilicate (TEOS) oxide shell) (1512), and encapsulating the first adhesion layer in a conductive shell (e.g., a polysilicon shell) (1514). The first adhesion layer can be formed as a single layer of TEOS oxide. The conductive shell can be formed as a single layer of polysilicon.

[0104] The method 1500 further includes: encapsulating the conductive shell (1516) in a second adhesive layer (e.g., a second TEOS oxide shell); and encapsulating the second adhesive layer (1518) in a barrier shell. The second adhesive layer may be formed as a monolayer TEOS oxide. The barrier shell may be formed as a monolayer silicon nitride.

[0105] Once the support structure is formed through processes 1510 to 1518, method 1500 further includes: bonding a bonding layer (e.g., a silicon oxide layer) to the support structure (1520); and bonding a substantially single-crystal layer (e.g., a single-crystal silicon layer) to the silicon oxide layer (1522). According to embodiments of the invention, other substantially single-crystal layers may also be used, including silicon carbide, sapphire, gallium nitride, aluminum nitride, germanium silicon, germanium, diamond, gallium trioxide, zinc oxide, etc. The bonding of the bonding layer may include deposition of a bonding material followed by planarization as described herein. As in one embodiment described below, a layer transfer process is used to bond the substantially single-crystal layer (e.g., a single-crystal silicon layer) to the bonding layer, in which the layer is a single-crystal silicon layer transferred from a silicon wafer.

[0106] Reference Figure 12 The bonding layer 1220 can be formed by depositing a thick oxide layer (e.g., 4 μm thick) and then thinning the oxide layer to approximately 1.5 μm using a chemical mechanical polishing (CMP) process. The thick initial oxide layer is used to fill voids and surface features present in the support structure, which may exist after polycrystalline core fabrication and during the formation of the bonding layer. Figure 12 The encapsulation layer shown continues to exist. The oxide layer can also be used as a dielectric layer for the device. The CMP process provides a substantially flat surface free of voids, particles, and other features, which can be used during wafer transfer to bond the single-crystal layer 1212 (e.g., a single-crystal silicon layer) to the bonding layer 1220. It should be understood that the bonding layer does not necessarily have the characteristics of an atomically flat surface, but should provide a substantially flat surface that will support the bonding of the single-crystal layer (e.g., a single-crystal silicon layer) with the desired reliability.

[0107] A layer transfer process is used to bond the single crystal layer 1222 (e.g., a single crystal silicon layer) to the bonding layer 1220. In some embodiments, a silicon wafer including the substantially single crystal layer 1222 (e.g., a single crystal silicon layer) is implanted to form a cleave plane. In this embodiment, after wafer bonding, the silicon substrate can be removed along with a portion of the single crystal silicon layer underneath the cleave plane, leaving a peeled single crystal silicon layer. The thickness of the single crystal layer 1222 can be varied to meet the specifications of various applications. In addition, the crystal orientation of the single crystal layer 1222 can be varied to meet the specifications of an application. Further, the doping level and profile of the single crystal layer can be varied to meet the specifications of a particular application. In some embodiments, the implantation depth can be adjusted to be greater than the final thickness of the single crystal layer 1222 desired. The additional thickness allows for removal of a damaged thin portion of the transferred substantially single crystal layer, leaving an undamaged portion having the desired final thickness. In some embodiments, the surface roughness can be modified for high quality epitaxial growth. Those of ordinary skill in the art will recognize a variety of variations, modifications, and alternatives.

[0108] In some embodiments, the single crystal layer 1222 can be thick enough to provide a high quality lattice template for the growth of one or more subsequent epitaxial layers, but thin enough to be compliant. The single crystal layer 1222 can be considered "compliant" when it is relatively thin such that its physical properties are less constrained, and can be similar to the material surrounding the single crystal layer, with a lesser tendency to create crystal defects. The compliance of the single crystal layer 1222 can be inversely proportional to the thickness of the single crystal layer 1222. Higher compliance can result in lower defect densities in epitaxial layers grown on the template, and can enable thicker epitaxial layer growth. In some embodiments, the thickness of the single crystal layer 1222 can be increased by epitaxial growth of silicon on the peeled silicon layer.

[0109] In some embodiments, the final thickness of the single crystal layer 1222 can be adjusted by thermal oxidation of the top of the peeled silicon layer, followed by oxide layer peeling with hydrofluoric acid (HF). For example, a peeled silicon layer with an initial thickness of 0.5 μm can be thermally oxidized to create a silicon dioxide layer with a thickness of approximately 420 nm. After the grown thermal oxide is removed, the remaining silicon in the transfer layer can have a thickness of approximately 53 nm. During thermal oxidation, implanted hydrogen can migrate to the surface. Thus, subsequent peeling of the oxide layer can remove some damage. In addition, thermal oxidation is typically performed at temperatures of 1000 °C or higher. The elevated temperature can also repair lattice damage.

[0110] The silicon oxide layer formed on top of the single crystal layer during thermal oxidation can be removed with HF acid etching. By adjusting the temperature and concentration of the HF solution and the stoichiometry and density of the silicon oxide, the etch selectivity of HF acid between silicon oxide and silicon (SiO2:Si) can be adjusted. Etch selectivity refers to the etch rate of one material relative to other materials. For (SiO2:Si), the selectivity of the HF solution can range from about 10: 1 to about 100: 1. A high etch selectivity can reduce the surface roughness from the initial surface roughness by a similar factor. However, the surface roughness of the resulting single crystal layer 1222 can still be greater than the desired surface roughness. For example, the root mean square (RMS) surface roughness of a bulk silicon (111) surface, as determined by a 2 μm x 2 μm atomic force microscope (AFM) scan, can be less than 0.1 nm prior to additional processing. In some embodiments, the desired surface roughness for epitaxial growth of gallium nitride material on silicon (111) can be, for example, less than 1 nm, less than 0.5 nm, or less than 0.2 nm in a 30 μm x 30 μm AFM scan area.

[0111] After thermal oxidation and oxide layer removal, if the surface roughness of the single crystal layer 1222 exceeds the desired surface roughness, additional surface smoothing processing will be performed. There are several methods of smoothing silicon surfaces. These methods can include hydrogen annealing, laser fine tuning, plasma smoothing, and touch polishing (e.g., CMP). These methods can involve preferential attack of high aspect ratio surface peaks. Thus, high aspect ratio features on the surface can be removed faster than low aspect ratio features, resulting in a smoother surface.

[0112] It should be understood that, Figure 15 The specific steps shown in FIG. 16 provide a particular method of manufacturing an engineered substrate according to an embodiment of the present application. Other sequences of steps can also be performed according to alternative embodiments. For example, alternative embodiments of the present application can perform the steps described above in a different order. Moreover, Figure 15 The individual steps shown in FIG. 16 can include multiple sub-steps, which can be performed in various orders that are suitable for the individual steps. In addition, additional steps can be added or removed depending on the particular application. Those of ordinary skill in the art can recognize a variety of changes, modifications, and alternatives.

[0113] Figure 16 A simplified flowchart of a method 1600 for fabricating a multilayer device on an engineered substrate according to some embodiments of the present application is shown. The engineered substrate has a substrate coefficient of thermal expansion. Referring to Figure 1 and Figure 2The engineered substrate 102 can include a ceramic substrate 110, a thin silicon (Si) layer 120 or a thin silicon germanium (SiGe) layer 220 formed on the ceramic substrate 110.

[0114] Referring to Figure 1 , Figure 2 and Figure 16 , the method 1600 can include growing a buffer layer 130 on the engineered substrate 102 (1602) and growing a first epitaxial layer 142 coupled to the buffer layer 130 (1604). The first epitaxial layer 142 can have an epitaxial coefficient of thermal expansion substantially the same as a thermal expansion coefficient of the substrate. In some embodiments, the first epitaxial layer 142 can include doped gallium nitride (GaN). Referring to Figure 6 In some other embodiments, the first epitaxial layer 142 can include aluminum gallium nitride (AlGaN).

[0115] The method 1600 can also include growing a second epitaxial layer 144 including undoped GaN coupled to the first epitaxial layer 142 and growing a third epitaxial layer 160 coupled to the second epitaxial layer 144. An interface between the second epitaxial layer 144 and the third epitaxial layer 160 can form a conductive channel 150 of a high electron mobility transistor (HEMT). In some embodiments, the third epitaxial layer 160 can include aluminum gallium nitride (AlGaN) or indium aluminum nitride (InAlN).

[0116] Referring to Figure 3 In some embodiments, the method 1600 can also include forming an electrical contact 310 through the engineered substrate 102 electrically coupled to the substantially single crystalline silicon layer 120. Referring to Figure 4 In some other embodiments, the method 1600 can also include growing a conductive epitaxial layer 420 disposed between the buffer layer 130 and the first epitaxial layer 142 and forming an electrical contact 410 through the first epitaxial layer 142 electrically coupled to the conductive epitaxial layer 420. Referring to Figure 5 In some embodiments, the method 1600 can also include forming a local monolayer 510 of silicon nitride (Si3N4) disposed between the buffer layer 130 and the conductive epitaxial layer 420.

[0117] It should be appreciated that Figure 16 The specific steps shown in FIG. 16 provide a particular method of manufacturing an engineered substrate according to an embodiment of the present application. Other sequences of steps can also be performed according to alternative embodiments. For example, alternative embodiments of the present application can perform the steps outlined above in a different order. Moreover, Figure 16The individual steps shown in the flowcharts of FIGS. 1-3 can include multiple sub-steps, which can be performed in various orders that are suitable for the individual steps. Additionally, additional steps can be added or removed depending on the particular application. Those of ordinary skill in the art will recognize a variety of changes, modifications, and alternatives.

[0118] Figure 17 FIG. 17 shows a simplified flowchart of a method 1700 for fabricating a multilayer device on an engineered substrate according to some other embodiments of the present application. The engineered substrate has a substrate thermal expansion coefficient. Referring to Figure 7 , the engineered substrate 102 can include a ceramic substrate 110 on which a thin silicon (Si) layer 120 is formed.

[0119] Referring to Figure 7 and Figure 17 , the method 1700 can include forming a buffer layer 130 on the engineered substrate 102 (1702) and growing one or more epitaxial layers 740 on the buffer layer 130 (1704). At least one of the one or more epitaxial layers 740 is characterized as having an epitaxial thermal expansion coefficient that is substantially the same as the substrate thermal expansion coefficient. In some embodiments, the one or more epitaxial layers 740 can include a superlattice of alternating layers of undoped GaN and doped GaN. The doped GaN can include carbon-doped GaN (C-GaN) or iron-doped GaN (Fe-GaN). The buffer layer 130 can include at least one of AIN, AlGaN, or AIN / AlGaN.

[0120] The method 1700 can also include growing an undoped GaN layer 144 coupled to the one or more epitaxial layers 740 and growing a first epitaxial layer 160 including aluminum gallium nitride (AlGaN) or indium aluminum nitride (InAlN) coupled to the undoped GaN layer 144. An interface between the undoped GaN layer 144 and the first epitaxial layer 160 can form a conductive channel 150 of a high electron mobility transistor (HEMT).

[0121] It will be appreciated that, Figure 17 The specific steps shown in the flowcharts of FIGS. 1-3 provide particular methods of fabricating an engineered substrate according to embodiments of the present application. Other sequences of steps can also be performed according to alternative embodiments. For example, alternative embodiments of the present application can perform the steps described above in a different order. Moreover, Figure 17 The individual steps shown in the flowcharts of FIGS. 1-3 can include multiple sub-steps, which can be performed in various orders that are suitable for the individual steps. Additionally, additional steps can be added or removed depending on the particular application. Those of ordinary skill in the art will recognize a variety of changes, modifications, and alternatives.

[0122] Figure 18 A simplified flowchart of a method 1800 for fabricating a multilayer device on an engineered substrate according to some other embodiments of the present application is shown. The engineered substrate has a substrate coefficient of thermal expansion. Referring to Figure 8 , the engineered substrate 102 can include a ceramic substrate 110 on which a thin silicon (Si) layer 120 is formed.

[0123] Referring to Figure 8 and Figure 18 , the method 1800 can include forming a buffer layer 130 on the engineered substrate 102 (1802) and growing a first epitaxial layer 840 coupled to the buffer layer 130 (1804). The first epitaxial layer 840 can have an epitaxial coefficient of thermal expansion that is substantially the same as the substrate coefficient of thermal expansion. In some embodiments, the first epitaxial layer 840 can include unintentionally doped GaN (uGaN). In some other embodiments, the first epitaxial layer 840 can include alternating layers of undoped GaN and doped GaN. In some embodiments, the doped GaN can include carbon-doped GaN (C-GaN) or iron-doped GaN (Fe-GaN).

[0124] The method 1800 can also include growing an aluminum gallium nitride (AlGaN) back barrier layer 810 coupled to the first epitaxial layer 840 (1806), growing an undoped gallium nitride (GaN) layer 144 coupled to the AlGaN back barrier layer 810 (1808), and growing a barrier layer 160 coupled to the undoped GaN layer 144 (1810). In some embodiments, the aluminum mole fraction of the AlGaN back barrier layer 810 is in a range from about 3% to about 15%. According to some embodiments, the barrier layer 160 can include AlGaN or InGaN.

[0125] It should be understood that Figure 18 the specific steps shown in the flowchart of FIG. 18 provide a particular method of fabricating an engineered substrate according to embodiments of the present application. Other sequences of steps can also be performed according to alternative embodiments. For example, alternative embodiments of the present application can perform the steps outlined above in a different order. Moreover, Figure 18 the individual steps shown in the flowchart of FIG. 18 can include multiple sub-steps that can be performed in various sequences as appropriate to the individual step. Furthermore, additional steps can be added or removed depending on the particular applications. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.

[0126] While some embodiments have been discussed in terms of layers, the term "layer" should be understood such that a layer can include a plurality of sub-layers that build up to form the layer of interest. Thus, the term "layer" is not intended to mean a single layer composed of a single material, but rather encompasses one or more materials layered in a composite manner to form the desired structure. Those of ordinary skill in the art can appreciate a variety of variations, modifications, and alternatives.

[0127] It is also to be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.

Claims

1. A method of fabricating a multilayer high electron mobility transistor (HEMT) device on an engineered substrate having a substrate coefficient of thermal expansion, the method comprising: providing an engineered substrate, the engineered substrate comprising: a polycrystalline substrate; a diffusion barrier encapsulating the polycrystalline substrate; a bonding layer coupled to the diffusion barrier; and a monocrystalline silicon layer coupled to the bonding layer; growing a buffer layer on the monocrystalline silicon layer; growing a first epitaxial layer coupled to the buffer layer, wherein the first epitaxial layer is characterized as having an epitaxial coefficient of thermal expansion that is substantially the same as the substrate coefficient of thermal expansion; growing an undoped gallium nitride (GaN) layer coupled to the first epitaxial layer; and growing a barrier layer coupled to the undoped gallium nitride (GaN) layer.

2. The method of claim 1, wherein, The first epitaxial layer comprises doped gallium nitride.

3. The method of claim 1, wherein, The first epitaxial layer comprises alternating layers of undoped gallium nitride and doped gallium nitride.

4. The method of claim 3, wherein, The doped gallium nitride comprises carbon-doped gallium nitride (C-GaN) or iron-doped gallium nitride (Fe-GaN).

5. The method of claim 1, further comprising: growing an aluminum gallium nitride (AlGaN) back-barrier layer coupled to the first epitaxial layer; wherein the undoped gallium nitride layer is coupled to the first epitaxial layer via the aluminum gallium nitride (AlGaN) back-barrier layer.

6. The method of claim 5, wherein, An aluminum mole fraction of the aluminum gallium nitride (AlGaN) back-barrier layer ranges from 3% to 15%.

7. The method of claim 1, wherein, The first epitaxial layer comprises at least one of a gallium nitride layer or an aluminum gallium nitride layer.

8. A multilayer high electron mobility transistor (HEMT) device formed on an engineered substrate having a substrate coefficient of thermal expansion, the multilayer high electron mobility transistor (HEMT) device comprising: an engineered substrate, the engineered substrate comprising: a polycrystalline substrate; a diffusion barrier encapsulating the polycrystalline substrate; a bonding layer coupled to the diffusion barrier; and a monocrystalline silicon layer coupled to the bonding layer; a buffer layer coupled to the monocrystalline silicon layer; a first epitaxial layer coupled to the buffer layer, wherein the first epitaxial layer is characterized as having an epitaxial coefficient of thermal expansion that is substantially the same as the substrate coefficient of thermal expansion; an undoped gallium nitride (GaN) layer coupled to the first epitaxial layer; and a barrier layer coupled to the undoped gallium nitride (GaN) layer.

9. The multi-layer high electron mobility transistor (HEMT) device of claim 8, wherein, The first epitaxial layer comprises doped gallium nitride.

10. The multi-layer high electron mobility transistor (HEMT) device of claim 8, wherein, The first epitaxial layer comprises alternating layers of undoped gallium nitride and doped gallium nitride.

11. The multilayer high electron mobility transistor (HEMT) device of claim 10, wherein, The doped gallium nitride comprises carbon-doped gallium nitride (C-GaN) or iron-doped gallium nitride (Fe-GaN).

12. The multilayer high electron mobility transistor (HEMT) device of claim 8, further comprising an aluminum gallium nitride (AlGaN) back-barrier layer coupled to the first epitaxial layer, wherein the undoped gallium nitride layer is coupled to the first epitaxial layer via the aluminum gallium nitride (AlGaN) back-barrier layer.

13. The multilayer high electron mobility transistor (HEMT) device of claim 12, wherein, An aluminum mole fraction of the aluminum gallium nitride (AlGaN) back-barrier layer ranges from 3% to 15%.

14. The multi-layer high electron mobility transistor (HEMT) device of claim 9, wherein, The doped gallium nitride comprises unintentionally doped gallium nitride.

15. The multilayer high electron mobility transistor (HEMT) device of claim 8, wherein, The first epitaxial layer comprises carbon-doped gallium nitride (C-GaN) or iron-doped gallium nitride (Fe-GaN).

16. The multilayer high electron mobility transistor (HEMT) device of claim 8, wherein, The first epitaxial layer comprises at least one of a gallium nitride (GaN) layer or an aluminum gallium nitride (AlGaN) layer.

17. The multilayer high electron mobility transistor (HEMT) device of claim 16, wherein, The aluminum gallium nitride AlGaN layer includes a carbon-doped aluminum gallium nitride C-AlGaN or a iron-doped aluminum gallium nitride Fe-AlGaN.

18. The multilayer high electron mobility transistor (HEMT) device of claim 8, wherein, The buffer layer includes at least one of AlN, AlGaN, or AlN / AlGaN.

19. An epitaxial semiconductor structure, comprising: an engineered substrate having a substrate coefficient of thermal expansion, the engineered substrate including: a polycrystalline ceramic core; a diffusion barrier layer encapsulating the polycrystalline ceramic core; a bonding layer coupled to the diffusion barrier layer; and a single crystalline silicon layer coupled to the bonding layer; a buffer layer coupled to the single crystalline silicon layer; a silicon nitride local layer coupled to the buffer layer; and an epitaxial layer formed on the silicon nitride local layer, wherein the epitaxial layer is characterized as having an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

20. The epitaxial semiconductor structure of claim 19, wherein, The silicon nitride local layer includes a local monolayer of silicon nitride.

21. An epitaxial semiconductor structure, comprising: an engineered substrate characterized as having a substrate coefficient of thermal expansion, and the engineered substrate including: a polycrystalline ceramic core; a diffusion barrier layer encapsulating the polycrystalline ceramic core; a bonding layer coupled to the diffusion barrier layer; and a single crystalline silicon layer coupled to the bonding layer; a buffer layer coupled to the single crystalline silicon layer; a silicon nitride local layer coupled to the buffer layer; and a gallium nitride GaN epitaxial layer formed on the silicon nitride local layer, wherein the gallium nitride GaN epitaxial layer is characterized as having an epitaxial coefficient of thermal expansion substantially equal to the substrate coefficient of thermal expansion.

22. The epitaxial semiconductor structure of claim 21, wherein the silicon nitride local layer includes a local monolayer of silicon nitride.

23. The epitaxial semiconductor structure of claim 21, further comprising an additional silicon nitride local layer coupled to the gallium nitride GaN epitaxial layer.

24. The epitaxial semiconductor structure of claim 21, further comprising one or more doped gallium nitride layers coupled to the gallium nitride GaN epitaxial layer.

25. The epitaxial semiconductor structure of claim 21, wherein, The silicon nitride local layer includes a plurality of local monolayers of silicon nitride.

25. The epitaxial semiconductor structure of claim 21, wherein the engineered substrate includes a plurality of polycrystalline ceramic cores.

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