Image sensor and method of forming an image sensor

Abstract

An image sensor and a method of forming the same, the structure comprising: a substrate, the substrate comprising a first surface; a capacitor structure on the first surface of the substrate, the capacitor structure comprising a first electrode layer, a dielectric layer on the first electrode layer, and a second electrode layer on the dielectric layer; a first plug on the first electrode layer; a second plug on the second electrode layer; a first top metal on the first plug, the first top metal having a width along a direction parallel to the surface of the substrate that is more than twice a width of the first plug along the direction parallel to the surface of the substrate, the first top metal electrically connected to a pixel region; a second top metal on the second plug, the second top metal having a width along a direction parallel to the surface of the substrate that is more than twice a width of the second plug along the direction parallel to the surface of the substrate, the second top metal electrically connected to an external voltage. The first plug and the second plug can occupy a smaller area to meet the needs of small size image sensors.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to an image sensor and a forming method of the image sensor. BACKGROUND

[0002] A CMOS image sensor (CIS) mainly forms an image by collecting photo-generated carriers to output signals, so the collection of photo-generated carriers has a decisive influence on the quality of the image. A traditional CMOS image sensor uses an FD junction capacitor to store photo-generated carriers collected by a photodiode, but the FD junction capacitor is greatly affected by the working current voltage of the transistor, has obvious parasitic effects, and has a large output signal noise.

[0003] A MIM (Metal-Insultor-Metal, MIM) capacitor has the characteristics of zero depletion and high conductivity, and the MIM capacitor is applied in a chip to replace a junction capacitor, which can effectively reduce the contact resistance and parasitic capacitance, and optimize the signal-to-noise ratio to reduce the effect of noise output.

[0004] However, with the continuous reduction in the size of the CMOS image sensor, the application of the MIM capacitor in the image sensor also faces challenges. SUMMARY

[0005] The technical problem solved by the present application is to provide an image sensor and a forming method of the image sensor to improve the performance of the image sensor.

[0006] To solve the above technical problems, the technical scheme of the present application provides an image sensor, comprising: a substrate, the substrate comprising a first surface, the substrate comprising a pixel region; a capacitor structure on the first surface of the substrate, the capacitor structure comprising a first electrode layer, a dielectric layer on the first electrode layer, and a second electrode layer on the dielectric layer; a first plug on the first electrode layer; a second plug on the second electrode layer; a first top layer metal on the first plug, the width of the first top layer metal along the direction parallel to the surface of the substrate is more than twice the width of the first plug along the direction parallel to the surface of the substrate, and the first top layer metal is electrically connected to the pixel region; a second top layer metal on the second plug, the width of the second top layer metal along the direction parallel to the surface of the substrate is more than twice the width of the second plug along the direction parallel to the surface of the substrate, and the second top layer metal is electrically connected to an external voltage.

[0007] Optionally, the pixel region has a light sensing structure, and the first surface of the substrate exposes the light sensing structure; the substrate further comprises a floating diffusion region, and the first surface of the substrate exposes the surface of the floating diffusion region.

[0008] Optionally, the application further comprises a transfer transistor on the first surface of the substrate, the transfer transistor is located on a part of the photosensitive structure, and the floating diffusion region is connected to the transfer transistor; the first top metal layer is electrically connected to the floating diffusion region.

[0009] Optionally, the application further comprises a conductive structure and a dielectric structure on the first surface of the substrate, the conductive structure is located in the dielectric structure, the conductive structure comprises a stack of a plurality of third plugs and a third metal layer on the third plugs, the width of the third metal layer is twice the width of the third plug; the capacitor structure is located on the conductive structure and the dielectric structure, and the first top metal layer is electrically connected to the floating diffusion region through the conductive structure.

[0010] Optionally, the area of the second electrode layer is smaller than the area of the first electrode layer, and the second electrode layer exposes a part of the dielectric layer surface on the first electrode layer; the application further comprises a barrier layer on the surface of the second electrode layer and the surface of the dielectric layer; a first dielectric layer on the dielectric structure, the capacitor structure and the barrier layer are located in the first dielectric layer, the first plug and the second plug are located in the first dielectric layer; a fourth plug in the first dielectric layer, the fourth plug is electrically connected to the conductive structure, and the first top metal layer is electrically connected to the conductive structure through the fourth plug.

[0011] Optionally, the aspect ratio of the first plug ranges from 5:1 to 8:1; the aspect ratio of the second plug ranges from 5:1 to 8:1; and the aspect ratio of the fourth plug ranges from 5:1 to 8:1.

[0012] Optionally, the application further comprises a second dielectric layer on the first dielectric layer, the first plug, the second plug, and the fourth plug, and the first top metal layer and the second top metal layer are located in the second dielectric layer.

[0013] Optionally, the application further comprises that the aspect ratio of the first top metal layer ranges from 2:1 to 4:1; and the aspect ratio of the second top metal layer ranges from 2:1 to 4:1.

[0014] Optionally, the substrate further comprises a second surface opposite to the first surface, and the image sensor further comprises a filter structure on the pixel region of the second surface of the substrate; and a lens structure on the filter structure.

[0015] Correspondingly, the present application also provides a forming method of an image sensor, comprising: providing a substrate, the substrate comprising a first surface, the substrate comprising a pixel region; forming a capacitor structure on the first surface of the substrate, the capacitor structure comprising a first electrode layer, a dielectric layer on the first electrode layer, and a second electrode layer on the dielectric layer; forming a first dielectric layer on the capacitor structure; forming a first plug and a second plug in the first dielectric layer, the first plug being on the first electrode layer, and the second plug being on the second electrode layer; forming a second dielectric layer on the first dielectric layer; forming a first top layer metal and a second top layer metal in the second dielectric layer, the first top layer metal being on the first plug, the width of the first top layer metal along a direction parallel to the surface of the substrate being more than twice the width of the first plug along the direction parallel to the surface of the substrate, the first top layer metal being electrically connected to the pixel region, the second top layer metal being on the second plug, the width of the second top layer metal along the direction parallel to the surface of the substrate being more than twice the width of the second plug along the direction parallel to the surface of the substrate, the second top layer metal being electrically connected to an external voltage.

[0016] Optionally, the pixel region has a photosensitive structure, and the first surface of the substrate exposes the photosensitive structure; the substrate further comprises a floating diffusion region, and the first surface of the substrate exposes the surface of the floating diffusion region.

[0017] Optionally, before forming the capacitor structure on the first surface of the substrate, the method further comprises: forming a transfer transistor on the first surface of the substrate, the transfer transistor being on part of the photosensitive structure, and the floating diffusion region being connected to the transfer transistor; and the first top layer metal being electrically connected to the floating diffusion region.

[0018] Optionally, after forming the transfer transistor on the first surface of the substrate and before forming the capacitor structure on the first surface of the substrate, the method further comprises: forming a conductive structure and a dielectric structure on the first surface of the substrate, the conductive structure being in the dielectric structure, the conductive structure comprising a stack of a plurality of third plugs and a third metal layer on the third plugs, the width of the third metal layer being more than twice the width of the third plugs; and the first top layer metal being electrically connected to the floating diffusion region through the conductive structure.

[0019] Optionally, the area of the second electrode layer is smaller than the area of the first electrode layer, and the second electrode layer exposes part of the surface of the dielectric layer on the first electrode layer; after forming the conductive structure and the dielectric structure, the method further comprises: forming a barrier layer on the surface of the second electrode layer and the surface of the dielectric layer, and the first dielectric layer being on the barrier layer.

[0020] Optionally, while forming the first plug and the second plug, the method further comprises: forming a fourth plug in the first dielectric layer, the fourth plug being electrically connected to the conductive structure, and the first top layer metal being electrically connected to the conductive structure through the fourth plug.

[0021] Optionally, the method for forming the first plug, the second plug, and the fourth plug includes: forming a first opening, a second opening, and a fourth opening within a first dielectric layer, wherein the first opening exposes a portion of the surface of the first electrode layer, the second opening exposes a portion of the surface of the second electrode layer, and the fourth opening exposes a portion of the surface of the conductive structure; forming a conductive material layer within the first opening, the second opening, the fourth opening, and on the first dielectric layer; planarizing the conductive material layer until the surface of the first dielectric layer is exposed; forming a first plug within the first opening, forming a second plug within the second opening, and forming a fourth plug within the fourth opening.

[0022] Optionally, the aspect ratio of the first opening is in the range of 5:1 to 8:1; the aspect ratio of the second opening is in the range of 5:1 to 8:1; and the aspect ratio of the fourth opening is in the range of 5:1 to 8:1.

[0023] Optionally, the method for forming the first top layer metal and the second top layer metal includes: forming a second dielectric layer on a first dielectric layer, a first plug, a second plug, and a fourth plug; forming a first groove and a second groove within the second dielectric layer, wherein the first groove exposes the top surfaces of the first plug and the fourth plug, and the second groove exposes the top surface of the second plug; forming a conductive material layer within the first groove, within the second groove, and on the second dielectric layer; planarizing the conductive material layer until the surface of the second dielectric layer is exposed; forming the first top layer metal within the first groove; and forming the second top layer metal within the second groove.

[0024] Optionally, the depth-to-width ratio of the first groove is in the range of 2:1 to 4:1; the depth-to-width ratio of the second groove is in the range of 2:1 to 4:1.

[0025] Optionally, the substrate further includes a second surface opposite to the first surface, and the method further includes: forming a filter structure on the pixel area of ​​the second surface of the substrate; and forming a lens structure on the filter structure.

[0026] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0027] The technical scheme of the present application forms the first plug and the second plug in the first dielectric layer first, the first plug is located on the first electrode layer, the second plug is located on the second electrode layer, then forms the first top layer metal and the second top layer metal in the second dielectric layer, the first top layer metal is located on the first plug, the second top layer metal is located on the second plug, the width of the first top layer metal is more than twice the width of the first plug, the width of the second top layer metal is more than twice the width of the second plug. The first plug and the first top layer metal are not formed at the same time, the second plug and the second top layer metal are not formed at the same time, the size of the first plug is much smaller than the size of the first top layer metal, the size of the second plug is much smaller than the size of the second top layer metal, so that the first plug and the second plug can occupy a smaller area to meet the needs of small size image sensors while meeting the capacitance structure capacity performance. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is a structural schematic diagram of an image sensor in an embodiment;

[0029] Figures 2 to 7 is a structural schematic diagram of an image sensor forming process in an embodiment of the present application. DETAILED DESCRIPTION

[0030] As described in the background, with the continuous reduction in the size of CMOS image sensors, the application of MIM capacitors in image sensors also faces challenges. Now, specific embodiments will be analyzed and described.

[0031] Figure 1 is a structural schematic diagram of an image sensor in an embodiment.

[0032] Please refer to Figure 1The image sensor comprises: a substrate 100, the substrate 100 comprising opposite first and second surfaces, the substrate comprising a pixel region, the pixel region having a photosensitive structure 101 therein, the substrate 100 further comprising a floating diffusion region 102, the first surface of the substrate 100 exposing a surface of the floating diffusion region 102; a transfer transistor 103 on the first surface of the substrate 100, the transfer transistor 103 being located on part of the photosensitive structure 101, and the floating diffusion region 102 being in contact with the transfer transistor 103; a conductive structure 104 on the first surface of the substrate; a capacitor structure on the first surface of the substrate 100, the capacitor structure comprising a first electrode layer 105, a dielectric layer 106 on the first electrode layer 105, and a second electrode layer 107 on the dielectric layer 106; a first plug 111 on the first electrode layer 105; a second plug 108 on the second electrode layer 107; a first top metal layer 112 on the first plug 111, the first top metal layer 112 being electrically connected to the floating diffusion region 102 of the pixel region through a fourth plug 110 and the conductive structure 104; and a second top metal layer 109 on the second plug 108.

[0033] In the image sensor, the transfer transistor 103 transfers electrons in the photosensitive structure 101 to the floating diffusion region 102, and the capacitor structure is electrically connected to the floating diffusion region 102 of the pixel region through the fourth plug 110 and the conductive structure 104, so as to store the electrons generated by the photosensitive structure 101.

[0034] However, in order to make the distance between the capacitor structure and the pixel region far enough to reduce the parasitic capacitance between the capacitor structure and the pixel region, the capacitor structure is usually electrically connected to a top metal layer, and the top metal layer needs a large surface area for subsequent connection with external circuits. The first plug 111, the first top metal layer 112 on the first plug 111, the second plug 108, and the second top metal layer 109 on the second plug 108 are all Damascene structures, so the size difference between the first plug 111 and the first top metal layer 112 is small, and the size difference between the second plug 108 and the second top metal layer 109 is small, so the first plug 111, the first top metal layer 112, the second plug 108, and the second top metal layer 109 occupy a large amount of space. When the size of the pixel region becomes smaller and smaller, the space for the capacitor structure and other metal traces on the pixel region is squeezed, and the capacitance of the capacitor structure cannot meet the requirements.

[0035] To address the aforementioned problems, the present invention provides an image sensor and a method for forming the image sensor. The method involves first forming a first plug and a second plug within a first dielectric layer, with the first plug located on a first electrode layer and the second plug located on a second electrode layer. Then, a first top-layer metal and a second top-layer metal are formed within the second dielectric layer, with the first top-layer metal located on the first plug and the second top-layer metal located on the second plug. The width of the first top-layer metal is more than twice the width of the first plug, and the width of the second top-layer metal is more than twice the width of the second plug. The first plug and the first top-layer metal are not formed simultaneously, and the second plug and the second top-layer metal are not formed simultaneously. Furthermore, the size of the first plug is significantly smaller than the size of the first top-layer metal, and the size of the second plug is significantly smaller than the size of the second top-layer metal. Therefore, while meeting the capacitance performance requirements of the capacitor structure, the first and second plugs can occupy a smaller area, thus satisfying the needs of a small-sized image sensor.

[0036] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0037] Figures 2 to 7 This is a schematic diagram of the image sensor formation process in an embodiment of the present invention.

[0038] Please refer to Figure 2 Provides a base of 200.

[0039] In this embodiment, the substrate 200 includes a first surface (not shown) and a second surface (not shown) opposite each other, and the substrate 200 includes a pixel area.

[0040] The pixel region has a photosensitive structure 201, and the first surface of the substrate 200 exposes the photosensitive structure 201; the substrate 200 also includes a floating diffusion region 202, and the first surface of the substrate 200 exposes the surface of the floating diffusion region 202.

[0041] In this embodiment, the substrate 200 is made of silicon. The photosensitive structure 201 includes a photodiode.

[0042] The floating diffusion region 202 contains doped ions, including N-type ions or P-type ions; the N-type ions include phosphorus ions, arsenic ions or antimony ions; the P-type ions include boron ions, boron-fluorine ions or indium ions.

[0043] Please refer to Figure 3 A transmission transistor 203 is formed on a first surface of the substrate 200. The transmission transistor 203 is located on a portion of the photosensitive structure 201, and the floating diffusion region 202 is connected to the transmission transistor 203.

[0044] The transfer transistor 203 is used to transfer the electrons collected in the photoactive structure 201 into the replica diffusion region 202.

[0045] The transfer transistor 203 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) on the gate dielectric layer.

[0046] The material of the gate dielectric layer includes silicon oxide, and the material of the gate electrode layer includes polysilicon.

[0047] Please continue to refer to Figure 3 A conductive structure and a dielectric structure 206 are formed on the first side of the substrate 200, the conductive structure is located in the dielectric structure 206, the conductive structure includes a stack of a plurality of layers of third plugs 204 and a plurality of layers of third metal layers 205 on the third plugs 204, and the width of the third metal layer 205 is more than twice the width of the third plug 204.

[0048] The dielectric structure 206 includes a stack of a plurality of layers of third dielectric layers (not shown) and a plurality of layers of fourth dielectric layers (not shown), and the plurality of layers of third plugs 204 of the conductive structure are respectively located in the plurality of layers of third dielectric layers, and the plurality of layers of third metal layers 205 are respectively located in the plurality of layers of fourth dielectric layers.

[0049] The method for forming the conductive structure and the dielectric structure 206 includes: forming a third dielectric layer on the first side of the substrate 200; forming a first recess (not shown) in the third dielectric layer, the first recess exposes the surface of the floating diffusion region 202; forming a third plug 204 in the first recess; forming a fourth dielectric layer on the third dielectric layer and the third plug 204; forming a second recess (not shown) in the fourth dielectric layer, the second recess exposes the top surface of the third plug 204; forming a third metal layer 205 in the second recess; forming a third dielectric layer on the fourth dielectric layer and the third metal layer 205; forming a first recess (not shown) in the third dielectric layer, the first recess exposes the surface of the third metal layer 205; forming a third plug 204 in the first recess; forming a fourth dielectric layer on the third dielectric layer and the third plug 204; forming a second recess (not shown) in the fourth dielectric layer, the second recess exposes the top surface of the third plug 204; and forming a third metal layer 205 in the second recess.

[0050] The material of the dielectric structure 206 includes a dielectric material, and the dielectric material includes one or more of a combination of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride. In this embodiment, the material of the dielectric structure 206 includes silicon oxide.

[0051] The material of the third metal layer 205 includes metal or metal nitride; the metal includes a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0052] Please refer to Figure 4 A stop layer 230 is formed on the medium structure 206 and the conductive structure; a fifth medium layer 211 is formed on the stop layer 230.

[0053] The material of the stop layer 230 is different from the material of the fifth medium layer 211, which is used as an etching stop layer for subsequent formation of a capacitor structure. The fifth medium layer 211 can keep a sufficient distance between the subsequently formed capacitor structure and the substrate 200, avoiding the case that the capacitor structure and the substrate 200 are too close to generate a large resistance.

[0054] The thickness of the fifth medium layer 211 is adjusted according to actual needs.

[0055] In this embodiment, the material of the fifth medium layer 211 includes silicon oxide, and the material of the stop layer 230 includes silicon nitride.

[0056] Please continue to refer to Figure 4 A capacitor structure is formed on the first surface of the substrate 200, which includes a first electrode layer 207, a dielectric layer 208 on the first electrode layer 207, and a second electrode layer 209 on the dielectric layer 208.

[0057] In this embodiment, the area of the second electrode layer 209 is smaller than the area of the first electrode layer 207, and the second electrode layer 209 exposes part of the surface of the dielectric layer 208 on the first electrode layer 207.

[0058] The formation method of the capacitor structure includes: forming a first electrode material layer (not shown) on the fifth medium layer 211; forming a dielectric material layer (not shown) on the first electrode material layer; forming a second electrode material layer (not shown) on the dielectric material layer; forming a first mask layer (not shown) on the second electrode material layer; etching the second electrode material layer, the dielectric material layer, and the first electrode material layer with the first mask layer as a mask until the surface of the fifth medium layer 211 is exposed, to form the first electrode layer 207, the dielectric layer 208 on the first electrode layer 207, and the initial second electrode layer (not shown) on the dielectric layer 208; forming a second mask layer (not shown) on the initial second electrode layer; etching the initial second electrode layer with the second mask layer as a mask until the surface of the dielectric layer 208 is exposed, to form the second electrode layer 209.

[0059] The material of the first electrode layer 207 and the second electrode layer 209 includes metal or metal nitride; the metal includes a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0060] The material of the dielectric layer 208 includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride.

[0061] Please continue to refer to Figure 4 A barrier layer 210 is formed on the surface of the second electrode layer 209 and the surface of the dielectric layer 208.

[0062] The barrier layer 210 is used to protect the capacitor structure.

[0063] The material of the barrier layer 210 is different from the material of the first dielectric layer formed subsequently. In this embodiment, the material of the barrier layer 210 includes silicon nitride.

[0064] In other embodiments, the barrier layer can not be formed.

[0065] Please continue to refer to Figure 4 A first dielectric layer 212 is formed on the barrier layer 210 and the fifth dielectric layer 211.

[0066] The material of the first dielectric layer 212 includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbon nitride, and silicon carbon oxynitride.

[0067] In this embodiment, the material of the first dielectric layer 212 includes silicon oxide.

[0068] Next, a first plug and a second plug are formed in the first dielectric layer 212, the first plug is located on the first electrode layer, and the second plug is located on the second electrode layer. The formation process of the first plug and the second plug please refer to Figure 5 and Figure 6 .

[0069] In this embodiment, while the first plug and the second plug are formed, a fourth plug is also formed in the first dielectric layer 212, the fourth plug is electrically connected with the conductive structure.

[0070] Please refer to Figure 5A first opening 213, a second opening 214 and a fourth opening 215 are formed in the first dielectric layer 212, the first opening 213 exposing part of the surface of the first electrode layer 207, the second opening 214 exposing part of the surface of the second electrode layer 209, and the fourth opening 215 exposing part of the surface of the conductive structure.

[0071] In particular, the fourth opening 215 exposes part of the surface of the third metal layer 205.

[0072] The method for forming the first opening 213, the second opening 214 and the fourth opening 215 includes forming a third mask layer (not shown) on the first dielectric layer 212, and etching the first dielectric layer 212 with the third mask layer as a mask to form the first opening 213, the second opening 214 and the fourth opening 215 in the first dielectric layer 212.

[0073] The aspect ratio of the first opening 213 ranges from 5:1 to 8:1, the aspect ratio of the second opening 214 ranges from 5:1 to 8:1, and the aspect ratio of the fourth opening 215 ranges from 5:1 to 8:1.

[0074] Please refer to Figure 6 A first plug 216 is formed in the first opening 213, a second plug 217 is formed in the second opening 214, and a fourth plug 218 is formed in the fourth opening 215.

[0075] The method for forming the first plug 216, the second plug 217 and the fourth plug 218 includes forming a conductive material layer (not shown) in the first opening 213, the second opening 214, the fourth opening 215 and on the first dielectric layer 212, and planarizing the conductive material layer until the surface of the first dielectric layer 212 is exposed to form the first plug 216 in the first opening 213, the second plug 217 in the second opening 214, and the fourth plug 218 in the fourth opening 215.

[0076] The material of the first plug 216, the second plug 217 and the fourth plug 218 includes metal or metal nitride, the metal includes one or more combinations of copper, aluminum, tungsten, cobalt, nickel and tantalum, and the metal nitride includes one or more combinations of tantalum nitride and titanium nitride.

[0077] In this embodiment, the material of the first plug 216, the second plug 217 and the fourth plug 218 includes tungsten.

[0078] Please refer to Figure 7 A second dielectric layer 219 is formed on the first dielectric layer 212, the first plug 216, the second plug 217 and the fourth plug 218.

[0079] The material of the second dielectric layer 219 includes a combination of one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon aluminum carbonitride, and silicon aluminum oxycarbonitride.

[0080] In this embodiment, the material of the second dielectric layer 219 includes silicon oxide.

[0081] Please continue to refer to Figure 7 The first top metal layer 221 is formed on the first plug 216, and the width of the first top metal layer 221 along the direction parallel to the surface of the substrate 200 is more than twice the width of the first plug 216 along the direction parallel to the surface of the substrate 200. The first top metal layer 221 is electrically connected to the pixel region. The second top metal layer 220 is formed on the second plug 217, and the width of the second top metal layer 220 along the direction parallel to the surface of the substrate 200 is more than twice the width of the second plug 217 along the direction parallel to the surface of the substrate 200. The second top metal layer 220 is electrically connected to the external voltage.

[0082] In this embodiment, the first top metal layer 221 is also formed on the fourth plug 218. The first top metal layer 221 is electrically connected to the conductive structure through the fourth plug 218. The first top metal layer 211 is electrically connected to the floating diffusion region 202 through the fourth plug 218 and the conductive structure. Thus, the capacitor structure is electrically connected to the photosensitive structure 201 in the pixel region through the first top metal layer 221, the fourth plug 218, the conductive structure, the floating diffusion region 202, and the transfer transistor 203. Thus, the electrons generated by the photosensitive structure 201 can be transmitted to the capacitor structure through the transfer transistor 203, the floating diffusion region 202, the conductive structure, the fourth plug 218, the first top metal layer 221, the first plug 216, so as to achieve the purpose of storing the electrons generated by the photosensitive structure 201 by the capacitor structure.

[0083] The method for forming the first top metal layer 221 and the second top metal layer 220 includes: forming a first recess (not shown) and a second recess (not shown) in the second dielectric layer 219. The first recess exposes the top surface of the first plug 216 and the fourth plug 218. The second recess exposes the top surface of the second plug 217. A conductive material layer (not shown) is formed in the first recess, the second recess, and on the second dielectric layer 219. The conductive material layer is planarized until the surface of the second dielectric layer 219 is exposed, thereby forming the first top metal layer 221 in the first recess and the second top metal layer 220 in the second recess.

[0084] The depth-to-width ratio of the first groove ranges from 2:1 to 4:1; and the depth-to-width ratio of the second groove ranges from 2:1 to 4:1.

[0085] The material of the first top layer metal 221 and the second top layer metal 220 includes metal or metal nitride; the metal includes a combination of one or more of copper, aluminum, tungsten, cobalt, nickel, and tantalum; and the metal nitride includes a combination of one or more of tantalum nitride and titanium nitride.

[0086] In this embodiment, the material of the first top layer metal 221 and the second top layer metal 220 includes copper.

[0087] The first top layer metal 221 is located on the first plug 216, and the second top layer metal 220 is located on the second plug 217; the width of the first top layer metal 221 is more than twice the width of the first plug 216, and the width of the second top layer metal 220 is more than twice the width of the second plug 217; the first plug 216 and the first top layer metal 221 are not formed at the same time, and the second plug 217 and the second top layer metal 220 are not formed at the same time; the size of the first plug 216 is much smaller than the size of the first top layer metal 221, and the size of the second plug 217 is much smaller than the size of the second top layer metal 220, so that the first plug 216 and the second plug 217 can occupy a smaller area to meet the needs of a small-size image sensor while meeting the capacitance value performance of the capacitor structure.

[0088] In this embodiment, after the first top layer metal 221 and the second top layer metal 220 are formed, the method further includes: forming a light filtering structure (not shown) on the second surface pixel area of the substrate 200; and forming a lens structure (not shown) on the light filtering structure.

[0089] The lens structure is used for allowing light to pass through the lens structure into the pixel area, and the light filtering structure is used for filtering light and allowing only light of a specific wavelength to enter the pixel area.

[0090] Correspondingly, the embodiment of the present application also provides an image sensor, please continue to refer to Figure 7 , comprising:

[0091] A substrate 200, the substrate 200 includes a first surface, and the substrate 200 includes a pixel area;

[0092] A capacitor structure located on the first surface of the substrate 200, the capacitor structure includes a first electrode layer 207, a dielectric layer 208 located on the first electrode layer 207, and a second electrode layer 209 located on the dielectric layer 208;

[0093] A first plug 216 located on the first electrode layer 207;

[0094] a second plug 217 on the second electrode layer 209;

[0095] a first top layer metal 221 on the first plug 216, the first top layer metal 221 has a width along a direction parallel to the surface of the substrate 200 that is more than twice the width of the first plug 216 along the direction parallel to the surface of the substrate 200, the first top layer metal 221 is electrically connected to the pixel region;

[0096] a second top layer metal 220 on the second plug 217, the second top layer metal 220 has a width along a direction parallel to the surface of the substrate 200 that is more than twice the width of the second plug 217 along the direction parallel to the surface of the substrate 200, the second top layer metal 220 is electrically connected to an external voltage.

[0097] In this embodiment, the pixel region has a photosensitive structure 201, the first surface of the substrate 200 exposes the photosensitive structure 201; the substrate 200 further includes a floating diffusion region 202, the first surface of the substrate 200 exposes the surface of the floating diffusion region 202.

[0098] In this embodiment, further including a transfer transistor 203 on the first surface of the substrate 200, the transfer transistor 203 is on part of the photosensitive structure 201, and the floating diffusion region 202 is connected to the transfer transistor 203; the first top layer metal 221 is electrically connected to the floating diffusion region 202.

[0099] In this embodiment, further including a conductive structure and a dielectric structure 206 on the first surface of the substrate 200, the conductive structure is in the dielectric structure 206, the conductive structure includes a stack of a plurality of third plugs 204 and a third metal layer 205 on the third plugs 204, the width of the third metal layer 205 is more than twice the width of the third plug 204; the capacitor structure is on the conductive structure and the dielectric structure 206, the first top layer metal 221 is electrically connected to the floating diffusion region 202 through the conductive structure.

[0100] In the embodiment, the area of the second electrode layer 209 is smaller than the area of the first electrode layer 207, and the second electrode layer 209 exposes part of the dielectric layer 208 surface on the first electrode layer 207; further comprising: a barrier layer 210 on the surface of the second electrode layer 209 and the surface of the dielectric layer 208; a first dielectric layer 212 on the dielectric structure 206, the capacitor structure and the barrier layer 210 are in the first dielectric layer 212, and the first plug 216 and the second plug 217 are in the first dielectric layer 212; a fourth plug 218 in the first dielectric layer 212, the fourth plug 218 is electrically connected with the conductive structure, and the first top metal layer 221 is electrically connected with the conductive structure through the fourth plug 218.

[0101] In the embodiment, the aspect ratio of the first plug 216 ranges from 5:1 to 8:1, the aspect ratio of the second plug 217 ranges from 5:1 to 8:1, and the aspect ratio of the fourth plug 218 ranges from 5:1 to 8:1.

[0102] In the embodiment, further comprising: a second dielectric layer 219 on the first dielectric layer 212, the first plug 216, the second plug 217 and the fourth plug 218, and the first top metal layer 221 and the second top metal layer 220 are in the second dielectric layer 219.

[0103] In the embodiment, further comprising: the aspect ratio of the first top metal layer 221 ranges from 2:1 to 4:1, and the aspect ratio of the second top metal layer 220 ranges from 2:1 to 4:1.

[0104] In the embodiment, the substrate 200 further comprises a second surface opposite to the first surface, and the image sensor further comprises: a filter structure on the pixel region of the second surface of the substrate 200; and a lens structure on the filter structure.

[0105] Although the present application has been disclosed as above, the present application is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims.

Claims

1. An image sensor, characterized by, The image sensor comprises: a substrate comprising a first surface, the substrate comprising a pixel region and a floating diffusion region, the pixel region having a photosensitive structure therein, the substrate first surface exposing a surface of the photosensitive structure and the floating diffusion region; a conductive structure and a dielectric structure on the substrate first surface, the conductive structure being within the dielectric structure; a capacitor structure on the conductive structure and the dielectric structure, the capacitor structure comprising a first electrode layer, a dielectric layer on the first electrode layer, and a second electrode layer on the dielectric layer; a first plug on the first electrode layer; a second plug on the second electrode layer; a fourth plug on the conductive structure, the fourth plug being electrically connected to the conductive structure; a first top layer metal on the first plug and the fourth plug, a width of the first top layer metal along a direction parallel to the substrate surface being more than twice a width of the first plug along the direction parallel to the substrate surface, the first top layer metal being electrically connected to the floating diffusion region through the fourth plug and the conductive structure; a second top layer metal on the second plug, a width of the second top layer metal along a direction parallel to the substrate surface being more than twice a width of the second plug along the direction parallel to the substrate surface, the second top layer metal being electrically connected to an external voltage.

2. The image sensor of claim 1, wherein, Further comprising: a transfer transistor on the substrate first surface, the transfer transistor being on part of the photosensitive structure, and the floating diffusion region being adjacent to the transfer transistor.

3. The image sensor of claim 2, wherein, The conductive structure comprises a stack of a plurality of third plugs and a third metal layer on the third plugs, a width of the third metal layer being more than twice a width of the third plugs; the first top layer metal being electrically connected to the floating diffusion region through the conductive structure.

4. The image sensor of claim 3, wherein, An area of the second electrode layer is less than an area of the first electrode layer, the second electrode layer exposing a surface of the dielectric layer on part of the first electrode layer; further comprising: a barrier layer on the surface of the second electrode layer and the surface of the dielectric layer; a first dielectric layer on the dielectric structure, the capacitor structure and the barrier layer being within the first dielectric layer, the first plug, the second plug and the fourth plug being within the first dielectric layer.

5. The image sensor of claim 4, wherein, An aspect ratio of the first plug ranges from 5:1 to 8:1; an aspect ratio of the second plug ranges from 5:1 to 8:1; an aspect ratio of the fourth plug ranges from 5:1 to 8:

1.

6. The image sensor of claim 4, wherein, Further comprising: a second dielectric layer on the first dielectric layer, the first plug, the second plug and the fourth plug, the first top layer metal and the second top layer metal being within the second dielectric layer.

7. The image sensor of claim 6, wherein, Further comprising: an aspect ratio of the first top layer metal ranges from 2:1 to 4:1; an aspect ratio of the second top layer metal ranges from 2:1 to 4:

1.

8. The image sensor of claim 1, wherein, The substrate further comprises a second surface opposite to the first surface, the image sensor further comprising: a filter structure on the pixel region of the substrate second surface; a lens structure on the filter structure.

9. A method of forming an image sensor, comprising: The image sensor comprises: providing a substrate comprising a first surface, the substrate comprising a pixel region and a floating diffusion region, the pixel region having a photosensitive structure therein, the substrate first surface exposing a surface of the photosensitive structure and the floating diffusion region; forming a conductive structure and a dielectric structure on the first surface of the substrate, the conductive structure being located in the dielectric structure; forming a capacitor structure on the conductive structure and the dielectric structure, the capacitor structure comprising a first electrode layer, a dielectric layer located on the first electrode layer, and a second electrode layer located on the dielectric layer; forming a first dielectric layer on the capacitor structure; forming a first plug, a second plug and a fourth plug in the first dielectric layer, the first plug being located on the first electrode layer, the second plug being located on the second electrode layer, and the fourth plug being located on the conductive structure; forming a second dielectric layer on the first dielectric layer; forming a first top metal and a second top metal in the second dielectric layer, the first top metal being located on the first plug and the fourth plug, the width of the first top metal along a direction parallel to the surface of the substrate being more than twice the width of the first plug along the direction parallel to the surface of the substrate, the second top metal being located on the second plug, the width of the second top metal along the direction parallel to the surface of the substrate being more than twice the width of the second plug along the direction parallel to the surface of the substrate, the second top metal being electrically connected to an external voltage, and the first top metal being electrically connected to the floating diffusion through the fourth plug and the conductive structure.

10. The method for forming an image sensor according to claim 9, wherein Before forming the conductive structure and the dielectric structure on the first surface of the substrate, the method further comprises forming a transfer transistor on the first surface of the substrate, the transfer transistor being located on part of the photosensitive structure, and the floating diffusion being connected to the transfer transistor.

11. The method for forming an image sensor according to Claim 9, wherein The conductive structure comprises a stack of a plurality of layers of third plugs and a third metal layer located on the third plugs, the width of the third metal layer being more than twice the width of the third plugs.

12. The method for forming an image sensor according to claim 9, wherein The area of the second electrode layer is smaller than the area of the first electrode layer, and the second electrode layer exposes part of the surface of the dielectric layer on the first electrode layer; After forming the capacitor structure, the method further comprises forming a barrier layer on the surface of the second electrode layer and the surface of the dielectric layer, and the first dielectric layer is located on the barrier layer.

13. The method for forming an image sensor according to claim 9, wherein The method for forming the first plug, the second plug and the fourth plug comprises: forming a first opening, a second opening and a fourth opening in the first dielectric layer, the first opening exposing part of the surface of the first electrode layer, the second opening exposing part of the surface of the second electrode layer, and the fourth opening exposing part of the surface of the conductive structure; forming a conductive material layer in the first opening, the second opening, the fourth opening and on the first dielectric layer; planarizing the conductive material layer until the surface of the first dielectric layer is exposed, thereby forming the first plug in the first opening, the second plug in the second opening, and the fourth plug in the fourth opening.

14. The method for forming an image sensor according to claim 13, wherein The aspect ratio of the first opening ranges from 5:1 to 8:1, the aspect ratio of the second opening ranges from 5:1 to 8:1, and the aspect ratio of the fourth opening ranges from 5:1 to 8:

1.

15. The method for forming an image sensor according to claim 9, wherein The forming method of the first top layer metal and the second top layer metal comprises: forming a second dielectric layer on the first dielectric layer, the first plug, the second plug and the fourth plug; forming a first recess and a second recess in the second dielectric layer, the first recess exposing the top surface of the first plug and the fourth plug, and the second recess exposing the top surface of the second plug; forming a conductive material layer in the first recess, the second recess and on the second dielectric layer; planarizing the conductive material layer until the surface of the second dielectric layer is exposed, forming the first top layer metal in the first recess and the second top layer metal in the second recess.

16. The method for forming an image sensor according to claim 15, wherein The aspect ratio of the first recess ranges from 2:1 to 4:1, and the aspect ratio of the second recess ranges from 2:1 to 4:

1.

17. The method for forming an image sensor according to Claim 9, wherein The substrate further comprises a second surface opposite to the first surface, and the method further comprises: forming a light filtering structure on the pixel region of the second surface of the substrate; and forming a lens structure on the light filtering structure.

Images