Variable doping structure shielded gate trench field effect transistor and preparation method thereof

Abstract

The present application relates to a shielded-gate trench field-effect transistor with a variable doping structure, comprising: a substrate region, a drift region, a shield gate, a control gate, a base region, a source region, an insulating layer, a source electrode, a drain electrode, and a metal gate electrode; the drift region, base region, source region, and source electrode are sequentially arranged above the substrate region, the drain electrode is arranged below the substrate region, and the control gate and shield gate are arranged on one side of the drift region from top to bottom; the doping type of the substrate region 1, drift region 2, and source region 7 are all a first doping type; the doping type of the base region 6 is a second doping type; the doping concentrations of the substrate region 1 and source region 7 are both greater than the doping concentration of the drift region; the base region 6 includes several doping distribution layers distributed from top to bottom; the doping concentrations of the several doping distribution layers decrease linearly from top to bottom. The solution provided in the present application can effectively shorten the channel length of the channel region, thereby reducing the on-resistance of the channel region.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a shielded gate trench field effect transistor with a variable doping structure and a preparation method thereof. Background Art

[0002] Compared with traditional trench transistors, shielded gate trench field-effect transistors have higher channel density and better charge compensation effect. Their shielded gate structure effectively reduces the transfer capacitance, so it has lower specific on-resistance, smaller conduction and switching losses, and higher operating frequency. Therefore, it is widely used in important fields such as power management.

[0003] When the breakdown voltage is less than 300V, especially when the breakdown voltage is less than 100V or even less than 40V, the channel region and the drift region have comparable specific on-resistance. Therefore, for low-voltage shielded gate trench field-effect transistors, improving the specific on-resistance of the channel region is as important as designing the drift region.

[0004] In the related technology, the patent document with publication number CN105957896B functionally discloses a super junction power device, which forms multiple grooves on the N-type epitaxial layer, is filled with P-type columns, and the doping concentration of the doping compensation layer gradually changes from the top to the bottom of the groove, which is used to compensate for the influence of the groove width at different depths on the charge balance of the P-type column and the N-type column, thereby improving the breakdown voltage of the super junction power device.

[0005] However, the above solution is a structural improvement to the drift region of the transistor, which has a significant effect on improving the breakdown voltage of the transistor, but has a lower impact on the specific on-resistance of the channel region, and cannot meet the demand of low-voltage shielded gate trench field-effect transistors for reducing the specific on-resistance. Summary of the Invention

[0006] In order to overcome the problems existing in the related art, the present application provides a shielded gate trench field effect transistor with a variable doping structure, which can effectively shorten the channel length of the channel region, thereby reducing the on-resistance of the channel region.

[0007] In a first aspect, the present application provides a shielded gate trench field effect transistor with a variable doping structure, comprising:

[0008] A substrate region 1, a drift region 2, a shield gate 4, a control gate 5, a base region 6, a source region 7, an insulating layer 3, a source electrode 8, a drain electrode 9, and a metal gate 10; the drift region 2, the base region 6, the source region 7, and the source electrode 8 are sequentially arranged above the substrate region 1, the drain electrode 9 is arranged below the substrate region 1, the control gate 5 and the shield gate 4 are arranged on the same side of the drift region 2 from top to bottom, and the control gate 5 is respectively attached to the base region 6 and the source region 7 through the insulating layer 3, and the shield gate 4 is attached to the drift region 2 through the insulating layer 3;

[0009] The doping type of the substrate region 1, the drift region 2 and the source region 7 are all the first doping type; the doping type of the body region 6 is the second doping type;

[0010] The doping concentrations of the substrate region 1 and the source region 7 are both greater than the doping concentration of the drift region; the base region 6 includes several doping distribution layers distributed from top to bottom; the doping concentrations of the several doping distribution layers decrease linearly from top to bottom.

[0011] In one embodiment, among the plurality of doping distribution layers, each doping distribution layer has the same thickness.

[0012] In one embodiment, the thickness of the doping distribution layer is 0.5 μm.

[0013] In one embodiment, the base region 6 includes a first doping distribution layer 61 , a second doping distribution layer 62 and a third doping distribution layer 63 distributed from top to bottom.

[0014] In one embodiment, the value range of the first doping distribution layer 61 is 1×10 17 cm -3 to 5×10 18 cm -3 The value range of the third doping distribution layer 63 is 1×10 15 cm -3 to 5×10 16 cm -3 .

[0015] A second aspect of the present application provides a method for preparing a shielded gate trench field effect transistor with a variable doping structure, which is used to prepare the shielded gate trench field effect transistor with a variable doping structure as described in any one of the above items, comprising:

[0016] preparing a substrate region with a semiconductor material of a first doping type;

[0017] forming a drain at the bottom of the substrate region;

[0018] epitaxially forming a drift region on the substrate region using a semiconductor material of a first doping type;

[0019] forming a plurality of doping distribution layers on the drift region using a semiconductor material of a second doping type with a linearly increasing doping concentration to obtain a base region;

[0020] Etching grooves on the drift region and the substrate region;

[0021] Depositing oxide, polysilicon, oxide and polysilicon in sequence in the trench to form an insulating layer, a shielding gate and a control gate;

[0022] Doping the substrate region with a semiconductor material of a first doping type to form a source region and a source electrode;

[0023] A metal gate is prepared above the trench;

[0024] A drain is fabricated below the substrate region to obtain the shielded gate trench field effect transistor with a variable doping structure.

[0025] In one embodiment, forming a plurality of doping distribution layers on the drift region using a semiconductor material of a second doping type with a linearly increasing doping concentration to obtain a base region includes:

[0026] On the drift region, the plurality of doping distribution layers are formed in sequence using a second doping type semiconductor material with linearly increasing doping concentration by ion implantation, diffusion or epitaxial growth to obtain a base region.

[0027] The technical solution provided by this application may have the following beneficial effects:

[0028] An embodiment of the present application provides a shielded gate trench field effect transistor with a variable doping structure, which adopts a longitudinal variable doping structure in the base region, that is, the doping concentration of the base region decreases uniformly along the direction from the source region to the drift region. According to the Poisson equation, the electric field in the channel region changes from a uniformly doped approximately triangular distribution to an approximately rectangular distribution. When the transistor is in forward conduction, the electric field in the channel region is modulated to improve the overall electric field in the channel region, so that the carriers in the channel region can reach velocity saturation more evenly, thereby obtaining a shorter channel length, thereby reducing the specific on-resistance of the channel region; when the transistor is in an avalanche state, the self-built electric field along the direction of increasing concentration introduced by the longitudinal variable doping structure accelerates the hole drift motion, reduces the voltage drop of the hole current along the base region, effectively suppresses the opening of the parasitic transistor in the base region, and improves the avalanche capability of the device.

[0029] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other objects, features and advantages of the present application will become more apparent through a more detailed description of exemplary embodiments of the present application in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present application.

[0031] Figure 1 Schematic diagram of the structure of a shielded gate trench field effect transistor with a variable doping structure shown in an embodiment of the present application;

[0032] Figure 2 1 is another structural schematic diagram of a shielded gate trench field effect transistor with a variable doping structure shown in an embodiment of the present application;

[0033] Figure 3 It is a schematic flow chart of a method for preparing a shielded gate trench field effect transistor with a variable doping structure shown in an embodiment of the present application. DETAILED DESCRIPTION

[0034] The preferred embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0035] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0036] It should be understood that although the terms "first", "second", "third", etc. may be used in this application to describe various information, this information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0037] Example 1

[0038] When the breakdown voltage is less than 300V, especially when the breakdown voltage is less than 100V or even less than 40V, the channel region and the drift region have comparable specific on-resistance. The structural improvement of the drift region has a significant effect on improving the breakdown voltage of the transistor, but has a lower impact on the specific on-resistance of the channel region, which cannot meet the demand of low-voltage shielded gate trench field-effect transistors for reducing the specific on-resistance.

[0039] In response to the above problems, an embodiment of the present application provides a shielded gate trench field effect transistor with a variable doping structure, which can effectively reduce the specific on-resistance of the channel region.

[0040] The technical solutions of the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0041] Figure 1 It is a structural schematic diagram of a shielded gate trench field effect transistor with a variable doping structure shown in an embodiment of the present application.

[0042] See also Figure 1 The variable doping structure shielded gate trench field effect transistor comprises:

[0043] Substrate region 1, drift region 2, shield gate 4, control gate 5, body region 6, source region 7, insulating layer 3, source electrode 8, drain electrode 9 and metal gate 10;

[0044] The drift region 2, the base region 6, the source region 7, and the source electrode 8 are sequentially arranged above the substrate region 1, the drain electrode 9 is arranged below the substrate region 1, the control gate 5 and the shield gate 4 are arranged on the same side of the drift region 2 from top to bottom, and the control gate 5 is respectively attached to the base region 6 and the source region 7 through the insulating layer 3, and the shield gate 4 is attached to the drift region 2 through the insulating layer 3;

[0045] The doping types of the substrate region 1, the drift region 2 and the source region 7 are all the first doping type; the doping type of the base region 6 is the second doping type; the doping concentrations of the substrate region 1 and the source region 7 are both greater than the doping concentration of the drift region 2; the base region 6 includes several layers of doping distribution layers distributed from top to bottom; the doping concentrations of the several layers of doping distribution layers decrease linearly from top to bottom.

[0046] Furthermore, the doping type of the shield gate 4 and the control gate 5 is the second doping type.

[0047] In the embodiments of the present application, the first doping type and the second doping type are N-type doping and P-type doping, respectively; or the first doping type and the second doping type are P-type doping and N-type doping, respectively. In actual applications, the setting of the doping type can be adjusted according to actual conditions and is not limited here.

[0048] In the embodiment of the present application, the plurality of doping distribution layers may be distributed at equal or unequal intervals. Preferably, the plurality of doping distribution layers are distributed at equal intervals in the base region, that is, the thickness of each doping distribution layer in the plurality of doping distribution layers is equal.

[0049] Preferably, the thickness of the doping distribution layer is 0.5 μm.

[0050] For example, the first doping type and the second doping type are N-type doping and P-type doping respectively:

[0051] In an embodiment of the present application, the base region 6 forms a variable doping structure with a uniformly decreasing doping concentration along the direction of the source region 7 pointing to the drift region 2. A longitudinal variable doping structure is introduced through the base region 6. When the transistor is in an avalanche state, the P-type doped base region 6 and the N-type doped drift region 2 are reverse biased. After the N-type doped drift region 2 is exhausted, electron-hole pairs are generated. When the holes flow into the P-type doped base region 6, the longitudinal variable doping structure introduces a self-built electric field along the direction of increasing doping concentration. The holes are accelerated under the action of the self-built field, so that the voltage caused by the holes flowing into the P-type doped base region 6 is small, which helps to suppress the opening of the doping distribution layer junction with the highest doping concentration in the N-type heavily doped source region 7 and the P-type doped base region 6, and is beneficial to improving the avalanche capability of the device.

[0052] In actual application, the number of doping distribution layers can be designed according to actual needs, which will not be described in detail here.

[0053] An embodiment of the present application provides a shielded gate trench field effect transistor with a variable doping structure, which adopts a longitudinal variable doping structure in the base region, that is, the doping concentration of the base region decreases uniformly along the direction from the source region to the drift region. According to the Poisson equation, the electric field in the channel region changes from a uniformly doped approximately triangular distribution to an approximately rectangular distribution. When the transistor is in forward conduction, the electric field in the channel region is modulated to improve the overall electric field in the channel region, so that the carriers in the channel region can reach velocity saturation more evenly, thereby obtaining a shorter channel length, thereby reducing the specific on-resistance of the channel region; when the transistor is in an avalanche state, the self-built electric field along the direction of increasing concentration introduced by the longitudinal variable doping structure accelerates the hole drift motion, reduces the voltage drop of the hole current along the base region, effectively suppresses the opening of the parasitic transistor in the base region, and improves the avalanche capability of the device.

[0054] Example 2

[0055] Based on the shielded gate trench field effect transistor with a variable doping structure shown in the first embodiment above, an embodiment of the present application provides a shielded gate trench field effect transistor with a variable doping structure having three doping distribution layers with equal spacing.

[0056] See also Figure 2 The variable doping structure shielded gate trench field effect transistor includes: a substrate region 1, a drift region 2, a shielding gate 4, a control gate 5, a body region 6, a source region 7, an insulating layer 3, a source electrode 8, a drain electrode 9 and a metal gate 10;

[0057] The drift region 2, the base region 6, the source region 7, and the source electrode 8 are sequentially arranged above the substrate region 1, the drain electrode 9 is arranged below the substrate region 1, the control gate 5 and the shield gate 4 are arranged on the same side of the drift region 2 from top to bottom, and the control gate 5 is respectively attached to the base region 6 and the source region 7 through the insulating layer 3, and the shield gate 4 is attached to the drift region 2 through the insulating layer 3;

[0058] The substrate region 1, the drift region 2 and the source region 7 are all N-type doped; the doping concentrations of the substrate region 1 and the source region 7 are greater than the doping concentration of the drift region; the body region 6, the shield gate 4 and the control gate 5 are all P-type doped;

[0059] The base region 6 includes a first doping distribution layer 61, a second doping distribution layer 62 and a third doping distribution layer 63 distributed from top to bottom; the doping concentrations of the first doping distribution layer 61, the second doping distribution layer 62 and the third doping distribution layer 63 decrease linearly; the first doping distribution layer 61, the second doping distribution layer 62 and the third doping distribution layer 63 have the same thickness.

[0060] In the embodiment of the present application, preferably, the thickness of the first doping distribution layer 61 , the second doping distribution layer 62 and the third doping distribution layer 63 are all 0.5 μm.

[0061] In the embodiment of the present application, the value range of the first doping distribution layer 61 is 1×10 17 cm -3 to 5×10 18 cm -3 The value range of the third doping distribution layer 63 is 1×10 15 cm -3 to 5×10 16 cm -3 .

[0062] In the embodiment of the present application, during the experimental stage, the cell mesa width of the shielded gate trench field effect transistor is set to 1 μm, the width of the trench is 0.2 μm, and the doping concentration of the shielding gate 4 is 7.9×10 16 cm -3 The thickness of the drift region 2 is 1.5 μm, the thickness of the substrate region 1 is 150 μm, the thickness of the body region 6 is 2 μm, and the doping concentration of the drift region 2 is 7.2×1016 cm -3 , the doping concentration of substrate region 1 is 5×10 19 cm -3 , the doping concentration of source region 7 is 5×10 19 cm -3 , the doping concentration of the control gate 5 is 1×10 20 cm -3 , the breakdown voltage is 37V and the specific on-resistance of the channel region is 0.017mΩ·cm 2 After the base region 6 is replaced with a vertically variable doping structure having three doping distribution layers, the doping concentration of the first doping distribution layer 61 is 5×10 17 cm -3 The doping concentration of the third doping distribution layer 63 is 5×10 15 cm -3 , the on-resistance of the channel region is reduced to 0.011mΩ·cm 2 .

[0063] It should be noted that the above description of the structural parameters of the shielded gate trench field effect transistor is only an example given in the experimental stage of the embodiment of the present application, and does not need to be the only limitation of the present application.

[0064] An embodiment of the present application provides a shielded gate trench field effect transistor with a variable doping structure, which adopts a longitudinal variable doping structure in the substrate region. According to the Poisson equation, the electric field in the channel region changes from a uniformly doped approximately triangular distribution to an approximately rectangular distribution. When the transistor is in forward conduction, the electric field in the channel region is modulated to improve the overall electric field in the channel region, so that the carriers in the channel region can reach velocity saturation more evenly, thereby obtaining a shorter channel length, thereby reducing the specific on-resistance of the channel region; when the transistor is in an avalanche state, the self-built electric field along the direction of increasing concentration introduced by the longitudinal variable doping structure accelerates the hole drift motion, reduces the voltage drop of the hole current along the substrate region, effectively suppresses the opening of the parasitic transistor in the substrate region, and improves the avalanche capability of the device.

[0065] Example 3

[0066] Corresponding to the aforementioned embodiment of the shielded gate trench field effect transistor with a variable doping structure, the present application also provides a method for preparing the shielded gate trench field effect transistor with a variable doping structure and corresponding embodiments.

[0067] Figure 3 It is a schematic flow chart of a method for preparing a shielded gate trench field effect transistor with a variable doping structure shown in an embodiment of the present application.

[0068] See also Figure 3The method for preparing the shielded gate trench field effect transistor with a variable doping structure comprises:

[0069] 301. Prepare a substrate region using a semiconductor material of a first doping type;

[0070] In the embodiment of the present application, the semiconductor material is a silicon material or a silicon carbide material. In step 301, the semiconductor material is an N-type heavily doped material, and the doping concentration thereof is in the range of 1×10 19 cm -3 to 5×10 20 cm -3 .

[0071] 302. Fabricate a drain at the bottom of the substrate region;

[0072] In an embodiment of the present application, a drain is formed on the bottom surface of the substrate region.

[0073] 303. Form a drift region by epitaxial growth on the substrate region using a semiconductor material of a first doping type;

[0074] In the embodiment of the present application, the semiconductor material is a silicon material or a silicon carbide material. In step 303, the semiconductor material is an N-type medium doped material, and the doping concentration range is 1×10 15 cm -3 to 5×10 17 cm -3 Preferably, the doping concentration of the N-type doping material is 5×10 16 cm -3 .

[0075] 304. Forming a plurality of doping distribution layers on the drift region using a semiconductor material of a second doping type with a linearly increasing doping concentration to obtain a base region;

[0076] In the embodiment of the present application, in step 304 , the semiconductor material is a P-type doped material.

[0077] In an embodiment of the present application, the plurality of doping distribution layers are sequentially formed on the drift region using a semiconductor material of a second doping type with a linearly increasing doping concentration by ion implantation, diffusion or epitaxial growth to obtain a base region;

[0078] Ion implantation is the process of doping silicon materials. In practice, a power device is placed at one end of an ion implanter, with a doping ion source located at the other. At the doping ion source, the dopant atoms are ionized, becoming charged and accelerated to ultra-high speeds by the electric field. They then penetrate the surface of the device, using their momentum to inject the doping atoms into the power device, forming a doped region.

[0079] The diffusion process is the process of doping pure impurity atoms into the surface of silicon materials. In practical applications, diborane or phosphine is usually used as an ion source, and intermittent diffusion or substitutional diffusion is used to dope pure impurity atoms into the surface of silicon materials.

[0080] The epitaxial process refers to the formation of a single crystal film on a single crystal substrate, and the single crystal film grows along the crystal image of the substrate.

[0081] Specifically, a third doping distribution layer is first formed on the drift region using a P-type doping semiconductor material with a third doping concentration, a second doping distribution layer is then formed on the drift region using a P-type doping semiconductor material with a second doping concentration, and a first doping distribution layer is then formed on the drift region using a P-type doping semiconductor material with a first doping concentration, to obtain the base region, wherein the first doping concentration, the second doping concentration and the third doping concentration decrease step by step.

[0082] 305. Etching grooves in the drift region and the substrate region;

[0083] In an embodiment of the present application, grooves are etched on the sides of the drift region and the base region by a photolithography process, and then the residual photoresist is removed by wet etching or dry etching.

[0084] 306. Depositing oxide, polysilicon, oxide, and polysilicon in sequence in the trench to form an insulating layer, a shield gate, and a control gate;

[0085] In an embodiment of the present application, preferably, oxide, medium-doped polysilicon, oxide and heavily-doped polysilicon are deposited in sequence in the trench to form an insulating layer, a shielding gate and a control gate; wherein the doping concentration of the heavily-doped polysilicon is greater than that of the medium-doped polysilicon.

[0086] In the embodiment of the present application, preferably, the doping concentration of the medium-doped polysilicon is 5×10 16 cm -3 .

[0087] 307. Doping the substrate region with a semiconductor material of the first doping type to form a source region and a source electrode;

[0088] In the embodiment of the present application, N-type heavily doped material is selected to prepare the source region, and the doping concentration thereof is in the range of 1×10 19 cm -3 to 5×10 20 cm -3 .

[0089] 308. Prepare a metal gate above the trench;

[0090] 309. A drain is fabricated below the substrate region to obtain a shielded gate trench field effect transistor with a variable doping structure.

[0091] An embodiment of the present application provides a method for preparing a shielded gate trench field effect transistor with a variable doping structure. The method adopts a longitudinal variable doping structure in the substrate region, and according to the Poisson equation, changes the electric field in the channel region from a uniformly doped approximately triangular distribution to an approximately rectangular distribution. When the transistor is in forward conduction, the electric field in the channel region is modulated to improve the overall electric field in the channel region, so that the carriers in the channel region can reach velocity saturation more evenly, thereby obtaining a shorter channel length, thereby reducing the specific on-resistance of the channel region; when the transistor is in an avalanche state, the self-built electric field along the direction of increasing concentration introduced by the longitudinal variable doping structure accelerates the hole drift motion, reduces the voltage drop of the hole current along the substrate region, effectively suppresses the opening of the parasitic transistor in the substrate region, and improves the avalanche capability of the device.

[0092] The scheme of the present application has been described in detail above with reference to the accompanying drawings. In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. Those skilled in the art should also be aware that the actions and modules involved in the description are not necessarily required for this application. In addition, it is understood that the steps in the method of the embodiment of the present application can be adjusted in sequence, merged and deleted according to actual needs, and the modules in the device of the embodiment of the present application can be merged, divided and deleted according to actual needs.

[0093] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems and methods according to multiple embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a part of a module, program segment or code, and the part of the module, program segment or code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order than that marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0094] The embodiments of the present application have been described above. The above description is illustrative and not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, their practical applications, or improvements to the technology in the market, or to enable other persons skilled in the art to understand the embodiments disclosed herein.

Claims

1. A shielded gate trench field effect transistor with a variable doping structure, characterized in that: include: A substrate region (1), a drift region (2), a shielding gate (4), a control gate (5), a base region (6), a source region (7), an insulating layer (3), a source electrode (8), a drain electrode (9) and a metal gate (10); the drift region (2), the base region (6), the source region (7) and the source electrode (8) are sequentially arranged above the substrate region (1), the drain electrode (9) is arranged below the substrate region (1), the control gate (5) and the shielding gate (4) are arranged on the same side of the drift region (2) from top to bottom, and the control gate (5) is respectively attached to the base region (6) and the source region (7) through the insulating layer (3), and the shielding gate (4) is attached to the drift region (2) through the insulating layer (3); The doping types of the substrate region (1), the drift region (2) and the source region (7) are all the first doping type; the doping type of the base region (6) is the second doping type; The doping concentrations of the substrate region (1) and the source region (7) are both greater than the doping concentration of the drift region; the base region (6) comprises a plurality of doping distribution layers distributed from top to bottom; the doping concentrations of the plurality of doping distribution layers decrease linearly from top to bottom; Among the plurality of doping distribution layers, each doping distribution layer has the same thickness.

2. The shielded gate trench field effect transistor with a variable doping structure according to claim 1, characterized in that: The thickness of the doping distribution layer is 0.5 μm.

3. The shielded gate trench field effect transistor with variable doping structure according to claim 1, characterized in that: The base region (6) comprises a first doping distribution layer (61), a second doping distribution layer (62) and a third doping distribution layer (63) distributed from top to bottom.

4. The shielded gate trench field effect transistor with a variable doping structure according to claim 3, characterized in that: The value range of the first doping distribution layer (61) is 1×10 17 cm -3 to 5×10 18 cm -3 The value range of the third doping distribution layer (63) is 1×10 15 cm -3 to 5×10 16 cm -3 .

5. A method for preparing a shielded gate trench field effect transistor with a variable doping structure, characterized in that: For preparing the shielded gate trench field effect transistor with variable doping structure according to any one of claims 1 to 4, comprising: preparing a substrate region with a semiconductor material of a first doping type; forming a drain at the bottom of the substrate region; epitaxially forming a drift region on the substrate region using a semiconductor material of a first doping type; forming a plurality of doping distribution layers on the drift region using a semiconductor material of a second doping type with a linearly increasing doping concentration to obtain a base region; Etching grooves on the drift region and the substrate region; Depositing oxide, polysilicon, oxide and polysilicon in sequence in the trench to form an insulating layer, a shielding gate and a control gate; Doping the substrate region with a semiconductor material of a first doping type to form a source region and a source electrode; A metal gate is prepared above the trench; A drain electrode is formed below the substrate region to obtain the shielded gate trench field effect transistor with a variable doping structure; Among the plurality of doping distribution layers, each doping distribution layer has the same thickness.

6. The method for preparing a shielded gate trench field effect transistor with a variable doping structure according to claim 5, characterized in that: The method of forming a plurality of doping distribution layers on the drift region using a semiconductor material of a second doping type with a linearly increasing doping concentration to obtain a base region comprises: On the drift region, the plurality of doping distribution layers are formed in sequence using a second doping type semiconductor material with linearly increasing doping concentration by ion implantation, diffusion or epitaxial growth to obtain a base region.

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