Display substrate and display device

Abstract

The display substrate and display device provided by the present disclosure include: a base substrate having a display area and a non-display area, a transistor located in the display area, and a pressure-sensitive touch virtual key located in the non-display area, wherein the pressure-sensitive touch virtual key includes at least one first piezoresistor, at least one second piezoresistor, at least one third piezoresistor, and at least one fourth piezoresistor, and the pressure-sensitive touch virtual key is arranged in the same layer as the active layer of the transistor; the first end of the first piezoresistor is electrically connected to the first end of the second piezoresistor, the second end of the first piezoresistor is electrically connected to the first end of the fourth piezoresistor, the first end of the third piezoresistor is electrically connected to the second end of the second piezoresistor, and the second end of the third piezoresistor is electrically connected to the second end of the fourth piezoresistor.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] As mobile phone designs evolve towards ultra-thin, full-screen, and borderless designs, the number of physical buttons is decreasing. From the disappearance of number keys to the disappearance of the Home button, both have been replaced by touch technology. As 3D screens cover ever-larger edges and phone thicknesses continue to decrease, the lack of space for physical side buttons is becoming increasingly prominent.

[0003] There are generally two current improvement solutions. One is to use the edge area of ​​the touch screen as a virtual button, that is, through a certain wake-up method (such as tapping twice) to display the virtual button on the screen, and then operate it through the touch screen. This method is prone to problems such as accidental touch and complicated operation, especially the feedback in the black screen standby state. The other is a pressure sensor solution, which attaches the pressure sensor module to the inner wall of the middle frame of the whole machine, and triggers the pressure sensor by pressing the deformation caused by the middle frame to realize the virtual button on the side. The disadvantage of this method is that it is limited by the physical space of the middle frame. For example, there is not enough space to reserve a pressure sensing module on ultra-thin products. In addition, the pressure sensing of the module itself will increase the cost, increase the difficulty of the whole machine process and increase the defect rate. Summary of the Invention

[0004] The embodiments of the present disclosure provide a display substrate and a display device, which are used to improve the problems of side buttons in the prior art, such as false touches, insensitive feedback, increased cost and process difficulty.

[0005] Therefore, an embodiment of the present disclosure provides a display substrate, comprising:

[0006] a base substrate, the base substrate comprising a display area and a non-display area located on at least one side of the display area;

[0007] a transistor, located in the display area;

[0008] A pressure-sensitive touch virtual key is located in the non-display area, and the pressure-sensitive touch virtual key includes at least one first piezoresistor, at least one second piezoresistor, at least one third piezoresistor and at least one fourth piezoresistor, wherein the at least one first piezoresistor, the at least one second piezoresistor, the at least one third piezoresistor and the at least one fourth piezoresistor are arranged in the same layer as the active layer of the transistor; the first end of the first piezoresistor is electrically connected to the first end of the second piezoresistor, the second end of the first piezoresistor is electrically connected to the first end of the fourth piezoresistor, the first end of the third piezoresistor is electrically connected to the second end of the second piezoresistor, and the second end of the third piezoresistor is electrically connected to the second end of the fourth piezoresistor.

[0009] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the first varistor has the same resistance value as the third varistor, the second varistor has the same resistance value as the fourth varistor, and the first varistor has a different resistance value than the second varistor.

[0010] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the pressure-sensitive touch virtual key includes a plurality of the first pressure-sensitive resistors, a plurality of the second pressure-sensitive resistors, a plurality of the third pressure-sensitive resistors and a plurality of the fourth pressure-sensitive resistors; wherein, each of the first pressure-sensitive resistors is arranged in parallel, each of the second pressure-sensitive resistors is arranged in parallel, each of the third pressure-sensitive resistors is arranged in parallel, and each of the fourth pressure-sensitive resistors is arranged in parallel.

[0011] In some embodiments, the display substrate provided in the embodiments of the present disclosure further includes: a first wiring, a second wiring, a third wiring, and a fourth wiring, wherein:

[0012] The first routing is electrically connected to the second end of the first varistor and the first end of the fourth varistor, the second routing is electrically connected to the second end of the third varistor and the second end of the fourth varistor, the third routing is electrically connected to the second end of the second varistor and the first end of the third varistor, and the fourth routing is electrically connected to the first end of the first varistor and the first end of the second varistor.

[0013] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, each of the first varistors, each of the second varistors, each of the third varistors, and each of the fourth varistors are arranged in sequence in the first direction, and each of the first varistors and each of the third varistors are arranged side by side in the second direction, and the at least one second varistor is located between the at least one first varistor and the at least one fourth varistor, wherein the first direction and the second direction are perpendicular to each other.

[0014] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, the first piezoresistor and the third piezoresistor each include: at least two first subsections and at least one second subsection, wherein each of the first subsections extends along the first direction, each of the second subsections extends along the second direction, and each of the first subsections is sequentially connected through each of the second subsections;

[0015] The second varistor and the fourth varistor respectively include: at least one third division, at least one fourth division and at least one fifth division, wherein each third division extends along a third direction, each fourth division extends along a fourth direction, each fifth division extends along the first direction, and each third division is connected to each fourth division in sequence through each fifth division; wherein the third direction is respectively intersected with the first direction and the second direction, the fourth direction is respectively intersected with the first direction and the second direction, and the third direction and the fourth direction intersect at an acute angle.

[0016] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, the lengths of the first piezoresistor and the third piezoresistor in the first direction are both greater than or equal to 55 μm and less than or equal to 165 μm, and the widths of the first piezoresistor and the third piezoresistor in the second direction are both greater than or equal to 25 μm and less than or equal to 75 μm; the line widths of the first subsection and the second subsection are both greater than or equal to 2.5 μm and less than or equal to 7.5 μm, and the spacing between two adjacent first subsections in the second direction is greater than or equal to 2.5 μm and less than or equal to 7.5 μm;

[0017] The lengths of the second varistor and the fourth varistor in the first direction are both greater than or equal to 50 μm and less than or equal to 150 μm, and the widths of the second varistor and the fourth varistor in the second direction are both greater than or equal to 50 μm and less than or equal to 150 μm; the line widths of the third section, the fourth section and the fifth section are all greater than or equal to 1.7 μm and less than or equal to 5.2 μm, and the angle between the third direction and the fourth direction is greater than or equal to 5° and less than or equal to 15°.

[0018] In some embodiments, in the display substrate provided by an embodiment of the present disclosure, the first wiring is located between the pressure-sensitive touch virtual key and the display area, and the first wiring is electrically connected to the second end of each of the first piezoresistors and the first end of each of the fourth piezoresistors;

[0019] The second routing includes a first sub-routing, a second sub-routing, and a third sub-routing that are sequentially arranged, wherein the first sub-routing is located between the first routing and the display area, the second sub-routing is located on a side of the at least one fourth piezoresistor away from the at least one second piezoresistor, the third sub-routing is located on a side of the pressure-sensitive touch virtual key away from the display area, and the third sub-routing is electrically connected to the second end of each of the third piezoresistors and the second end of each of the fourth piezoresistors;

[0020] The third routing includes a fourth sub-routing, a fifth sub-routing, a sixth sub-routing, a seventh sub-routing, an eighth sub-routing, a ninth sub-routing, and a tenth sub-routing, which are sequentially arranged, wherein the fourth sub-routing is located between the second routing and the display area, the fifth sub-routing is located on a side of the second routing away from the at least one second piezoresistor, the sixth sub-routing is located on a side of the third sub-routing away from the display area, the seventh sub-routing is located on a side of the at least one third piezoresistor away from the at least one second piezoresistor, the eighth sub-routing is located between the at least one first piezoresistor and the at least one third piezoresistor, the ninth sub-routing is located between the at least one third piezoresistor and the at least one second piezoresistor, the tenth sub-routing is located between the at least one second piezoresistor and the third sub-routing, and the tenth sub-routing is electrically connected to the second end of each of the second piezoresistors, and the eighth and ninth sub-routing are electrically connected to the first end of each of the third piezoresistors;

[0021] The fourth routing includes an eleventh sub-routing, a twelfth sub-routing, a thirteenth sub-routing and a fourteenth sub-routing, which are arranged in sequence, wherein the eleventh sub-routing is located on a side of the seventh sub-routing away from the at least one third piezoresistor, the twelfth sub-routing is located between the fifth sub-routing and the at least one first piezoresistor, the thirteenth sub-routing is located between the at least one first piezoresistor and the at least one second piezoresistor, and the fourteenth sub-routing is located between the at least one second piezoresistor and the first routing, and the twelfth sub-routing and the thirteenth sub-routing are electrically connected to the first end of each first piezoresistor, and the fourteenth sub-routing is electrically connected to the first end of each second piezoresistor.

[0022] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the at least one third varistor, the at least one first varistor, the at least one second varistor and the at least one fourth varistor are arranged sequentially in the first direction, and the first varistor, the second varistor, the third varistor and the fourth varistor all extend along the second direction.

[0023] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, the lengths of the first piezoresistor and the third piezoresistor in the second direction are both greater than or equal to 50 μm and less than or equal to 150 μm, and the widths of the first piezoresistor and the third piezoresistor in the first direction are both greater than or equal to 2.5 μm and less than or equal to 7.5 μm;

[0024] The lengths of the second varistor and the fourth varistor in the second direction are both greater than or equal to 40 μm and less than or equal to 120 μm, and the widths of the second varistor and the fourth varistor in the first direction are both greater than or equal to 2.5 μm and less than or equal to 7.5 μm.

[0025] In some embodiments, in the display substrate provided in the embodiments of the present disclosure, the first routing includes a fifteenth sub-routing, a sixteenth sub-routing, a seventeenth sub-routing, an eighteenth sub-routing, and a nineteenth sub-routing, which are sequentially arranged, wherein the fifteenth sub-routing is located between the pressure-sensitive touch virtual key and the display area, the sixteenth sub-routing is located on a side of the at least one fourth piezoresistor away from the at least one second piezoresistor, the seventeenth sub-routing is located on a side of the at least one fourth piezoresistor away from the display area, the eighteenth sub-routing is located between the at least one fourth piezoresistor and the at least one second piezoresistor, the nineteenth sub-routing is located between the at least one first piezoresistor and the display area, the seventeenth sub-routing is electrically connected to the first end of each of the fourth piezoresistors, and the nineteenth sub-routing is electrically connected to the second end of each of the first piezoresistors;

[0026] The second wiring is located between the nineteenth sub-wiring and the display area, and the second wiring is electrically connected to the second end of each of the third varistors and the second end of each of the fourth varistors;

[0027] The third routing includes a 20th sub-routing, a 21st sub-routing, and a 22nd sub-routing that are sequentially arranged, wherein the 20th sub-routing is located between the second routing and the display area, the 21st sub-routing is located on a side of the at least one third piezoresistor away from the at least one first piezoresistor, and the 22nd sub-routing is located on a side of the pressure-sensitive touch virtual key away from the display area, and the 22nd sub-routing is electrically connected to the second end of each of the second piezoresistors and the first end of each of the third piezoresistors;

[0028] The fourth routing includes a twenty-third sub-route, a twenty-fourth sub-route, a twenty-fifth sub-route, a twenty-sixth sub-route and a twenty-seventh sub-route which are arranged in sequence, wherein the twenty-third sub-route is located on the side of the pressure-sensitive touch virtual key away from the display area, the twenty-fourth sub-route is located between the eighteenth sub-route and the at least one second pressure-sensitive resistor, the twenty-fifth sub-route is located between the twenty-tenth sub-route and the at least one second pressure-sensitive resistor, the twenty-sixth sub-route is located between the at least one second pressure-sensitive resistor and the at least one first pressure-sensitive resistor, the twenty-seventh sub-route is located between the twenty-second sub-route and the at least one first pressure-sensitive resistor, the twenty-fifth sub-route is electrically connected to the first end of each of the second pressure-sensitive resistors, and the twenty-seventh sub-route is electrically connected to the first end of each of the first pressure-sensitive resistors.

[0029] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the first varistor, the second varistor, the third varistor and the fourth varistor all extend along the first direction, the at least one first varistor is located between the at least one third varistor and the display area, and the at least one second varistor is located between the at least one fourth varistor and the display area.

[0030] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, the lengths of the first piezoresistor and the third piezoresistor in the first direction are both greater than or equal to 55 μm and less than or equal to 165 μm, and the widths of the first piezoresistor and the third piezoresistor in the second direction are both greater than or equal to 5 μm and less than or equal to 15 μm;

[0031] The lengths of the second varistor and the fourth varistor in the first direction are both greater than or equal to 175 μm and less than or equal to 525 μm, and the widths of the second varistor and the fourth varistor in the second direction are both greater than or equal to 10 μm and less than or equal to 30 μm.

[0032] In some embodiments, in the display substrate provided in the embodiments of the present disclosure, the first routing line includes a twenty-eighth sub-routing line and a twenty-ninth sub-routing line that are sequentially arranged, wherein the twenty-eighth sub-routing line is located between the pressure-sensitive touch virtual key and the display area, the twenty-ninth sub-routing line is located on a side of the at least one fourth piezoresistor away from the at least one third piezoresistor, the twenty-eighth sub-routing line is electrically connected to the second end of each of the first piezoresistors, and the twenty-ninth sub-routing line is electrically connected to the first end of each of the fourth piezoresistors;

[0033] The second routing includes a 30th sub-routing, a 31st sub-routing, and a 32nd sub-routing that are sequentially arranged, wherein the 30th sub-routing is located between the 28th sub-routing and the display area, the 31st sub-routing is located on a side of the 29th sub-routing away from the pressure-sensitive touch virtual key, the 32nd sub-routing is located on a side of the pressure-sensitive touch virtual key away from the display area, and the 32nd sub-routing is electrically connected to the second end of each of the third piezoresistors and the second end of each of the fourth piezoresistors;

[0034] The third routing includes a thirty-third sub-routing, a thirty-fourth sub-routing, a thirty-fifth sub-routing, and a thirty-sixth sub-routing, which are sequentially arranged, wherein the thirty-third sub-routing is located between the 30th sub-routing and the display area, the thirty-fourth sub-routing is located on a side of the thirty-first sub-routing away from the pressure-sensitive touch virtual key, the thirty-fifth sub-routing is located on a side of the at least one third piezoresistor away from the at least one fourth piezoresistor, the thirty-seventh sub-routing is located between the at least one first piezoresistor and the at least one third piezoresistor, and the thirty-seventh sub-routing is electrically connected to the second end of each of the second piezoresistors and the first end of each of the third piezoresistors;

[0035] The fourth route includes a thirty-eighth sub-route, a thirty-ninth sub-route, a fortieth sub-route, a forty-first sub-route and a forty-second sub-route which are arranged in sequence, wherein the thirty-eighth sub-route is located on the side of the pressure-sensitive touch virtual key away from the display area, the thirty-ninth sub-route is located on the side of the thirty-fifth sub-route away from the pressure-sensitive touch virtual key, the fortieth sub-route is located between the thirty-seventh sub-route and the at least one first pressure-sensitive resistor, the forty-first sub-route is located between the at least one second pressure-sensitive resistor and the at least one first pressure-sensitive resistor, the forty-second sub-route is located between the twenty-eighth sub-route and the at least one second pressure-sensitive resistor, the forty-first sub-route is electrically connected to the first end of each of the first pressure-sensitive resistors, and the forty-second sub-route is electrically connected to the first end of each of the second pressure-sensitive resistors.

[0036] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the line widths of the first routing line, the second routing line, the third routing line and the fourth routing line are all greater than or equal to 2.5 μm and less than or equal to 7.5 μm, and the line spacing is greater than or equal to 1 μm and less than or equal to 4.5 μm.

[0037] In some embodiments, the display substrate provided in the embodiments of the present disclosure further includes: a first bridge line, a second bridge line, a third bridge line, a fourth bridge line, a fifth bridge line, a sixth bridge line, a seventh bridge line, and an eighth bridge line, wherein:

[0038] The first bridge wire is connected between the first routing line and the second end of the first piezoresistor, the second bridge wire is connected between the first routing line and the first end of the fourth piezoresistor, the third bridge wire is connected between the second routing line and the second end of the third piezoresistor, the fourth bridge wire is connected between the second routing line and the second end of the fourth piezoresistor, the fifth bridge wire is connected between the third routing line and the second end of the second piezoresistor, the sixth bridge wire is connected between the third routing line and the first end of the third piezoresistor, the seventh bridge wire is connected between the fourth routing line and the first end of the first piezoresistor, and the eighth bridge wire is connected between the fourth routing line and the first end of the second piezoresistor.

[0039] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, the first routing line, the second routing line, the third routing line, and the fourth routing line are all provided on the same layer as the gate of the transistor;

[0040] The first bridge wire, the second bridge wire, the third bridge wire, the fourth bridge wire, the fifth bridge wire, the sixth bridge wire, the seventh bridge wire, and the eighth bridge wire are all provided in the same layer as the source and drain of the transistor.

[0041] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the layer where the gate of the transistor is located is located between the active layer of the transistor and the layer where the source and drain of the transistor are located, and the material of the active layer of the transistor includes low-temperature polysilicon.

[0042] In some embodiments, the display substrate provided in the embodiments of the present disclosure further includes a ground line provided in the same layer as the gate of the transistor, and the ground line surrounds the third wiring.

[0043] In some embodiments, in the above-mentioned display substrate provided by the embodiments of the present disclosure, the pressure-sensitive touch virtual key is at least one of a power key, a volume key, and a game key.

[0044] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, including a display substrate, a power supply, and a pressure sensing chip, wherein the display substrate is the above-mentioned display substrate provided in the embodiment of the present disclosure;

[0045] The first end of the first varistor and the first end of the second varistor are both electrically connected to the positive electrode of the power supply;

[0046] The second end of the third varistor and the second end of the fourth varistor are both electrically connected to the negative electrode of the power supply;

[0047] The second end of the first piezoresistor and the first end of the fourth piezoresistor are both electrically connected to the first test end of the pressure sensing chip;

[0048] The second end of the second piezoresistor and the first end of the third piezoresistor are both electrically connected to the second test end of the pressure sensing chip.

[0049] The beneficial effects of the present disclosure are as follows:

[0050] The display substrate and display device provided by the embodiments of the present disclosure include a base substrate, which includes a display area and a non-display area located on at least one side of the display area; a transistor located in the display area; a pressure-sensitive touch virtual key located in the non-display area, and the pressure-sensitive touch virtual key includes at least one first piezoresistor, at least one second piezoresistor, at least one third piezoresistor and at least one fourth piezoresistor, wherein the at least one first piezoresistor, at least one second piezoresistor, at least one third piezoresistor and at least one fourth piezoresistor are arranged in the same layer as the active layer of the transistor; the first end of the first piezoresistor is electrically connected to the first end of the second piezoresistor, the second end of the first piezoresistor is electrically connected to the first end of the fourth piezoresistor, the first end of the third piezoresistor is electrically connected to the second end of the second piezoresistor, and the second end of the third piezoresistor is electrically connected to the second end of the fourth piezoresistor. The present invention utilizes the semiconductor piezoresistive effect of the active layer of a transistor to create a pressure-sensitive touch virtual key in the non-display area using the material of the active layer. The first, second, third, and fourth piezoresistors of the pressure-sensitive touch virtual key are connected in a Wheatstone bridge configuration. When pressed, the first, second, third, and fourth piezoresistors deform, causing their resistance to change. This resistance change causes a current change, and touch feedback is achieved by identifying the current change. This internal integration of the pressure-sensitive touch virtual key eliminates the need for a separate pressure-sensing module, and the Wheatstone bridge circuit offers high accuracy and sensitivity. Therefore, it effectively overcomes existing side key issues such as false touches, insensitive feedback, and increased cost and process difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 A schematic structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0052] Figure 2 A schematic diagram of another structure of a display substrate provided in an embodiment of the present disclosure;

[0053] Figure 3 A schematic diagram of the structure of a pressure-sensitive touch virtual key provided in an embodiment of the present disclosure;

[0054] Figure 4 A schematic diagram of another structure of a display substrate provided in an embodiment of the present disclosure;

[0055] Figure 5 for Figure 3 The equivalent circuit diagram of the pressure-sensitive touch virtual button shown;

[0056] Figure 6 A schematic diagram of a pressure-sensitive touch virtual key identifying a touch press provided by an embodiment of the present disclosure;

[0057] Figure 7 A schematic diagram of another structure of a pressure-sensitive touch virtual key provided in an embodiment of the present disclosure;

[0058] Figure 8 A schematic diagram of another structure of a pressure-sensitive touch virtual key provided in an embodiment of the present disclosure;

[0059] Figure 9 for Figure 7 and Figure 8 The equivalent circuit diagram of the pressure-sensitive touch virtual button shown;

[0060] Figure 10 for Figure 3 A partial enlarged view of the pressure-sensitive touch virtual button shown;

[0061] Figure 11 for Figure 3 A schematic diagram showing the connection between the first trace and the pressure-sensitive touch virtual button;

[0062] Figure 12 for Figure 3 Schematic diagram of the connection between the second trace and the pressure-sensitive touch virtual button;

[0063] Figure 13 for Figure 3 Schematic diagram of the connection between the third trace and the pressure-sensitive touch virtual button;

[0064] Figure 14 for Figure 3 Schematic diagram of the connection between the fourth trace and the pressure-sensitive touch virtual button;

[0065] Figure 15 for Figure 7 A schematic diagram showing the connection between the first trace and the pressure-sensitive touch virtual button;

[0066] Figure 16 for Figure 7 Schematic diagram of the connection between the second trace and the pressure-sensitive touch virtual button;

[0067] Figure 17 for Figure 7 Schematic diagram of the connection between the third trace and the pressure-sensitive touch virtual button;

[0068] Figure 18 for Figure 7 Schematic diagram of the connection between the fourth trace and the pressure-sensitive touch virtual button;

[0069] Figure 19 for Figure 8 A schematic diagram showing the connection between the first trace and the pressure-sensitive touch virtual button;

[0070] Figure 20 for Figure 8 Schematic diagram of the connection between the second trace and the pressure-sensitive touch virtual button;

[0071] Figure 21 for Figure 8 Schematic diagram of the connection between the third trace and the pressure-sensitive touch virtual button;

[0072] Figure 22 for Figure 8 Schematic diagram of the connection between the fourth trace and the pressure-sensitive touch virtual button. DETAILED DESCRIPTION

[0073] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that the sizes and shapes of the figures in the drawings do not reflect the actual scale and are only intended to illustrate the contents of the present disclosure. Throughout, the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions.

[0074] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in this disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0075] The embodiment of the present disclosure provides a display substrate, such as Figures 1 to 4 Shown, including:

[0076] A base substrate 101, the base substrate 101 including a display area AA and a non-display area BB located on at least one side of the display area AA;

[0077] Transistor 102, located in display area AA;

[0078] The pressure-sensitive touch virtual key 103 is located in the non-display area BB. The pressure-sensitive touch virtual key 103 includes at least one first pressure-sensitive resistor (for example, T1, T1'), at least one second pressure-sensitive resistor (for example, R1, R1'), at least one third pressure-sensitive resistor (for example, T2, T2') and at least one fourth pressure-sensitive resistor (for example, R2, R2'). R2') is arranged in the same layer as the active layer of the transistor 102; the first end of the first varistor (for example, T1, T1') is electrically connected to the first end of the second varistor (for example, R1, R1'), the second end of the first varistor (for example, T1, T1') is electrically connected to the first end of the fourth varistor (for example, R2, R2'), the first end of the third varistor (for example, T2, T2') is electrically connected to the second end of the second varistor (for example, R1, R1'), and the second end of the third varistor (for example, T2, T2') is electrically connected to the second end of the fourth varistor (for example, R2, R2').

[0079] In the above-mentioned display substrate provided in the embodiment of the present disclosure, if Figures 4 to 6As shown, the semiconductor piezoresistive effect of the active layer of the transistor 102 is utilized to manufacture a pressure-sensitive touch virtual key 103 using the material of the active layer in the non-display area BB, and the first piezoresistor (e.g., T1, T1'), the second piezoresistor (e.g., R1, R1'), the third piezoresistor (e.g., T2, T2'), and the fourth piezoresistor (e.g., R2, R2') of the pressure-sensitive touch virtual key 103 are configured to be connected in a Wheatstone bridge manner. When pressed, the first piezoresistor (e.g., T1, T1'), the second piezoresistor (e.g., R1, R1'), the third piezoresistor (e.g., T2, T2'), and the fourth piezoresistor (e.g., R2, R2') are deformed, causing their resistance to change. The resistance change causes the current to change, and touch feedback can be achieved by identifying the change in current. This method of internalizing the pressure-sensitive touch virtual button 103 eliminates the need for a separate pressure-sensitive module, and the Wheatstone bridge is a circuit with high accuracy and sensitivity. Therefore, it effectively improves the problems of side buttons in the existing technology, such as false touches, insensitive feedback, increased cost and process difficulty, etc., increases the added value of the display substrate, and meets the future needs of integration.

[0080] It should be noted that in this disclosure, "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for producing a specific pattern, and then using the same mask through a single patterning process. That is, one patterning process corresponds to one mask (also known as a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or at different heights or have different thicknesses.

[0081] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, in order to improve touch sensitivity, the first piezoresistor (for example, T1, T1') and the third piezoresistor (for example, T2, T2') have the same resistance value, the second piezoresistor (for example, R1, R1') and the fourth piezoresistor (for example, R2, R2') have the same resistance value, and the first piezoresistor (for example, T1, T1') and the second piezoresistor (for example, R1, R1') have different resistance values.

[0082] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 3 and Figure 5As shown, the pressure-sensitive touch virtual key 103 may include multiple first pressure-sensitive resistors (e.g., T1, T1'), multiple second pressure-sensitive resistors (e.g., R1, R1'), multiple third pressure-sensitive resistors (e.g., T2, T2'), and multiple fourth pressure-sensitive resistors (e.g., R2, R2'); wherein each first pressure-sensitive resistor (e.g., T1, T1') is arranged in parallel, each second pressure-sensitive resistor (e.g., R1, R1') is arranged in parallel, each third pressure-sensitive resistor (e.g., T2, T2') is arranged in parallel, and each fourth pressure-sensitive resistor (e.g., R2, R2') is arranged in parallel. This arrangement can effectively reduce resistance and improve touch sensitivity.

[0083] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 3 、 Figure 7 and Figure 8 As shown, it may also include: a first line L1, a second line L2, a third line L3 and a fourth line L P , wherein the first trace L1 is electrically connected to the second end of the first varistor (for example, T1, T1') and the first end of the fourth varistor (for example, R2, R2'), the second trace L2 is electrically connected to the second end of the third varistor (for example, T2, T2') and the second end of the fourth varistor (for example, R2, R2'), the third trace L3 is electrically connected to the second end of the second varistor (for example, R1, R1') and the first end of the third varistor (for example, T2, T2'), and the fourth trace L P The first end of the first piezoresistor (eg, T1, T1') and the first end of the second piezoresistor (eg, R1, R1') are electrically connected to each other through the first trace L1, the second trace L2, the third trace L3 and the fourth trace L P Realize the current change caused by touch.

[0084] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 3 As shown, each first piezoresistor (e.g., T1, T1'), each second piezoresistor (e.g., R1, R1'), each third piezoresistor (e.g., T2, T2'), and each fourth piezoresistor (e.g., R2, R2') are arranged in sequence in the first direction Y, and each first piezoresistor (e.g., T1, T1') and each third piezoresistor (e.g., T2, T2') are arranged side by side in the second direction X, and all second piezoresistors (e.g., R1, R1') are located between all first piezoresistors (e.g., T1, T1') and all fourth piezoresistors (e.g., R2, R2'). The first direction Y and the second direction X are perpendicular to each other. This arrangement is conducive to ensuring a sufficiently large touch deformation force-bearing surface. At the same time, the use of dual resistors in parallel can effectively reduce resistance and improve touch sensitivity.

[0085] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 10 As shown, the first varistor (eg, T1) and the third varistor (eg, T2) respectively include: at least two first sub-sections T 11 and at least one second subdivision T 12 , where each first division T 11 Extending along the first direction Y, each second section T 12 Extending along the second direction X, each first section T 11 Through each second division T 12 connected in sequence; the second varistor (eg, R1, R1') and the fourth varistor (eg, R2') respectively include: at least one third section R 11 , at least one fourth subdivision R 12 and at least one fifth division R 13 , among which, each third division R 11 Extending along the third direction d, each fourth section R 12 Extending along the fourth direction d', each fifth subsection R 13 Extending along the first direction Y, each third section R 11 By each Fifth Division R 13 With each fourth division R 12 connected in sequence; wherein the third direction d is arranged to intersect with the first direction Y and the second direction X, respectively, and the fourth direction d' is arranged to intersect with the first direction Y and the second direction X, respectively, and the third direction d and the fourth direction d' intersect at an acute angle θ. It can be seen that the patterns of the first piezoresistors (e.g., T1, T1'), the second piezoresistors (e.g., R1, R1'), the third piezoresistors (e.g., T2, T2'), and the fourth piezoresistors (e.g., R2, R2') are all arranged in an approximately "W" shape, so that the first piezoresistors (e.g., T1, T1'), the second piezoresistors (e.g., R1, R1'), the third piezoresistors (e.g., T2, T2'), and the fourth piezoresistors (e.g., R2, R2') can fully absorb deformation in the lateral direction (i.e., the second direction X) and the longitudinal direction (i.e., the first direction Y), thereby increasing the resistance change caused by the piezoresistive effect, and are suitable for display substrates subjected to multi-directional compressive deformation.

[0086] In some embodiments, in the above-mentioned display substrate improved in the embodiments of the present disclosure, as Figure 10As shown, the length H1 of the first varistor (for example, T1) and the third varistor (for example, T2) in the first direction Y is greater than or equal to 55 μm and less than or equal to 165 μm (for example, 110 μm), and the width W1 of the first varistor (for example, T1) and the third varistor (for example, T2) in the second direction X is greater than or equal to 25 μm and less than or equal to 75 μm (for example, 50 μm); the line width of the first subsection T11 and the second subsection T12 is greater than or equal to 2.5 μm and less than or equal to 7.5 μm (for example, 5 μm), and the width of two adjacent first subsections T11 and T12 is greater than or equal to 2.5 μm and less than or equal to 7.5 μm (for example, 5 μm). 1 The spacing width in the second direction X is greater than or equal to 2.5 μm and less than or equal to 7.5 μm (for example, 5 μm); the length H2 of the second varistor (for example, R1, R1') and the fourth varistor (for example, R2') in the first direction Y is greater than or equal to 50 μm and less than or equal to 150 μm (for example, 100 μm), and the width W2 of the second varistor (for example, R1, R1') and the fourth varistor (for example, R2, R2') in the second direction X is greater than or equal to 50 μm and less than or equal to 150 μm (for example, 100 μm); the third section R 11 、4th Division R 12 and the Fifth Division R 13 The line width is greater than or equal to 1.7 μm and less than or equal to 5.2 μm (e.g., 3.4 μm), and the angle θ between the third direction d and the fourth direction d' is greater than or equal to 5° and less than or equal to 15° (e.g., 10°). In specific implementations, the above parameters may vary depending on factors such as the stacking design, thickness, composition, and desired resistance value of the display substrate.

[0087] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 3 、 Figures 11 to 14 As shown, the first trace L1 is located between the pressure-sensitive touch virtual key 103 and the display area AA, and the first trace L1 is electrically connected to the second end of each first pressure-sensitive resistor (e.g., T1, T1') and the first end of each fourth pressure-sensitive resistor (e.g., R2, R2');

[0088] The second routing line L2 includes the first sub-routing lines L arranged in sequence 201 , the second sub-line L 202 And the third line L 203 , where the first sub-line L 201 Located between the first line L1 and the display area AA, the second sub-line L 202 Located on the side of at least one fourth varistor (eg, R2, R2') away from at least one second varistor (eg, R1, R1'), the third sub-line L 203 Located on the side of the pressure-sensitive touch virtual key 103 away from the display area AA, and the third sub-line L 203electrically connected to the second end of each third piezoresistor (e.g., T2, T2') and the second end of each fourth piezoresistor (e.g., R2, R2');

[0089] The third routing line L3 includes the fourth sub-routing lines L 301 、The fifth line L 302 、The sixth line L 303 、The seventh child's route is L 304 、The eighth sub-line L 305 、Ninth line L 306 And the tenth line L 307 , where the fourth sub-line L 301 Located between the second line L2 and the display area AA, the fifth sub-line L 302 Located on the side of the second line L2 away from at least one second varistor (eg, R1, R1'), the sixth sub-line L 303 Located on the third sub-line L 203 On the side away from the display area AA, the seventh sub-line L 304 Located on the side of at least one third varistor (eg, T2, T2') away from at least one second varistor (eg, R1, R1'), the eighth sub-line L 305 Located between at least one first piezoresistor (eg, T1, T1') and at least one third piezoresistor (eg, T2, T2'), the ninth sub-line L 306 Located between at least one third varistor (eg, T2, T2') and at least one second varistor (eg, R1, R1'), the tenth sub-line L 307 Located between at least one second varistor (eg R1, R1') and the third sub-line L 203 Between, and the tenth sub-line L 307 The eighth sub-line L is electrically connected to the second end of each second varistor (eg, R1, R1'). 305 And the ninth child's line L 306 electrically connected to the first end of each third varistor (e.g., T2, T2');

[0090] The fourth line L P Including the eleventh sub-line L arranged in sequence 401 , the twelfth sub-line L 402 、The thirteenth line L 403 and the fourteenth sub-line L 404 , among which, the eleventh sub-line L 401 Located on the seventh sub-line L 304 A side away from at least one third varistor (eg, T2, T2'), the twelfth sub-line L 402Located between the fifth sub-line and at least one first varistor (eg, T1, T1'), the thirteenth sub-line L 403 Located between at least one first piezoresistor (eg, T1, T1') and at least one second piezoresistor (eg, R1, R1'), the fourteenth sub-line L 404 Located between at least one second piezoresistor (eg, R1, R1') and the first trace L1, and the twelfth trace L 402 and the thirteenth son's line L 403 The fourteenth sub-line L is electrically connected to the first end of each first varistor (eg, T1, T1'). 404 The first terminal is electrically connected to each second varistor (eg, R1, R1').

[0091] The first line L1, the second line L2, the third line L3 and the fourth line L P The wiring method can, on the one hand, electrically connect the first varistors (e.g., T1, T1'), the second varistors (e.g., R1, R1'), the third varistors (e.g., T2, T2') and the fourth varistors (e.g., R2, R2') into a Wheatstone bridge, and on the other hand effectively avoid short circuits between different wires, while making full use of the space of the non-display area BB and utilizing a narrow frame design.

[0092] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 7 As shown, at least one third piezoresistor (e.g., T2), at least one first piezoresistor (e.g., T1), at least one second piezoresistor (e.g., R1), and at least one fourth piezoresistor (e.g., R2) are arranged sequentially in the first direction Y, and the first piezoresistor (e.g., T1), the second piezoresistor (e.g., R1), the third piezoresistor (e.g., T2), and the fourth piezoresistor (e.g., R2) all extend along the second direction X. This arrangement of the first piezoresistor (e.g., T1), the second piezoresistor (e.g., R1), the third piezoresistor (e.g., T2), and the fourth piezoresistor (e.g., R2) can enhance sensitivity to deformation in the lateral direction (i.e., the second direction X), and has a simple structural design without the need for complex patterning, making it suitable for display substrates that deform under unidirectional pressure.

[0093] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 7As shown, the lengths of the first varistor (e.g., T1) and the third varistor (e.g., T2) in the second direction X are both greater than or equal to 50 μm and less than or equal to 150 μm (e.g., 100 μm), and the widths of the first varistor (e.g., T1) and the third varistor (e.g., T2) in the first direction Y are both greater than or equal to 2.5 μm and less than or equal to 7.5 μm (e.g., 5 μm); the lengths of the second varistor (e.g., R1) and the fourth varistor (e.g., R2) in the second direction X are both greater than or equal to 40 μm and less than or equal to 120 μm (e.g., 80 μm), and the widths of the second varistor (e.g., R1) and the fourth varistor (e.g., R2) in the first direction Y are both greater than or equal to 2.5 μm and less than or equal to 7.5 μm (e.g., 5 μm). In specific implementations, the above parameters may vary depending on factors such as the stacking design, thickness, composition, and resistance value to be designed of the display substrate.

[0094] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 7 、 Figures 15 to 18 As shown, the first routing line L1 includes fifteenth sub-routing lines L arranged sequentially. 101 、16th sub-line L 102 、The 17th sub-line L 103 、The eighteenth sub-line L 104 and the 19th line L 105 , among which, the fifteenth sub-line L 101 Located between the pressure-sensitive touch virtual key 103 and the display area AA, the sixteenth sub-line L 102 Located on the side of at least one fourth piezoresistor (eg, R2) away from at least one second piezoresistor (eg, R1), the seventeenth sub-line L 103 Located on the side of at least one fourth piezoresistor (eg R2) away from the display area, the eighteenth sub-line L 104 Located between at least one fourth piezoresistor (eg, R2) and at least one second piezoresistor (eg, R1), the nineteenth sub-line L 105 Located between at least one first piezoresistor (eg, T1) and the display area AA, the seventeenth sub-line L 103 The first end of each fourth piezoresistor (eg R2) is electrically connected to the nineteenth sub-line L 105 electrically connected to the second end of each first varistor (e.g., T1);

[0095] The second line L2 is located at the nineteenth sub-line L 105 and the display area AA, and the second wiring L2 is electrically connected to the second end of each third piezoresistor (for example, T2) and the second end of each fourth piezoresistor (for example, R2);

[0096] The third routing line L3 includes the twentieth sub-routing line L1 arranged in sequence 308 、The 21st sub-line L 309 and the 22nd sub-line L 310 , among which, the 20th sub-line L 308 Located between the second line L2 and the display area AA, the twenty-first sub-line L 309 Located on the side of at least one third varistor (eg, T2) away from at least one first varistor (eg, T1), the twenty-second sub-line L 310 Located on the side of the pressure-sensitive touch virtual key 103 away from the display area AA, the twenty-second sub-line L 310 electrically connected to the second end of each second piezoresistor (e.g., R1) and the first end of each third piezoresistor (e.g., T2);

[0097] The fourth line L P Including the 23rd sub-line L arranged in sequence 405 、The 24th sub-line L 406 、The 25th sub-line L 407 、The 26th sub-line L 408 and the twenty-seventh sub-line L 409 , among which, the 23rd sub-line L 405 Located on the pressure-sensitive touch virtual button L 103 On the side away from the display area AA, the twenty-fourth sub-line L 406 Located on the 18th sub-line L 104 Between at least one second varistor (eg, R1), the twenty-fifth sub-line L 407 Located on the 20th sub-line L 308 Between at least one second varistor (eg, R1), the twenty-sixth sub-line L 408 Located between at least one second piezoresistor (eg, R1) and at least one first piezoresistor (eg, T1), the twenty-seventh sub-line L 409 Located on the 22nd sub-line L 310 Between at least one first varistor (eg, T1), the twenty-fifth sub-line L 407 The twenty-seventh sub-line L is electrically connected to the first end of each second varistor (eg, R1). 409 The first terminal is electrically connected to each first varistor (eg, T1 ).

[0098] The first line L1, the second line L2, the third line L3 and the fourth line L PThe wiring method can, on the one hand, electrically connect the first varistor (e.g., T1), the second varistor (e.g., R1), the third varistor (e.g., T2), and the fourth varistor (e.g., R2) into a Wheatstone bridge, and on the other hand effectively avoid short circuits between different wires, while making full use of the space of the non-display area BB and utilizing a narrow frame design.

[0099] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 8 As shown, the first varistor (e.g., T1), the second varistor (e.g., R1), the third varistor (e.g., T2), and the fourth varistor (e.g., R2) all extend along the first direction Y. At least one first varistor (e.g., T1) is located between at least one third varistor (e.g., T2) and the display area AA, and at least one second varistor (e.g., R1) is located between at least one fourth varistor (e.g., R2) and the display area AA. 1) The second piezoresistor (e.g., R1), the third piezoresistor (e.g., T2), and the fourth piezoresistor (e.g., R2) can enhance the sensitivity to longitudinal deformation (i.e., the first direction Y), and the structural design is simple without the need for complex patterning, and is suitable for display substrates that are deformed in one direction under pressure.

[0100] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 8 As shown, the lengths of the first varistor (e.g., T1) and the third varistor (e.g., T2) in the first direction Y are both greater than or equal to 55 μm and less than or equal to 165 μm (e.g., 110 μm), and the widths of the first varistor (e.g., T1) and the third varistor (e.g., T2) in the second direction X are both greater than or equal to 5 μm and less than or equal to 15 μm (e.g., 10 μm); the lengths of the second varistor (e.g., R1) and the fourth varistor (e.g., R2) in the first direction Y are both greater than or equal to 175 μm and less than or equal to 525 μm (e.g., 350 μm), and the widths of the second varistor (e.g., R1) and the fourth varistor (e.g., R2) in the second direction X are both greater than or equal to 10 μm and less than or equal to 30 μm (e.g., 20 μm). In specific implementations, the above parameters may vary depending on factors such as the stacking design, thickness, composition, and resistance value to be designed of the display substrate.

[0101] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 8 、 Figures 19 to 22 As shown, the first routing line L1 includes the twenty-eighth sub-routing lines L arranged sequentially. 106 and the twenty-ninth sub-line L 107 , among which, the 28th sub-line L 106Located between the pressure-sensitive touch virtual key 103 and the display area AA, the twenty-ninth sub-line L 107 Located on the side of at least one fourth varistor (eg, R2) away from at least one third varistor (eg, T2), the twenty-eighth sub-line L 106 The twenty-ninth sub-line L is electrically connected to the second end of each first varistor (eg, T1). 107 electrically connected to the first end of each fourth varistor (e.g., R2);

[0102] The second routing line L2 includes a thirtieth sub-routing line L2 which is arranged in sequence. 204 、The 31st sub-line L 205 and the 32nd sub-line L 206 , among which, the 30th sub-line L 204 Located on the 28th sub-line L 106 Between the display area AA, the thirty-first sub-line L 205 Located on the 29th sub-line L 107 Aside from the pressure-sensitive touch virtual button 103, the 32nd sub-line L 206 Located on the side of the pressure-sensitive touch virtual key 103 away from the display area AA, the thirty-second sub-line L 206 electrically connected to the second end of each third piezoresistor (e.g., T2) and the second end of each fourth piezoresistor (e.g., R2);

[0103] The third routing line L3 includes a thirty-third sub-routing line L3 which is arranged in sequence 311 、The 34th sub-line L 312 、The 35th sub-line L 313 、The 36th sub-line L 314 and the 37th child's line L 315 , among which, the thirty-third sub-line L 311 Located on the 30th sub-line L 204 Between the display area AA, the thirty-fourth sub-line L 312 Located on the 31st sub-line L 205 Away from the side of the pressure-sensitive touch virtual button 103, the thirty-fifth sub-line L 313 Located on the 33rd sub-line L 206 On the side away from the display area AA, the thirty-sixth sub-line L 314 Located on the side of at least one third varistor (eg, T2) away from at least one fourth varistor (eg, R2), the thirty-seventh sub-line L 315 Located between at least one first piezoresistor (eg, T1) and at least one third piezoresistor (eg, T2), the thirty-seventh sub-line L 315electrically connected to the second end of each second piezoresistor (e.g., R1) and the first end of each third piezoresistor (e.g., T2);

[0104] The fourth line L P Including the 38th sub-line L arranged in sequence 410 、The 39th child's route L 411 、40th sub-line L 412 、The 41st sub-line L 413 and the 42nd sub-line L 414 , among which, the 38th sub-line L 410 Located on the side of the pressure-sensitive touch virtual key 103 away from the display area AA, the thirty-ninth sub-line L 411 Located on the 35th sub-line L 313 Away from the side of the pressure-sensitive touch virtual button 103, the fortieth sub-line L 412 Located on the 37th sub-line L 315 Between at least one first piezoresistor (eg, T1), the forty-first sub-line L 413 Located between at least one second piezoresistor (eg, R1) and at least one first piezoresistor (eg, T1), the forty-second sub-line L 414 Located on the 28th sub-line L 106 Between at least one second varistor (eg, R1), the forty-first sub-line L 413 The forty-second sub-line L is electrically connected to the first end of each first varistor (eg, T1). 414 The first terminal is electrically connected to each second varistor (eg, R1 ).

[0105] The first line L1, the second line L2, the third line L3 and the fourth line L P The wiring method can, on the one hand, electrically connect the first varistor (e.g., T1), the second varistor (e.g., R1), the third varistor (e.g., T2), and the fourth varistor (e.g., R2) into a Wheatstone bridge, and on the other hand effectively avoid short circuits between different wires, while making full use of the space of the non-display area BB and utilizing a narrow frame design.

[0106] In some embodiments, in the display substrate provided in the embodiment of the present disclosure, in order to avoid short circuits between adjacent lines and ensure that the signal loss on each line is small, a first line L1, a second line L2, a third line L3 and a fourth line L4 can be provided. P The line width is greater than or equal to 2.5 μm and less than or equal to 7.5 μm (for example, 5 μm), and the line spacing is greater than or equal to 1 μm and less than or equal to 4.5 μm (for example, 2 μm, 3 μm, etc.).

[0107] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figures 11 to 22 As shown, it may also include: a first bridge wire C1, a second bridge wire C2, a third bridge wire C3, a fourth bridge wire C4, a fifth bridge wire C5, a sixth bridge wire C6, a seventh bridge wire C7 and an eighth bridge wire C8, wherein the first bridge wire C1 is connected between the first wire L1 and the second end of the first varistor (for example, T1, T1'), the second bridge wire C2 is connected between the first wire L1 and the first end of the fourth varistor (for example, R2, R2'), the third bridge wire C3 is connected between the second wire L2 and the second end of the third varistor (for example, T2, T2'), the fourth bridge wire C4 is connected between the second wire L2 and the second end of the fourth varistor (for example, R2, R2'), the fifth bridge wire C5 is connected between the third wire L3 and the second end of the second varistor (for example, R1, R1'), the sixth bridge wire C6 is connected between the third wire L3 and the first end of the third varistor (for example, T2, T2'), and the seventh bridge wire C7 is connected between the fourth wire L P The eighth bridge line C8 is connected to the fourth trace L between the first end of the first varistor (eg, T1, T1') and the first end of the first varistor (eg, T1, T1'). P In this way, each varistor, each trace, and each bridge wire can be respectively arranged in different film layers to fully utilize the space of the non-display area BB and ensure a narrow frame.

[0108] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 4 As shown, the first line L1, the second line L2, the third line L3 and the fourth line L PAll are provided on the same layer as the gate of transistor 102; the first bridge wire C1, the second bridge wire C2, the third bridge wire C3, the fourth bridge wire C4, the fifth bridge wire C5, the sixth bridge wire C6, the seventh bridge wire C7, and the eighth bridge wire C8 are all provided on the same layer as the source and drain of transistor 102. This on-layer arrangement avoids the need for separate fabrication processes for routing and bridge wires, saving costs and enabling a lightweight design. Furthermore, since the layer where the gate of transistor 102 is located is relatively close to the active layer of transistor 102, the excellent conductivity of the metal (e.g., molybdenum, MO) in the layer where the gate of transistor 102 is located can be utilized to effectively reduce signal loss and interference caused by routing resistance. Furthermore, when the touch structure is fabricated using the active layer material of transistor 102, the routing is fabricated using the gate material of transistor 102, and the bridge wire is fabricated using the source and drain of transistor 102, only the fabrication processes for the active layer, gate, and source and drain layers of transistor 102 need to be changed. The materials and fabrication processes for related film layers above transistor 102, such as the light-emitting device and touch layer, do not need to be changed, demonstrating excellent compatibility. Furthermore, since the light-emitting device and touch layer are typically located in display area AA, the pressure-sensitive touch virtual button 103 in non-display area BB will not affect the light-emitting device and touch layer.

[0109] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 4 As shown, the layer where the gate of the transistor 102 is located can be located between the active layer of the transistor 102 and the layer where the source and drain of the transistor 102 are located, and the material of the active layer of the transistor 102 includes low-temperature polysilicon. In other words, the transistor 102 is a top-gate low-temperature polysilicon transistor 102. In some embodiments, the transistor 102 can be a driving transistor 102 electrically connected to the anode 1041 of the light-emitting device 104. In order to avoid the corrosion of the light-emitting device 104 by water, oxygen, etc., an encapsulation layer (TFE) covering the light-emitting device 104 is usually provided. The pressure-sensitive touch virtual key 103 provided in the present disclosure can also be covered by the encapsulation layer to protect the pressure-sensitive touch virtual key 103 from water, oxygen, etc. by the encapsulation layer.

[0110] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 3 、 Figure 7 and Figure 8 As shown, a ground line GND provided on the same layer as the gate of the transistor 102 may also be included, and the ground line GND surrounds the third line L3 to prevent interference of static electricity and the like on the third line L3.

[0111] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the pressure-sensitive touch virtual key 103 can be at least one of the power key Power, the volume key VOL+ / VOL-, and the game key L / R, or a virtual key that can realize other edge touch functions, which is not limited here.

[0112] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as Figure 4 and Figure 6 As shown, the display substrate may further include: a buffer layer 105, a first gate insulating layer 106, a second gate insulating layer 107, an interlayer dielectric layer 108, a planarization layer 109, a pixel defining layer 110, a support layer 111, a polarizer 112, a protective cover 113, and a storage capacitor Cst, etc. Other essential components of the display substrate are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limiting the present disclosure.

[0113] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, including the above-mentioned display substrate provided by the embodiment of the present disclosure. Since the principle of solving the problem by the display device is similar to the principle of solving the problem by the above-mentioned display substrate, the implementation of the display device can refer to the embodiment of the above-mentioned display substrate, and the repeated parts will not be repeated.

[0114] Specifically, the display device provided by the embodiment of the present disclosure is as follows: Figure 2 、 Figure 5 and Figure 9 As shown, it includes a display substrate 001, a power supply 002 and a pressure sensing chip 003, wherein the first end of the first piezoresistor (for example, T1, T1') and the first end of the second piezoresistor (for example, R1, R1') are both electrically connected to the positive pole of the power supply 002; the second end of the third piezoresistor (for example, T2, T2') and the second end of the fourth piezoresistor (for example, R2, R2') are both electrically connected to the negative pole of the power supply 002; the second end of the first piezoresistor (for example, T1, T1') and the first end of the fourth piezoresistor (for example, R2, R2') are both electrically connected to the first test end of the pressure sensing chip 003; the second end of the second piezoresistor (for example, R1, R1') and the first end of the third piezoresistor (for example, T2, T2') are both electrically connected to the second test end of the pressure sensing chip 003.

[0115] For example, in Figure 5In the embodiment, a pressure-sensitive touch virtual key 103 includes two first pressure-sensitive resistors (e.g., T1 and T1') connected in parallel, two second pressure-sensitive resistors (e.g., R1 and R1') connected in parallel, two third pressure-sensitive resistors (e.g., T2 and T2') connected in parallel, and two fourth pressure-sensitive resistors (e.g., R2 and R2') connected in parallel. When pressed, the voltage change caused by the touch pressure detected by the pressure-sensitive chip 003 is expressed as follows:

[0116]

[0117] For example, in Figure 5 In the embodiment, a pressure-sensitive touch virtual key 103 includes a first pressure-sensitive resistor (e.g., T1), a second pressure-sensitive resistor (e.g., R1), a third pressure-sensitive resistor (e.g., T2), and a fourth pressure-sensitive resistor (e.g., R2). When pressed, the voltage change caused by the touch pressure detected by the pressure-sensitive chip 003 is expressed as follows:

[0118] ΔV=V*[R1 / (T1+R1)]-V*[R2 / (T2+R2)].

[0119] In some embodiments, the display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or the like. The display device includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, a memory, a processor, and a power supply. In addition, it will be understood by those skilled in the art that the above structure does not constitute a limitation on the display device provided in the embodiments of the present disclosure. In other words, the display device provided in the embodiments of the present disclosure may include more or fewer of the above components, or a combination of certain components, or a different arrangement of components.

[0120] Although preferred embodiments of the present disclosure have been described, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display substrate, characterized in that: include: a base substrate, the base substrate comprising a display area and a non-display area located on at least one side of the display area; a transistor, located in the display area; A pressure-sensitive touch virtual key, located in the non-display area, the pressure-sensitive touch virtual key comprising at least one first piezoresistor, at least one second piezoresistor, at least one third piezoresistor, and at least one fourth piezoresistor, wherein the at least one first piezoresistor, the at least one second piezoresistor, the at least one third piezoresistor, and the at least one fourth piezoresistor are arranged in the same layer as the active layer of the transistor; a first end of the first piezoresistor is electrically connected to a first end of the second piezoresistor, a second end of the first piezoresistor is electrically connected to a first end of the fourth piezoresistor, a first end of the third piezoresistor is electrically connected to a second end of the second piezoresistor, and a second end of the third piezoresistor is electrically connected to a second end of the fourth piezoresistor; a first routing line, a second routing line, a third routing line, and a fourth routing line, wherein the first routing line is electrically connected to the second end of the first varistor and the first end of the fourth varistor, the second routing line is electrically connected to the second end of the third varistor and the second end of the fourth varistor, the third routing line is electrically connected to the second end of the second varistor and the first end of the third varistor, and the fourth routing line is electrically connected to the first end of the first varistor and the first end of the second varistor; The first routing line includes a first line segment located between the pressure-sensitive touch virtual key and the display area, the second routing line includes a second line segment located between the first line segment and the display area, the third routing line includes a third line segment located between the second line segment and the display area, and a fourth line segment located on a side of the pressure-sensitive touch virtual key away from the display area, the fourth routing line includes a fifth line segment located on a side of the pressure-sensitive touch virtual key away from the display area, and the fifth line segment and the fourth line segment are spaced apart in their extension directions.

2. The display substrate according to claim 1, wherein The first varistor and the third varistor have the same resistance value, the second varistor and the fourth varistor have the same resistance value, and the first varistor and the second varistor have different resistance values.

3. The display substrate according to claim 1, wherein The pressure-sensitive touch virtual key includes multiple first pressure-sensitive resistors, multiple second pressure-sensitive resistors, multiple third pressure-sensitive resistors and multiple fourth pressure-sensitive resistors; wherein, each of the first pressure-sensitive resistors is arranged in parallel, each of the second pressure-sensitive resistors is arranged in parallel, each of the third pressure-sensitive resistors is arranged in parallel, and each of the fourth pressure-sensitive resistors is arranged in parallel.

4. The display substrate according to claim 1, wherein Each of the first varistors, each of the second varistors, each of the third varistors, and each of the fourth varistors are arranged in sequence in the first direction, and each of the first varistors and each of the third varistors are arranged side by side in the second direction, and the at least one second varistor is located between the at least one first varistor and the at least one fourth varistor, wherein the first direction and the second direction are perpendicular to each other.

5. The display substrate according to claim 4, wherein: The first varistor and the third varistor respectively include: at least two first subsections and at least one second subsection, wherein each of the first subsections extends along the first direction, each of the second subsections extends along the second direction, and each of the first subsections is sequentially connected through each of the second subsections; The second varistor and the fourth varistor respectively include: at least one third division, at least one fourth division and at least one fifth division, wherein each third division extends along a third direction, each fourth division extends along a fourth direction, each fifth division extends along the first direction, and each third division is connected to each fourth division in sequence through each fifth division; wherein the third direction is respectively intersected with the first direction and the second direction, the fourth direction is respectively intersected with the first direction and the second direction, and the third direction and the fourth direction intersect at an acute angle.

6. The display substrate according to claim 5, wherein: The lengths of the first varistor and the third varistor in the first direction are both greater than or equal to 55 μm and less than or equal to 165 μm, and the widths of the first varistor and the third varistor in the second direction are both greater than or equal to 25 μm and less than or equal to 75 μm; the line widths of the first subsection and the second subsection are both greater than or equal to 2.5 μm and less than or equal to 7.5 μm, and the spacing between two adjacent first subsections in the second direction is greater than or equal to 2.5 μm and less than or equal to 7.5 μm; The lengths of the second varistor and the fourth varistor in the first direction are both greater than or equal to 50 μm and less than or equal to 150 μm, and the widths of the second varistor and the fourth varistor in the second direction are both greater than or equal to 50 μm and less than or equal to 150 μm; the line widths of the third section, the fourth section and the fifth section are all greater than or equal to 1.7 μm and less than or equal to 5.2 μm, and the angle between the third direction and the fourth direction is greater than or equal to 5° and less than or equal to 15°.

7. The display substrate according to claim 5, wherein: The first wiring is located between the pressure-sensitive touch virtual key and the display area, and the first wiring further includes a first connecting line located on a side of the first line segment away from the display area, the first line segment being electrically connected to the second end of each of the first piezoresistors and the first end of each of the fourth piezoresistors through the first connecting line; The second routing includes a first sub-routing, a second sub-routing, and a third sub-routing that are sequentially arranged, wherein the first sub-routing is the second line segment, the second sub-routing is located on a side of the at least one fourth piezoresistor away from the at least one second piezoresistor, the third sub-routing is located on a side of the pressure-sensitive touch virtual key away from the display area, and the third sub-routing is electrically connected to the second end of each of the third piezoresistors and the second end of each of the fourth piezoresistors; The third routing includes a fourth sub-routing, a fifth sub-routing, a sixth sub-routing, a seventh sub-routing, an eighth sub-routing, a ninth sub-routing, and a tenth sub-routing that are sequentially arranged, wherein the fourth sub-routing is the third line segment, the fifth sub-routing is located on a side of the second routing away from the at least one second piezoresistor, the sixth sub-routing is the fourth line segment and is located on a side of the third sub-routing away from the display area, the seventh sub-routing is located on a side of the at least one third piezoresistor away from the at least one second piezoresistor, the eighth sub-routing is located between the at least one first piezoresistor and the at least one third piezoresistor, the ninth sub-routing is located between the at least one third piezoresistor and the at least one second piezoresistor, the tenth sub-routing is located between the at least one second piezoresistor and the third sub-routing, and the tenth sub-routing is electrically connected to the second end of each of the second piezoresistors, and the eighth sub-routing and the ninth sub-routing are electrically connected to the first end of each of the third piezoresistors; The fourth routing includes an eleventh sub-routing, a twelfth sub-routing, a thirteenth sub-routing and a fourteenth sub-routing arranged in sequence, wherein the eleventh sub-routing includes the fifth line segment, and the eleventh sub-routing is located on a side of the seventh sub-routing away from the at least one third piezoresistor, the twelfth sub-routing is located between the fifth sub-routing and the at least one first piezoresistor, the thirteenth sub-routing is located between the at least one first piezoresistor and the at least one second piezoresistor, the fourteenth sub-routing is located between the at least one second piezoresistor and the first routing, and the twelfth sub-routing and the thirteenth sub-routing are electrically connected to the first end of each first piezoresistor, and the fourteenth sub-routing is electrically connected to the first end of each second piezoresistor.

8. The display substrate according to claim 1, wherein The at least one third varistor, the at least one first varistor, the at least one second varistor and the at least one fourth varistor are arranged sequentially in the first direction, and the first varistor, the second varistor, the third varistor and the fourth varistor all extend along the second direction.

9. The display substrate according to claim 8, wherein: The lengths of the first varistor and the third varistor in the second direction are both greater than or equal to 50 μm and less than or equal to 150 μm, and the widths of the first varistor and the third varistor in the first direction are both greater than or equal to 2.5 μm and less than or equal to 7.5 μm; The lengths of the second varistor and the fourth varistor in the second direction are both greater than or equal to 40 μm and less than or equal to 120 μm, and the widths of the second varistor and the fourth varistor in the first direction are both greater than or equal to 2.5 μm and less than or equal to 7.5 μm.

10. The display substrate according to claim 8, wherein The first routing includes a fifteenth sub-routing, a sixteenth sub-routing, a seventeenth sub-routing, an eighteenth sub-routing, and a nineteenth sub-routing that are sequentially arranged, wherein the fifteenth sub-routing is the first line segment, the sixteenth sub-routing is located on a side of the at least one fourth piezoresistor away from the at least one second piezoresistor, the seventeenth sub-routing is located on a side of the at least one fourth piezoresistor away from the display area, the eighteenth sub-routing is located between the at least one fourth piezoresistor and the at least one second piezoresistor, the nineteenth sub-routing is located between the at least one first piezoresistor and the display area, the seventeenth sub-routing is electrically connected to a first end of each of the fourth piezoresistors, and the nineteenth sub-routing is electrically connected to a second end of each of the first piezoresistors; The second routing line is located between the nineteenth sub-routing line and the display area, and the second routing line further includes a second connecting line located on a side of the second line segment away from the display area, the second line segment being electrically connected to the second end of each of the third varistors and the second end of each of the fourth varistors through the second connecting line; The third routing includes a 20th sub-routing, a 21st sub-routing, and a 22nd sub-routing that are sequentially arranged, wherein the 20th sub-routing is the third line segment, the 21st sub-routing is located on a side of the at least one third varistor away from the at least one first varistor, and the 22nd sub-routing is the fourth line segment, and the 22nd sub-routing is electrically connected to the second end of each of the second varistors and the first end of each of the third varistors; The fourth route includes a twenty-third sub-route, a twenty-fourth sub-route, a twenty-fifth sub-route, a twenty-sixth sub-route and a twenty-seventh sub-route arranged in sequence, wherein the twenty-third sub-route is the fifth line segment, the twenty-fourth sub-route is located between the eighteenth sub-route and the at least one second piezoresistor, the twenty-fifth sub-route is located between the twenty-tenth sub-route and the at least one second piezoresistor, the twenty-sixth sub-route is located between the at least one second piezoresistor and the at least one first piezoresistor, the twenty-seventh sub-route is located between the twenty-second sub-route and the at least one first piezoresistor, the twenty-fifth sub-route is electrically connected to the first end of each second piezoresistor, and the twenty-seventh sub-route is electrically connected to the first end of each first piezoresistor.

11. The display substrate according to claim 1, wherein The first varistor, the second varistor, the third varistor and the fourth varistor all extend along the first direction, the at least one first varistor is located between the at least one third varistor and the display area, the at least one second varistor is located between the at least one fourth varistor and the display area, the at least one first varistor and the at least one third varistor are arranged along the second direction, and the at least one second varistor and the at least one fourth varistor are arranged along the second direction.

12. The display substrate according to claim 11, wherein The lengths of the first varistor and the third varistor in the first direction are both greater than or equal to 55 μm and less than or equal to 165 μm, and the widths of the first varistor and the third varistor in the second direction are both greater than or equal to 5 μm and less than or equal to 15 μm; The lengths of the second varistor and the fourth varistor in the first direction are both greater than or equal to 175 μm and less than or equal to 525 μm, and the widths of the second varistor and the fourth varistor in the second direction are both greater than or equal to 10 μm and less than or equal to 30 μm.

13. The display substrate according to claim 11, wherein: The first routing line includes a twenty-eighth sub-routing line and a twenty-ninth sub-routing line that are sequentially arranged, wherein the twenty-eighth sub-routing line is the first line segment, and the twenty-ninth sub-routing line is located on a side of the at least one fourth varistor away from the at least one third varistor. The first routing line also includes a third connecting line located on a side of the first line segment away from the display area, the first line segment is electrically connected to the second end of each of the first varistors via the third connecting line, and the twenty-ninth sub-routing line is electrically connected to the first end of each of the fourth varistors. The second routing includes a 30th sub-routing, a 31st sub-routing, and a 32nd sub-routing that are sequentially arranged, wherein the 30th sub-routing is the second line segment and is located between the 28th sub-routing and the display area, the 31st sub-routing is located on a side of the 29th sub-routing away from the pressure-sensitive touch virtual key, the 32nd sub-routing is located on a side of the pressure-sensitive touch virtual key away from the display area, and the 32nd sub-routing is electrically connected to the second end of each of the third piezoresistors and the second end of each of the fourth piezoresistors; The third routing includes a thirty-third sub-routing, a thirty-fourth sub-routing, a thirty-fifth sub-routing, a thirty-sixth sub-routing, and a thirty-seventh sub-routing, which are sequentially arranged, wherein the thirty-third sub-routing is the third line segment and is located between the 30th sub-routing and the display area, the thirty-fourth sub-routing is located on a side of the thirty-first sub-routing away from the pressure-sensitive touch virtual key, the thirty-fifth sub-routing is the fourth line segment and is located on a side of the thirty-third sub-routing away from the display area, the thirty-sixth sub-routing is located on a side of the at least one third piezoresistor away from the at least one fourth piezoresistor, the thirty-seventh sub-routing is located between the at least one first piezoresistor and the at least one third piezoresistor, and the thirty-seventh sub-routing is electrically connected to the second end of each of the second piezoresistors and the first end of each of the third piezoresistors; The fourth route includes a thirty-eighth sub-route, a thirty-ninth sub-route, a fortieth sub-route, a forty-first sub-route and a forty-second sub-route which are arranged in sequence, wherein the thirty-eighth sub-route is the fifth line segment, the thirty-ninth sub-route is located on the side of the thirty-fifth sub-route away from the pressure-sensitive touch virtual key, the fortieth sub-route is located between the thirty-seventh sub-route and the at least one first pressure-sensitive resistor, the forty-first sub-route is located between the at least one second pressure-sensitive resistor and the at least one first pressure-sensitive resistor, the forty-second sub-route is located between the twenty-eighth sub-route and the at least one second pressure-sensitive resistor, the forty-first sub-route is electrically connected to the first end of each of the first pressure-sensitive resistors, and the forty-second sub-route is electrically connected to the first end of each of the second pressure-sensitive resistors.

14. The display substrate according to any one of claims 1 to 13, wherein: The line widths of the first routing line, the second routing line, the third routing line, and the fourth routing line are all greater than or equal to 2.5 μm and less than or equal to 7.5 μm, and the line spacings are greater than or equal to 1 μm and less than or equal to 4.5 μm.

15. The display substrate according to any one of claims 1 to 13, wherein: Also includes: a first bridge connection, a second bridge connection, a third bridge connection, a fourth bridge connection, a fifth bridge connection, a sixth bridge connection, a seventh bridge connection, and an eighth bridge connection, wherein The first bridge wire is connected between the first routing line and the second end of the first piezoresistor, the second bridge wire is connected between the first routing line and the first end of the fourth piezoresistor, the third bridge wire is connected between the second routing line and the second end of the third piezoresistor, the fourth bridge wire is connected between the second routing line and the second end of the fourth piezoresistor, the fifth bridge wire is connected between the third routing line and the second end of the second piezoresistor, the sixth bridge wire is connected between the third routing line and the first end of the third piezoresistor, the seventh bridge wire is connected between the fourth routing line and the first end of the first piezoresistor, and the eighth bridge wire is connected between the fourth routing line and the first end of the second piezoresistor.

16. The display substrate according to claim 15, wherein The first routing line, the second routing line, the third routing line and the fourth routing line are all arranged on the same layer as the gate of the transistor; The first bridge wire, the second bridge wire, the third bridge wire, the fourth bridge wire, the fifth bridge wire, the sixth bridge wire, the seventh bridge wire, and the eighth bridge wire are all provided in the same layer as the source and drain of the transistor.

17. The display substrate according to claim 16, wherein: The layer where the gate of the transistor is located is located between the active layer of the transistor and the layer where the source and drain of the transistor are located, and the material of the active layer of the transistor includes low-temperature polysilicon.

18. The display substrate according to any one of claims 1 to 13, wherein: It also includes a ground line provided at the same layer as the gate of the transistor, and the ground line surrounds the third wiring.

19. The display substrate according to any one of claims 1 to 13, wherein: The pressure-sensitive touch virtual key is at least one of a power key, a volume key, and a game key.

20. A display device, characterized in that: Comprising a display substrate, a power supply and a pressure sensing chip, wherein the display substrate is the display substrate according to any one of claims 1 to 19; The first end of the first varistor and the first end of the second varistor are both electrically connected to the positive electrode of the power supply; The second end of the third varistor and the second end of the fourth varistor are both electrically connected to the negative electrode of the power supply; The second end of the first piezoresistor and the first end of the fourth piezoresistor are both electrically connected to the first test end of the pressure sensing chip; The second end of the second piezoresistor and the first end of the third piezoresistor are both electrically connected to the second test end of the pressure sensing chip.

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