A high-speed target frequency domain phase compensation method

Abstract

A method for frequency-domain phase compensation of high-speed targets is characterized by being based on an FPGA and DSP architecture. The DSP calculates phase compensation-related parameters based on current radar operating parameters, writes the parameters to the FPGA via an EMIF interface, and the FPGA calculates the phase to be compensated based on the phase compensation-related parameters. A compensation factor is obtained through a lookup table, and the high-speed target echo signal is compensated in the frequency domain based on the phase to be compensated. This invention meets both real-time requirements and software versatility.

Description

Technical Field

[0001] The present invention relates to the field of radar signal processing, and in particular to a high-speed target frequency domain phase compensation method. Background Art

[0002] Currently, compensation for high-speed target echoes is mainly achieved through interpolation operations or multi-dimensional parameter searches, which have the problems of large computational complexity and complex implementation methods, and are not conducive to real-time processing. Summary of the Invention

[0003] The object of the present invention is to provide a high-speed target frequency domain phase compensation method that meets both the real-time requirements and the versatility of the software.

[0004] In order to achieve the above-mentioned object, the present invention provides a high-speed target frequency domain phase compensation method, which is characterized in that the high-speed target frequency domain phase compensation method is based on FPGA and DSP architecture. The DSP calculates phase compensation related parameters according to the current radar operating parameters, writes the parameters into the FPGA through the EMIF interface, and the FPGA calculates the phase to be compensated according to the phase compensation related parameters, obtains the compensation factor through a lookup table, and compensates the high-speed target echo signal in the frequency domain according to the phase to be compensated.

[0005] The phase compensation related parameters include: a first parameter Param1, a second parameter Param2 and a third parameter Param3;

[0006] The first parameter Param1 represents the missile-target speed and the radar working repetition period. DSP calculates the first parameter Param1 of INT32 type according to the target speed Vel and the repetition period Tr = Vel×Tr×10 3 ×2 16 , of which 10 3 For unit conversion, 2 16 To meet the precision requirement, the first parameter Param1 is quantized to a 30-bit parameter and configured to the FPGA through the EMIF interface.

[0007] The second parameter Param2 represents the radar operating carrier frequency f0. DSP calculates the INT64 type parameter based on the radar carrier frequency f0 and the speed of light c. 10 of them 3 For unit conversion, 2 40 To meet the precision requirement, the second parameter Param2 is quantized to a 39-bit parameter and configured to the FPGA through the EMIF interface.

[0008] The third parameter Param3 represents the echo acquisition frequency and the accumulated number of radar working pulses. DSP calculates the INT32 type parameter according to the sampling frequency fs, the speed of light c and the number of pulses RangNum. 10 of them 3 For unit conversion, 2 40 To meet the precision requirement, the third parameter Param3 is quantized to a 19-bit parameter and configured to the FPGA through the EMIF interface.

[0009] The method for calculating the phase to be compensated by the FPGA includes:

[0010] Calculate the intra-pulse compensation parameters: Instantiate a multiplier IP core in the FPGA to multiply the radar echo range gate number by the third parameter Param3 in real time. Add the result to the second parameter Param2 to obtain ParamA.

[0011] Calculate the inter-pulse compensation parameters: Count the number of pulses according to the pulse repetition period PRT, instantiate a multiplier IP core in the FPGA, and multiply the pulse count value by the first parameter Param1 to obtain parameter ParamB;

[0012] Accumulation of compensation parameter phase: Instantiate a multiplier IP core in the FPGA, multiply ParamA and ParamB, and calculate the phase value ParamC that needs to be compensated;

[0013] The compensation phase calculated by FPGA is:

[0014] The method for FPGA to obtain the compensation factor by looking up the table includes:

[0015] Generate a lookup table on the FPGA: Calculate the cosine and sinine values ​​corresponding to different phase values ​​in Matlab, quantize them into 16-bit, 16,384-point values, and store them in two coe files. Instantiate two memory IP cores in the FPGA, configure the memory IP cores as ROM type, and store the two coe files generated by Matlab in two ROMs as lookup tables for phase change compensation.

[0016] FPGA obtains the compensation factor: the phase value ParamC that needs to be compensated is used as the address of the two memory IP cores, and the cosine and sinine values ​​of the final compensation factor are output.

[0017] The method for the FPGA to compensate the high-speed target echo signal in the frequency domain according to the phase to be compensated includes:

[0018] Echo signal time-frequency conversion: An FFT IP core is instantiated in the FPGA. The down-converted high-speed target echo signal is used as the input of the FFT IP core. The output of the FFT IP core is the frequency domain signal of the radar echo, which implements the Fourier transform of the radar echo signal.

[0019] Frequency-domain complex multiplication: Instantiate a complex multiplier IP core in the FPGA, use the cosine value of the compensation factor as the real part and the sin value of the compensation factor as the imaginary part, and perform complex multiplication with the radar echo frequency-domain signal to complete frequency-domain phase compensation;

[0020] Frequency-time conversion of the compensated signal: Instantiate an IFFT IP core in the FPGA and use the result after frequency-domain phase compensation as the input of the IFFT IP core. The output of the IFFT IP core is the compensated echo signal.

[0021] The present invention has the following advantages:

[0022] 1. The FPGA+DSP architecture is used to perform phase compensation on high-speed target echoes in the frequency domain, making full use of the advantages of FPGA parallel processing and DSP flexible control to improve the real-time performance of processing.

[0023] 2. When using FPGA to implement high-speed target frequency domain phase compensation, a stream processing method is adopted to reduce the demand for memory.

[0024] 3. The compensation parameters can be flexibly configured by DSP, which improves the versatility of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a flow chart of a high-speed target frequency domain phase compensation method provided by the present invention. DETAILED DESCRIPTION

[0026] The following is based on Figure 1 The preferred embodiments of the present invention will be described in detail.

[0027] The present invention provides a frequency-domain phase compensation method for high-speed targets. The method is based on an FPGA and DSP architecture. The DSP calculates phase compensation-related parameters based on current radar operating parameters, writes the parameters to the FPGA via an EMIF interface, and the FPGA calculates the phase to be compensated based on the phase compensation-related parameters. The compensation factor is obtained through a lookup table, and the high-speed target echo signal is compensated in the frequency domain according to the phase to be compensated. This allows the radar echo signal to be effectively accumulated, thereby achieving the purpose of accurate detection of high-speed targets in a long-term accumulation working mode.

[0028] The phase compensation parameters include: Param1, Param2, and Param3. Param1 represents the missile-target velocity and the radar repetition rate, covering radar operating modes such as high-speed targets and long-term accumulation. Param2 represents the radar operating carrier frequency f0, covering carrier frequencies ranging from millimeter waves to infrared bands. Param3 represents the echo acquisition frequency and the number of radar pulse accumulations, covering radar operating modes such as high / low acquisition speeds and long / short-term accumulation. These parameters are calculated by the DSP and configured to the FPGA via the EMIF interface, achieving the advantages of universal and adaptable frequency-domain phase compensation.

[0029] like Figure 1 As shown, in one embodiment of the present invention, the high-speed target frequency domain phase compensation method includes the following steps:

[0030] Step S1, DSP calculates the first parameter Param1, the second parameter Param2 and the third parameter Param3;

[0031] Calculate the first parameter Param1: Calculate the INT32 type parameter Param1 = Vel×Tr×10 in DSP according to the target speed Vel and repetition period Tr 3 ×2 16 (10 of which 3 For unit conversion, 2 16 The first parameter Param1 is quantized to a parameter with a bit width of 30 bits and is configured to the FPGA through the EMIF interface;

[0032] Calculate the second parameter Param2: Calculate the INT64 type parameter in DSP based on the radar carrier frequency f0 and the speed of light c (10 of which 3 For unit conversion, 2 40 The second parameter Param2 is quantized to a parameter with a bit width of 39 bits and is configured to the FPGA through the EMIF interface;

[0033] Calculate the third parameter Param3: Calculate the INT32 type parameter in DSP based on the sampling frequency fs, the speed of light c and the number of pulses RangNum (10 of which 3 For unit conversion, 2 40 The third parameter Param3 is quantized to a parameter with a bit width of 19 bits and configured to the FPGA through the EMIF interface;

[0034] Step S2: FPGA calculates the phase that needs to be compensated;

[0035] Step S2.1, calculate the intra-pulse compensation parameters: instantiate a multiplier IP core in the FPGA, multiply the radar echo range gate number by the third parameter Param3 in real time, and add the result to the second parameter Param2 to obtain ParamA;

[0036] Step S2.2, calculate the inter-pulse compensation parameter: count the number of pulses according to the pulse repetition period PRT, instantiate a multiplier IP core in the FPGA, multiply the pulse count value by the first parameter Param1 to obtain parameter ParamB;

[0037] Step S2.3, accumulation of compensation parameter phase: Instantiate a multiplier IP core in the FPGA, multiply ParamA and ParamB, and calculate the phase value ParamC that needs to be compensated;

[0038] The compensation phase calculated by FPGA is:

[0039] Step S3: FPGA obtains the compensation factor through a lookup table according to the phase to be compensated;

[0040] Step S3.1, FPGA generates a lookup table;

[0041] In Matlab, the cosine and sinine values ​​corresponding to different phase values ​​are calculated and quantized into 16-bit, 16,384-point values. These values ​​are then stored in two coe files. Two memory IP cores are instantiated in the FPGA and configured as ROM type. The two coe files generated by Matlab are then stored in two ROMs as lookup tables for phase change compensation.

[0042] Step S3.2, FPGA obtains compensation factor;

[0043] Use the phase value ParamC that needs to be compensated as the address of the two memory IP cores, and output the cosine and sinine values ​​of the final compensation factors;

[0044] Step S4: FPGA compensates the high-speed target echo signal in the frequency domain according to the phase that needs to be compensated;

[0045] Step S4.1, echo signal time-frequency conversion: Instantiate an FFT IP core in the FPGA and use the down-converted high-speed target echo signal as the input of the FFT IP core. The output of the FFT IP core is the frequency domain signal of the radar echo, which implements the Fourier transform of the radar echo signal.

[0046] Step S4.2, frequency domain complex multiplication: Instantiate a complex multiplier IP core in the FPGA, use the cosine value of the compensation factor as the real part, and the sin value of the compensation factor as the imaginary part, and perform complex multiplication with the echo frequency domain signal output in step S4.1 to complete the frequency domain phase compensation;

[0047] Step S4.3, frequency-time conversion of compensated signal: Instantiate an IFFT IP core in the FPGA, and use the frequency domain phase compensation result output in step S4.2 as the input of the IFFT IP core. The output of the IFFT IP core is the compensated echo signal.

[0048] The present invention has the following advantages:

[0049] 1. The FPGA+DSP architecture is used to perform phase compensation on high-speed target echoes in the frequency domain, making full use of the advantages of FPGA parallel processing and DSP flexible control to improve the real-time performance of processing.

[0050] 2. When using FPGA to implement high-speed target frequency domain phase compensation, a stream processing method is adopted to reduce the demand for memory.

[0051] 3. The compensation parameters can be flexibly configured by DSP, which improves the versatility of the present invention.

[0052] It should be noted that in the embodiments of the present invention, the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of the embodiments. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0053] Although the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description is not intended to limit the present invention. After reading the above description, various modifications and substitutions of the present invention will become apparent to those skilled in the art. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A high-speed target frequency domain phase compensation method, characterized in that: The high-speed target frequency domain phase compensation method is based on an FPGA and DSP architecture. The DSP calculates phase compensation-related parameters based on the current radar operating parameters, writes the parameters into the FPGA through the EMIF interface, and the FPGA calculates the phase to be compensated based on the phase compensation-related parameters. The compensation factor is obtained through a lookup table, and the high-speed target echo signal is compensated in the frequency domain according to the phase to be compensated. The phase compensation related parameters include: a first parameter Param1, a second parameter Param2 and a third parameter Param3; The first parameter Param1 represents the missile-target speed and the radar working repetition period. DSP calculates the first parameter Param1 of INT32 type according to the target speed Vel and the repetition period Tr = Vel×Tr×10 3 ×2 16 , of which 10 3 For unit conversion, 2 16 To meet the precision requirement, the first parameter Param1 is quantized to a 30-bit parameter and configured to the FPGA through the EMIF interface. The second parameter Param2 represents the radar operating carrier frequency f0. DSP calculates the INT64 type parameter based on the radar carrier frequency f0 and the speed of light c. 10 of them 3 For unit conversion, 2 40 To meet the precision requirement, the second parameter Param2 is quantized to a 39-bit parameter and configured to the FPGA through the EMIF interface. The third parameter Param3 represents the echo acquisition frequency and the accumulated number of radar working pulses. DSP calculates the INT32 type parameter according to the sampling frequency fs, the speed of light c and the number of pulses RangNum. 10 of them 3 For unit conversion, 2 40 To meet the precision requirement, the third parameter Param3 is quantized to a 19-bit parameter and configured to the FPGA through the EMIF interface.

2. The high-speed target frequency domain phase compensation method according to claim 1, wherein: The method for calculating the phase to be compensated by the FPGA includes: Calculate the intra-pulse compensation parameters: Instantiate a multiplier IP core in the FPGA to multiply the radar echo range gate number by the third parameter Param3 in real time. Add the result to the second parameter Param2 to obtain ParamA. Calculate the inter-pulse compensation parameters: Count the number of pulses according to the pulse repetition period PRT, instantiate a multiplier IP core in the FPGA, and multiply the pulse count value by the first parameter Param1 to obtain parameter ParamB; Accumulation of compensation parameter phase: Instantiate a multiplier IP core in the FPGA, multiply ParamA and ParamB, and calculate the phase value ParamC that needs to be compensated; The compensation phase calculated by FPGA is:

3. The high-speed target frequency domain phase compensation method according to claim 2, wherein: The method for FPGA to obtain the compensation factor by looking up the table includes: Generate a lookup table on the FPGA: Calculate the cosine and sinine values ​​corresponding to different phase values ​​in Matlab, quantize them into 16-bit, 16,384-point values, and store them in two coe files. Instantiate two memory IP cores in the FPGA, configure the memory IP cores as ROM type, and store the two coe files generated by Matlab in two ROMs as lookup tables for phase change compensation. FPGA obtains the compensation factor: the phase value ParamC that needs to be compensated is used as the address of the two memory IP cores, and the cosine and sinine values ​​of the final compensation factor are output.

4. The high-speed target frequency domain phase compensation method according to claim 3, wherein: The method for the FPGA to compensate the high-speed target echo signal in the frequency domain according to the phase to be compensated includes: Echo signal time-frequency conversion: An FFT IP core is instantiated in the FPGA. The down-converted high-speed target echo signal is used as the input of the FFT IP core. The output of the FFT IP core is the frequency domain signal of the radar echo, which implements the Fourier transform of the radar echo signal. Frequency-domain complex multiplication: Instantiate a complex multiplier IP core in the FPGA, use the cosine value of the compensation factor as the real part and the sin value of the compensation factor as the imaginary part, and perform complex multiplication with the radar echo frequency-domain signal to complete frequency-domain phase compensation; Frequency-time conversion of the compensated signal: Instantiate an IFFT IP core in the FPGA and use the result after frequency domain phase compensation as the input of the IFFT IP core. The output of the IFFT IP core is the compensated echo signal.

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