Adaptive buffer partitioning

Abstract

This application is directed to adaptive buffer partitioning. A memory system can include a buffer for storing data (e.g., associated with a read command or a write command received from a host system). For example, the buffer can buffer data associated with a write command prior to storing the data at a memory device of the memory system. In another example, the buffer can buffer data associated with a read command prior to transmitting the data to the host system. In some cases, the buffer can include a first portion configured to store data associated with one or more read commands, a second portion configured to store data associated with one or more write commands, and a third portion configured to store data associated with one or more read commands or one or more write commands.

Description

[0001] CROSS REFERENCE

[0002] The present application claims priority to U.S. Patent Application No. 16 / 950,596, entitled “ADAPTIVE BUFFER PARTITIONING,” filed November 17, 2020, to Patriarca et al., which claims priority to U.S. Provisional Patent Application No. 63 / 068,949, entitled “ADAPTIVE BUFFER PARTITIONING,” filed August 21, 2020, to Patriarca et al., both of which are assigned to the present assignee and expressly incorporated by reference herein. TECHNICAL FIELD

[0003] The technical field relates to adaptive buffer partitioning. BACKGROUND

[0004] Memory devices are widely used in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within a memory device into various states. For example, binary memory cells can be programmed into one of two supported states, often denoted by a logic 1 or logic 0. In some examples, an individual memory cell can support more than two states, any of which can be stored. To access stored information, a component can read or sense at least one stored state in a memory device. To store information, a component can write or program a state in a memory device.

[0005] There are a variety of types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self- selective memory, chalcogenide memory technologies, and others. Memory cells can be volatile or non-volatile. Non-volatile memory, such as FeRAM, can maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory devices, such as DRAM, can lose their stored state when disconnected from an external power source. SUMMARY

[0006] A non-transitory computer-readable medium storing code is described. The code can include instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive, from a host system, a write command associated with a data set; determine, for a buffer configured to buffer data being transferred between the host system and a set of memory devices of a memory system, an amount of space within the buffer available to store the data set is sufficient to store the data set, where the amount of available space within the buffer is based at least in part on a first portion of the buffer associated with read commands, a second portion of the buffer associated with write commands, and a third portion of the buffer associated with read commands and write commands; transmit, to the host system, an indication that the amount of space within the buffer is sufficient to store the data set; and receive, from the host system, the data set through the buffer based at least in part on transmitting the indication.

[0007] A non-transitory computer-readable medium storing code is described. The code can include instructions that, when executed by a processor of an electronic device, cause the electronic device to: receive, from a host system, a read command associated with a data set; determine, for a buffer configured to buffer data being transferred between a set of memory devices of a memory system and the host system, an amount of space within the buffer available to store the data set, where the amount of available space within the buffer is based at least in part on a first portion of the buffer associated with read commands, a second portion of the buffer associated with write commands, and a third portion of the buffer associated with read commands and write commands; issue the read command to a memory device of the set of memory devices based at least in part on the amount of space within the buffer being sufficient to store the data set; and transfer the data set from the memory device to the buffer based at least in part on issuing the read command.

[0008] An apparatus is described. The apparatus can include an interface configured to communicate with a host system and configured to receive one or more read commands and one or more write commands from the host system; a set of memory devices configured to store one or more data sets based at least in part on the one or more read commands and the one or more write commands; and a buffer coupled with the interface and the set of memory devices and configured to transfer the one or more data sets between the interface and the set of memory devices according to the one or more read commands and one or more write commands, the buffer comprising: a first portion configured to store data associated with the one or more read commands; a second portion configured to store data associated with the one or more write commands; and a third portion configured to store data associated with the one or more read commands and the one or more write commands. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 An example of a system supporting adaptive buffer partitioning is described in accordance with the examples disclosed herein.

[0010] Figure 2 An example of a memory device supporting adaptive buffer partitioning is described in accordance with the examples disclosed herein.

[0011] Figure 3 An example of a system supporting adaptive buffer partitioning is described in accordance with the examples disclosed herein.

[0012] Figure 4 An example of a buffer configuration supporting adaptive buffer partitioning is described in accordance with the examples disclosed herein.

[0013] Figure 5 And 6 An example flow diagram of supporting adaptive buffer partitioning is described in accordance with the examples disclosed herein.

[0014] Figure 7 A block diagram of a memory system supporting adaptive buffer partitioning is shown in accordance with aspects of the present disclosure.

[0015] Figure 8 And 9 A flow diagram illustrating one or more methods of supporting adaptive buffer partitioning is shown in accordance with the examples disclosed herein. DETAILED DESCRIPTION

[0016] A memory system can receive access commands (e.g., read commands, write commands) from a host system. The memory system can manage a queue of read and write commands using read and write buffer space. That is, data associated with read commands and data associated with write commands can be buffered within the buffer space before being transmitted to the host system or stored at a memory device of the memory system, respectively. In some cases, the memory system can use hardware for memory allocation and deallocation, including loading data to buffers and transferring data between the host system and the memory device of the memory system. Additionally, some memory systems can have a fixed allocation of read and write buffer space. In some examples, the total buffer space can be split between read and write buffer space, but the split can be static (e.g., permanent) or semi-static (e.g., the split can not change frequently and have limitations, such as being a clear buffer for upcoming split). In some cases (e.g., for consecutive read commands, for consecutive write commands), the fixed partitioning can not accommodate changes in the command sequence, especially at high data rates. Thus, the speed (e.g., latency, data rate) of the memory system can be affected based on the availability of space within the buffer space to store data associated with read or write commands.

[0017] In examples described herein, a memory system can include a buffer with adaptive partitioning. For example, the buffer can include a first portion dedicated as a read buffer (e.g., for storing data associated with read commands), a second portion dedicated as a write buffer (e.g., for storing data associated with write commands), and a third portion that can be dynamically allocated to store data associated with read or write commands. In some cases, the memory system can include firmware that determines an amount of space within the buffer that is available for data associated with read commands (e.g., after receiving a read command) or data associated with write commands (e.g., after receiving a write command). The memory system can determine an amount of available space based on the first, second, and third portions of the buffer that are being used based on previously received read or write commands. Additionally, the firmware at the memory system can send an indication that space is available to process a command (e.g., receive data for a write command, retrieve data from a memory device for a read command).

[0018] Features of the disclosure are described initially in the context of the systems and dies described with reference to Figure 1 and 2 Features of the disclosure are described in the context of the systems, buffer configurations, and flowcharts described with reference to Figures 3-6 Features of the disclosure are described in the context of the systems, buffer configurations, and flowcharts described with reference to Figures 7 to 9 These and other features of the disclosure are further illustrated and described with reference to the apparatus diagrams and flowcharts related to adaptive buffer partitioning described with reference to

[0019] Figure 1 An example of a system 100 that supports adaptive buffer splitting is described in accordance with the examples disclosed herein. The system 100 includes a host system 105 coupled with a memory system 110.

[0020] The memory system 110 can be or include any device or collection of devices that includes at least one memory array. For example, the memory system 110 can be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-Line Memory Module (DIMM), a Small Outline DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), among other possibilities.

[0021] The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other conveyance), an Internet of Things (IoT) enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes memory and a processing device.

[0022] The system 100 can include a host system 105 that can be coupled with the memory system 110. In some examples, this coupling can include an interface with a host system controller 106, which can be an example of a control component configured to cause the host system 105 to perform various operations in accordance with examples as described herein. The host system 105 can include one or more devices, and in some cases can include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 can include an application configured to communicate with the memory system 110 or a device therein. The processor chipset can include one or more cores, one or more caches (e.g., local to the host system 105 or included in a memory of the host system 105), a memory controller (e.g., a NVDIMM controller), and a storage protocol controller (e.g., a UFS controller, a PCIe controller, a SATA controller). The host system 105 can use the memory system 110, for example, to write data to the memory system 110 and to read data from the memory system 110. Although Figure 1 Although one memory system 110 is shown in FIG. 1, it should be understood that the host system 105 can be coupled with any number of memory systems 110.

[0023] The host system 105 can be coupled with the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise convey control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a serial advanced technology attachment (SATA) interface, a UFS interface, an eMMC interface, a peripheral component interconnect express (PCIe) interface, a USB interface, Fibre Channel, a small computer system interface (SCSI), serial attached SCSI (SAS), double data rate (DDR), a dual in-line memory module (DIMM) interface (e.g., a DIMM socket interface that supports DDR), an open NAND flash interface (ONFI), low power double data rate (LPDDR). In some examples, one or more such interfaces can be included in or otherwise supported between a host system controller 106 of the host system 105 and a memory system controller 115 of the memory system 110. In some examples, the host system 105 can be coupled with the memory system 110 via a respective physical host interface for each memory device 130 or memory device 140 included in the memory system 110 (e.g., the host system controller 106 can be coupled with the memory system controller 115).

[0024] The memory system 110 can include a memory system controller 115, memory devices 130, and memory devices 140. The memory devices 130 can include one or more memory arrays of a first type of memory cells (e.g., one type of non-volatile memory cells), and the memory devices 140 can include one or more memory arrays of a second type of memory cells (e.g., one type of volatile memory cells). While one memory device 130 and one memory device 140 are shown in the example of Figure 1 While one memory device 130 and one memory device 140 are shown in the example of

[0025] The memory system controller 115 can be coupled with and in communication with the host system 105 (e.g., via a physical host interface) and can be an example of a control component configured to cause the memory system 110 to perform various operations in accordance with examples as described herein. The memory system controller 115 can also be coupled with and in communication with the memory devices 130 or the memory devices 140 for operations such as reading data, writing data, erasing data, or refreshing data at the memory devices 130 or the memory devices 140, as well as other such operations that can generally be referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more of the memory devices 130 or the memory devices 140 to execute such commands (e.g., at memory arrays within the one or more memory devices 130 or the memory devices 140). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to effectuate desired accesses to the memory devices 130 or the memory devices 140. And in some cases, the memory system controller 115 can exchange data with the host system 105 as well as the one or more memory devices 130 or the memory devices 140 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 can convert responses (e.g., data packets or other signals) associated with the memory devices 130 or the memory devices 140 into corresponding signals for the host system 105.

[0026] The memory system controller 115 can be configured for other operations associated with the memory devices 130 or the memory devices 140. For example, the memory system controller 115 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory devices 130 or the memory devices 140.

[0027] The memory system controller 115 can include hardware such as one or more integrated circuits or discrete components, a buffer memory, or a combination thereof. The hardware can include circuitry with special-purpose (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 can be or include a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0028] The memory system controller 115 can also include a local memory 120. In some cases, the local memory 120 can include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 can additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for internal storage or computation, for example, in connection with the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 can serve as a cache for the memory system controller 115.

[0029] Although Figure 1 Although the example of the memory system 110 has been illustrated as including the memory system controller 115, in some cases, the memory system 110 can not include the memory system controller 115. For example, the memory system 110 can additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or can include one or more local controllers 135 or local controllers 145, respectively, internal to the memory devices 130 or the memory devices 140, to perform the functions attributed herein to the memory system controller 115. Generally, one or more of the functions attributed herein to the memory system controller 115 can in some cases instead be performed by the host system 105, the local controllers 135 or the local controllers 145, or any combination thereof.

[0030] The memory devices 140 can include one or more arrays of volatile memory cells. For example, the memory devices 140 can include random access memory (RAM) memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells. In some examples, the memory devices 140 can support random access operations with reduced latency relative to the memory devices 130 (e.g., by the host system 105), or can provide one or more other performance differences relative to the memory devices 130.

[0031] The memory device 130 can include one or more arrays of non-volatile memory cells. For example, the memory device 130 can include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), resistive memory, other chalcogenide-based memory, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive-bridge RAM (CBRAM), resistive random-access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM).

[0032] In some examples, the memory device 130 or the memory device 140 can include (e.g., on the same die or within the same package) a local controller 135 or a local controller 145, respectively, which can perform operations on one or more memory cells of the memory device 130 or the memory device 140. The local controller 135 or the local controller 145 can operate in conjunction with the memory system controller 115, or can perform one or more functions attributed herein to the memory system controller 115. In some cases, the memory device 130 or the memory device 140 including the local controller 135 or the local controller 145 can be referred to as a managed memory device, and can include a memory array and related circuitry in combination with a local (e.g., on-die or in-package) controller (e.g., the local controller 135 or the local controller 145). An example of a managed memory device is a managed NAND (MNAND) device.

[0033] In some cases, the memory device 130 can be or include a NAND device (e.g., a NAND flash device). The memory device 130 can be or include a memory die 160. For example, in some cases, the memory device 130 can be a package including one or more dies 160. In some examples, a die 160 can be a piece of electronic-grade semiconductor (e.g., a silicon die cut from a silicon wafer) cut from a wafer. Each die 160 can include one or more planes 165, and each plane 165 can include a set of respective blocks 170, where each block 170 can include a set of respective pages 175, and each page 175 can include a set of memory cells.

[0034] In some cases, the NAND memory devices 130 can include memory cells configured to each store one bit of information, which can be referred to as single-level cells (SLCs). Additionally or alternatively, the NAND memory devices 130 can include memory cells configured to each store multiple bits of information, which can be referred to as multi-level cells (MLCs) if configured to each store two bits of information, triple-level cells (TLCs) if configured to each store three bits of information, quad-level cells (QLCs) if configured to each store four bits of information, or more generally as multi-level memory cells. Multi-level memory cells can provide greater storage density relative to SLC memory cells, but in some cases can involve narrower read or write margins or greater complexity for supporting circuitry.

[0035] In some cases, a plane 165 can refer to a group of blocks 170, and in some cases, parallel operations can occur within different planes 165. For example, parallel operations can be performed on memory cells within different blocks 170 so long as the different blocks 170 are in different planes 165. In some cases, performing parallel operations in different planes 165 can be subject to one or more restrictions, such as performing parallel operations on memory cells within different pages 175 that have the same page address within their respective planes 165 (e.g., in relation to command decoding, page address decoding circuitry, or other circuitry shared across the planes 165).

[0036] In some cases, a block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share a common word line (e.g., coupled thereto), and memory cells in the same string can share a common digit line (which can alternatively be referred to as a bit line) (e.g., coupled thereto).

[0037] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first level of granularity (e.g., at a page granularity level), but can be erased at a second level of granularity (e.g., at a block granularity level). That is, a page 175 can be the smallest unit of memory (e.g., a collection of memory cells) that can be programmed or read independently (e.g., simultaneously as part of a single program or read operation), and a block 170 can be the smallest unit of memory (e.g., a collection of memory cells) that can be erased independently (e.g., simultaneously as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Thus, for example, in some cases, a used page 175 can not be updated until the entire block 170 that includes the page 175 has been erased.

[0038] In some cases, the memory system controller 115, the local controller 135, or the local controller 145 can perform operations for the memory device 130 or the memory device 140 (e.g., as part of one or more media management algorithms), such as wear leveling, background refresh, garbage collection, erase, block scan, health monitoring, or other, or any combination of these operations. In some examples, the host system 105 can initiate a garbage collection operation by sending a host active garbage collection (HAGC) command. For example, within the memory device 130, a block 170 can have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in the block 170 to have invalid data in order to erase and reuse the block 170, an algorithm called “garbage collection” can be invoked to allow the block 170 to be erased and freed as a free block for subsequent write operations. Garbage collection can refer to a set of media management operations including, for example: selecting a block 170 containing valid and invalid data; selecting pages 175 in the block containing valid data; copying the valid data from the selected pages 175 to a new location (e.g., a free page 175 in another block 170); marking the data in the previously selected pages 175 as invalid; and erasing the selected block 170. As a result, the number of erased blocks 170 can be increased so that more blocks 170 can be used to store subsequent data (e.g., data subsequently received from the host system 105).

[0039] The system 100 can include any number of non-transitory computer- readable media that support adaptive buffer partitioning. For example, the host system 105, the memory system controller 115, the memory device 130, or the memory device 140 can include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware) for performing the functions attributed herein to the host system 105, the memory system controller 115, the memory device 130, or the memory device 140. For example, such instructions, when executed by the host system 105 (e.g., by the host system controller 106), by the memory system controller 115, by the memory device 130 (e.g., by the local controller 135), or by the memory device 140 (e.g., by the local controller 145), can cause the host system 105, the memory system controller 115, the memory device 130, or the memory device 140 to perform the associated functions described herein.

[0040] In examples described herein, memory system 110 can include a buffer with adaptive partitioning. For example, the buffer can include a first portion dedicated as a read buffer (e.g., for storing data associated with read commands), a second portion dedicated as a write buffer (e.g., for storing data associated with write commands), and a third portion that can be dynamically allocated to store data associated with read or write commands. In some cases, memory system 110 can include firmware (e.g., at memory system controller 115) that determines an amount of space within the buffer that can be used for data associated with read commands (e.g., after a read command is received) or data associated with write commands (e.g., after a write command is received). The firmware can determine the amount of available space based on a fullness (e.g., an occupancy) of the third portion of the buffer based on previously received read or write commands. Additionally, the firmware at memory system 110 can send an indication that space is available to process a command (e.g., receive data for a write command, retrieve data from a memory device for a read command).

[0041] Figure 2 An example of a memory device 200 that supports adaptive buffer partitioning in accordance with examples disclosed herein is described. In some cases, memory device 200 can be an example of the memory device 130 described with reference to Figure 1 FIG. 1. Figure 2 is an illustrative representation of various components and features of memory device 200. Thus, it should be appreciated that the components and features of memory device 200 are shown to illustrate functional interrelationships, and are not necessarily the actual physical locations within memory device 200. Additionally, while some elements included in Figure 2 are labeled with a numeric designator, while other corresponding elements are not labeled, they are the same or will be understood to be similar in order to increase the visibility and clarity of the depicted features.

[0042] Memory device 200 can include one or more memory units, such as memory unit 205-a and memory unit 205-b. In the enlarged view of memory unit 205-a, for example, memory unit 205 can be a NAND memory unit, such as a flash or other type.

[0043] Each memory cell 205 can be programmable to store a logic value representing one or more bits of information. In some cases, a single memory cell 205 (e.g., an SLC memory cell 205) can be programmable to one of two supported states and thus can store one bit of information (e.g., a logic 0 or a logic 1) at a time. In other cases, a single memory cell 205 (e.g., an MLC, TLC, QLC, or other type of multi-level memory cell 205) can be programmable to one of more than two supported states and thus can store more than one bit of information at a time. In some examples, a single MLC memory cell 205 can be programmable to one of four supported states and thus can store two bits of information corresponding to one of four logic values (e.g., logic 00, logic 01, logic 10, or logic 11) at a time. In some examples, a single TLC memory cell 205 can be programmable to one of eight supported states and thus can store three bits of information corresponding to one of eight logic values (e.g., 000, 001, 010, 011, 100, 101, 110, or 111) at a time. In some examples, a single QLC memory cell 205 can be programmable to one of sixteen supported states and thus can store four bits of information corresponding to one of sixteen logic values (e.g., 0000, 0001,..., 1111) at a time.

[0044] In some cases, multi-level memory cells 205 (e.g., MLC memory cells, TLC memory cells, or QLC memory cells) can be physically different from SLC cells. For example, multi-level memory cells 205 can use different cell geometries or can be fabricated using different materials. In some cases, multi-level memory cells 205 can be physically the same or similar to SLC cells, and other circuitry in a memory block (e.g., a controller, sense amplifiers, drivers) can be configured to operate the memory cells as SLC cells, or MLC cells, or TLC cells, etc.

[0045] Different types of memory cells 205 can store information in different ways. In a DRAM memory array, for example, each memory cell 205 can include a capacitor that includes a dielectric material (e.g., an insulator) that stores an electric charge representing a programmable state and thus stored information. In a FeRAM memory array, as another example, each memory cell 205 can include a capacitor that includes a ferroelectric material that stores an electric charge or polarization representing a programmable state and thus stored information.

[0046] In some NAND memory arrays (e.g., flash arrays), each memory cell 205 can include a transistor with a floating gate or dielectric material for storing an amount of electric charge representing a logic value. For example, Figure 2The NAND memory cell 205-a includes a transistor 210 (e.g., a metal-oxide- semiconductor (MOS) transistor) that can be used to store a logic value. The transistor 210 has a control gate 215 and can also include a floating gate 220, where the floating gate 220 is sandwiched between two portions of dielectric material 225. The transistor 210 includes a first node 230 (e.g., a source or drain) and a second node 235 (e.g., a drain or source). A logic value can be stored in the transistor 210 by placing (e.g., writing, storing) a quantity of electrons (e.g., a charge quantity) on the floating gate 220. The amount of charge stored on the floating gate 220 can depend on the logic value to be stored. The charge stored on the floating gate 220 can affect the threshold voltage of the transistor 210, which in turn affects the amount of current that flows through the transistor 210 when the transistor 210 is activated (e.g., when a voltage is applied to the control gate 215).

[0047] The logic value stored in the transistor 210 can be sensed (e.g., as part of a read operation) by activating the transistor 210 by applying a voltage to the control gate 215 (e.g., via the word line 262, to the control node 240) and measuring (e.g., detecting, sensing) the resulting amount of current that flows through the first node 230 or the second node 235 (e.g., via the digit line 265). For example, the sensing component 270 can determine whether the SLC memory cell 205 stores a logic 0 or a logic 1 in binary (e.g., based on the presence or absence of current through the memory cell 205 when a read voltage is applied to the control gate 215, or based on whether the current is above or below a threshold current). For a multi-level memory cell 205, the sensing component 270 can determine the logic value stored in the memory cell 205 based on various intermediate threshold current levels when a read voltage is applied to the control gate 215. In one example of a multi-level architecture, the sensing component 270 can determine the logic value of a TLC memory cell 205 based on eight different current levels or current ranges that define the eight potential logic values that can be stored by the TLC memory cell 205.

[0048] A memory cell 205 can be written to by applying one of two voltages (e.g., a voltage above a threshold or a voltage below a threshold) to the SLC memory cell 205 to store or not store charge on the floating gate 220 and thereby cause the memory cell 205 to store one of two possible logical values. For example, when a first voltage is applied to the control node 240 (e.g., via the word line 262) relative to the bulk node 245 of the transistor 210 (e.g., when the control node 240 is at a higher voltage compared to the bulk), electrons can tunnel into the floating gate 220. In some cases, the bulk node 245 can be alternatively referred to as the body node. The injection of electrons into the floating gate 220 can be referred to as programming the memory cell 205 and can occur as part of a program operation. In some cases, a programmed memory cell can be considered to store a logical 0. When a second voltage is applied to the control node 240 (e.g., via the word line 262) relative to the bulk node 245 of the transistor 210 (e.g., when the control node 240 is at a lower voltage compared to the bulk node 245), electrons can leave the floating gate 220. The removal of electrons from the floating gate 220 can be referred to as erasing the memory cell 205 and can occur as part of an erase operation. In some cases, an erased memory cell is considered to store a logical 1. In some cases, memory cells 205 due to a page 175 share a common word line 262, so the memory cells 205 can be programmed at a page 175 granularity level, and memory cells 205 due to a block share a commonly biased bulk node 245, so the memory cells 205 can be erased at a block 170 granularity level.

[0049] In contrast to writing SLC memory cells 205, writing multi-level (e.g., MLC, TLC, or QLC) memory cells 205 can involve applying different voltages to the memory cells 205 (e.g., to their control nodes 240 or bulk nodes 245) at a finer granularity level to more finely control the amount of charge stored on the floating gates 220, thereby enabling a larger set of logical values to be represented. Thus, multi-level memory cells 205 can provide greater density of storage relative to SLC memory cells 205, but in some cases can involve narrower read or write margins or greater complexity for supporting circuitry.

[0050] Charge-trapping NAND memory cells 205 can operate in a similar manner to floating gate NAND memory cells 205, but in addition or instead of storing charge on the floating gate 220, the charge-trapping NAND memory cells 205 can store charge representing a logical state in the dielectric material below the control gate 215. Thus, charge-trapping NAND memory cells 205 can or can not include a floating gate 220.

[0051] In some examples, each row of memory cells 205 can be connected to a corresponding word line 262, and each column of memory cells 205 can be connected to a corresponding digit line 265. Thus, one memory cell 205 can be located at an intersection of a word line 262 and a digit line 265. This intersection can be referred to as an address of the memory cell 205. A digit line 265 can be alternatively referred to as a bit line. In some cases, the word lines 262 and the digit lines 265 can be substantially perpendicular to each other and can create a memory cell array 205. In some cases, the word lines 262 and the digit lines 265 can be generally referred to as access lines or select lines.

[0052] In some cases, the memory device 200 can include a three-dimensional (3D) memory array in which multiple two-dimensional (2D) memory arrays can be formed on top of each other. This can increase the number of memory cells 205 that can be placed or fabricated on a single die or substrate compared to 2D arrays, which in turn can reduce production costs, or improve performance of the memory array, or both. In Figure 2 In examples, the memory device 200 includes multiple levels (e.g., decks) of memory cells 205. In some examples, the levels can be separated by electrically insulating material. Each level can be aligned or positioned such that the memory cells 205 can be aligned (e.g., precisely aligned, overlapping, or approximately aligned) with each other across each level, forming a memory cell stack 275. In some cases, the memory cell stack 275 can be referred to as a memory cell string 205.

[0053] Access to the memory cells 205 can be controlled by a row decoder 260 and a column decoder 250. For example, the row decoder 260 can receive a row address from the memory controller 255 and activate the appropriate word line 262 based on the received row address. Similarly, the column decoder 250 can receive a column address from the memory controller 255 and activate the appropriate digit line 265. Thus, by activating one word line 262 and one digit line 265, one memory cell 205 can be accessed.

[0054] After access, the memory cell 205 can be read or sensed by the sensing component 270. For example, the sensing component 270 can be configured to determine a stored logic value of the memory cell 205 based on a signal generated by accessing the memory cell 205. The signal can include a current, a voltage, or both, the current and voltage on the digit line 265 of the memory cell 205 can depend on the logic value stored by the memory cell 205. The sensing component 270 can include various transistors or amplifiers configured to detect and amplify the signal (e.g., current or voltage) on the digit line 265. The logic value of the memory cell 205 as detected by the sensing component 270 can be output via the input / output 280. In some cases, the sensing component 270 can be part of the column decoder 250 or the row decoder 260, or the sensing component 270 can otherwise be connected to or in electronic communication with the column decoder 250 or the row decoder 260.

[0055] The memory cell 205 can be programmed or written by activating the relevant word line 262 and digit line 265 to enable a logic value (e.g., representing one or more bits of information) to be stored in the memory cell 205. The column decoder 250 or the row decoder 260 can accept data for writing to the memory cell 205, e.g., from the input / output 280. As previously discussed, in the case of NAND memory (e.g., flash memory used in some NAND and 3D NAND memory devices), the memory cell 205 can be written by storing an electron in a floating gate or insulating material.

[0056] The memory controller 255 can control the operation (e.g., read, write, rewrite, refresh) of the memory cells 205 through various components, such as the row decoder 260, the column decoder 250, and the sensing component 270. In some cases, one or more of the row decoder 260, the column decoder 250, and the sensing component 270 can be in the same location as the memory controller 255. The memory controller 255 can generate row address signals and column address signals in order to activate the desired word lines 262 and digit lines 265. In some examples, the memory controller 255 can generate and control various voltages or currents used during the operation of the memory device 200.

[0057] In the examples described herein, the input / output 280 can communicate with a buffer having adaptive partitioning. The buffer can include a first portion dedicated as a read buffer (e.g., for storing data associated with read commands), a second portion dedicated as a write buffer (e.g., for storing data associated with write commands), and a third portion that can be dynamically allocated for storing data associated with read or write commands. Thus, the input / output 280 can receive data from the buffer to be stored at the memory device 200 (e.g., based on a write command). That is, the buffer can store data associated with a write command in the second portion or the third portion and can transfer the data to the input / output 280 for storage at the memory device 200. Additionally, the input / output 280 can transfer data (e.g., from the memory device 200) to the buffer based on a read command. In some cases, the input / output 280 can transfer data to the buffer after receiving a read command (e.g., from the reference Figure 1 memory system controller 115) based on the buffer having sufficient space for storing data associated with the read command.

[0058] Figure 3 An example of a system 300 that supports adaptive buffer partitioning in accordance with the examples disclosed herein is described. In some cases, the system 300 can be an example of the system 100 described with reference to Figure 1 Additionally, the system 300 can implement aspects of the system 100 and the memory device 200 described with reference to Figure 1 and 2 For example, the host system 305 can be an example of the host system 105, the memory system 310 can be an example of the memory system 110, and the memory system controller 315 can be an example of the memory system controller 115. Additionally, the set of memory devices 330 can include one or more memory devices described with reference to Figure 1 and 2 For example, the set of memory devices 330 can include NAND memory, PCM, self-selecting memory, 3D XPoint, other chalcogenide-based memory, FERAM, MRAM, NOR (e.g., NOR flash) memory, STT-MRAM, CBRAM, RRAM, or OxRAM.

[0059] The memory system 310 can additionally include an interface 320, a buffer 325, and a bus 335. The set of memory devices 330 can communicate with the memory system controller 315 and the buffer 325 directly or via the bus 335 using protocols specific to each type of memory device within the set of memory devices 330. Additionally, the buffer 325 and the interface 320 can communicate using protocols specific to the memory system 310 (e.g., with each other, with the memory system controller 315).

[0060] The memory system 310 can communicate with the host system 305 through the interface 320 (e.g., a front end of the memory system 310). In some cases, the interface 320 can manage the transfer of data and commands between the host system 305 and the memory system 310. That is, the interface 320 can communicate with the host system 305 according to a protocol (e.g., a Universal Flash Storage (UFS) protocol, an eMMC protocol, a PCIe). In some cases, the host system 305 can transmit one or more read or write commands to the memory system 310 via the interface 320. The interface 320 can transfer the commands (e.g., directly or via the bus 335) to the memory system controller 315. In instances where the host system 305 transmits a write command to the memory system 310, the host system 305 can additionally transmit data to the memory system 310 via the interface 320. In instances where the host system 305 transmits a read command to the memory system 310, the memory system 310 can transmit data to the host system 305 via the interface 320.

[0061] When performing an access operation (e.g., executing a read command or a write command received from the host system 305), the memory system 310 can buffer data associated with the access operation in the buffer 325 (e.g., a mid-end of the memory system 310). That is, in instances where the host system 305 transmits a read command to the memory system 310, the memory system controller 315 can facilitate the transfer of data associated with the read command from a memory device of the set of memory devices 330 to the buffer 325. The buffer 325 can temporarily store the data before transmitting the data to the host system 305 via the interface 320. Additionally, in instances where the host system 305 transmits a write command to the memory system 310, the memory system controller 315 can facilitate the transmission of data associated with the write command from the host system 305 to the buffer 325 (e.g., via the interface 320). The buffer 325 can temporarily store the data before transferring the data to one of the memory devices of the set of memory devices 330. The temporary storage of data within the buffer 325 can refer to the storage of data in the buffer 325 during the execution of an access command. That is, after the access command is completed, the data can no longer be maintained in the buffer 325 (e.g., overwritten by data used for additional read or write commands). Additionally, the buffer 325 can be a non-cache buffer. That is, the host system 305 can not read data directly from the buffer 325. For example, a read command can be placed on a queue without the operation of matching an address to an address already in the buffer (e.g., without a cache address match or lookup operation).

[0062] The memory system controller 315 can additionally store a queue that includes access commands (e.g., read commands, write commands) associated with data currently stored in the buffer 325. That is, as the buffer 325 stores data associated with an access command, the memory system controller 315 can store the access command in the queue. In some cases, each command in the queue can be associated with an address at the buffer 325. That is, a pointer can be maintained that indicates where data associated with each command is stored in the buffer 325. Thus, when a command is removed from the queue (e.g., due to the command completing), the address at which the data previously stored associated with the command can be used to store data associated with a new command. In some cases, buffer address management (e.g., pointers addressing locations in the buffer) can be performed by hardware circuitry (e.g., logic gate circuitry).

[0063] The buffer 325 can store and read data associated with read commands and write commands with adaptive partitioning. That is, the buffer 325 can include a first portion dedicated as a read buffer (e.g., for storing data associated with read commands), a second portion dedicated as a write buffer (e.g., for storing data associated with write commands), and a third portion that can be dynamically allocated to store data associated with read or write commands. Thus, based on commands received from the host system 305, the third portion of the buffer 325 can store data associated with read commands, data associated with write commands, or a combination of data associated with read commands and data associated with write commands. In some cases, the adaptive partitioning of the buffer 325 (e.g., the third portion of the buffer 325 is configured to store data associated with read commands or write commands) can reduce the likelihood that the buffer 325 does not have sufficient space for data associated with commands received from the host system when compared to a buffer with static or semi-static partitioning.

[0064] The memory system controller 315 can include firmware (e.g., controller firmware) to determine an amount of space within the buffer 325 available to store data associated with a received command. For example, if the host system 305 transmits a write command to the memory system 310, the memory system controller 315 can determine an amount of space available within the buffer 325 to store data associated with the write command. That is, the memory system controller 315 can determine an amount of space available within the first portion of the buffer 325 and the third portion of the buffer 325. If the memory system controller 315 determines that there is sufficient space within the buffer 325 to store data associated with the write command, the memory system 310 can transmit an availability indication (e.g., a ready-to-transfer indication) to the host system via the interface 320. Subsequently, the interface 320 can transfer data associated with the write command to the buffer 325 for temporary storage. In addition, the memory system controller 315 can add the write command to a queue.

[0065] In instances in which the host system 305 transmits a read command to the memory system 310, the memory system controller 315 can determine an amount of space within the buffer 325 available to store data associated with the read command. That is, the memory system controller 315 can determine an amount of space available within the second portion of the buffer 325 and the third portion of the buffer 325. If the memory system controller 315 determines that there is sufficient space within the buffer 325 to store data associated with the read command, the memory system 310 issues the read command to a memory device within the set of memory devices. Subsequently, the memory devices of the set of memory devices 330 can transfer data associated with the read command to the buffer 325 for temporary storage. In addition, the memory system controller 315 can add the read command to a queue.

[0066] Data can additionally be transferred from the buffer 325. For example, the memory system controller 315 can include a queue of previously received read and write commands. The memory system controller 315 can complete execution of the previously received commands according to an order (e.g., a first-in, first-out order, according to an order of the queue) and can subsequently remove the commands from the queue. To complete execution of a write command, the memory system controller 315 can transfer data associated with the write command temporarily stored in the buffer 325 to a memory device of the set of memory devices 330 for storage. After the write command is completed, the memory system controller 315 can remove the write command from the queue. To complete execution of a read command, the memory system controller 315 can transmit data associated with the read command temporarily stored in the buffer 325 to the host system 305 via the interface 320. After the read command is completed, the memory system controller 315 can remove the read command from the queue.

[0067] The memory system controller 315 can additionally be configured for operations associated with the set of memory devices 330. For example, the memory system controller 315 can perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, caching operations, media management operations, background refresh, health monitoring, and address translations between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 305 and physical addresses (e.g., physical block addresses) associated with memory cells within the set of memory devices 330. That is, the host system 305 can issue a command indicating one or more LBAs, and the memory system controller 315 can identify one or more physical block addresses indicated by the LBAs. In some cases, one or more contiguous LBAs can be non-contiguous physical block addresses.

[0068] Figure 4 An example of a buffer configuration 400 that supports adaptive buffer splitting according to examples disclosed herein is illustrated. The buffer configuration 400 (of buffer 425) can be referenced with respect to FIG. 4A. Figures 1 to 3 An example configuration of a memory system internal buffer is described. The buffer 425 can include a read buffer 405 (e.g., for storing data associated with read commands), a read and write buffer 410 (e.g., for storing data associated with read commands or write commands), and a write buffer 415 (e.g., for storing data associated with write commands).

[0069] The buffer 425 can have a total buffer size 435, where the buffer size 435 corresponds to a maximum amount of data that the buffer 425 can store. The buffer 425 can additionally have a minimum read buffer size 420. The minimum read buffer size 420 corresponds to a portion of the buffer 425 that is dedicated to storing data associated with read commands (e.g., a size of the read buffer 405). Additionally, the buffer 425 can be associated with a minimum write buffer size 430. The minimum write buffer size 430 corresponds to a portion of the buffer 425 that is dedicated to storing data associated with write commands (e.g., a size of the write buffer 415).

[0070] A maximum read buffer size 440 can correspond to a maximum amount of data associated with read commands that the buffer 425 can be configured to store. That is, the maximum read buffer size 440 can correspond to a size of the read buffer 405 and the read and write buffer 410. A maximum write buffer size 445 can correspond to a maximum amount of data associated with write commands that the buffer 425 can be configured to store. That is, the maximum write buffer size 445 can correspond to a size of the read and write buffer 410 and the write buffer 415.

[0071] During initialization of the buffer 425 (e.g., and buffer partitions), a controller associated with the buffer 425 (e.g., a memory system controller as described herein) can determine an amount of space within the buffer 425 available to store data associated with read and write commands. For example, the controller can determine that the amount of space within the buffer 425 available to store data associated with read commands is equal to the maximum read buffer size 440 because the read buffer 405 and the read and write buffer 410 are empty during initialization. Additionally, the controller can determine that the amount of space within the buffer available to store data associated with write commands is equal to the maximum write buffer size 445 because the read and write buffer 410 and the write buffer 415 are empty during initialization. In some cases, the controller can store an indication of the amount of space within the buffer 425 available to both read and write commands in a separate counter at the controller. In some other cases, the controller can store an indication of the amount of space within the buffer 425 currently used to store data associated with read commands in a first counter and an indication of the amount of space within the buffer 425 currently used to store data associated with write commands in a second counter. During initialization, both the first and second counters can be initialized to zero (e.g., indicating that the buffer 425 does not store any data associated with read or write commands).

[0072] When a memory system (e.g., a memory system including the buffer 425) receives a write command, the controller can compare a size of data associated with the write command to the amount of space within the buffer 425 available to store data associated with the write command. For example, the controller can compare the size of data associated with the write command to a value stored in a counter at the controller (e.g., indicating the amount of space within the buffer 425 available to store data associated with write commands). In some cases, the controller can determine a difference between the maximum write buffer size 445 and the value stored in the counter (e.g., indicating the amount of space within the buffer 425 currently used to store data associated with write commands) and the amount of data associated with read commands within the read and write buffer 410, thus determining the amount of space within the buffer 425 available to store data associated with the write command. In the event the controller determines that there is sufficient space within the buffer 425 to store data associated with the write command, the controller can transmit an availability indication to the host system. The controller can also instruct a buffer manager (e.g., a hardware layer that allocates / de-allocates space within the buffer 425) to allocate space and receive data from the memory system to store within the buffer 425. The host system can then transmit the data to the memory system to be temporarily stored at the buffer 425.

[0073] The controller can update the value of the counter indicating the amount of space within the buffer that can be used to store data associated with a read command (e.g., in the case that data associated with a write command is stored in the read and write buffer 410). In some cases, the controller can increment the value of the counter indicating the amount of space within the buffer 425 that is currently used to store data associated with a read command. In some cases, the controller can update the value of the counter immediately after transmitting the available data indication within the buffer 425 to the host system. Additionally, the controller can update the value of the counter indicating the amount of space within the buffer that can be used to store data associated with a read command (e.g., in the case that data associated with a write command is stored in the read and write buffer 410).

[0074] When a memory system (e.g., a memory system including the buffer 425) receives a read command, the controller can compare the size of data associated with the read command to the space within the buffer 425 that can be used to store data associated with the read command. For example, the controller can compare the size of data associated with the read command to the value stored in the counter at the controller (e.g., indicating the amount of space within the buffer 425 that can be used to store data associated with the read command). In some cases, the controller can determine the difference between the maximum read buffer size 440 and the value stored in the counter (e.g., indicating the amount of space within the buffer 425 that is currently used to store data associated with the read command) and the amount of data associated with a write command within the read and write buffer 410, thus determining the amount of space in the buffer 425 that can be used to store data associated with the read command. In the case that the controller determines that there is sufficient space in the buffer 425 to store data associated with the read command, the controller can issue the read command to a memory device at the memory system. The memory device can then transfer the data to the buffer 425.

[0075] The controller can update the value of the counter indicating the amount of space in the buffer that can be used to store data associated with a read command. For example, the controller can decrement the value of the counter according to the size of the data (e.g., subtract the size of the data from the value of the counter). In some cases, the controller can increment the value of the counter indicating the amount of space in the buffer 425 that is currently used to store data associated with a write command. In some cases, the controller can update the value of the counter immediately after transferring data associated with a read command to the buffer 425. Additionally, the controller can update the value of the counter indicating the amount of space in the buffer that can be used to store data associated with a read command (e.g., in the case that data associated with a read command is stored in the read and write buffer 410). Thus, the amount of space in the buffer 425 that can be used to store data associated with a read command or a write command is based on the amount of data associated with previously received read and write commands (e.g., still in the queue associated with incomplete read and write commands).

[0076] The controller can include a queue of previously received read and write commands associated with data that is being stored in the buffer 425 (e.g., incomplete read and write commands). The controller can complete execution of the previously received commands and can remove the commands from the queue. To complete execution of a write command, the controller can transfer data associated with the write command that is being stored in the buffer 425 to the memory device for storage. Based on transferring the data from the buffer 425 to the memory device, the controller can update the value of the counter indicating the amount of space in the buffer that can be used to store data associated with a write command. For example, the controller can increment the value of the counter according to the size of the data (e.g., can add the size of the data to the value of the counter). Additionally, the controller can update the value of the counter indicating the amount of space in the buffer that can be used to store data associated with a read command (e.g., in the case that data associated with a write command is stored in the read and write buffer 410).

[0077] To complete execution of a read command, the controller can transmit data associated with the read command that is being stored in the buffer 425 to the host system. Based on transmitting the data from the buffer 425 to the host system, the controller can update the value of the counter indicating the amount of space in the buffer that can be used to store data associated with a read command. For example, the controller can increment the value of the counter according to the size of the data (e.g., can add the size of the data to the value of the counter). Additionally, the controller can update the value of the counter indicating the amount of space in the buffer that can be used to store data associated with a write command (e.g., in the case that data associated with a write command is stored in the read and write buffer 410).

[0078] Figure 5An example of a flow diagram 500 that supports adaptive buffer partitioning in accordance with the examples disclosed herein is illustrated. The flow diagram 500 can be performed by the memory system controller 115, the memory controller 255, or the memory system controller 315 described with reference to Figures 1 to 4 The execution of the write command. The operations of the flow diagram 500 can be performed by the memory system controller 115, the memory controller 255, or the memory system controller 315 described with reference to Figures 1 to 3 Additionally, in some examples, the flow diagram 500 can be implemented as instructions stored in a memory (e.g., firmware stored in the local memory 120 or other memory controller or memory system as described herein). For example, the instructions, when executed by a controller (e.g., the memory system controller 315) can cause the controller to perform the operations of the flow diagram 500.

[0079] At 505, an initialization procedure can be performed. For example, the memory system can perform one or more initialization procedures (e.g., after the memory system is powered on). During initialization, the memory system can determine an amount of space within a buffer that is available to store data associated with a write command. For example, the memory system can determine that the amount of space within the buffer that is available to store data associated with a write command is equal to a maximum write buffer size. The memory system can store a value that indicates the amount of space within the buffer that is available to store data associated with a write command.

[0080] At 510, a write command can be received. For example, the memory system receives a write command associated with a set of data from a host system.

[0081] At 515, an amount of space at the buffer that is available to store data associated with the write command can be determined. For example, the memory system can determine an amount of space within the buffer that is configured to buffer data being transferred between the host system and a set of memory devices of the memory system that is available to store the set of data associated with the write command. In some cases, the amount of space can be based on a first portion of the buffer that is associated with read commands, a second portion of the buffer that is associated with write commands, and a third portion of the buffer that is associated with read commands and write commands. Additionally, the amount of space can be based on a first availability of space within the second portion of the buffer that is associated with write commands and a second availability of space within the third portion of the buffer that is associated with read commands and write commands.

[0082] At 520, the memory system can determine whether the amount of space within the buffer available to store the data set is sufficient to store the data set. If the memory system determines that the amount of space within the buffer available to store the data set is sufficient to store the data set, the memory system can proceed to 525. That is, the memory system can proceed to 525 in response to determining that the amount of space within the buffer available to store the data set is sufficient to store the data set. Alternatively, if the memory system determines that the amount of space within the buffer available to store the data set is insufficient to store the data set, the memory system can proceed to 515. That is, the memory system can proceed to 515 in response to determining that the amount of space within the buffer available to store the data set is insufficient to store the data set. In some cases, the memory system can subsequently determine (e.g., at 520) that the data set is sufficient to store in the buffer after another data set has been transferred from the buffer (e.g., to a memory device, to a host system).

[0083] At 525, a value indicative of the amount of space within the buffer available to store data associated with the write command (e.g., based on the size of the data set) can be decremented (e.g., based on the size of the data).

[0084] At 530, an indication that the amount of space within the buffer is sufficient to store the data set can be transmitted by the memory system to the host system. In some cases, the memory system can transmit the indication that the amount of space within the buffer is sufficient to store the data set based on decrementing the value indicative of the amount of space within the buffer available to store data associated with the write command.

[0085] At 535, the data set can be received by the memory system from the host system based on transmitting the indication. Additionally, the memory system can add the write command associated with the data set to a queue including incomplete command sets.

[0086] At 540, the data set can be transferred from the buffer to a memory device of the set of memory devices based on receiving the data set from the host system. In some cases, the memory system can then remove the write command associated with the data set from the queue (e.g., based on completing execution of the write command by transferring the data set to the memory device).

[0087] At 545, the stored value indicative of the amount of space within the buffer available to store data associated with the write command can be incremented (e.g., based on the size of the data set) based on transferring the data set to the memory device.

[0088] Figure 6 An example of a flow diagram 600 that supports adaptive buffer splitting is described in accordance with the examples disclosed herein. The flow diagram 600 can be related to the execution of a read command as described with reference to Figures 1 to 4 the operations of the flow diagram 600 can be performed by the memory system as described with reference to Figures 1 to 3The described memory system controller 115, memory controller 255, or memory system controller 315 performs. Additionally, in some examples, flowchart 600 can be implemented as instructions stored in a memory (e.g., firmware stored in local memory 120 or other memory controller or memory system as described herein). For example, the instructions, when executed by a controller (e.g., memory system controller 315), can cause the controller to perform the operations of flowchart 600.

[0089] At 605, an initialization procedure can be performed (e.g., after power up of the memory system). During initialization, the memory system can determine an amount of space within the buffer that is available to store data associated with a read command. For example, the memory system can determine that the amount of space within the buffer that is available to store data associated with a read command is equal to a maximum read buffer size. The memory system can store a value that indicates the amount of space within the buffer that is available to store data associated with a read command.

[0090] At 610, a read command associated with a data set can be received by the memory system from the host system.

[0091] At 615, an amount of space within the buffer that is configured to buffer a set of memory devices of the memory system that are available to store a data set associated with a read command and a host system in transit can be determined by the memory system. In some cases, the amount of space can be based on a first portion of the buffer that is associated with a read command, a second portion of the buffer that is associated with a write command, and a third portion of the buffer that is associated with a read command and a write command. Additionally, the amount of space can be based on a first availability of space within the first portion of the buffer that is associated with a read command and a second availability of space within the third portion of the buffer that is associated with a read command and a write command.

[0092] At 620, the memory system can determine whether the amount of space within the buffer that is available to store the data set is sufficient to store the data set. If the memory system determines that the amount of space within the buffer that is available to store the data set is sufficient to store the data set, the memory system can proceed to 625. That is, in response to determining that the amount of space within the buffer that is available to store the data set is sufficient to store the data set, the memory system can proceed to 625. Alternatively, if the memory system determines that the amount of space within the buffer that is available to store the data set is insufficient to store the data set, the memory system can proceed to 615. That is, in response to determining that the amount of space within the buffer that is available to store the data set is insufficient to store the data set, the memory system can proceed to 615. In some cases, the memory system can subsequently determine (e.g., at 620) that the availability in the buffer is sufficient to store the data set after another data set has been transferred from the buffer (e.g., to a memory device, to a host system).

[0093] At 625, a value indicative of an amount of space within the buffer available to store data associated with the read command can be decremented (e.g., based on a size of the data set).

[0094] At 630, the memory system can issue the read command to a memory device of the set of memory devices at the memory system based on determining that the amount of space within the buffer is sufficient to store the data set. Additionally, the memory system can issue the read command based on decrementing the value indicative of the amount of space within the buffer available to store data associated with the read command.

[0095] At 635, the data set can be transferred from the memory device to the buffer based on issuing the read command. In some cases, the memory device can transfer the data to the buffer based on decrementing the value indicative of the amount of space within the buffer available to store data associated with the read command. Additionally, the memory system can add the read command associated with the data set to the queue including the set of incomplete commands.

[0096] At 640, the data set can be transmitted from the buffer to the host system based on transferring the data to the buffer. In some cases, the memory system can then remove the read command associated with the data set from the queue (e.g., based on completing execution of the read command by transferring the data set to the host).

[0097] At 645, the stored value indicative of the amount of space within the buffer available to store data associated with the read command can be incremented (e.g., based on a size of the data set) based on transmitting the data to the host system.

[0098] Figure 7 A block diagram 700 of a memory system 705 that supports adaptive buffer splitting in accordance with examples disclosed herein is shown. The memory system 705 can be an example of the memory system described with reference to Figures 1 to 6 The aspects of the memory system described. The memory system 705 can include a command interface 710, an available space manager 715, a space indication manager 720, a data manager 725, and a value manager 730. Each of these modules can communicate, directly or indirectly (e.g., via one or more buses), with one another.

[0099] The command interface 710 can receive a write command associated with a data set from a host system. Additionally, the command interface 710 can receive a read command associated with the data set from the host system.

[0100] The available space manager 715 can determine that an amount of space within a buffer configured to buffer data being transferred between a host system and a set of memory devices of a memory system is sufficient to store a data set associated with a write command. In some cases, the buffer can include a first portion of the buffer associated with read commands, a second portion of the buffer associated with write commands, and a third portion of the buffer associated with read commands and write commands. Here, the available space manager 715 can determine the amount of space available within the buffer based on the first, second, and / or third portions of the buffer. For example, the available space manager 715 can determine the amount of space within the buffer based on the portions of the buffer configured to store data associated with write commands (e.g., the second portion and the third portion). In some cases, the available space manager 715 can also determine the amount of space within the buffer based on the first portion of the buffer.

[0101] In some examples, the available space manager 715 can determine the amount of space within the buffer available to store a data set associated with a write command based on a first amount of space available within a second portion of the buffer associated with write commands and a second amount of space available within a third portion of the buffer associated with read commands and write commands. In some cases, the first amount of space available within the second portion of the buffer associated with write commands is based on an amount of data associated with a first queue containing previously received write commands. In some cases, the second amount of space available for the third portion of the buffer associated with read commands and write commands is based on an amount of data associated with a second queue containing previously received read commands and previously received write commands. In some examples, the available space manager 715 can compare a data set size to a value indicative of an amount of space within the buffer available to store data associated with a write command, where determining that the amount of space within the buffer is sufficient to store the data set is based on the comparison.

[0102] The available space manager 715 can determine, for a buffer configured to buffer data being transferred between a set of memory devices of a memory system and a host system, that an amount of space within the buffer available to store a set of data associated with a read command is sufficient to store the set of data. In some cases, the buffer can include a first portion of the buffer associated with read commands, a second portion of the buffer associated with write commands, and a third portion of the buffer associated with read commands and write commands. Here, the available space manager 715 can determine the amount of space within the buffer available to store the set of data associated with the read command based on the first, second, and / or third portions of the buffer. For example, the available space manager 715 can determine the amount of space within the buffer based on the portions of the buffer configured to store data associated with read commands (e.g., the first portion and the third portion). In some cases, the available space manager 715 can also determine the amount of space within the buffer based on the second portion of the buffer.

[0103] In some examples, the available space manager 715 can determine, based on a first availability of space within the first portion of the buffer associated with read commands and a second availability of space within the third portion of the buffer associated with read commands and write commands, that the amount of space within the buffer available to store the set of data associated with the read command is sufficient to store the set of data. In some cases, the first availability of space within the first portion of the buffer associated with read commands is based on an amount of data associated with a first queue that includes previously received read commands. In some cases, the second availability of space for the third portion of the buffer associated with read commands and write commands is based on an amount of data associated with a second queue that includes previously received read commands and previously received write commands. In some examples, the available space manager 715 can compare the size of the set of data to a value indicative of the amount of space within the buffer available to store data associated with the read command, where determining that the amount of space within the buffer is sufficient to store the set of data is based on the comparison.

[0104] The space indication manager 720 can transmit, to the host system, an indication that the amount of space within the buffer is sufficient to store a set of data (e.g., associated with a write command). Additionally, the space indication manager 720 can issue, to a memory device of the set of memory devices, a read command based on the amount of space within the buffer being sufficient to store a set of data (e.g., associated with a read command).

[0105] The data manager 725 can receive, from the host system, a set of data through the buffer based on transmitting an indication (e.g., an indication that the amount of space within the buffer is sufficient to store a set of data associated with a write command). In some examples, the data manager 725 can transfer, from the buffer, the set of data to a memory device of the set of memory devices based on receiving the set of data from the host system.

[0106] The data manager 725 can transfer a data set from the memory device to the buffer based on issuing the read command. In some examples, the data manager 725 can transmit the data set from the buffer to the host system according to the read command and based on transferring the data set to the buffer.

[0107] The value manager 730 can store a value indicative of an amount of space available (e.g., available for data associated with a write command) within the buffer. In some examples, the value manager 730 can update the value indicative of an amount of space available within the buffer for storing data associated with a write command, where transmitting an indication (e.g., an indication that an amount of space within the buffer is sufficient to store a data set associated with a write command) can be based on updating the value. Here, updating the value can include decrementing the value based on a data set size. In some cases, the value manager 730 can update the value indicative of an amount of space available within the buffer for storing data associated with a write command based on transferring a data set to the memory device. Here, updating the value can include incrementing the value based on a data set size.

[0108] Additionally, the value manager 730 can store a value indicative of an amount of space available (e.g., available for data associated with a read command) within the buffer. In some examples, the value manager 730 can update the value indicative of an amount of space available within the buffer for storing data associated with a read command, where transferring a data set to the buffer can be based on updating the value. Here, updating the value can include decrementing the value based on a data set size. In some cases, the value manager 730 can update the value indicative of an amount of space available within the buffer for storing data associated with a read command based on transmitting a data set to the host system. Here, updating the value can include incrementing the value based on a data set size.

[0109] Figure 8 A flow diagram illustrating one or more methodologies 800 that support adaptive buffer splitting is shown. The operations of methodology 800 can be implemented by a memory system or its components as described herein. For example, the operations of methodology 800 can be performed by a memory system as described with reference to Figure 7 FIG. 1 through FIG. 7. In some examples, a memory system can execute a set of instructions to control the functional elements of the memory system to perform the described functions. Additionally or alternatively, the memory system can perform aspects of the described functions using special-purpose hardware.

[0110] At 805, the memory system can receive a write command associated with a data set from a host system. The operations of 805 can be performed according to the methods described herein. In some examples, aspects of the operations of 805 can be performed by a command interface as described with reference to Figure 7 FIG. 1 through FIG. 7. In some examples, a memory system can execute a set of instructions to control the functional elements of the memory system to perform the described functions. Additionally or alternatively, the memory system can perform aspects of the described functions using special-purpose hardware.

[0111] At 810, the memory system can determine, for a buffer configured to buffer data being transferred between the host system and the set of memory devices of the memory system, that an amount of space within the buffer available to store a set of data associated with a write command is sufficient to store the set of data, where the amount of available space within the buffer is based on a first portion of the buffer associated with a read command, a second portion of the buffer associated with a write command, and a third portion of the buffer associated with the read command and the write command. The operations of 810 can be performed according to the methods described herein. In some examples, aspects of the operations of 810 can be performed by a space manager as described with reference to Figure 7 FIG. 9 illustrates an example of a system including a host system and a memory system in accordance with aspects of the present disclosure.

[0112] At 815, the memory system can transmit, to the host system, an indication that the amount of space within the buffer is sufficient to store the set of data. The operations of 815 can be performed according to the methods described herein. In some examples, aspects of the operations of 815 can be performed by a space indication manager as described with reference to Figure 7 FIG. 9 illustrates an example of a system including a host system and a memory system in accordance with aspects of the present disclosure.

[0113] At 820, the memory system can receive, from the host system through the buffer, the set of data based on transmitting the indication. The operations of 820 can be performed according to the methods described herein. In some examples, aspects of the operations of 820 can be performed by a data manager as described with reference to Figure 7 FIG. 9 illustrates an example of a system including a host system and a memory system in accordance with aspects of the present disclosure.

[0114] In some examples, an apparatus as described herein can perform a method or methods, such as method 800. The apparatus can include features, means, or instructions for receiving, from a host system, a write command associated with a set of data, determining, for a buffer configured to buffer data being transferred between the host system and a set of memory devices of a memory system, that an amount of space within the buffer available to store the set of data associated with the write command is sufficient to store the set of data, where the amount of available space within the buffer is based on a first portion of the buffer associated with a read command, a second portion of the buffer associated with a write command, and a third portion of the buffer associated with the read command and the write command, transmitting, to the host system, an indication that the amount of space within the buffer is sufficient to store the set of data, and receiving, from the host system through the buffer, the set of data based on transmitting the indication.

[0115] Some examples of the method 800 and the apparatus described herein can further include operations, features, means, or instructions for determining, based on a first amount of space available within the second portion of the buffer associated with a write command and a second amount of space available within the third portion of the buffer associated with a read command and a write command, the amount of space within the buffer available for storing a data set associated with the write command; and storing a value indicating the amount of available space within the buffer.

[0116] Some cases of the method 800 and the apparatus described herein can further include operations, features, means, or instructions for comparing a size of the data set to the value indicating the amount of space within the buffer available for storing data associated with the write command, where determining that the amount of space within the buffer is sufficient to store the data set can be based on the comparison.

[0117] Some examples of the method 800 and the apparatus described herein can further include operations, features, means, or instructions for updating the value indicating the amount of space within the buffer available for storing data associated with the write command, where transmitting the indication is based on updating the value.

[0118] In some examples of the method 800 and the apparatus described herein, updating the value can include operations, features, means, or instructions for decrementing the value based on the size of the data set.

[0119] In some cases of the method 800 and the apparatus described herein, the first amount of space available within the second portion of the buffer associated with a write command can be based on an amount of data associated with a first queue including a previously received write command, and the second amount of space available for the third portion of the buffer associated with a read command and a write command can be based on an amount of data associated with a second queue including a previously received read command and a previously received write command.

[0120] Some examples of the method 800 and the apparatus described herein can further include operations, features, means, or instructions for transferring the data set from the buffer to a memory device of the set of memory devices based on receiving the data set from the host system.

[0121] Some examples of the method 800 and the apparatus described herein can further include operations, features, means, or instructions for updating a value indicating the amount of space within the buffer available for storing data associated with the write command based on transferring the data set to the memory device.

[0122] In some cases of the method 800 and the apparatus described herein, updating the value can include operations, features, means, or instructions for incrementing the value based on a size of the data set.

[0123] Figure 9 A flow diagram illustrating one or more methods 900 of explaining supporting adaptive buffer splitting is shown in accordance with aspects of the present disclosure. Operations of the method 900 can be implemented by a memory system, or its component, as described herein. For example, operations of the method 900 can be performed by a memory system as described with reference to Figure 7 In some examples, a memory system can execute a set of instructions to control the functional elements of a memory system to perform the described functions. Additionally or alternatively, a memory system can perform aspects of the described functions using special-purpose hardware.

[0124] At 905, the memory system can receive a read command associated with a data set from a host system. Operations of 905 can be performed in accordance with the methods described herein. In some examples, aspects of the operations of 905 can be performed by a command interface as described with reference to Figure 7 FIG. 1.

[0125] At 910, the memory system can determine, for a buffer configured to buffer data being transferred between a set of memory devices of the memory system and a host system, an amount of space within the buffer available to store a data set associated with the read command is sufficient to store the data set, where the amount of available space within the buffer is based on a first portion of the buffer associated with the read command, a second portion of the buffer associated with a write command, and a third portion of the buffer associated with the read command and the write command. Operations of 910 can be performed in accordance with the methods described herein. In some examples, aspects of the operations of 910 can be performed by an available space manager as described with reference to Figure 7 FIG. 1.

[0126] At 915, the memory system can issue the read command to a memory device of the set of memory devices based on the amount of space within the buffer sufficient to store the data set. Operations of 915 can be performed in accordance with the methods described herein. In some examples, aspects of the operations of 915 can be performed by an available space manager as described with reference to Figure 7 FIG. 1.

[0127] At 920, the memory system can transfer the data set from the memory device to the buffer based on issuing the read command. Operations of 920 can be performed in accordance with the methods described herein. In some examples, aspects of the operations of 920 can be performed by a data manager as described with reference to Figure 7 FIG. 1.

[0128] In some examples, an apparatus as described herein can perform one or more methods, such as the method 900. The apparatus can include features, means, or instructions (e.g., instructions of a non-transitory computer-readable medium that can be executed by a processor) for receiving a read command associated with a data set from a host system, determining, for a buffer configured to buffer data being transferred between a set of memory devices of a memory system and the host system, an amount of space within the buffer available to store a data set associated with the read command is sufficient to store the data set, where the amount of available space within the buffer is based on a first portion of the buffer associated with the read command, a second portion of the buffer associated with a write command, and a third portion of the buffer associated with the read command and the write command, issuing the read command to a memory device of the set of memory devices based on the amount of space within the buffer being sufficient to store the data set, and transferring the data set from the memory device to the buffer based on issuing the read command.

[0129] Some examples of the method 900 and apparatus described herein can further include operations, features, means, or instructions for determining the amount of space within the buffer available to store the data set associated with the read command based on a first availability of space within the first portion of the buffer associated with the read command and a second availability of space within the third portion of the buffer associated with the read command and the write command, and storing a value indicative of the amount of available space within the buffer.

[0130] Some instances of the method 900 and apparatus described herein can further include operations, features, means, or instructions for comparing a size of the data set to the value indicative of the amount of space within the buffer available to store data associated with the read command, where determining that the amount of space within the buffer is sufficient to store the data set can be based on the comparison.

[0131] Some examples of the method 900 and apparatus described herein can further include operations, features, means, or instructions for updating the value indicative of the amount of space within the buffer available to store data associated with the read command, where transferring the data set to the buffer is based on updating the value.

[0132] In some examples of the method 900 and apparatus described herein, updating the value can include operations, features, means, or instructions for decrementing the value based on the size of the data set.

[0133] In some cases of the method 900 and the apparatus described herein, the first space availability within the first portion of the buffer associated with read commands can be based on an amount of data associated with a first queue including previously received read commands, and the second space availability for the third portion of the buffer associated with read commands and write commands can be based on an amount of data associated with a second queue including previously received read commands and previously received write commands.

[0134] Some examples of the method 900 and the apparatus described herein can further include operations, features, means, or instructions for transmitting the data set from the buffer to the host system in accordance with the read command and based on transferring the data set to the buffer.

[0135] Some examples of the method 900 and the apparatus described herein can further include operations, features, means, or instructions for updating the value indicating the amount of space within the buffer available to store data associated with the read command based on transmitting the data set to the host system.

[0136] In some cases of the method 900 and the apparatus described herein, updating the value can include operations, features, means, or instructions for incrementing the value based on a size of the data set.

[0137] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods can be combined.

[0138] An apparatus is described. The apparatus can include an interface configured to communicate with a host system and configured to receive one or more read commands and one or more write commands from the host system; a set of memory devices configured to store one or more data sets based on the one or more read commands and the one or more write commands; and a buffer coupled with the interface and the set of memory devices and configured to transfer the one or more data sets between the interface and the set of memory devices in accordance with the one or more read commands and one or more write commands, the buffer including: a first portion configured to store data associated with the one or more read commands; a second portion configured to store data associated with the one or more write commands; and a third portion configured to store data associated with the one or more read commands and the one or more write commands.

[0139] Some examples of the device can include a first counter configured to store a value indicative of an amount of space available within the second portion of the buffer and the third portion of the buffer to store data associated with the one or more write commands.

[0140] Some examples of the device can include decrementing the value stored by the first counter based on storing data associated with the one or more write commands within the second portion of the buffer or the third portion of the buffer; and incrementing the value stored by the first counter based on transferring data associated with the one or more write commands from the buffer to a memory device of the set of memory devices.

[0141] Some examples of the device can include a second counter configured to store a value indicative of an amount of space available within the first portion of the buffer and the third portion of the buffer to store data associated with read commands.

[0142] Some examples of the device can include decrementing the value stored by the second counter based on storing data associated with the one or more read commands within the first portion of the buffer or the third portion of the buffer; and incrementing the value stored by the second counter based on transmitting data associated with the one or more read commands from the buffer to the host system.

[0143] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by a person of ordinary skill in the art that the signals can represent a bus of signals, where the bus can have a variety of bit widths.

[0144] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components in which an electron is supported to flow between the components. Components are considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if there exists any conductive path between the components that can support the flow of a signal between the components at any time. The conductive path between components that are in electronic communication with each other (or in conductive contact or connected or coupled to each other) can be open or closed at any given time, based on the operation of the device that includes the connected components. The conductive path between connected components can be a direct conductive path between the components, or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some examples, the flow of a signal between connected components can be interrupted for a period of time, e.g., using one or more intervening components such as switches or transistors.

[0145] The term "coupled" refers to the condition of components moving from an open relationship between the components, in which a signal cannot currently be communicated between the components through a conductive path, to a closed relationship between the components, in which a signal can be communicated between the components through a conductive path. When a component such as a controller couples other components together, the component initiates a change that allows a signal to flow between the other components via a conductive path that previously did not permit the flow of a signal.

[0146] The term "isolated" refers to a relationship between components in which a signal cannot currently flow between the components. Components are isolated from each other if there is an open circuit between the components. For example, components that are isolated from each other by a switch positioned between the two components are isolated from each other when the switch is open. When a controller decouples two components, the controller effects a change that prevents a signal from flowing between the components using a conductive path that previously permitted the flow of a signal.

[0147] Devices discussed herein, including memory arrays, can be formed on a semiconductor substrate such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some examples, the substrate is a semiconductor wafer. In other examples, the substrate can be a silicon-on-insulator (SOI) substrate such as a silicon-on-glass (SOG) or a silicon-on-sapphire (SOP), or an epitaxial material of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping method.

[0148] The switching components or transistors discussed herein can represent field effect transistors (FETs) and include three-terminal devices that include a source, a drain, and a gate. The terminals can be connected to other electronic components by conductive material, such as metal. The source and drain can be conductive and can include heavily doped, e.g., degenerate, semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., majority carriers are electrons), the FET can be referred to as an n-type FET. If the channel is p-type (i.e., majority carriers are holes), the FET can be referred to as a p-type FET. The channel can be capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type or p-type FET, respectively, can cause the channel to become conductive. A transistor can be "on" or "activated" when a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate. A transistor can be "off' or "deactivated" when a voltage less than the transistor's threshold voltage is applied to the transistor gate.

[0149] The description set forth herein, in connection with the appended drawings, describes example configurations and does not represent all the examples that can be implemented or that are within the scope of the claims. The term "exemplary" used herein means "serving as an example, instance, or illustration," and not "preferred" over other examples. The detailed description includes specific details for the purpose of providing an understanding of the described techniques. These techniques, however, can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form in order to avoid obscuring the concepts of the described examples.

[0150] In the appended figures, similar components or features can have the same reference label. Further, various components of the same type can be distinguished by following the convention, in which the first digit or digits identify the component, the second digit identifies the number of that component, and the third digit identifies a specific instance of the component. The specification can use a numbering notation in the form of XX_Y_Z, where XX is the component number, Y is the individual count for the component, and Z is the specific instance.

[0151] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other configuration). The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other configuration).

[0152] The techniques described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein, including in the claims, "or" as used in a list of items (for example, a list of items prefaced by a phrase such as "at least one of" or "one or more of") indicates an inclusive list such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase "based on" shall not be construed as a reference to a closed set of conditions. For example, an exemplary step that is described as "based on condition A" can be based on both a condition A and a condition B without departing from the scope of the present disclosure. In other words, as used herein, the phrase "based on" shall be construed in the same manner as the phrase "based at least in part on." The terms "if' and "as" are used interchangeably, when used to describe conditional nature of an action or process.

[0153] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can comprise RAM, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0154] The description herein is presented to enable any person skilled in the art to make or use the disclosure. Modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not intended to be limited to the examples described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: store, to a memory system comprising a set of memory devices, a first value indicative of an amount of space within a buffer available to store data associated with read commands, wherein the first value is based at least in part on a size of a second portion of the buffer dedicated to read buffering; store, to the memory system, a second value indicative of an amount of space within the buffer available to store data associated with write commands, wherein the second value is based at least in part on a size of a first portion of the buffer dedicated to write buffering and a size of a third portion of the buffer associated with read and write commands; receive, from a host system, a write command associated with a set of data; compare, by the memory system, a size of the set of data with the second value based at least in part on receiving the write command; determine, for the buffer configured to buffer data being transferred between the host system and the set of memory devices and based at least in part on a result of the comparison, that an amount of space within the buffer available to store the set of data associated with the write command is sufficient to store the set of data, wherein the amount of space available within the buffer is based at least in part on the second value; transmit, to the host system, an indication that the amount of space within the buffer is sufficient to store the set of data; receive, by the buffer from the host system, the set of data based at least in part on transmitting the indication; update the second value by an amount corresponding to the size of the set of data; and update the first value by the amount corresponding to the size of the set of data based at least in part on determining that the set of data is stored in the third portion of the buffer.

2. The non-transitory computer-readable medium of claim 1, wherein the instructions that, when executed by the processor of the electronic device, further cause the electronic device to: determine the second value based at least in part on a first availability of space within the first portion of the buffer and a second availability of space within the third portion of the buffer associated with read and write commands; and store the second value indicative of the amount of space within the buffer available to store data associated with write commands.

3. The non-transitory computer-readable medium of claim 2, wherein: the first availability of space within the first portion of the buffer is based at least in part on an amount of data associated with a first queue comprising previously received write commands; and the second availability of space for the third portion of the buffer associated with read and write commands is based at least in part on an amount of data associated with a second queue comprising previously received read commands and previously received write commands.

4. The non-transitory computer-readable medium of claim 2, wherein the instructions that, when executed by the processor of the electronic device, further cause the electronic device to: ​ based at least in part on receiving the data set from the host system, transferring the data set from the buffer to a memory device of the set of memory devices.

5. The non-transitory computer-readable medium of claim 4, wherein the instructions, which when executed by the processor of the electronic device, further cause the electronic device to: based at least in part on transferring the data set to the memory device, update the second value indicative of the amount of space within the buffer available to store data associated with the write command.

6. The non-transitory computer-readable medium of claim 5, wherein the instructions to update the second value further cause the electronic device to increment the second value based at least in part on a size of the data set.

7. A non-transitory computer-readable medium storing code comprising instructions that, when executed by a processor of an electronic device, cause the electronic device to: store, to a memory system comprising a set of memory devices, a first value indicative of an amount of space within a buffer available to store data associated with a read command, wherein the first value is based at least in part on a size of a second portion of the buffer dedicated to read buffering and a size of a third portion of the buffer associated with read commands and write commands; store, to the memory system, a second value indicative of an amount of space of the buffer available to store data associated with a write command, wherein the second value is based at least in part on a size of a first portion of the buffer dedicated to write buffering; receive, from a host system, a read command associated with a data set; based at least in part on receiving the read command, compare, by the memory system, a size of the data set to the first value; determine, for the buffer configured to buffer data being transferred between the set of memory devices and the host system, and based at least in part on a result of the comparison, that an amount of space within the buffer available to store the data set associated with the read command is sufficient to store the data set, wherein the amount of space available within the buffer is based at least in part on the first value; based at least in part on the amount of space within the buffer being sufficient to store the data set, issue the read command to a memory device of the set of memory devices; based at least in part on issuing the read command, transfer the data set from the memory device to the buffer; based at least in part on determining that the data set is stored in the third portion of the buffer, update the second value in an amount corresponding to a size of the data set; and update the first value in the amount corresponding to the size of the data set.

8. The non-transitory computer-readable medium of claim 7, wherein the instructions, which when executed by the processor of the electronic device, further cause the electronic device to: determine the first value based at least in part on a first availability of space within the second portion of the buffer and a second availability of space within the third portion of the buffer associated with read commands and write commands; and storing the first value indicative of the amount of space within the buffer available to store data associated with a read command.

9. The non-transitory computer-readable medium of claim 8, wherein: the first space availability within the second portion of the buffer is based at least in part on an amount of data associated with a first queue comprising previously received read commands; and the second space availability for the third portion of the buffer associated with read commands and write commands is based at least in part on an amount of data associated with a second queue comprising previously received read commands and previously received write commands.

10. The non-transitory computer-readable medium of claim 8, wherein the instructions, which when executed by the processor of the electronic device, further cause the electronic device to: transmit the data set from the buffer to the host system in accordance with the read command and based at least in part on transferring the data set to the buffer.

11. The non-transitory computer-readable medium of claim 10, wherein the instructions, which when executed by the processor of the electronic device, further cause the electronic device to: update the first value indicative of the amount of space within the buffer available to store data associated with the read command based at least in part on transmitting the data set to the host system.

12. The non-transitory computer-readable medium of claim 11, wherein the instructions to update the first value further cause the electronic device to increment the first value based at least in part on a size of the data set.

13. A memory device, comprising: an interface configured to communicate with a host system and configured to receive one or more read commands and one or more write commands from the host system; a set of memory devices of a memory system configured to store one or more data sets based at least in part on the one or more read commands and the one or more write commands; and a buffer coupled with the interface and the set of memory devices and configured to transfer the one or more data sets between the interface and the set of memory devices in accordance with the one or more read commands and one or more write commands, the buffer comprising: a first portion dedicated to read buffering; a second portion dedicated to write buffering; and a third portion configured to store data associated with the one or more read commands and the one or more write commands, wherein the memory device is configured to: store a first value indicative of an amount of space within the buffer available to store data associated with a read command, wherein the first value is based at least in part on a size of the first portion and a size of the third portion; store a second value indicative of an amount of space within the buffer available to store data associated with a write command, wherein the second value is based at least in part on a size of the second portion and a size of the third portion; based at least in part on determining whether a first set of data received by the memory device in association with a write command is stored in the third portion and based at least in part on comparing, by the memory system, a size of the first set of data to the second value, updating the first value to correspond to an amount of size of the one or more sets of data; based at least in part on determining whether a second set of data received by the memory device in association with a read command is stored in the third portion and based at least in part on comparing, by the memory system, a size of the second set of data to the first value, updating the second value to correspond to an amount of size of the one or more sets of data.

14. The memory device of claim 13, further comprising a first counter configured to store the second value indicative of an amount of space within the second portion of the buffer and the third portion of the buffer available to store data associated with the one or more write commands.

15. The memory device of claim 14, further comprising a controller configured to: decrement the second value stored by the first counter based at least in part on storing data associated with the one or more write commands within the second portion of the buffer or the third portion of the buffer; and increment the second value stored by the first counter based at least in part on transferring data associated with the one or more write commands from the buffer to a memory device of the set of memory devices.

16. The memory device of claim 13, further comprising a second counter configured to store the first value indicative of an amount of space within the first portion of the buffer and the third portion of the buffer available to store data associated with read commands.

17. The memory device of claim 16, further comprising a controller configured to: decrement the first value stored by the second counter based at least in part on storing data associated with the one or more read commands within the first portion of the buffer or the third portion of the buffer; and increment the first value stored by the second counter based at least in part on transmitting data associated with the one or more read commands from the buffer to the host system.

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