Integrated circuit device

Abstract

An integrated circuit device includes a sense amplifier configured to sense a voltage change of a bit line, wherein the sense amplifier includes a sense amplifier cell connected to the bit line and a complementary bit line, configured to sense the voltage change of the bit line in response to a control signal, configured to adjust voltages of the bit line and the complementary sense bit line based on the sensed voltage change, and including a first PMOS transistor and a first NMOS transistor, and a first offset cancellation cell connecting the bit line to the complementary sense bit line in response to an offset cancellation signal, and including a first offset cancellation transistor arranged between the first NMOS transistor and the first PMOS transistor, wherein the first offset cancellation transistor shares a common impurity region with the first NMOS transistor.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0116217, filed on September 10, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to integrated circuit devices, and more specifically, to integrated circuit devices including a sense amplifier. Background Technology

[0004] Because electronic products need to be miniaturized, multifunctional, and high-performance, high-capacity integrated circuit devices are required, and increasing integration density is necessary to provide such devices. As the feature size of memory devices, such as DRAM devices, decreases, the gate length of the transistors used to drive the memory devices (e.g., transistors constituting sense amplifiers) can decrease, or threshold voltage deviations in the transistors may occur. As a result, the problem of offset noise in the sense amplifier may arise. Summary of the Invention

[0005] This disclosure provides an integrated circuit device with excellent electrical characteristics, wherein the sense amplifier has a relatively low and relatively uniform threshold voltage even when the feature size of the memory device is reduced.

[0006] According to one aspect of this disclosure, an integrated circuit device includes a sense amplifier configured to sense voltage changes in a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, the sense amplifier unit being configured to sense the voltage changes in the bit line in response to a control signal and adjust the voltages of the sense bit line and the complementary sense bit line based on the sensed voltage changes, the sense amplifier unit including a first PMOS transistor and a first NMOS transistor; and a first offset cancellation unit connecting the bit line to the complementary sense bit line in response to an offset cancellation signal, the first offset cancellation unit including a first offset cancellation transistor disposed between the first NMOS transistor and the first PMOS transistor, wherein the first offset cancellation transistor and the first NMOS transistor share a common impurity region.

[0007] According to one aspect of this disclosure, an integrated circuit device includes a sense amplifier configured to sense voltage changes on a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, the sense amplifier unit being configured to sense the voltage changes on the bit line in response to a control signal and to adjust the voltages of the sense bit line and the complementary sense bit line based on the sensed voltage changes, the sense amplifier unit including a first NMOS transistor; and a first offset cancellation unit connecting the bit line to the complementary sense bit line in response to an offset cancellation signal, the first offset cancellation unit including a component adjacent to the first NMOS transistor. A first offset cancellation transistor is disposed, wherein the first NMOS transistor includes: a first gate pattern disposed on a first active region of a substrate, the first gate pattern including a pair of first sidewalls extending in a first direction parallel to the upper surface of the substrate and a pair of second sidewalls extending in a second direction parallel to the upper surface of the substrate; a first impurity region disposed in a first upper portion of the substrate and adjacent to one of the first sidewalls of the pair of first sidewalls of the first gate pattern; and a common impurity region disposed in a second upper portion of the substrate and adjacent to one of the second sidewalls of the pair of second sidewalls of the first gate pattern.

[0008] According to one aspect of this disclosure, an integrated circuit device includes a sense amplifier configured to read voltage changes of a bit line, wherein the sense amplifier includes: a sense amplifier unit connected to the bit line and a complementary bit line, the sense amplifier unit being configured to read the voltage changes of the bit line in response to a control signal and adjust the voltages of the sense bit line and the complementary sense bit line based on the read voltage changes, the sense amplifier unit including a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; and a first offset cancellation unit that connects the bit line to the complementary sense bit line in response to an offset cancellation signal, the first offset cancellation unit including a first offset cancellation transistor disposed adjacent to the first NMOS transistor, wherein the first PMOS transistor is connected between a first control signal line and the complementary sense bit line, wherein a first gate pattern of the first PMOS transistor is connected to the sense bit line, wherein the second PMOS transistor is connected between the first control signal line and the sense bit line, wherein the... The second gate pattern of the second PMOS transistor is connected to the complementary read bit line, wherein the first NMOS transistor is connected between the second control signal line and the complementary read bit line, wherein the third gate pattern of the first NMOS transistor is connected to the bit line, wherein the second NMOS transistor is connected between the second control signal line and the read bit line, wherein the fourth gate pattern of the second NMOS transistor is connected to the complementary bit line, and wherein the first NMOS transistor includes: the third gate pattern disposed on a first active region of a substrate, the third gate pattern including a pair of first sidewalls extending in a first direction parallel to the upper surface of the substrate and a pair of second sidewalls extending in a second direction parallel to the upper surface of the substrate; a first impurity region disposed in a first upper portion of the substrate and adjacent to one of the first sidewalls of the pair of first sidewalls of the third gate pattern; and a common impurity region disposed in a second upper portion of the substrate and adjacent to one of the second sidewalls of the pair of second sidewalls of the third gate pattern. Attached Figure Description

[0009] The embodiments will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a block diagram illustrating an example construction of an integrated circuit device according to an example embodiment;

[0011] Figure 2 This is a plan view constructed according to an example arrangement of an integrated circuit device based on an example embodiment;

[0012] Figure 3This is a circuit diagram of the readout amplifier according to an example embodiment;

[0013] Figure 4 This is an equivalent circuit diagram of the readout amplifier unit according to the example embodiment;

[0014] Figure 5 This is a schematic diagram illustrating the arrangement of the readout amplifier according to an example embodiment;

[0015] Figure 6 yes Figure 5 A magnified view of region CX1 in the image;

[0016] Figure 7 It is along Figure 6 A cross-sectional view taken by line A1-A1' in the diagram;

[0017] Figure 8 It is along Figure 6 A cross-sectional view taken from line B1-B1' in the diagram;

[0018] Figure 9 This is a layout diagram of the readout amplifier according to an example embodiment;

[0019] Figure 10 It is along Figure 9 A cross-sectional view taken by line A1-A1' in the diagram;

[0020] Figure 11 This is a layout diagram of the readout amplifier according to an example embodiment;

[0021] Figure 12 It is along Figure 11 A cross-sectional view taken from line B1-B1' in the diagram;

[0022] Figure 13 yes Figure 11 A schematic layout diagram of the active region and the first gate pattern in the diagram;

[0023] Figure 14 This is a layout diagram of the cell array region of an integrated circuit device according to an example embodiment;

[0024] Figure 15 It is along Figure 14 A cross-sectional view taken by line A2-A2' in the diagram;

[0025] Figure 16 This is a layout diagram of the cell array region of an integrated circuit device according to an example embodiment;

[0026] Figure 17 This is a perspective view of an integrated circuit device;

[0027] Figure 18 It shows along Figure 16The cross-sectional view taken by lines X1-X1' and Y1-Y1' in the diagram;

[0028] Figure 19 It is a layout diagram of the cell array region of an integrated circuit device according to an example embodiment; and

[0029] Figure 20 This is a perspective view of an integrated circuit device. Detailed Implementation

[0030] The following describes exemplary embodiments in detail with reference to the accompanying drawings.

[0031] It will be understood that when an element or layer is referred to as being "above," "over," "on," "below," "below," "connected to," or "coupled to" another element or layer, that element or layer may be directly above, above, above, below, below, or under that other element or layer, directly connected to or coupled to that other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being "above," "over," "below," "below," "below," "directly connected to," or "directly coupled to" another element or layer, there are no intermediate elements or layers. Throughout the text, the same reference numerals denote the same elements.

[0032] In this document, for ease of description, spatial relative terms such as “above,” “over,” “up,” “above,” “below,” “below,” “under,” “under,” etc., are used to describe the relationship of one element or feature to another element(s), as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are also intended to cover different orientations of the device during use or operation. For example, if the device in the figures is flipped, an element described as “below” or “under” other elements or features will be oriented as “above” other elements or features. Therefore, the term “below” can encompass both above and below orientations. The device can be oriented in other ways (rotated 90 degrees or other directions), and the spatial relative descriptions used herein are interpreted accordingly.

[0033] For the sake of brevity, conventional components of a semiconductor device may or may not be described in detail in this document.

[0034] Figure 1 This is a block diagram illustrating an example construction of an integrated circuit device 100 according to an example embodiment.

[0035] refer to Figure 1The integrated circuit device 100 may include a first region 22 and a second region 24. The integrated circuit device 100 may include a semiconductor-based memory device. For example, the integrated circuit device 100 may include volatile memory (such as dynamic random access memory (RAM) (DRAM), synchronous DRAM (SDRAM), double data rate (DDR) SDRAM (DDRSDRAM), low power double data rate SDRAM (LPDDR SDRAM), graphics DDR (GDDR) synchronous DRAM (SDRAM) (GDDRSDRAM), DDR3 SDRAM, DDR4 SDRAM and thyristor RAM (TRAM)) and non-volatile memory (such as phase change RAM (PRAM), magnetic RAM (MRAM) and resistive RAM (RRAM)).

[0036] In some embodiments, the first region 22 may include a memory cell region of a DRAM device, and the second region 24 may include a peripheral circuitry region of a DRAM device. The first region 22 may include a memory cell array 22A.

[0037] The second region 24 can output data via the data line DQ in response to commands CMD, addresses ADDR, and control signals received from an external device (e.g., a memory controller). The integrated circuit device 100 may include a command decoder 52, control logic 54, an address buffer 62, a row decoder 64, a column decoder 66, a sense amplifier 70, and data input / output (I / O) circuitry 80.

[0038] The memory cell array 22A may include multiple memory cells arranged in a matrix format with multiple rows and columns. The memory cell array 22A may include multiple word lines WL (see reference) connected to the memory cells. Figure 3 ) and multiple bit lines BL (reference) Figure 1 Multiple word lines (WL) can be connected to rows of memory cells, and multiple bit lines (BL) can be connected to columns of memory cells.

[0039] Command decoder 52 can decode write enable signal / WE, row address strobe signal / RAS, column address strobe signal / CAS, chip select signal / CS, etc., received from external devices (e.g., memory controllers), thereby generating control signals corresponding to commands CMD by control logic 54. Command CMD may include activation commands, read commands, write commands, precharge commands, etc.

[0040] Address buffer 62 can receive address ADDR from the memory controller, which is an external device. Address ADDR may include row address RA for addressing rows of memory cell array 22A and column address CA for addressing columns of memory cell array 22A. Address buffer 62 can provide row address RA to row decoder 64 and column address CA to column decoder 66.

[0041] The row decoder 64 can select any one of the multiple word lines WL connected to the memory cell array 22A. The row decoder 64 can decode the row address RA received from the address buffer 62, select any word line WL corresponding to the row address RA, and activate the selected word line WL.

[0042] The column decoder 66 can select any one of the multiple bit lines BL of the memory cell array 22A. The column decoder 66 can decode the column address CA received from the address buffer 62 and select the specific bit line BL corresponding to the column address CA.

[0043] The sense amplifier 70 can be connected to the bit lines BL of the memory cell array 22A. The sense amplifier 70 can read the voltage changes of a selected bit line from the multiple bit lines BL, amplify and output the read voltage changes. The data input / output circuit 80 can output data to the outside via the data line DQ based on the voltage read and amplified by the sense amplifier 70.

[0044] The sense amplifier 70 can receive an isolation signal ISO and an offset cancellation signal OC from control logic 54. The sense amplifier 70 can perform an offset cancellation operation based on the isolation signal ISO and the offset cancellation signal OC. For example, offset can refer to a difference in characteristics, such as the threshold voltage between the semiconductor elements constituting the sense amplifier 70. For example... Figure 3 As shown, the sense amplifier 70 may include an NMOS transistor and an offset cancellation transistor sharing a common impurity region. Because the NMOS transistor and offset cancellation transistor included in the sense amplifier 70 share a common impurity region, the NMOS transistor can have a relatively low uniformity threshold.

[0045] In the integrated circuit device 100 according to the example embodiment, the effective read margin of the read amplifier 70 can be improved as the read amplifier 70 performs an offset cancellation operation.

[0046] Figure 2 This is a plan view constructed according to an example arrangement of an integrated circuit device 100 in an example embodiment.

[0047] refer to Figure 2The integrated circuit device 100 may include a plurality of first regions 22. Each of the plurality of first regions 22 may be surrounded by a second region 24. In some example embodiments, each of the plurality of first regions may include a cell array region MCA of DRAM elements, and the second region 24 may include a core region and a region in which peripheral circuitry of DRAM elements is formed (hereinafter referred to as the "peripheral circuitry region").

[0048] Section 24 may include a sub-word line driver block SWD, a sense amplifier block S / A, and a junction block CJT. Multiple sense amplifiers 70 (see reference) can be arranged in the sense amplifier block S / A. Figure 1 The junction block CJT can be located at the intersection of the sub-word line driver block SWD and the sense amplifier block S / A. The power driver and ground driver for driving the sense amplifier 70 can be alternately arranged in the junction block CJT. Peripheral circuitry such as inverter chains and input / output circuits can also be formed in the second zone 24.

[0049] Figure 3 This is a circuit diagram of the readout amplifier 70 according to an example embodiment. Figure 4 This is an equivalent circuit diagram of the readout amplifier unit 75 according to the example embodiment.

[0050] refer to Figure 3 and Figure 4 The sense amplifier 70 may include a first isolation unit 71 and a second isolation unit 72, a first offset cancellation unit 73 and a second offset cancellation unit 74, and a sense amplifier unit 75.

[0051] The first isolation unit 71 can be connected between the bit line BL and the read bit line SABL, and the second isolation unit 72 can be connected between the complementary bit line BLB and the complementary read bit line SABLB. The first isolation unit 71 and the second isolation unit 72 can receive the isolation signal ISO and operate in response to the isolation signal ISO.

[0052] The first isolation unit 71 may include a first isolation transistor ISO_1, which connects or blocks between the bit line BL and the read bit line SABL in response to the isolation signal ISO. One end of the first isolation transistor ISO_1 may be connected to the bit line BL, the other end of the first isolation transistor ISO_1 may be connected to the read bit line SABL, and the gate of the first isolation transistor ISO_1 may be connected to the line of the isolation signal ISO.

[0053] The second isolation unit 72 may include a second isolation transistor ISO_2, which connects or blocks between the complementary bit line BLB and the complementary read bit line SABLB in response to the isolation signal ISO. One end of the second isolation transistor ISO_2 may be connected to the complementary bit line BLB, the other end of the second isolation transistor ISO_2 may be connected to the complementary read bit line SABLB, and the gate of the second isolation transistor ISO_2 may be connected to the line of the isolation signal ISO.

[0054] The first offset cancellation unit 73 can be connected between the bit line BL and the complementary read bit line SABLB, and the second offset cancellation unit 74 can be connected between the complementary bit line BLB and the read bit line SABLB. The first offset cancellation unit 73 and the second offset cancellation unit 74 can receive an offset cancellation signal OC and operate in response to the offset cancellation signal OC.

[0055] The first offset cancellation unit 73 may include a first offset cancellation transistor OC_1, which is used to connect or block between bit line BL and complementary read bit line SABLB in response to the offset cancellation signal OC. One end of the first offset cancellation transistor OC_1 may be connected to bit line BL, the other end of the first offset cancellation transistor OC_1 may be connected to complementary read bit line SABLB, and the gate of the first offset cancellation transistor OC_1 may be connected to the line of the offset cancellation signal OC.

[0056] The second offset cancellation unit 74 may include a second offset cancellation transistor OC_2, which connects or blocks between the complementary bit line BLB and the read bit line SABL in response to the offset cancellation signal OC. One end of the second offset cancellation transistor OC_2 may be connected to the complementary bit line BLB, the other end of the second offset cancellation transistor OC_2 may be connected to the read bit line SABL, and the gate of the second offset cancellation transistor OC_2 may be connected to the line of the offset cancellation signal OC.

[0057] The sense amplifier unit 75 can be connected between the sense bit line SABL and the complementary sense bit line SABLB, and can detect and amplify the voltage difference between the sense bit line BL and the complementary sense bit line BLB according to the first control signal LA and the second control signal LAB. The sense amplifier unit 75 may include a first PMOS transistor P_1 and a second PMOS transistor P_2, as well as a first NMOS transistor N_1 and a second NMOS transistor N_2.

[0058] One end of the first PMOS transistor P_1 can be connected to the complementary read bit line SABLB, and the other end of the first PMOS transistor P_1 can be connected to the line of the first control signal LA. The gate of the first PMOS transistor P_1 can also be connected to the read bit line SABLB. Similarly, one end of the second PMOS transistor P_2 can be connected to the read bit line SABLB, and the other end of the second PMOS transistor P_2 can be connected to the line of the first control signal LA. The gate of the second PMOS transistor P_2 can also be connected to the complementary read bit line SABLB.

[0059] One end of the first NMOS transistor N_1 can be connected to the complementary read bit line SABLB, and the other end of the first NMOS transistor N_1 can be connected to the line of the second control signal LAB. The gate of the first NMOS transistor N_1 can also be connected to bit line BL. One end of the first NMOS transistor N_1 and the other end of the first offset cancellation transistor OC_1 can also be connected to the complementary read bit line SABLB. The first NMOS transistor N_1 and the first offset cancellation transistor OC_1 can share the common impurity region SDC (reference). Figure 6 For example, one end of the first NMOS transistor N_1 and the other end of the first offset cancellation transistor OC_1 may include a portion of the same active region (e.g., the first common impurity region SDC1).

[0060] One end of the second NMOS transistor N_2 can be connected to the read bit line SABL, and the other end of the second NMOS transistor N_2 can be connected to the line of the second control signal LAB. The gate of the second NMOS transistor N_2 can be connected to the complementary bit line BLB. One end of the second NMOS transistor N_2 can be connected to the read bit line SABL, and the other end of the second offset cancellation transistor OC_2 can also be connected to the read bit line SABL. The second NMOS transistor N_2 and the second offset cancellation transistor OC_2 can share a common impurity region. For example, one end of the second NMOS transistor N_2 and the other end of the second offset cancellation transistor OC_2 may include a portion of the same active region (e.g., the second common impurity region SDC2).

[0061] Bit line BL can be connected to one end of the cell transistor MCT included in the memory cell MC. Word line WL can be connected to the gate of the cell transistor MCT.

[0062] Figure 5 This is a schematic diagram illustrating the arrangement of the readout amplifier 70 according to an example embodiment. Figure 6 yes Figure 5 A magnified view of region CX1 in the image. Figure 7 It is along Figure 6The cross-sectional view taken by line A1-A1' in the diagram, and Figure 8 It is along Figure 6 The cross-sectional view taken from line B1-B1' in the diagram.

[0063] refer to Figures 5 to 8 The sense amplifier 70 can be arranged between bit line BL and complementary bit line BLB. The first PMOS transistor P_1 and the second PMOS transistor P_2 can be arranged in the center portion of the sense amplifier 70 and on either side of the sense amplifier 70. The first NMOS transistor N_1 can be arranged adjacent to bit line BL, and the second NMOS transistor N_2 can be arranged adjacent to complementary bit line BLB.

[0064] The first PMOS transistor P_1 may include an active region P10 and a gate pattern P12, and the second PMOS transistor P_2 may include an active region P20 and a gate pattern P22. The active region P10 of the first PMOS transistor P_1 may be connected to the active region P20 of the second PMOS transistor P_2, but is not limited thereto.

[0065] The first NMOS transistor N_1 may include an active region N10 and a first gate pattern N12, and the second NMOS transistor N_2 may include an active region N20 and a second gate pattern N22.

[0066] The first offset cancellation transistor OC_1 and the first isolation transistor ISO_1 can be disposed between the first NMOS transistor N_1 and the first PMOS transistor P_1. The first offset cancellation transistor OC_1 can be disposed adjacent to the first NMOS transistor N_1, and the first isolation transistor ISO_1 can be disposed adjacent to the first PMOS transistor P_1. The first offset cancellation transistor OC_1 may include an active region OC10 and a first offset cancellation gate pattern OC12, and the first isolation transistor ISO_1 may include an active region OC10 and a first isolation gate pattern ISO12.

[0067] The active region OC10 of the first offset elimination transistor OC_1 can be connected to the active region N10 of the first NMOS transistor N_1. In this case, the active region OC10 can be integrally formed with the active region N10 instead of being separated from it. The active regions OC10 and N10 can be doped with impurity ions, and represent the upper part of the substrate 110 with a certain impurity concentration.

[0068] The second offset cancellation transistor OC_2 and the second isolation transistor ISO_2 can be disposed between the second NMOS transistor N_2 and the second PMOS transistor P_2. The second offset cancellation transistor OC_2 can be disposed adjacent to the second NMOS transistor N_2, and the second isolation transistor ISO_2 can be disposed adjacent to the second PMOS transistor P_2. The second offset cancellation transistor OC_2 may include an active region OC20 and a second offset cancellation gate pattern OC22, and the second isolation transistor ISO_2 may include an active region OC20 and a second isolation gate pattern ISO22.

[0069] The active region OC20 of the second offset cancellation transistor OC_2 can be connected to the active region N20 of the second NMOS transistor N_2. In this case, the active region OC20 can be formed integrally with the active region N20 instead of being separated from it.

[0070] The offset cancellation signal OC can be transmitted to the first offset cancellation gate pattern OC12 and the second offset cancellation gate pattern OC22, and the isolation signal ISO can be transmitted to the first isolation gate pattern ISO12 and the second isolation gate pattern ISO22.

[0071] Figure 5 An example is shown in which a first NMOS transistor N_1, a first offset cancellation transistor OC_1, a first isolation transistor ISO_1, a first PMOS transistor P_1, a second PMOS transistor P_2, a second isolation transistor ISO_2, a second offset cancellation transistor OC_2, and a second NMOS transistor N_2 are arranged sequentially in a first direction X, and four groups of these transistors are arranged in a second direction Y. Two adjacent first NMOS transistors N_1 in the second direction Y can share an active region N10, and two adjacent second NMOS transistors N_2 in the second direction Y can share an active region N20. Two adjacent first PMOS transistors P_1 in the second direction Y can share an active region P10, and two adjacent second PMOS transistors P_2 in the second direction Y can share an active region P20. However, this disclosure is not limited thereto.

[0072] like Figure 6 As shown, for example, a first active region AC1 can be defined in the substrate 110. The first active region AC1 can be a region formed by doping impurity ions onto the upper part of the substrate 110, and Figure 5 The active region N10 of the first NMOS transistor N_1 and the active region OC10 of the first offset cancellation transistor OC_1 shown can be collectively referred to as the first active region AC1.

[0073] The first active area AC1 may include a first main active area AM1, a second main active area AM2, and an extended active area AE. The extended active area AE may be arranged between the first main active area AM1 and the second main active area AM2.

[0074] The first gate pattern N12 may extend in the first direction X with a relatively long length on the first main active region AM1 (see [reference]). Figure 6 Furthermore, the first offset elimination gate pattern OC12 on the second main active region AM2 can extend in the second direction Y with a relatively long length. The width of the extended active region AE in the second direction Y (i.e., the distance across the active region AE) can be smaller than the width of the first main active region AM1 in the second direction Y (i.e., the distance across the first main active region AM1) or the width of the second main active region AM2 in the second direction Y (i.e., the distance across the second main active region AM2).

[0075] The channel region CHR can be formed in the portion of the first primary active region AM1 that overlaps perpendicularly with the first gate pattern N12. In some embodiments, when the substrate 110 includes a portion of a wafer having a crystallographic orientation according to the crystallographic {001} plane of silicon, the channel direction of the channel region CHR can be... <100> Orientation (e.g.,

[100] and

[010] orientations). In some embodiments, when the substrate 110 includes a portion of a wafer having a crystallographic orientation according to the crystallographic {110} plane of silicon, the channel orientation of the channel region CHR may be <110> Direction (e.g.,

[110] direction). However, the channel direction of the channel region CHR is not limited to this.

[0076] The active region N10 of the first NMOS transistor N_1 can correspond to the first main active region AM1, and the active region OC10 of the first offset cancellation transistor OC_1 can correspond to the second main active region AM2. As described above, the two first NMOS transistors N_1 can share the active region N10 in the second direction Y, and therefore, the two first gate patterns N12 can be arranged separately from each other in the first main active region AM1 in the second direction Y. Furthermore, two first offset cancellation transistors OC_1 that are adjacent to each other in the second direction Y can not share the active region OC10, but can share the first offset cancellation gate pattern OC12. Therefore, the two second main active regions AM2 can be arranged separately from each other in the second direction Y, and one first offset cancellation gate pattern OC12 can extend in the second direction Y to intersect or overlap with the two second main active regions AM2.

[0077] The first gate pattern N12 may include a pair of first sidewalls NSW1 extending in the first direction X and separated from each other in the second direction Y, and a pair of second sidewalls NSW2 extending in the second direction Y and separated from each other in the first direction X. A first impurity region SD1 may be disposed in a first main active region AM1 disposed adjacent to one of the first sidewalls NSW1 of the first gate pattern N12. For example, the first impurity region SD1 may include a highly doped region doped with N-type impurities. The first impurity region SD1 may correspond to the source or drain region of the first NMOS transistor N_1. Figure 6 As shown, a first contact CON1 can be arranged on the first impurity region SD1.

[0078] The common impurity region SDC can be disposed in the second main active region AM2, which is adjacent to a second sidewall NSW2 of the first gate pattern N12. The common impurity region SDC can correspond to the source or drain region of the first NMOS transistor N_1. A common contact COC can be disposed on the common impurity region SDC.

[0079] like Figure 6 As shown, for example, the first impurity region SD1 and the common impurity region SDC can be arranged in an asymmetrical structure centered on the first gate pattern N12. For instance, the first impurity region SD1 can be arranged adjacent to one of the pair of first sidewalls NSW1 of the first gate pattern N12, and the common impurity region SDC can be arranged adjacent to one of the pair of second sidewalls NSW2 of the first gate pattern N12. In other words, the first impurity region SD1 can be arranged separately from the first gate pattern N12 in the second direction Y, and the common impurity region SDC can be arranged separately from the first gate pattern N12 in the first direction X.

[0080] Since the first impurity region SD1 and the common impurity region SDC are arranged in an asymmetrical structure centered on the first gate pattern N12, when the first NMOS transistor N_1 is turned on, a carrier movement path MD10 with an L-shape or an inverted L-shape can be formed from the first impurity region SD1 to the common impurity region SDC, and carriers can move along the carrier movement path MD10 in both the first direction X and the second direction Y. Furthermore, since the common impurity region SDC is formed in the second main active region AM2, the carrier movement path MD10 can extend from the common impurity region SDC to the first main active region AM1 via the extended active region AE.

[0081] The first offset-eliminating gate pattern OC12 may include a pair of first sidewalls OSW1 extending in the second direction Y and separated from each other in the first direction X. A common impurity region SDC may be disposed in the portion of the second main active region AM2 adjacent to one of the first sidewalls OSW1, and a common contact COC may be disposed on the common impurity region SDC. The common impurity region SDC may correspond to the source or drain region of the first NMOS transistor N_1, and may also correspond to the source or drain region of the first offset-eliminating transistor OC_1.

[0082] The second impurity region SD2 can be disposed in the portion of the second main active region AM2 adjacent to the other first sidewall OSW1 of a pair of first sidewalls OSW1, and the second contact CON2 can be disposed on the second impurity region SD2. The second impurity region SD2 can correspond to the source region or drain region of the first offset elimination transistor OC_1. Additionally, the third impurity region SD3 can be disposed in the portion of the second main active region AM2 adjacent to the sidewall of the first isolation gate pattern ISO12, and the third contact CON3 can be disposed on the third impurity region SD3. Furthermore, the gate contact COG1 can be disposed on the first gate pattern N12.

[0083] like Figure 7 and Figure 8 As shown, each of the first gate pattern N12, the first offset-eliminating gate pattern OC12, and the first isolation gate pattern ISO12 may include a gate insulating layer 120P, a gate electrode 130P, and a gate capping layer 142P. The gate electrode 130P may have a stacked structure of a first conductive layer 132P, a second conductive layer 134P, and a third conductive layer 136P. Additionally, gate spacers 138P may be disposed on the sidewalls of the stacked structure. The first gate pattern N12, the first offset-eliminating gate pattern OC12, and the first isolation gate pattern ISO12 may be covered by an interlayer insulating layer 150P.

[0084] The gate insulating layer 120P may include at least one of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, an oxide / nitride / oxide (ONO) layer, and a high-k dielectric layer with a dielectric constant higher than that of the silicon oxide layer. The gate electrode 130P may include a first conductive layer 132P, a second conductive layer 134P, and a third conductive layer 136P. The gate spacer 138P may include silicon nitride, and the gate cap layer 142P may include silicon nitride. Each of the first contact CON1, the second contact CON2, the third contact CON3, the common contact COC, and the gate contact COG1 may include a conductive barrier layer 162P and a contact conductive layer 164P.

[0085] In some example embodiments, the materials constituting the first conductive layer 132P, the second conductive layer 134P, and the third conductive layer 136P of the gate electrode 130P can be respectively related to the lower conductive pattern 132B included in the bit line BL in each cell array region MCA (see reference). Figure 15 ), intermediate conductive pattern 134B (reference) Figure 15 ) and the conductive pattern 136B (reference) Figure 15 The constituent materials of the conductive barrier layer 162P and the contact conductive layer 164P can be the same as those of the landing pads LP in the cell array region MCA (reference). Figure 15 The conductive barrier layer 162P and the landing pad conductive layer 164B included in the ) (refer to Figure 15 The constituent materials are the same. However, this disclosure is not limited thereto.

[0086] As described above, the first NMOS transistor N_1 and the first offset cancellation transistor OC_1 can share the common impurity region SDC and the common contact COC. Therefore, the effective gate length Lg of the first NMOS transistor N_1 can be increased. For example, the effective gate length Lg can be from approximately 10 nm to approximately 500 nm, but is not limited thereto.

[0087] In related art devices, the first NMOS transistor N_1 may include a pair of impurity regions disposed on both sides of a pair of first sidewalls NSW1, and the width of the gate pattern (width in the second direction Y) may be reduced as the integrated circuit device is scaled down, and there may also be a problem that the effective gate length Lg is reduced. In this case, since the distance between the pair of impurity regions and the channel region is relatively short, the following problems may occur: drain-induced barrier lowering (DIBL) occurs, and the threshold voltage of the transistor constituting the sense amplifier increases, or the threshold voltage deviation increases.

[0088] However, according to the example embodiment, since the first impurity region SD1 and the common impurity region SDC are arranged in an asymmetrical structure centered on the first gate pattern N12, the first gate pattern N12 can have a relatively large width (or a relatively long effective gate length Lg). Furthermore, because a relatively long distance is ensured between the first gate pattern N12 and the common impurity region SDC, an increase in the threshold voltage due to the DIBL phenomenon can be prevented. Therefore, the transistor constituting the sense amplifier 70 according to the example embodiment can have a relatively low threshold voltage or a relatively uniform threshold voltage, and the integrated circuit device 100 including the sense amplifier 70 can have excellent electrical performance.

[0089] Figure 9This is a layout diagram of the readout amplifier 70A according to an example embodiment, and Figure 10 It is along Figure 9 The cross-sectional view taken by line A1-A1' in the diagram. Figure 9 and Figure 10 In, with Figures 1 to 8 The same reference numerals in the figures can represent the same components.

[0090] refer to Figure 9 and Figure 10 The first impurity region SD1 can be arranged adjacent to one of the first sidewalls NSW1 of the pair of first sidewalls NSW1 of the first gate pattern N12, and the common impurity region SDC can be arranged adjacent to one of the second sidewalls NSW2 of the pair of second sidewalls NSW2 of the first gate pattern N12. One of the first sidewalls NSW1 of the pair of first sidewalls NSW1 of the first gate pattern N12 can be aligned with the sidewall of the first main active region AM1A. The width of the first main active region AM1A in the second direction Y can be less than [a certain value]. Figures 6 to 8 The width of the first primary active region AM1 is shown.

[0091] In related technology devices, the first NMOS transistor N_1 may include a pair of impurity regions arranged on both sides of a pair of first sidewalls NSW1, and the width of the gate pattern (width in the second direction Y) may be reduced as the integrated circuit device is scaled down, and there may also be a problem that the effective gate length Lg is reduced.

[0092] However, according to the example embodiment, since the common impurity region SDC is formed on one side of a pair of second sidewalls NSW2, sufficient distance in the second direction Y can be ensured between the first gate pattern N12 and the first impurity region SD1, or the width of the first gate pattern N12 in the second direction Y can be increased. Therefore, a decrease in the threshold voltage due to the DIBL phenomenon can be prevented. Thus, the transistor constituting the sense amplifier 70 according to the example embodiment can have a relatively low threshold voltage or a relatively uniform threshold voltage.

[0093] Figure 11 This is a layout diagram of the readout amplifier 70B according to an example embodiment, and Figure 12 It is along Figure 11 The cross-sectional view taken from line B1-B1' in the diagram. Figure 13 yes Figure 11 A schematic layout diagram of the first active region AC1 and the first gate pattern N12 in [the image / structure]. Figures 11 to 13 In, with Figures 1 to 10 The same reference numerals in the figures can represent the same components.

[0094] refer to Figure 11 and Figure 13 The first impurity region SD1 can be arranged adjacent to one of the first sidewalls NSW1 of the pair of first sidewalls NSW1 of the first gate pattern N12, and the common impurity region SDC can be arranged adjacent to one of the second sidewalls NSW2 of the pair of second sidewalls NSW2 of the first gate pattern N12. The first sidewall NSW1 of the pair of first sidewalls NSW1 of the first gate pattern N12 can be aligned with the sidewall of the first main active region AM1B.

[0095] The width of the first primary active region AM1B in the first direction X can be less than Figures 6 to 8 The width of the first primary active region AM1 is shown, and the width of the extended active region AEB in the first direction X can be greater than [the width of the extended active region AEB in the first direction X]. Figures 6 to 8 The width of the extended active region AE is shown.

[0096] The first channel region CHR1 can be formed in the portion of the first main active region AM1B that perpendicularly overlaps with the first gate pattern N12, and the second channel region CHR2 can be formed in the portion of the extended active region AEB that perpendicularly overlaps with the first gate pattern N12. The first channel region CHR1 can have a first width w11 in the second direction Y, and the second channel region CHR2 can have a second width w12 in the second direction Y, and the second width w12 can be smaller than the first width w11 (see...). Figure 13 For example, the first width w11 can be from about 10 nm to about 500 nm, and the second width w12 can be from about 5 nm to about 400 nm, but the embodiments are not limited thereto.

[0097] like Figure 13 As shown, for example, in a plan view, a stepped portion CHS with an L-shape or an inverse L-shape can be defined at the boundary between the first channel region CHR1 and the second channel region CHR2. The first gate pattern N12 can overlap perpendicularly with the stepped portion CHS, and therefore, the first NMOS transistor N_1 can have a relatively long effective gate length Lg. For example, the stepped portion CHS can have a first length Lg1 in the second direction Y and a second length Lg2 in the first direction X, and the effective gate length Lg of the first NMOS transistor N_1 can correspond to the sum of the first length Lg1 and the second length Lg2. Here, the second length Lg2 can indicate the width of the second channel region CHR2 that overlaps perpendicularly with the first gate pattern N12 in the first direction X, and the first length Lg1 can indicate the difference between the first width w11 of the first channel region CHR1 and the second width w12 of the second channel region CHR2. In some embodiments, the effective gate length Lg of the first NMOS transistor N_1 can be greater than the first width w11 of the first channel region CHR1.

[0098] like Figure 11 As shown, when the first NMOS transistor N_1 is turned on, a carrier movement path MD10 with an L-shape or an inverted L-shape can be formed from the first impurity region SD1 to the common impurity region SDC, and carriers can move along the carrier movement path MD10 in both the first direction X and the second direction Y. Since the extended active region AEB is formed with a relatively large width, the length of the carrier movement path MD10 can also be increased.

[0099] Figure 14 This is a layout diagram of the cell array region MCA of the integrated circuit device 100 according to an example embodiment, and Figure 15 It is along Figure 14 The cross-sectional view taken from line A2-A2' in the diagram.

[0100] refer to Figure 14 and Figure 15 The cell array region MCA can include DRAM devices of the buried gate cell array transistor (BCAT) type.

[0101] Device isolation trenches 112T can be formed in the substrate 110, and device isolation layers 112 can be formed in the device isolation trenches 112T. Multiple second active regions AC2 can be defined in the substrate 110 in the cell array region MCA by means of the device isolation layers 112.

[0102] Each of the plurality of second active regions AC2 may have a major axis in an inclined direction relative to the first direction X and the second direction Y. A plurality of word lines WL may extend parallel to each other across the plurality of first active regions AC1 in the first direction X. A plurality of bit lines BL may extend parallel to each other across the plurality of word lines WL in the second direction Y. The plurality of bit lines BL may be connected to the plurality of first active regions AC1 via direct contact DC.

[0103] Multiple buried contacts BC can be formed between two adjacent bit lines BL. The multiple buried contacts BC can be arranged in a row in the first direction X and the second direction Y. Multiple landing pads LP can be formed on the multiple buried contacts BC. The multiple buried contacts BC and the multiple landing pads LP can connect the bottom electrode of the capacitor formed on the upper part of the multiple bit lines BL to the first active region AC1. The multiple landing pads LP can each partially overlap with the multiple buried contacts BC.

[0104] In the cell array region MCA, a plurality of word line trenches extending in the first direction X are formed in the substrate 110, and a plurality of gate dielectric layers, a plurality of word lines, and a plurality of cap insulating layers can be formed in the plurality of word line trenches. The plurality of word lines can correspond to Figure 14 The multiple letter lines WL are shown.

[0105] A buffer layer 122 may be formed on the substrate 110 in the cell array region MCA. The buffer layer 122 may include a first insulating layer 122A and a second insulating layer 122B. A plurality of direct contacts DC may be formed in a plurality of direct contact holes DCH in the substrate 110. The plurality of direct contacts DC may be connected to a plurality of second active regions AC2.

[0106] Multiple bit lines BL can extend in the second direction Y on the substrate 110 and multiple direct contacts DC. Each of the multiple bit lines BL can be connected to the second active region AC2 via the direct contacts DC. Each of the multiple bit lines BL may include a lower conductive pattern 132B, an intermediate conductive pattern 134B, and an upper conductive pattern 136B sequentially stacked on the substrate 110. The lower conductive pattern 132B may include doped polysilicon. The intermediate conductive pattern 134B and the upper conductive pattern 136B may each include TiN, TiSiN, tungsten (W), tungsten silicide, or combinations thereof. In an example embodiment, the intermediate conductive pattern 134B may include TiN, TiSiN, or combinations thereof, and the upper conductive pattern 136B may include W.

[0107] Each of the multiple bit lines BL can be covered by an insulating cover structure. The insulating cover structure may include a lower cover pattern 142B, an insulating layer pattern 144, an upper cover pattern 146, and an insulating liner 148. The lower cover pattern 142B, the insulating layer pattern 144, and the upper cover pattern 146 may be sequentially stacked on the multiple bit lines BL, and the insulating liner 148 may be disposed on one sidewall of the two sidewalls of the lower cover pattern 142B, the insulating layer pattern 144, and the upper cover pattern 146 extending in the second direction Y.

[0108] The direct contact DC can be formed in the direct contact hole DCH formed in the substrate 110 and can extend to a level higher than the upper surface of the substrate 110. The lower side of the direct contact DC can be surrounded by an insulating liner 148R and a direct contact spacer 154, and the upper side of the direct contact DC can be surrounded by an insulating structure 170 described later.

[0109] Multiple conductive plugs 156 and multiple insulating barriers can be arranged in a row between two adjacent bits in the second direction Y of the multiple bit lines BL. The multiple conductive plugs 156 can extend from the recesses RS formed in the substrate 110 in the vertical direction Z. The multiple conductive plugs 156 can constitute... Figure 14 The multiple buried contact components BC are shown.

[0110] Multiple metal silicide layers 158B and multiple landing pads LP can be formed on multiple conductive plugs 156. The metal silicide layers 158B and the landing pads LP can be configured to overlap perpendicularly to the conductive plugs 156. The metal silicide layers 158B may include cobalt silicide, nickel silicide, or manganese silicide. Each of the multiple landing pads LP can be connected to the conductive plug 156 via the metal silicide layers 158B.

[0111] Multiple landing pads LP may cover at least a portion of the upper surface of the cover pattern 146 to vertically overlap a portion of multiple bit lines BL. Each of the multiple landing pads LP may include a conductive barrier layer 162B and a landing pad conductive layer 164B. When viewed in a plan view, the multiple landing pads LP may have multiple island-shaped patterns.

[0112] Multiple landing pads LP can be electrically insulated from each other by an insulating structure 170 that fills the insulating space 170S around and between them. The insulating structure 170 may include a first material layer 172 and a second material layer 174. The first material layer 172 may surround the two sidewalls of the bit line BL and the sidewalls of the landing pads LP, and the second material layer 174 may surround the landing pads LP on the first material layer 172.

[0113] Figure 16 This is a layout diagram of the cell array region MCA of the integrated circuit device 200 according to an example embodiment. Figure 17 This is a perspective view of integrated circuit device 200, and Figure 18 It shows along Figure 16 The cross-sectional view taken by lines X1-X1' and Y1-Y1' in the diagram.

[0114] refer to Figures 16 to 18 The cell array region MCA may include a vertical channel transistor (VCT) type DRAM device. A VCT may refer to a structure in which the channel length of the channel layer 230 extends from the substrate 210 in the vertical direction Z. The cell array region MCA may include a substrate 210, multiple first conductors 220, a channel layer 230, a gate electrode 240, a gate insulating layer 250, and a capacitor structure 280.

[0115] A lower insulating layer 212 can be disposed on the substrate 210, and a plurality of first conductive lines 220 can be spaced apart from each other in a first direction X and extend in a second direction Y on the lower insulating layer 212. A plurality of first insulating patterns 222 can be disposed on the lower insulating layer 212 to fill the space between the plurality of first conductive lines 220. The plurality of first insulating patterns 222 can extend in the second direction Y, and the upper surface of the plurality of first insulating patterns 222 can be at the same level as the upper surface of the plurality of first conductive lines 220. The plurality of first conductive lines 220 can be used as bit lines of an integrated circuit device 200.

[0116] In an example embodiment, the plurality of first conductive lines 220 may include doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. For example, the plurality of first conductive lines 220 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrO x RuO x Or combinations thereof, but not limited thereto. The plurality of first wires 220 may comprise a single layer or multiple layers of the materials described above. In an example embodiment, the plurality of first wires 220 may comprise a two-dimensional (2D) semiconductor material, and for example, the 2D semiconductor material may comprise graphene or carbon nanotubes or combinations thereof.

[0117] The channel layer 230 can be arranged in a matrix on the plurality of first conductors 220, spaced apart from each other in the first direction X and the second direction Y. The channel layer 230 can have a first width in the first direction X and a first height in the vertical direction Z, and the first height can be greater than the first width. For example, the first height can be approximately 2 to approximately 10 times the first width, but is not limited thereto. The bottom of the channel layer 230 can be used as a first source / drain region, the upper part of the channel layer 230 can be used as a second source / drain region, and the portion of the channel layer 230 between the first source / drain region and the second source / drain region can be used as a channel region.

[0118] In an example embodiment, the channel layer 230 may include an oxide semiconductor, and the oxide semiconductor may include, for example, In... x Ga y Zn z O、In x Ga y Si z O、In x Sn y Zn z O、In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O、Sn x O、Hf x In y Zn zO.Ga x Zn y Sn z O, Al x Zn y Sn z O、Yb x Ga y Zn z O、In x Ga y O or combinations thereof. The channel layer 230 may comprise a single layer or multiple layers of oxide semiconductor. In some example embodiments, the bandgap energy of the channel layer 230 may be greater than the bandgap energy of silicon. For example, the channel layer 230 may have a bandgap energy of approximately 1.5 eV to approximately 5.6 eV. For example, the channel layer 230 may have optimal channel performance when it has a bandgap energy of approximately 2.0 eV to approximately 4.0 eV. For example, the channel layer 230 may be polycrystalline or amorphous, but is not limited thereto. In example embodiments, multiple channel layers 230 may comprise 2D semiconductor materials, and the 2D semiconductor materials may comprise, for example, graphene or carbon nanotubes or combinations thereof.

[0119] The gate electrode 240 may extend on both sidewalls of the channel layer 230 in a first direction X. The gate electrode 240 may include a first sub-gate electrode 240P1 facing the first sidewall of the channel layer 230 and a second sub-gate electrode 240P2 facing the second sidewall opposite to the first sidewall of the channel layer 230. Since a channel layer 230 is arranged between the first sub-gate electrode 240P1 and the second sub-gate electrode 240P2, the integrated circuit device 200 may have a dual-gate transistor structure. However, this disclosure is not limited to this, and a single-gate transistor structure may be achieved by omitting the second sub-gate electrode 240P2 and forming only the first sub-gate electrode 240P1 facing the first sidewall of the channel layer 230.

[0120] The gate electrode 240 may comprise doped polysilicon, metal, conductive metal nitride, conductive metal silicide, conductive metal oxide, or combinations thereof. For example, the gate electrode 240 may comprise doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or IrO. x RuO x Or combinations thereof, but not limited to these.

[0121] The gate insulating layer 250 may surround the sidewalls of the channel layer 230 and may be disposed between the channel layer 230 and the gate electrode 240. In an example embodiment, the gate insulating layer 250 may include a silicon oxide layer, a silicon oxynitride layer, a high-k dielectric layer with a dielectric constant higher than that of the silicon oxide layer, or a combination thereof. The high-k dielectric layer may include a metal oxide or a metal oxynitride. For example, the high-k dielectric layer that can be used as the gate insulating layer 250 may include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, or a combination thereof, but is not limited thereto.

[0122] Multiple second insulating patterns 232 may extend over the multiple second insulating patterns 232 in a second direction Y, and a channel layer 230 may be disposed between two adjacent second insulating patterns 232. Furthermore, a first buried layer 234 and a second buried layer 236 may be disposed in the space between two adjacent second insulating patterns 232 and between two adjacent channel layers 230. The first buried layer 234 may be disposed at the bottom of the space between two adjacent channel layers 230, and the second buried layer 236 may be formed to fill the remaining space between two adjacent channel layers 230 on the first buried layer 234. The upper surface of the second buried layer 236 may be disposed at the same level as the upper surface of the channel layer 230, and the second buried layer 236 may cover the upper surface of the gate electrode 240. Conversely, the multiple second insulating patterns 232 may be formed as a material layer continuous with the multiple first insulating patterns 222. As another example, the second burial layer 236 may be formed as a material layer that is continuous with the first burial layer 234.

[0123] Capacitor contacts 260 can be disposed on the channel layer 230. The capacitor contacts 260 can be arranged to overlap the channel layer 230 perpendicularly, and can be arranged separately from each other in a matrix configuration in the first direction X and the second direction Y. The capacitor contacts 260 may include doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, or IrO. x RuO x Or a combination thereof, but not limited thereto. The upper insulating layer 262 may surround the sidewalls of the capacitor contacts 260 on the plurality of second insulating patterns 232 and the plurality of second buried layers 236.

[0124] An etch stop layer 270 may be disposed on the upper insulating layer 262, and a capacitor structure 280 may be disposed on the etch stop layer 270. The capacitor structure 280 may include a lower electrode 282, a capacitor dielectric layer 284, and an upper electrode 286.

[0125] The lower electrode 282 can penetrate the etch stop layer 270 and is electrically connected to the upper surface of the capacitor contact 260. The lower electrode 282 can be formed as a column extending in the vertical direction Z, but is not limited thereto. In an example embodiment, the lower electrode 282 can be arranged to overlap the capacitor contact 260 perpendicularly and can be arranged separately from each other in a matrix in the first direction X and the second direction Y. As another example, a landing pad can also be arranged between the capacitor contact 260 and the lower electrode 282, such that the lower electrode 282 is arranged in a hexagonal shape.

[0126] Figure 19 This is a layout diagram of the cell array region MCA of the integrated circuit device 200A according to an example embodiment, and Figure 20 This is a perspective view of integrated circuit device 200A.

[0127] refer to Figure 19 and Figure 20 The cell array region MCA may include a VCT type DRAM device. The cell array region MCA may include a substrate 210A, multiple first conductive lines 220A, a channel structure 230A, a contact gate electrode 240A, multiple second conductive lines 242A, and a capacitor structure 280.

[0128] Multiple active regions AC can be defined on the substrate 210A by a first device isolation layer 212A and a second device isolation layer 214A. A channel structure 230A can be arranged in each active region AC, and the channel structure 230A may include a first active pillar 230A1 and a second active pillar 230A2 extending in the vertical direction Z, respectively, and a connection unit 230L connected to the bottom of the first active pillar 230A1 and the bottom of the second active pillar 230A2. A first impurity region 230S1 may be arranged in the connection unit 230L, and a second impurity region 230S2 may be arranged in the upper part of the first active pillar 230A1 and the second active pillar 230A2. Each of the first active pillar 230A1 and the second active pillar 230A2 can constitute an independent unit memory cell.

[0129] Multiple first conductors 220A may extend in a direction intersecting each of the multiple active regions AC (e.g., in the second direction Y). One of the multiple first conductors 220A may be arranged on a connection unit 230L between a first active post 230A1 and a second active post 230A2, and this first conductor 220A may be arranged on a first impurity region 230S1. Another first conductor 220A adjacent to one of the first conductors 220A may be arranged between two channel structures 230A. One of the multiple first conductors 220A may be used as a common bit line included in two unit memory cells, which are composed of a first active post 230A1 and a second active post 230A2 arranged on both sides of the first conductor 220A.

[0130] A contact gate electrode 240A may be disposed between two adjacent channel structures 230A in the second direction Y. For example, the contact gate electrode 240A may be disposed between a first active post 230A1 included in a channel structure 230A and a second active post 230A2 of the channel structure 230A adjacent to the first active post 230A1, and the contact gate electrode 240A may be shared by the first active post 230A1 and the second active post 230A2 disposed on two sidewalls of the contact gate electrode 240A. A gate insulating layer 250A may be disposed between the contact gate electrode 240A and the first active post 230A1 and between the contact gate electrode 240A and the second active post 230A2. A plurality of second conductors 242A may extend on the upper surface of the contact gate electrode 240A in the first direction X. The plurality of second conductors 242A may be used as word lines of an integrated circuit device 200A.

[0131] The capacitor contact 260A can be arranged on the channel structure 230A. The capacitor contact 260A can be arranged on the second impurity region 230S2, and the capacitor structure 280 can be arranged on the capacitor contact 260A.

[0132] Although this disclosure has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. An integrated circuit device comprising a sense amplifier configured to sense voltage variations on bit lines, wherein, The sense amplifier includes: A substrate in which a first active region is defined. A sense amplifier unit connected to the bit line and the complementary bit line, the sense amplifier unit being configured to read out the voltage change of the bit line in response to a control signal and adjust the voltage of the sense bit line and the complementary sense bit line based on the read out voltage change, the sense amplifier unit including a first PMOS transistor and a first NMOS transistor; and A first offset cancellation unit, which connects the bit line to the complementary readout bit line in response to an offset cancellation signal, includes a first offset cancellation transistor disposed between the first NMOS transistor and the first PMOS transistor. The first offset elimination transistor shares a common impurity region with the first NMOS transistor. The first active region includes a first main active region, a second main active region, and an extended active region arranged between the first main active region and the second main active region. The first NMOS transistor is arranged in the first main active region. The first offset cancellation transistor is disposed in the second main active region, and The common impurity region is located in a portion of the second main active region.

2. The integrated circuit device according to claim 1, wherein, The first NMOS transistor includes: A first gate pattern is disposed on the first main active region, the first gate pattern including a pair of first sidewalls extending in a first direction parallel to the upper surface of the substrate and a pair of second sidewalls extending in a second direction parallel to the upper surface of the substrate. A first impurity region is disposed in a first upper portion of the substrate and adjacent to one of the pair of first sidewalls of the first gate pattern; and The common impurity region is disposed in the second upper portion of the substrate and is adjacent to one of the second sidewalls of the pair of second sidewalls of the first gate pattern.

3. The integrated circuit device according to claim 2, wherein, The first offset cancellation transistor includes: A first offset-eliminating gate pattern is disposed on the second main active region, the first offset-eliminating gate pattern including a pair of third sidewalls extending in the second direction; The common impurity region is arranged adjacent to one of the pair of third sidewalls; and The second impurity region is arranged adjacent to another third sidewall of the pair of third sidewalls of the first offset elimination gate pattern.

4. The integrated circuit device according to claim 3, wherein, The readout amplifier further includes: A first contact element is disposed on the first impurity region; A common contact element, which is arranged on the common impurity area; and The second contact is arranged on the second impurity region.

5. The integrated circuit device according to claim 4, in, The first contact is arranged adjacent to one of the pair of first sidewalls of the first gate pattern, and The common contact is arranged adjacent to one of the pair of second sidewalls of the first gate pattern.

6. The integrated circuit device according to claim 3, wherein, The first active region includes a channel region that overlaps with the first gate pattern. The channel region includes a first channel region having a first width in the second direction and a second channel region having a second width in the second direction that is less than the first width. In the plan view, the L-shaped stepped portion is defined at the boundary between the first channel area and the second channel area.

7. The integrated circuit device according to claim 6, wherein, The sum of the length of the step portion in the first direction and the length of the step portion in the second direction is greater than the first width of the first channel area.

8. The integrated circuit device according to claim 7, wherein, The first NMOS transistor has an effective gate length greater than the first width.

9. The integrated circuit device according to claim 1, wherein, The sense amplifier unit further includes a second PMOS transistor and a second NMOS transistor. The first PMOS transistor is connected between the first control signal line and the complementary readout bit line. The first gate pattern of the first PMOS transistor is connected to the readout bit line. The second PMOS transistor is connected between the first control signal line and the readout bit line. The second gate pattern of the second PMOS transistor is connected to the complementary readout bit line. The first NMOS transistor is connected between the second control signal line and the complementary readout bit line. The third gate pattern of the first NMOS transistor is connected to the bit line. The second NMOS transistor is connected between the second control signal line and the read bit line, and The fourth gate pattern of the second NMOS transistor is connected to the complementary bit line.

10. An integrated circuit device comprising a sense amplifier configured to sense voltage variations on bit lines, wherein, The sense amplifier includes: A sense amplifier unit connected to the bit line and the complementary bit line, the sense amplifier unit being configured to read out the voltage change of the bit line in response to a control signal and adjust the voltage of the sense bit line and the complementary sense bit line based on the read out voltage change, the sense amplifier unit including a first NMOS transistor; and A first offset cancellation unit connects the bit line to the complementary readout bit line in response to an offset cancellation signal. The first offset cancellation unit includes a first offset cancellation transistor disposed adjacent to the first NMOS transistor. The first NMOS transistor includes: A first gate pattern is disposed on a first active region of a substrate. The first gate pattern includes a pair of first sidewalls extending in a first direction parallel to the upper surface of the substrate and a pair of second sidewalls extending in a second direction parallel to the upper surface of the substrate. A first impurity region is disposed in a first upper portion of the substrate and adjacent to one of the pair of first sidewalls of the first gate pattern; and A common impurity region is disposed in the second upper portion of the substrate and is adjacent to one of the second sidewalls of the pair of second sidewalls of the first gate pattern. The first offset elimination transistor further includes the common impurity region. The first active region includes a first main active region, a second main active region, and an extended active region disposed between the first main active region and the second main active region, wherein the first gate pattern is disposed on the first main active region. The first offset cancellation transistor is disposed on the second main active region, and The common impurity region is located in a portion of the second main active region.

11. The integrated circuit device according to claim 10, wherein, The first offset cancellation transistor includes a first offset cancellation gate pattern disposed on the first active region and a pair of third sidewalls extending in the second direction. Wherein, the first gate pattern extends in the first direction, and The first offset elimination gate pattern extends in the second direction.

12. The integrated circuit device according to claim 11, wherein, The first offset cancellation transistor further includes: The second impurity region is arranged adjacent to another third sidewall of the pair of third sidewalls of the first offset elimination gate pattern. The common impurity region is arranged to be adjacent to one of the third sidewalls of the pair of third sidewalls of the first offset elimination gate pattern.

13. The integrated circuit device according to claim 10, wherein, The first active region includes a channel region that overlaps with the first gate pattern. The channel region includes a first channel region having a first width in the second direction and a second channel region having a second width in the second direction that is less than the first width. In the plan view, the L-shaped stepped portion is defined at the boundary between the first channel area and the second channel area.

14. The integrated circuit device of claim 10, further comprising: A first contact is disposed on a first impurity region adjacent to one of the pair of first sidewalls of the first gate pattern; as well as A common contact is disposed on the common impurity region and adjacent to one of the pair of second sidewalls of the first gate pattern.

15. An integrated circuit device comprising a sense amplifier configured to sense voltage variations on bit lines, wherein, The sense amplifier includes: A sense amplifier unit connected to the bit line and the complementary bit line, the sense amplifier unit being configured to read out the voltage change of the bit line in response to a control signal and adjust the voltage of the sense bit line and the complementary sense bit line based on the read out voltage change, the sense amplifier unit including a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; and A first offset cancellation unit, which connects the bit line to the complementary readout bit line in response to an offset cancellation signal, includes a first offset cancellation transistor disposed adjacent to the first NMOS transistor. The first PMOS transistor is connected between the first control signal line and the complementary readout bit line. The first gate pattern of the first PMOS transistor is connected to the readout bit line. The second PMOS transistor is connected between the first control signal line and the readout bit line. The second gate pattern of the second PMOS transistor is connected to the complementary readout bit line. The first NMOS transistor is connected between the second control signal line and the complementary readout bit line. The third gate pattern of the first NMOS transistor is connected to the bit line. The second NMOS transistor is connected between the second control signal line and the readout bit line. Wherein, the fourth gate pattern of the second NMOS transistor is connected to the complementary bit line, and The first NMOS transistor includes: The third gate pattern is disposed on a first active region of the substrate, and the third gate pattern includes a pair of first sidewalls extending in a first direction parallel to the upper surface of the substrate and a pair of second sidewalls extending in a second direction parallel to the upper surface of the substrate. A first impurity region is disposed in a first upper portion of the substrate and adjacent to one of the pair of first sidewalls of the third gate pattern; and A common impurity region is disposed in the second upper portion of the substrate and is adjacent to one of the second sidewalls of the pair of second sidewalls of the third gate pattern.

16. The integrated circuit device according to claim 15, wherein, The first offset cancellation transistor further includes: A first offset-eliminating gate pattern is disposed on the first active region of the substrate, the first offset-eliminating gate pattern including a pair of third sidewalls extending in the second direction; The common impurity region is arranged adjacent to one of the pair of third sidewalls of the first offset elimination gate pattern; and The second impurity region is arranged adjacent to another third sidewall of the pair of third sidewalls of the first offset elimination gate pattern.

17. The integrated circuit device according to claim 16, wherein, The readout amplifier also includes a common contact disposed on the common impurity region, and The first NMOS transistor and the first offset elimination transistor share the common impurity region and the common contact.

18. The integrated circuit device according to claim 16, wherein, The first active region includes: The first main active region overlaps perpendicularly with the first gate pattern; The second main active region overlaps perpendicularly with the first offset-eliminating gate pattern; and An extended active region is arranged between the first main active region and the second main active region. Wherein, the width of the extended active region in the second direction is smaller than the width of the second main active region in the second direction.

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