Embedded semiconductor random access memory structure and method of controlling the same

Abstract

The application discloses an embedded semiconductor random access memory structure and a control method thereof, and belongs to the technical field of semiconductor memories. The memory structure comprises a ferroelectric memory cell for storing information and a tunneling field effect transistor connected with the memory cell, and the tunneling field effect transistor is used for controlling the ferroelectric memory cell and performing write operation and read operation. A plurality of the memory structures form a semiconductor memory array, and the control method comprises write 0, write 1, read and rewrite steps. The application utilizes the unidirectional conduction characteristic and extremely low leakage current characteristic of the tunneling field effect transistor, can reduce the operating voltage and power consumption of the memory array, and can improve the memory integration density. The application is suitable for manufacturing of semiconductor memory chips, and the control method and circuit are relatively simple.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor memory, and particularly relates to an embedded random access memory structure and a control method thereof. BACKGROUND

[0002] From the development trend of information technology, ultra-low power integrated circuit applications have become the mainstream direction. Mobile computing and communication, intelligent hardware, Internet of Things, wearable devices, biomedical chips and other portable and implantable chips have accounted for a high proportion in electronic products and are growing rapidly. For these mobile devices, power consumption directly affects the user experience and reliability. However, as the feature size of integrated circuits continues to decrease in proportion according to Moore's Law, the power consumption of integrated circuits has been rising, and the static power consumption will gradually exceed the dynamic power consumption, becoming a bottleneck factor that slows down or limits the further development of semiconductor technology. Therefore, how to reduce chip power consumption has become the core problem of integrated circuit technology.

[0003] Memory is an indispensable component in electronic information processing systems. In the past, the performance of memory has been continuously improved with the continuous progress of CMOS technology. However, in recent years, on the one hand, the transistor leakage problem caused by size miniaturization is becoming more and more serious, which not only increases the power consumption of the memory, but also worsens the retention characteristics of the memory cell, and the development of the memory encounters a more obvious bottleneck; on the other hand, the rapid development of artificial intelligence and the Internet of Things and other fields has put forward higher requirements on the capacity, speed and power consumption and other performance indicators of the memory. Under such background, due to the high density, wide bandwidth and fast reading speed of embedded dynamic random access memory (eDRAM), the overall performance of the system can be improved, therefore, embedded dynamic random access memory has been concerned in recent years.

[0004] Dynamic random access memory needs refresh operation to keep the correctness of stored information. The greater the transistor leakage current in the memory cell, the easier the stored information is destroyed, the shorter the refresh operation needs, and the higher the power consumption caused by the refresh operation. To solve this problem, the independent dynamic random access memory specially designs the transistor structure in the memory cell, such as using a buried gate structure to increase the channel length and reduce the leakage current. However, the unique transistor structure design increases the process difficulty of integration with logic devices and implementation of embedded memory. Therefore, the embedded dynamic random access memory usually adopts the following two methods. One is the 1T1C memory cell structure, and the control tube T selects the IO CMOS device of the same node, thereby causing the single memory area to increase and the storage capacity to decrease. The other is to use the multi-T memory cell structure, and the gate capacitance of the CMOS is used as the storage capacitor, but the storage window is small, and the retention performance is poor.

[0005] However, the tunneling field-effect transistor (TFET) adopts a new conduction mechanism of band-to-band tunneling (BTBT), controls the tunneling width of the tunneling junction at the junction between the source and the channel through the gate electrode, so that when the device is turned on, the valence band electrons of the source tunnel to the conduction band of the channel to form a tunneling current, and when the device is turned off, only a small amount of electrons in the conduction band of the source drift to the conduction band of the drain. Therefore, the tunneling field-effect transistor breaks through the theoretical limit of the sub-threshold slope of the traditional MOSFET, greatly reduces the off-state leakage current of the device, and has extremely low static power consumption and dynamic power consumption. Therefore, using the tunneling field-effect transistor as the control tube does not need to refresh the memory cell, can improve the retention characteristics of the memory, and further reduce the power consumption. At the same time, the tunneling field-effect transistor used for logic and storage functions has the same structure and is compatible with the existing CMOS process, without increasing the process cost and the area of a single memory, it can be integrated on the same chip.

[0006] The ferroelectric capacitor has a greater polarization intensity than the dielectric capacitor of the same volume, and has a part of ferroelectric polarization. Replacing the dielectric capacitor and the MOS gate capacitor with the ferroelectric capacitor as the storage capacitor can obtain a larger storage window at the same process node, thereby further reducing the area of a single memory and increasing the integration degree. Since the ferroelectric polarization can maintain the original polarization intensity without voltage, and the change of the polarization intensity is voltage-driven, only current is generated in the process of reversing the ferroelectric polarization, therefore, using the ferroelectric capacitor as the storage cell has excellent characteristics such as low power consumption and long retention time. In addition, hafnium-based ferroelectric materials have the advantages of low operating voltage, fast flipping speed, good CMOS process compatibility, and good size scaling, and can be prepared by CMOS process back-end integration. The hafnium-based ferroelectric capacitor is integrated on the same chip as the above-mentioned tunneling field-effect transistor. SUMMARY

[0007] The present application aims to provide an embedded semiconductor random access memory structure and its read-write method, which uses a hafnium-based ferroelectric capacitor as a ferroelectric memory cell and connects it with a tunneling field effect transistor in a unique way to perform read-write operation, so as to reduce the operating voltage and power consumption, increase the integration density, etc.

[0008] To achieve the above-mentioned purpose, the present application provides an embedded semiconductor random access memory structure, which comprises a hafnium-based ferroelectric capacitor as a memory cell and a tunneling field effect transistor for operating the memory cell, wherein the hafnium-based ferroelectric capacitor is composed of a hafnium-based ferroelectric material layer, a metal upper plate and a metal lower plate, and the tunneling field effect transistor comprises a source, a drain, a low-doped channel region and a gate. The gate of the tunneling field effect transistor is connected with any one of a plurality of word lines, the source is connected with any one of a plurality of bit lines, and the two ends of the ferroelectric capacitor are connected with the drain of the tunneling field effect transistor and any one of a plurality of plate lines, respectively. The voltage applied to the metal upper plate of the hafnium-based ferroelectric capacitor is controlled by controlling the gate of the tunneling field effect transistor, so as to realize the selection of the memory cell.

[0009] The method for controlling the embedded semiconductor random access memory comprises three steps of writing 1, writing 0 and reading.

[0010] The step of writing 1 is as follows: a first voltage is applied to the plate line connected with the semiconductor memory structure; a second voltage is applied to the word line connected with the semiconductor memory structure; and a third voltage is applied to the bit line connected with the semiconductor memory structure; thus the source junction of the tunneling field effect transistor in the semiconductor memory structure is positively biased, the on-state current thereof is diffusion current, the ferroelectric polarization direction is reversed to point from the metal upper plate to the plate line, and the information in the memory structure is written as 1.

[0011] Further, the first voltage is 0V; the second voltage ranges from V D to V B ; the third voltage is V D ; and V B ranges from 0V to 6V, which are selected according to the actual circuit design.

[0012] The step of writing 0 is: applying a fourth voltage to the bit line connected to the semiconductor memory structure; applying a fifth voltage to the word line connected to the semiconductor memory structure; applying a sixth voltage to the plate line connected to the semiconductor memory structure; thereby making the source junction of the tunneling field effect transistor in the semiconductor memory structure reverse biased, the on current of which is band-to-band tunneling current, the ferroelectric polarization direction flips to point from the plate line to the metal upper plate, and the information in the memory structure is written as 0.

[0013] Further, the fourth voltage is 0V; the fifth voltage is V A ; the sixth voltage is V A ; the range of V A is 0V to 5V, which is selected according to actual circuit design.

[0014] The step of reading is: floating the bit line connected to the semiconductor memory structure; applying a seventh voltage to the word line connected to the semiconductor memory structure; applying an eighth voltage to the plate line connected to the semiconductor memory structure; thereby making the tunneling field effect transistor in the semiconductor memory structure turn on, the ferroelectric polarization flips, the bit line voltage rises, and the data stored in the memory structure is read based on the size of the bit line voltage change.

[0015] Further, the seventh voltage is V A ; the range of the eighth voltage is V A ; the range of V A is 0V to 5V, which is selected according to actual circuit design.

[0016] The memory structure proposed by the present application constitutes a semiconductor memory array. The above control method can be used to operate the memory structure in the array. Specifically, when writing the memory structure in the array, it is necessary to first write 1 to all memory structures, and then write 0 to individual memory structures. After reading all the memory structures in a row, it is necessary to rewrite all the memory structures in the row.

[0017] The step of rewriting the semiconductor memory array is: applying a ninth voltage to a certain row word line in the semiconductor memory array; applying a tenth voltage to a corresponding row plate line in the semiconductor memory array; applying an eleventh voltage to the word lines of the remaining rows; applying a twelfth voltage to the plate lines of the remaining rows; applying a thirteenth voltage to the bit lines connected to the memory structures storing information of 0 in the row; and applying a fourteenth voltage to the bit lines connected to the memory structures storing information of 1 in the row. Thus, the tunneling field effect transistor in all the memory structures in the row is turned on, the ferroelectric polarization of the memory structure originally storing information of 0 is reversed to point from the plate line to the metal upper plate, and the information in the memory structure is rewritten to 0. Then, a fifteenth voltage is applied to a corresponding row word line in the semiconductor memory array, and a sixteenth voltage is applied to a corresponding row plate line in the semiconductor memory array. The ferroelectric polarization of the memory structure originally storing information of 1 is reversed to point from the metal upper plate to the plate line, and the information in the memory structure is rewritten to 1.

[0018] Further, the ninth voltage is V A , the tenth voltage ranges from V A , the eleventh voltage is 0V, the twelfth voltage is V A , the thirteenth voltage is 0V, the fourteenth voltage is V B , the fifteenth voltage is V D , and the sixteenth voltage is 0V. V A ranges from 0V to 5V, V B ranges from 0V to 6V, and V D ranges from 0V to 2V, which are selected according to actual circuit design.

[0019] The control method of the embedded semiconductor random access memory structure of the application uses a tunneling field effect transistor to perform read and write operations on a ferroelectric memory cell. The unidirectional conduction characteristic and extremely low leakage current characteristic of the tunneling field effect transistor can reduce the power consumption and operating voltage of the memory, increase the integration density of the memory, and enhance the retention characteristic of the memory. The hafnium-based ferroelectric memory cell can increase the storage window, increase the integration density of the memory, and enhance the retention characteristic of the memory. The application is suitable for the existing CMOS process integration, and the control method and control circuit are relatively simple. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 is a sectional view of a typical ferroelectric memory cell.

[0021] Figure 2 is a sectional view of a typical tunneling field effect transistor.

[0022] Figure 3 A schematic equivalent circuit diagram of an embedded semiconductor random access memory structure according to the present invention.

[0023] Figure 4 A cross-sectional view of an embodiment of an embedded semiconductor random access memory structure according to the present invention.

[0024] Figure 5 A top view of an embodiment of an embedded semiconductor random access memory structure according to the present invention.

[0025] Figure 6 A schematic equivalent circuit diagram of an embodiment of an embedded semiconductor random access memory structure according to the present invention.

[0026] Figure 7 A schematic equivalent circuit diagram of an embodiment of a method of controlling a semiconductor memory array according to the present invention for writing a 1.

[0027] Figure 8 A schematic equivalent circuit diagram of an embodiment of a method of controlling a semiconductor memory array according to the present invention for writing a 0.

[0028] Figure 9 A schematic equivalent circuit diagram of an embodiment of a method of controlling a semiconductor memory array according to the present invention for reading.

[0029] Figure 10 A schematic equivalent circuit diagram of an embodiment of a method of controlling a semiconductor memory array according to the present invention for rewriting.

[0030] In the figure:

[0031] 1 - Metal upper plate; 2 - Ferroelectric layer;

[0032] 3 - Metal lower plate; 4 - Lightly doped semiconductor substrate;

[0033] 5 - N-type doped drain region; 6 - P-type doped source region;

[0034] 7 - Gate dielectric layer; 8 - Gate;

[0035] 9 - Tunneling field effect transistor; 10 - Ferroelectric memory cell;

[0036] 11 - STI isolation; 12 - Side wall;

[0037] 13 - Word line; 14 - Bit line;

[0038] 15 - Plate line; 16 - Via. DETAILED DESCRIPTION

[0039] An exemplary embodiment of the present application will be further described below with reference to the accompanying drawings. It is noted that the purpose of the disclosed embodiments is to help further understand the present application, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present application and the appended claims. Therefore, the present application should not be limited to the disclosed embodiments, and the scope of the present application is defined by the scope of the claims.

[0040] Figure 1 is a cross-sectional view of a typical ferroelectric memory cell, Figure 2 is a cross-sectional view of a typical tunneling field effect transistor, Figure 4 is a cross-sectional view of a memory structure provided by the present application, Figure 1 , 2 , 4 only shows a possible ferroelectric memory cell structure and tunneling field effect transistor structure provided by the present application, and different modifications can be made to the structure, such as a trench structure, a stacked structure for the ferroelectric memory cell, a vertical nanowire structure, a fin-shaped gate structure for the tunneling field effect transistor.

[0041] Figure 5 is a top view of a memory structure and its interconnection lines provided by the present application. As shown in Figure 4 and Figure 5 , the lightly doped semiconductor substrate can be P-type or N-type. The gate dielectric is SiO2, or HfO2, Hf x La y O, etc. high dielectric constant gate dielectric. The gate conductive layer is n-type doped polysilicon, or TiN, TaN, etc. metal material. A sidewall structure composed of dielectric materials such as silicon dioxide and silicon nitride is used. The P-type heavily doped region is connected to the source of the tunneling field effect transistor and the bit line; the N-type heavily doped region is connected to the drain of the tunneling field effect transistor and the memory cell; the hafnium-based ferroelectric material layer, the metal upper plate and the metal lower plate together serve as the memory cell, and the materials of the metal upper and lower plates can be TiN, TaN, etc. metal material. In the read and write operation, the voltage applied to the metal upper plate can be controlled by controlling the gate of the tunneling field effect transistor, thereby achieving the selection function of the memory cell.

[0042] Figure 6 is an equivalent circuit diagram of a memory structure control method provided by the present application. As shown in Figure 6 , the bit line BL is connected to the source of the tunneling field effect transistor, the word line WL is connected to the gate of the tunneling field effect transistor, and the plate line PL is connected to the metal lower plate of the ferroelectric memory cell. The metal upper plate of the ferroelectric memory cell is connected to the drain of the tunneling field effect transistor, and this node is named SN (Storage Node). A plurality of Figure 4The memory structure shown can constitute a semiconductor memory array, such as Figure 7 , Figure 8 , Figure 9 and Figure 10 are equivalent circuit diagrams for writing 1, writing 0, reading and rewriting to a semiconductor memory array, respectively.

[0043] Specifically, when writing information to a semiconductor memory array, a write 1 operation is first performed on all memory structures, and then a write 0 operation is performed on individual memory structures.

[0044] The step of writing 1 to a semiconductor memory array is shown in Figure 7 :

[0045] All plate lines PLn (n = 1, 2, 3) are all applied with a voltage of 0 V;

[0046] The word line WLn (n = 1, 2, 3) is applied with a voltage of 1 V, and the remaining word lines WLn (n = 2, 3) are applied with a voltage of 0 V;

[0047] All bit lines BLn (n = 1, 2, 3, 4) are all applied with a voltage of 3.5 V;

[0048] When V WL1 = 1 V and V BLn(n＝1,2,3,4) = 3.5 V, the source junction of the tunneling field effect transistor is positively biased, and there is a diffusion current passing through, transmitting the bit line voltage to the upper plate of the ferroelectric storage unit. When PL1 is 0 V, the voltage across the ferroelectric storage unit is greater than its coercive voltage, and the ferroelectric polarization flips to point from the upper plate to the plate line, and the storage information of the corresponding memory structure changes to 1.

[0049] The step of writing 0 to a semiconductor memory array is shown in Figure 8 :

[0050] The bit line voltage of the memory structure corresponding to the individual write 0 is lowered to 0 V, such as BL1 and BL4, and the voltage of the remaining bit lines is maintained at 3.5 V, such as BL2 and BL3;

[0051] The word line voltage of the selected row is raised to 3 V, i.e. the voltage of WL1 is raised to 3 V, and the voltage of the remaining word lines WLn (n = 2, 3) is lowered to 0 V.

[0052] The plate line PL1 is applied with a voltage of 3 V, and the remaining plate lines, such as PLn (n = 2, 3), are applied with a voltage of 0 V;

[0053] For the memory structure that needs to write 0, the source junction of the tunneling field effect transistor is reversely biased, the ferroelectric polarization is reversed to point to the metal upper plate from the plate line, and the stored information becomes 0. For the memory structure that the information remains 1, the voltage direction between the ferroelectric storage unit is the same as when writing 1, and the ferroelectric polarization does not reverse, and the stored information remains 1. After the write 0 operation is completed, the plate line PL1 voltage, the bit line BLn (n=2, 3) voltage, and the word line WL1 voltage are sequentially lowered to 0V, which can ensure that the information in each memory structure remains unchanged. After that, each memory structure enters the holding state.

[0054] The reading step of the semiconductor memory array is as shown in Figure 9

[0055] All bit lines BLn (n=1, 2, 3, 4) are set to a floating state;

[0056] A voltage of 3V is applied to the word line WL1, and a voltage of 0V is applied to the remaining word lines WLn (n=2, 3);

[0057] A voltage of 3V is applied to the plate line PL1, and a voltage of 0V is applied to the remaining plate lines PLn (n=2, 3);

[0058] As for the write 0 operation, at this time, the voltage applied to each ferroelectric storage unit in the WL1 row exceeds the coercive voltage thereof, the ferroelectric polarization is reversed to point to the upper plate from the plate line, the charge amount in the ferroelectric storage unit changes, and the changed charge amount is redistributed between the ferroelectric capacitor and the bit line capacitor, resulting in an increase in the bit line voltage. For the memory structure that stores 1, the ferroelectric polarization change amount will be greater than that of the memory structure that stores 0, and the stable value of the bit line voltage will also be higher than that of the bit line connected to the memory structure that stores 0. By reading the bit line voltage value in the stable state, the information stored in the memory structure can be read.

[0059] Since the reading operation of the semiconductor memory array destroys the stored information in the memory structure, the information therein needs to be re-written. The rewriting step of the semiconductor memory array is as shown in Figure 10

[0060] The voltage of each word line remains consistent with that in the reading operation, that is, a voltage of 3V is applied to the word line WL1, and a voltage of 0V is applied to the remaining word lines WLn (n=2, 3);

[0061] The plate line PL1 voltage remains consistent with that in the reading operation, that is, a voltage of 3V is applied to the plate line PL1, and a voltage of 2.5V is applied to the remaining plate lines PLn (n=2, 3);

[0062] ​​The voltage of each bit line is pulled up to 3.5V or pulled down to 0V by a sense amplifier in the peripheral circuit of the memory array according to the stored information in the connected memory structure. Specifically, if the stored information in the memory structure is 1, the voltage of the corresponding bit line is pulled up to 3.5V. If the stored information in the memory structure is 0, the voltage of the corresponding bit line is pulled down to 0V.

[0063] For the memory cells connected by BL1 and BL4, the voltage of the ferroelectric memory cell is higher than the coercive voltage due to the voltage of 3V on the plate line PL1, and the ferroelectric polarization is reversed to point to the upper plate from the plate line, and the stored information is rewritten as 0. After the operation of rewriting 0 is completed, the voltage on the plate line PL1 is lowered to 0V, and the voltage on the word line WL1 is lowered to 1V, then for the ferroelectric memory cell connected by BL2 and BL3, the ferroelectric polarization is reversed to point to the plate line from the upper plate, and the stored information is rewritten as 1. At this time, the ferroelectric polarization direction of the memory structure connected by BL1 and BL4 remains unchanged, and the stored information remains 0. After the operation of rewriting 1 is completed, the voltage of the bit line BLn (n=2, 3) is lowered to 0V at the same time as the voltage of each plate line PLn (n=1, 2, 3), and then the voltage on the word line WL1 is lowered to 0V, the information in each memory structure can be kept unchanged, and each memory structure enters the holding state.

[0064] Although the present application has been disclosed with reference to the preferred embodiments, it is not intended to limit the present application. Any person skilled in the art can make many possible changes and modifications to the technical solutions of the present application, or modify equivalent embodiments with equivalent changes, without departing from the scope of the technical solutions of the present application, by using the methods and technical contents disclosed above. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, without departing from the content of the technical solutions of the present application, shall still fall within the scope of protection of the technical solutions of the present application.

Claims

1. A control method for an embedded semiconductor random access memory structure, characterized in that, An embedded semiconductor random access memory (RAM) structure includes a hafnium-based ferroelectric capacitor as a memory cell and a tunneling field-effect transistor (TF-FET) for operating the memory cell. The hafnium-based ferroelectric capacitor consists of a hafnium-based ferroelectric material layer, a metal upper plate, and a metal lower plate. The TF-FET includes a source, a drain, a lightly doped channel region, and a gate. The gate of the TF-FET is connected to any one of multiple word lines, and its source is connected to any one of multiple bit lines. The two ends of the ferroelectric capacitor are connected to the drain of the TF-FET and any one of the multiple plate lines, respectively. By controlling the gate of the TF-FET, the voltage applied to the metal upper plate of the hafnium-based ferroelectric capacitor is controlled, thereby achieving the selection of the memory cell. Specifically, this includes three steps: writing 1, writing 0, and reading. The steps for writing 1 are as follows: apply a first voltage to the board line connected to the memory structure; apply a second voltage to the word line connected to the memory structure; apply a third voltage to the bit line connected to the memory structure; thereby forward biasing the source junction of the tunneling field-effect transistor in the memory structure, making its conduction current a diffusion current, and reversing the ferroelectric polarization direction from the upper metal plate to the board line, and the information in the memory structure is written as 1. The steps for writing 0 are as follows: apply a fourth voltage to the bit line connected to the memory structure; apply a fifth voltage to the word line connected to the memory structure; apply a sixth voltage to the plate line connected to the memory structure; thereby reverse biasing the source junction of the tunneling field-effect transistor in the memory structure, making its conduction current a band tunneling current, and reversing the ferroelectric polarization direction from the plate line to the upper metal plate, thus writing the information in the memory structure as 0; The reading steps are as follows: floating the bit lines connected to the memory structure; applying a seventh voltage to the word lines connected to the memory structure; applying an eighth voltage to the board lines connected to the memory structure; thereby turning on the tunneling field-effect transistors in the memory structure, causing the ferroelectric polarization to flip, raising the bit line voltage, and reading the data stored in the memory structure based on the magnitude of the change in the bit line voltage.

2. The control method as described in claim 1, characterized in that, Multiple embedded semiconductor random access memory structures form a semiconductor memory array. When performing a write operation on a memory structure in the semiconductor memory array, it is necessary to first write 1 to all memory structures, then write 0 to individual memory structures, and then read all memory structures in a certain row before rewriting all memory structures in that row.

3. The control method as described in claim 2, characterized in that, The rewrite operation consists of the following steps: applying a ninth voltage to a word line in a row of the semiconductor memory array; applying a tenth voltage to the corresponding board line in the semiconductor memory array; and applying an eleventh voltage to the word lines of the remaining rows. Apply the twelfth voltage to the board lines of the remaining rows; apply the thirteenth voltage to the bit lines connected to the memory structures in this row that store information of 0; A fourteenth voltage is applied to the bit line connected to the memory structure in this row that stores information 1; this turns on the tunneling field-effect transistors in all memory structures in this row. The ferroelectric polarization of the memory structure that originally stored information 0 is flipped so that the plate line points to the upper metal plate, and the information in the memory structure is rewritten to 0. Then, a fifteenth voltage is applied to the corresponding row word line in the semiconductor memory array, and a sixteenth voltage is applied to the corresponding row plate line in the semiconductor memory array. The ferroelectric polarization of the memory structure that originally stored information 1 is flipped so that the upper metal plate points to the plate line, and the information in the memory structure is rewritten to 1.

4. The control method as described in claim 1, characterized in that, The first voltage is 0V; the range of the second voltage is V. D The third voltage is V B V D The range is from 0V to 2V, V B The range is from 0V to 6V.

5. The control method as described in claim 1, characterized in that, The fourth voltage is 0V; the fifth voltage is V. A The sixth voltage is V. A V A The range is from 0V to 5V.

6. The control method as described in claim 1, characterized in that, The seventh voltage is V A The range of the eighth voltage is V. A V A The range is from 0V to 5V.

7. The control method as described in claim 3, characterized in that, The ninth voltage is V A The range of the tenth voltage is V. A The eleventh voltage is 0V; the twelfth voltage is V. A The thirteenth voltage is 0V; the fourteenth voltage is V. B The fifteenth voltage is V. D The sixteenth voltage is 0V, V A The range is 0V to 5V, V B The range is from 0V to 6V, V D The range is from 0V to 2V.

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