An embedded semiconductor random access memory structure and a control method thereof

Abstract

The application discloses an embedded semiconductor random access memory structure and a control method thereof, and belongs to the technical field of semiconductor memories. The memory structure comprises a ferroelectric memory cell for storing information and a tunneling field effect transistor connected with the memory cell, and the tunneling field effect transistor is used for controlling the ferroelectric memory cell and performing write operation and read operation. A plurality of the memory structures form a semiconductor memory array, and the control method comprises write 0, write 1, read and rewrite steps. The application utilizes the unidirectional conduction characteristic and extremely low leakage current characteristic of the tunneling field effect transistor, can reduce the operating voltage and power consumption of the memory array, and can improve the memory integration density. The application is suitable for manufacturing of semiconductor memory chips, and the control method and circuit are relatively simple.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor memory technology, specifically relating to an embedded random access memory structure and its control method. Background Technology

[0002] From the perspective of information technology development trends, ultra-low power integrated circuit applications have become the mainstream. Portable and implantable chips, such as those used in mobile computing and communication, smart hardware, the Internet of Things, wearable devices, and biomedical chips, already account for a significant and rapidly growing proportion of electronic products. For these mobile devices, power consumption directly impacts user experience and reliability. However, as the feature size of integrated circuits continues to decrease proportionally according to Moore's Law, the power consumption of integrated circuits has been rising. Static power consumption will gradually exceed dynamic power consumption, becoming a bottleneck factor that slows down or limits the further development of semiconductor technology. Therefore, how to reduce chip power consumption has become a core issue in integrated circuit technology.

[0003] Memory is an indispensable component of electronic information processing systems. In the past, thanks to continuous advancements in CMOS technology, memory performance has been constantly improved. However, in recent years, on the one hand, the leakage current problem of transistors caused by miniaturization has become increasingly serious, increasing memory power consumption and deteriorating the retention characteristics of memory cells, thus encountering a significant bottleneck in memory development; on the other hand, the rapid development of fields such as artificial intelligence and the Internet of Things has placed higher demands on the capacity, speed, and power consumption of memory. Against this backdrop, embedded dynamic random access memory (eDRAM) has attracted much attention in recent years due to its high density, wide bandwidth, and fast read speed, which can improve the overall performance of the system.

[0004] Dynamic Random Access Memory (DRAM) requires refresh operations to maintain the correctness of stored information. The greater the leakage current of the transistors in the memory cell, the more easily the stored information is corrupted; the shorter the refresh cycle, the higher the power consumption of the refresh operation. To address this issue, independent DRAMs employ special designs for the transistor structure in their memory cells, such as using buried gate structures to increase channel length and reduce leakage current. However, this unique transistor structure design increases the difficulty of integrating with logic devices and implementing embedded memory. Therefore, embedded DRAMs typically employ two methods: one is a 1T1C memory cell structure, where the control transistor T uses an I / O CMOS device at the same node, resulting in increased area and decreased storage capacity per memory cell; the other is a multi-T memory cell structure, using CMOS gate capacitors as storage capacitors, but this results in a smaller storage window and poorer retention performance.

[0005] However, tunneling field-effect transistors (TFETs) employ a novel band-to-band tunneling (BTBT) conduction mechanism. By controlling the tunneling width of the tunnel junction at the source-channel interface through the gate electrode, when the device is turned on, valence band electrons from the source tunnel to the conduction band of the channel, forming a tunneling current. When the device is turned off, only a small number of electrons from the source conduction band drift to the drain conduction band. Therefore, while breaking the theoretical limit of the subthreshold slope of traditional MOSFETs, TFETs significantly reduce the off-state leakage current, exhibiting extremely low static and dynamic power consumption. Thus, using TFETs as control transistors eliminates the need for memory cell refresh operations, improving memory retention characteristics and further reducing power consumption. Furthermore, TFETs used for logic and memory functions have identical structures and are compatible with existing CMOS processes, allowing integration onto the same chip without increasing process costs or the area of ​​individual memory cells.

[0006] Ferroelectric capacitors have a greater polarization intensity than dielectric capacitors of the same volume, with an additional ferroelectric polarization portion. Replacing dielectric capacitors and MOS gate capacitors with ferroelectric capacitors as storage capacitors can achieve a larger storage window at the same process node, thereby further reducing the area of ​​a single memory and increasing integration density. Since ferroelectric polarization can maintain its original polarization intensity without voltage application, and changing this polarization intensity is voltage-driven, generating current only during ferroelectric polarization switching, ferroelectric capacitors as storage cells have excellent characteristics such as low power consumption and long hold time. In addition, hafnium-based ferroelectric materials have advantages such as low operating voltage, fast switching speed, good CMOS process compatibility, and good size miniaturization. Hafnium-based ferroelectric capacitors can be fabricated using CMOS back-end integration methods and integrated with the aforementioned tunneling field-effect transistors on the same chip. Summary of the Invention

[0007] The purpose of this invention is to propose an embedded semiconductor random access memory structure and its read / write method. This memory structure uses a special capacitor as the storage structure and a special transistor as the control tube for read / write operations, thereby achieving the goals of reducing operating voltage and increasing integration density.

[0008] To achieve the aforementioned objectives, this invention proposes an embedded semiconductor random access memory (RAM) structure. The RAM structure includes a hafnium-based ferroelectric capacitor as a memory cell and a tunneling field-effect transistor (TFET) structure for operating the memory cell. The hafnium-based ferroelectric capacitor comprises a hafnium-based ferroelectric material layer, a metal upper plate, and a metal lower plate. The TFET includes a source, a drain, a lightly doped channel region, and a gate. The gate of the TFET is connected to any one of multiple word lines, and its source is connected to any one of multiple plate lines. The two ends of the ferroelectric capacitor are connected to the drain of the TFET and any one of multiple bit lines, respectively. By controlling the gate of the TFET, the voltage applied to the metal upper plate of the hafnium-based ferroelectric capacitor is controlled, thereby achieving the selection of the memory cell.

[0009] The method for controlling this memory structure includes three steps: writing 0, writing 1, and reading.

[0010] The steps for writing 0 to the memory structure are as follows: apply a first voltage to the bit line connected to the semiconductor memory structure; apply a second voltage to the word line connected to the semiconductor memory structure; apply a third voltage to the plate line connected to the semiconductor memory structure; thereby forward biasing the source junction of the tunneling field-effect transistor in the semiconductor memory structure, making its conduction current a diffusion current, and reversing the ferroelectric polarization direction from the upper metal plate to the bit line, thus writing the information in the memory structure as 0.

[0011] Furthermore, the first voltage is 0V; the second voltage is V. D The third voltage is V B V D The range is from 0V to 2V, V B The range is from 0V to 6V, and the appropriate voltage should be selected based on the actual circuit design.

[0012] The steps for writing 1 to the memory structure are as follows: apply a fourth voltage to the plate line connected to the semiconductor memory structure; apply a fifth voltage to the word line connected to the semiconductor memory structure; apply a sixth voltage to the bit line connected to the semiconductor memory structure; thereby reversing the source junction of the tunneling field-effect transistor in the semiconductor memory structure, making its conduction current a band tunneling current, and reversing the ferroelectric polarization direction from the bit line to the upper metal plate, thus writing 1 to the information in the memory structure.

[0013] Furthermore, the fourth voltage is 0V; the fifth voltage is V. A The sixth voltage is V. A V A The range is from 0V to 5V, and the appropriate voltage should be selected based on the actual circuit design.

[0014] The steps for reading the memory structure are as follows: floating the bit lines connected to the semiconductor memory structure; applying a seventh voltage to the word lines connected to the semiconductor memory structure; applying an eighth voltage to the board lines connected to the semiconductor memory structure; thereby turning on the tunneling field-effect transistors in the semiconductor memory structure, causing the ferroelectric polarization to flip, raising the bit line voltage, and reading the data stored in the memory structure based on the magnitude of the change in the bit line voltage.

[0015] Furthermore, the seventh voltage is V D The range of the eighth voltage is V. B V D The range is from 0V to 2V, V B The range is from 0V to 6V, and the appropriate voltage should be selected based on the actual circuit design.

[0016] The memory structures proposed in this invention form a semiconductor memory array. The aforementioned control method can be used to operate on the memory structures in the array. Specifically, when performing a write operation on a memory structure in the array, it is necessary to first write 0 to all memory structures in the selected row, and then write 1 to individual memory structures. After performing a read operation on all memory structures in a certain row, it is necessary to rewrite all memory structures in that row.

[0017] The steps for rewriting the semiconductor memory structure are as follows: A ninth voltage is applied to a row of word lines in the semiconductor memory array; a tenth voltage is applied to the corresponding row of board lines in the semiconductor memory array; an eleventh voltage is applied to the word lines and board lines of the remaining rows; a twelfth voltage is applied to the bit lines connected to memory structures in this row that store 0 information; and a thirteenth voltage is applied to the bit lines connected to memory structures in this row that store 1 information. This turns on the tunneling field-effect transistors in all semiconductor memory structures in this row. The ferroelectric polarization of the memory structures that originally stored 0 information flips so that the upper metal plate points to the bit line, and the information in these memory structures is rewritten to 0. Then, a fourteenth voltage is applied to the corresponding row of word lines in the semiconductor memory array, and a fifteenth voltage is applied to the corresponding row of board lines in the semiconductor memory array. The ferroelectric polarization of the memory structures that originally stored 1 information flips so that the bit lines point to the upper metal plate, and the information in these memory structures is rewritten to 1.

[0018] Furthermore, the ninth voltage is V D The tenth voltage is V. B The eleventh voltage is 0V; the twelfth voltage is 0V; the thirteenth voltage is V. A The fourteenth voltage is V. A The fifteenth voltage is 0V. A The range is 0V to 5V, V B The range is from 0V to 6V, V D The range is from 0V to 2V, and the appropriate value should be selected based on the actual circuit design.

[0019] This invention discloses an embedded random access memory structure and its control method, employing tunneling field-effect transistors (TEPTJs) to perform read and write operations on ferroelectric memory cells. The unidirectional conduction and extremely low leakage current characteristics of TPTJs can reduce memory power consumption and operating voltage, increase memory integration density, and enhance memory retention characteristics. Hafnium-based ferroelectric memory cells can increase the memory window, further enhance memory integration density, and improve memory retention characteristics. The semiconductor memory structure and control method described in this invention achieve lower power consumption, lower operating voltage, and higher integration density, while also being highly suitable for existing CMOS process integration. Furthermore, its control method and control circuit are relatively simple. Attached Figure Description

[0020] Figure 1 This is a cross-sectional view of a typical ferroelectric memory cell.

[0021] Figure 2 This is a cross-sectional view of a typical tunneling field-effect transistor.

[0022] Figure 3This is a schematic equivalent circuit diagram of the embedded semiconductor random access memory structure of the present invention.

[0023] Figure 4 This is a cross-sectional view of an embodiment of the embedded semiconductor random access memory structure of the present invention.

[0024] Figure 5 This is a top view of an embodiment of the embedded semiconductor random access memory structure of the present invention.

[0025] Figure 6 This is an equivalent circuit diagram of an embodiment of the embedded semiconductor random access memory structure of the present invention.

[0026] Figure 7 This is an equivalent circuit diagram for writing 0 to an embodiment of the semiconductor memory structure array control method provided by the present invention.

[0027] Figure 8 The equivalent circuit diagram for writing 1 in the embodiment of the semiconductor memory array control method provided by the present invention.

[0028] Figure 9 This is an equivalent circuit diagram for reading from an embodiment of the semiconductor memory array control method provided by the present invention.

[0029] Figure 10 The equivalent circuit diagram for rewriting the embodiment of the semiconductor memory array control method provided by the present invention.

[0030] In the picture:

[0031] 1—Metallic upper electrode plate; 2—Ferroelectric layer;

[0032] 3—Metal lower electrode; 4—Lightly doped semiconductor substrate;

[0033] 5 – N-type doped drain region; 6 – P-type doped source region;

[0034] 7—Gate dielectric layer; 8—Gate;

[0035] 9—Tunneling field-effect transistor; 10—Ferroelectric memory cell;

[0036] 11—STI isolation; 12—Side wall;

[0037] 13 – Word line; 14 – Position line;

[0038] 15 – Plate line; 16 – Through hole. Detailed Implementation

[0039] An exemplary embodiment of the present invention will now be further described with reference to the accompanying drawings. It should be noted that the purpose of disclosing the embodiments is to aid in further understanding the present invention; however, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the claims.

[0040] Figure 1 This is a cross-sectional view of a typical ferroelectric memory cell. Figure 2 This is a cross-sectional view of a typical tunneling field-effect transistor. Figure 4 This is a cross-sectional view of a memory structure provided by the present invention. Figure 1 , 2 The structures shown in 4 are only the ferroelectric memory cell structure and the tunneling field-effect transistor structure provided by the present invention. Different transformations can be made to their structures, such as using trench structure or stacked structure for ferroelectric memory cells, and using vertical nanowire structure or fin gate structure for tunneling field-effect transistors.

[0041] Figure 5 This is a top view of a semiconductor memory array and its interconnects provided by the present invention. Figure 4 and Figure 5 The lightly doped semiconductor substrate can be P-type or N-type. The gate dielectric is SiO2, or HfO2, Hf x La y The gate dielectric is made of high dielectric constant materials such as O. The gate conductive layer is made of n-type doped polycrystalline silicon, or metallic materials such as TiN or TaN. The sidewall structure is made of dielectric materials such as silicon dioxide and silicon nitride. The heavily doped P-type region serves as the source of the tunneling field-effect transistor and is connected to the plate line; the heavily doped N-type region serves as the drain of the tunneling field-effect transistor and is connected to the memory cell; the hafnium-based ferroelectric material, along with the upper and lower metal plates, serves as the memory cell. The metal plates can be made of metallic materials such as TiN or TaN. During read and write operations, the voltage applied to the upper metal plate can be controlled by controlling the gate of the tunneling field-effect transistor, thus achieving the selection of the memory cell.

[0042] Figure 6 An equivalent circuit diagram of a memory structure control method provided by the present invention. (See diagram below.) Figure 6 As shown, the bit line BL is connected to the lower plate of the ferroelectric memory cell, the word line WL is connected to the gate of the tunneling field-effect transistor, and the plate line PL is connected to the source of the tunneling field-effect transistor. The metal upper plate of the ferroelectric memory cell is connected to the drain of the tunneling field-effect transistor. This node is named SN (Storage Node). Multiple such... Figure 4The memory structure shown can be used to construct a semiconductor memory array, such as Figure 7 , Figure 8 , Figure 9 and Figure 10 The equivalent circuit diagrams are shown for writing 0, writing 1, reading, and rewriting a semiconductor memory array, respectively.

[0043] Specifically, when writing information to a semiconductor memory array, it is necessary to first write 0 to all memory structures in the selected row, and then write 1 to individual memory structures.

[0044] The steps for writing 0 to a semiconductor memory array are as follows: Figure 7 As shown:

[0045] Apply a voltage of 0V to all bit lines BLn (n = 1, 2, 3, 4);

[0046] Apply a voltage of 1V to word line WLn (n=1,2) and a voltage of 0V to the remaining word line WL3;

[0047] Apply a voltage of 3.5V to the board line PLn (n=1,2), and apply a voltage of 0V to the remaining board line PL3;

[0048] When the word line voltage is 1V and the plate line voltage is 3.5V, the source junction of the tunneling field-effect transistor is forward biased, and a diffusion current flows through it, transferring the plate line voltage to the upper plate of the ferroelectric memory cell. When the bit line voltage is 0V, the voltage across the ferroelectric memory cell is greater than its coercive voltage, and the ferroelectric polarization flips so that it points from the upper plate to the bit line, and the stored information in the corresponding memory structure becomes 0.

[0049] The steps for writing 1 to a semiconductor memory array are as follows: Figure 8 As shown:

[0050] Reduce the voltage on the board line PLn (n=1,2) to 0V;

[0051] Increase the voltage on word line WL1 to 3V, and decrease the voltage on the remaining word lines WLn (n=2,3) to 0V;

[0052] Increase the bit line voltage to 3V for individual memory structures that need to be written with 1, such as BL2 and BL3, while keeping the voltage of the remaining bit lines at 0V, such as BL1 and BL4.

[0053] For memory structures that require writing a 1, the source junction of the tunneling field-effect transistor is reverse-biased, and the ferroelectric polarization flips so that the bit line points to the upper plate, storing the information as a 1. For memory structures where the information is kept as 0, the voltage across the ferroelectric storage cell becomes 0V, preventing the ferroelectric polarization from flipping, and the stored information remains 0. After completing the write operation, the voltage of the bit line BLn (n=2,3) and the word line WL1 are sequentially reduced to 0V to ensure that the information in each memory structure remains unchanged after the write operation. Afterward, each memory structure enters a hold state.

[0054] The steps for reading from a semiconductor memory array are as follows: Figure 9 As shown:

[0055] Set all bit lines BLn (n = 1, 2, 3, 4) to floating state;

[0056] Apply a voltage of 1V to word line WL1 and a voltage of 0V to the remaining word lines WLn (n=2,3);

[0057] Apply a voltage of 3.5V to board line PL1 and a voltage of 0V to the remaining board lines PLn (n=2,3);

[0058] Similar to the write-0 operation, the voltage applied to each ferroelectric memory cell in row WL1 exceeds its coercive voltage. Its ferroelectric polarization flips, pointing from the upper plate to the bit line. The charge in the ferroelectric memory cell changes, and this changed charge is redistributed between the ferroelectric capacitor and the bit line capacitor, causing the bit line voltage to rise. In a memory structure storing 1, the change in ferroelectric polarization is greater than in a memory structure storing 0, and the stable value of its bit line voltage is also higher than that of the bit line connected to the memory structure storing 0. By reading the stable bit line voltage value, the information stored in the memory structure can be read.

[0059] Because reading from a semiconductor memory array destroys the information stored in the memory structure, it is necessary to rewrite that information. The steps for rewriting a semiconductor memory array are as follows: Figure 10 As shown:

[0060] The voltage of each word line remains consistent with that during the read operation, that is, a voltage of 1V is applied to word line WL1, and a voltage of 0V is applied to the other word lines WLn (n=2,3);

[0061] The voltage of board line PL1 remains consistent with that during the reading operation, i.e., a voltage of 3.5V is applied to board line PL1, and a voltage of 0V is applied to the other board lines PLn (n=2,3);

[0062] Each bit line voltage is either pulled up to 3V or pulled down to 0V by a sensitive amplifier in the peripheral circuit of the memory array, depending on the information stored in the connected memory structure. Specifically, if the information stored in the memory structure is 1, the corresponding bit line voltage will be pulled up to 3V. If the information stored in the memory structure is 0, the corresponding bit line voltage will be pulled down to 0V.

[0063] For memory cells with a bit line voltage of 0V, such as those connected to BL1 and BL4, the voltage across the ferroelectric memory cell is higher than the coercive voltage due to the 3.5V voltage on the plate line PL1. This causes the ferroelectric polarization to flip back from the upper plate to the bit line, and the stored information is rewritten to 0. After rewriting to 0, the voltage on the word line WL1 is increased to 3V, and the voltage on the plate line PL1 is decreased to 0V. For ferroelectric memory cells with a bit line voltage of 3V, such as those connected to BL2 and BL3, the ferroelectric polarization will flip back from the bit line to the upper metal plate, and the stored information will be rewritten to 1. At this point, the ferroelectric polarization direction remains unchanged in the memory structures connected to BL1 and BL4, and the stored information remains 0. After rewriting to 1, the voltages of the bit lines BLn (n=2,3) and the word line WL1 need to be successively reduced to 0V to maintain the information in each memory structure, and each memory structure enters a hold state.

[0064] While the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the invention. Any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the scope of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A control method for an embedded semiconductor random access memory structure, characterized in that, An embedded semiconductor random access memory (RAM) structure includes a hafnium-based ferroelectric capacitor as a memory cell and a tunneling field-effect transistor (TF-FET) for operating the memory cell. The hafnium-based ferroelectric capacitor consists of a hafnium-based ferroelectric material layer, a metal upper plate, and a metal lower plate. The TF-FET includes a source, a drain, a lightly doped channel region, and a gate. The gate of the TF-FET is connected to any one of multiple word lines, and its source is connected to any one of multiple plate lines. The two ends of the ferroelectric capacitor are connected to the drain of the TF-FET and any one of multiple bit lines, respectively. By controlling the gate of the TF-FET, the voltage applied to the metal upper plate of the hafnium-based ferroelectric capacitor is controlled, thereby achieving the selection of the memory cell. Specifically, this includes three steps: writing 1, writing 0, and reading. The steps for writing 0 are as follows: apply a first voltage to the bit line connected to the memory structure; apply a second voltage to the word line connected to the memory structure; apply a third voltage to the plate line connected to the memory structure; thereby forward biasing the source junction of the tunneling field-effect transistor in the memory structure, making its conduction current a diffusion current, and reversing the ferroelectric polarization direction from the upper metal plate to the bit line, and the information in the memory structure is written as 0. The steps for writing 1 are as follows: apply a fourth voltage to the plate line connected to the memory structure; apply a fifth voltage to the word line connected to the memory structure; apply a sixth voltage to the bit line connected to the memory structure; thereby reversing the source junction of the tunneling field-effect transistor in the memory structure, making its conduction current a band tunneling current, and reversing the ferroelectric polarization direction from the bit line to the upper metal plate, and the information in the memory structure is written as 1; The reading steps are as follows: floating the bit lines connected to the memory structure; applying a seventh voltage to the word lines connected to the memory structure; applying an eighth voltage to the board lines connected to the memory structure; thereby turning on the tunneling field-effect transistors in the memory structure, causing the ferroelectric polarization to flip, raising the bit line voltage, and reading the data stored in the memory structure based on the magnitude of the change in the bit line voltage.

2. The control method as described in claim 1, characterized in that, Multiple embedded semiconductor random access memory structures form a semiconductor memory array. When performing a write operation on a memory structure in the semiconductor memory array, first write 0 to all memory structures in the selected row, and then write 1 to individual memory structures. After performing a read operation on all memory structures in a certain row, it is necessary to rewrite all memory structures in that row.

3. The control method as described in claim 2, characterized in that, The rewrite operation involves the following steps: applying a ninth voltage to a word line in a row of the semiconductor memory array; applying a tenth voltage to the corresponding board line in the semiconductor memory array; applying an eleventh voltage to the word lines and board lines of the remaining rows; applying a twelfth voltage to the bit lines connected to memory structures in this row that store 0 information; applying a thirteenth voltage to the bit lines connected to memory structures in this row that store 1 information; thereby turning on the tunneling field-effect transistors in all memory structures in this row, causing the ferroelectric polarization of the memory structures that originally stored 0 information to flip so that the upper metal plate points to the bit line, and the information in the semiconductor memory is rewritten to 0; applying a fourteenth voltage to the corresponding word line in the semiconductor memory array; applying a fifteenth voltage to the corresponding board line in the semiconductor memory array; causing the ferroelectric polarization of the memory structures that originally stored 1 information to flip so that the bit line points to the upper metal plate, and the information in the semiconductor memory is rewritten to 1.

4. The control method as described in claim 1, characterized in that, The first voltage is 0V; the second voltage is V. D The third voltage is V B V D The range is from 0V to 2V, V B The range is from 0V to 6V.

5. The control method as described in claim 1, characterized in that, The fourth voltage is 0V; the fifth voltage is V. A The sixth voltage is V. A V A The range is from 0V to 5V.

6. The control method as described in claim 1, characterized in that, The seventh voltage is V D The range of the eighth voltage is V. B V D The range is from 0V to 2V, V B The range is from 0V to 6V.

7. The control method as described in claim 3, characterized in that, The ninth voltage is V D The tenth voltage is V. B The eleventh voltage is 0V; the twelfth voltage is 0V; the thirteenth voltage is V. A The fourteenth voltage is V. A The fifteenth voltage is 0V; V A The range is 0V to 5V, V B The range is from 0V to 6V, V D The range is from 0V to 2V.

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