Storage devices and their programming methods

Abstract

A programming method for a storage device includes: simultaneously initiating programming of a first plane and a second plane; and when the first plane has been successfully programmed but the second plane has not yet been successfully programmed, bypassing the first plane and continuing programming of the second plane.

Description

[0001] This application is a divisional application of the patent filed on April 23, 2020, with application number 202080000923.0, entitled "Storage Device and Programming Method Thereof". Technical Field

[0002] This invention relates to storage devices and programming methods thereof, and more specifically, to storage devices and programming methods thereof for eliminating programming interference. Background Technology

[0003] Recently, the semiconductor memory field has received increasing attention. Semiconductor memories can be volatile or non-volatile. Non-volatile semiconductor memory devices can retain data even when no power is applied, and are therefore widely used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices.

[0004] Based on the structural configuration of the memory array, memory devices can be classified into single-plane and multi-plane types. Single-plane memory devices consist of a memory array arranged in a single plane, while multi-plane memory devices consist of a memory array arranged in multiple planes. When programming a multi-plane memory device, two or more planes can be programmed and verified simultaneously according to a multi-plane programming scheme to improve programming efficiency. However, when a multi-plane memory device contains defective (or degraded) planes, both the normal plane and the defective (or degraded) plane will be repeatedly programmed in an attempt to program data into the defective (or degraded) plane. This reduces programming speed, decreases programming efficiency, and causes programming interference in the normal plane.

[0005] Therefore, there is a need to provide a storage device and a programming method thereof that bypass certain planes, such as normal planes, so that normal planes are not subjected to programming stress from unnecessary programming pulses. Summary of the Invention

[0006] Therefore, the object of the present invention is to provide a storage device and a related programming method to eliminate programming interference.

[0007] This invention discloses a programming method for a storage device. The programming method includes: simultaneously initiating programming of at least two planes in the storage device;

[0008] When the first plane is successfully programmed but the second plane is not successfully programmed, bypass the first plane and continue programming the second plane until either of the second planes is successfully programmed and bypassed or the programming reaches a predetermined programming pulse count;

[0009] Wherein, the first plane is one or more of the at least two planes; the second plane is the plane other than the first plane among the at least two planes.

[0010] The present invention also discloses a storage device. The storage device includes at least two planes; and a control circuit coupled to the at least two planes; wherein,

[0011] The control circuit is configured to: when the first plane is successfully programmed and the second plane is not successfully programmed, bypass the first plane and continue programming the second plane until either of the second planes is successfully programmed and the bypass is completed or the programming reaches a predetermined programming pulse count;

[0012] Wherein, the first plane is one or more of the at least two planes; the second plane is the plane other than the first plane among the at least two planes.

[0013] These and other objects of the invention will undoubtedly become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various accompanying drawings. Attached Figure Description

[0014] Figure 1 This is a block diagram of a storage device according to an embodiment of the present invention.

[0015] Figure 2 yes Figure 1 A schematic diagram of the planar structure of the storage device shown.

[0016] Figure 3 This is a counterpart to the embodiments of the present invention. Figure 1 The flowchart shows a programming method for programming the storage device.

[0017] Figure 4 This is a schematic diagram showing the waveform of the programming voltage according to an embodiment of the present invention.

[0018] Figure 5 This is a counterpart to the embodiments of the present invention. Figure 1 The flowchart shows a programming method for programming the storage device.

[0019] Figure 6 This is an embodiment of the present invention. Figure 1 The diagram shows a schematic of the selected circuit in the control circuit shown. Detailed Implementation

[0020] Figure 1This is a block diagram of a memory device 10 according to an embodiment of the present invention. The memory device 10 may have a dual-plane structure and may include a control circuit 100, a word line driver 120, a plurality of bit line drivers 131, 132 and a plurality of planes (also referred to as memory planes) 141, 142.

[0021] In simple terms, planes 141 and 142 can be programmed and verified simultaneously. When plane 141 (also known as the first plane) has been successfully programmed, but plane 142 has not, plane 141 can be bypassed, and plane 142 (also known as the second plane) can still be programmed. Once plane 141 has passed all verifications, bypassing plane 141 and not performing subsequent programming reduces the time spent attempting to apply unnecessary programming impulses to plane 141 and eliminates programming interference in plane 141.

[0022] Please also refer to Figure 2 , it is Figure 1 The diagram shows planes 141 and 142 of the memory device 10. Plane 141 can be divided into multiple blocks 141B1 to 141Bi. Each block 141B1 to 141Bi includes multiple strings, which may be NAND strings. Each string may include, but is not limited to, two select cells and multiple memory cells connected in series. Select cells located at the top of a string are configured to connect the string to multiple bit lines BL11 to BL1m and can be controlled by applying an appropriate voltage to the string select line SSL1. Select cells located at the bottom of a string are configured to connect the string to the common source line CSL1 and can be controlled by applying an appropriate voltage to the ground select line GSL1. The control gates of the memory cells in each string are respectively connected to multiple word lines WL11 to WL1n.

[0023] Similarly, plane 142 can be divided into multiple blocks 142B1 to 142Bi. Each block in blocks 142B1 to 142Bi includes multiple strings, which may be NAND strings. Each string may include, but is not limited to, two select cells and multiple memory cells connected in series. Select cells located at the top of a string are configured to connect the string to multiple bit lines BL21 to BL2m and can be controlled by applying an appropriate voltage to the string select line SSL2. Select cells located at the bottom of a string are configured to connect the string to the common source line CSL2 and can be controlled by applying an appropriate voltage to the ground select line GSL2. The control gates of the memory cells in each string are respectively connected to multiple word lines WL21 to WL2n.

[0024] like Figure 2As shown, planes 141 and 142 have the same structure (or a mirror image structure). Although a dual-plane structure is used in this embodiment, it should be understood that other numbers of planes may be used within the scope of this invention. Furthermore, two-dimensional planar memory structures, three-dimensional stacked structures, NAND flash memory structures, and / or NOR flash memory structures may be implemented in planes 141 and 142. Each block in blocks 141B1 to 141Bi and 142B1 to 142Bi may be divided into multiple pages as shown by dashed lines. In some embodiments, blocks are conventional units of erasure, and pages are conventional units of programming. However, other erasure / programming units may also be used. Typically, bit lines BL11 to BL1m or BL21 to BL2m run at the top of the string in a direction perpendicular to word lines WL11 to WL1n or WL21 to WL2n, respectively, where i, m, and n are integers greater than 1, but are not limited thereto.

[0025] Those skilled in the art will understand that the number of memory cells in a string does not limit the scope of the invention. Furthermore, the memory cells in a string can be floating-gate transistors or charge-trapping transistors. Each memory cell can store 1 bit of data or two or more bits of data, and therefore can be of single-cell (SLC), multi-cell (TLC), three-cell (TLC), four-cell (QLC), or higher-level types. Each memory cell can hold one of Q possible programming states, where Q is a positive integer equal to or greater than 2; generally, Q = 2 for SLC, Q = 4 for MLC, Q = 8 for TLC, and Q = 16 for QLC.

[0026] Control circuitry 100 can be coupled to word line driver 120 and bit line drivers 131, 132. Word line driver 120 can be coupled to plane 141 via serial select line SSL1, word lines WL11 to WL1n, and ground select line GSL1. Word line driver 120 can be coupled to plane 142 via serial select line SSL2, word lines WL21 to WL2n, and ground select line GSL2. Bit line driver 131 can be coupled to plane 141 via bit lines BL11 to BL1m. Bit line driver 132 can be coupled to plane 142 via bit lines BL21 to BL2m. The memory cell array in plane 141 can be addressed by word lines WL11 to WL1n and bit lines BL11 to BL1m, and the memory cell array in plane 142 can be addressed by word lines WL21 to WL2n and bit lines BL21 to BL2m.

[0027] The control circuit 100 may be a controller, an embedded microprocessor, a microcontroller, etc. The control circuit 100 can communicate with an external host to receive data stored in planes 141 and 142, and to send data extracted from planes 141 and 142. The control circuit 100 can receive commands, addresses, or data from the external host and generate bit line address signals Scadr1, Scadr2 and word line address signal Sradr. The word line driver 120 can operate in response to the word line address signal Sradr from the control circuit 100 to select the word line for read, program, erase, and verify operations. The bit line drivers 131 and 132 can operate in response to the bit line address signals Scadr1 and Scadr2 from the control circuit 100 to generate bit line signals to select the bit line for read, program, erase, and verify operations. In some embodiments, the control circuitry 100 includes a voltage reference circuit for providing voltages for read, program, erase, and verification operations, and the bit line drivers 131, 132, and word line driver 120 include switches for selecting voltages. In other embodiments, the bit line drivers 131, 132, and word line driver 120 include voltage generation circuitry, and the control circuitry 100 provides digital control information to instruct the bit line drivers 131, 132, and word line driver 120 to drive various voltages on bit lines BL11 to BL1m, BL21 to BL2m, and word lines WL11 to WL1n, WL21 to WL2n. However, the manner in which voltages are generated or directed to the bit lines BL11 to BL1m, BL21 to BL2m, and word lines WL11 to WL1n, WL21 to WL2n does not limit the scope of the invention.

[0028] Figure 3 This is a flowchart of a programming method 30 according to an embodiment of the present invention, which is used for programming... Figure 1 The storage device 10 shown is programmed. Programming method 30 can be compiled into program code.

[0029] Method 30 can be executed by control circuit 100 and includes the following steps:

[0030] Step S300: Begin.

[0031] Step S302: Simultaneously begin programming the first plane and the second plane.

[0032] Step S304: When the first plane has been successfully programmed but the second plane has not been successfully programmed, bypass the first plane and continue programming the second plane.

[0033] Step S306: End.

[0034] In step S302, the control circuit 100 simultaneously begins programming two planes (e.g., planes 141, 142) or more planes of the storage device 10 to achieve a multi-plane programming scheme in which two or more planes can be programmed and verified simultaneously. However, in step S304, when plane 141 has been successfully programmed but plane 142 has not yet been successfully programmed, plane 141 is bypassed while plane 142 is still programmed. By bypassing plane 141 after all verifications have been passed, programming interference can be eliminated.

[0035] For example, control circuit 100 can use an incremental step pulse programming (ISPP) scheme to program planes 141 and 142. Please refer to [reference needed]. Figure 4 This is a schematic diagram illustrating the programming voltage waveform of an embodiment of the present invention. Multiple programming pulses Vpp1 to Vpp6 can be applied to the block in increasing amplitudes, and each consecutive programming pulse (e.g., programming pulse Vpp2) can exceed the immediately preceding programming pulse (e.g., programming pulse Vpp1) by one programming step. The programming step can vary depending on the programming state or other requirements. Programming pulse Vpp1 can be applied to both planes 141 and 142 to simultaneously begin programming planes 141 and 142. On the other hand, if block 141B1 has been successfully programmed before programming pulse Vpp5 is applied, block 141B1 can be affected only by programming pulses Vpp1 to Vpp4, but bypass subsequent programming pulses Vpp5 and Vpp6. Therefore, block 141B1 will not be subjected to the programming pressure of the unnecessary programming pulses Vpp5 and Vpp6. However, block 142B1 needs to be programmed by more programming pulses (i.e., programming pulses Vpp5 and Vpp6) for a longer period of time (because the number of programming pulses is greater) to eliminate or at least reduce programming interference in block 141B1.

[0036] Block 141B1 can be programmed up to a first programming pulse count (equal to 4) corresponding to programming pulses Vpp1 to Vpp4, and block 142B1 can be programmed up to a second programming pulse count (equal to 6) corresponding to programming pulses Vpp1 to Vpp6. The first programming pulse count is less than the second programming pulse count. Block 142B1 can be programmed until the maximum programming pulse count Cpmax (also known as the predetermined programming pulse count) (e.g., equal to 6) is reached. If block 142B1 is still not successfully programmed, block 142B1 can be identified as a defective block. Since programming pulse Vpp6 is the last programming pulse corresponding to the maximum programming pulse count Cpmax, the control circuit 100 can stop programming block 142B1. Although the control circuit 100 does not simultaneously terminate the programming of blocks 141B1 and 142B1 (whether successfully or unsuccessfully programmed), it simultaneously begins programming blocks 141B1 (the first memory cell) and 142B1 (the second memory cell), which is followed by block 141B2 (the third memory cell), and the second memory cell is followed by block 142B2 (the fourth memory cell). The time from the start of programming block 141B1 to the start of programming block 141B2 depends on the time from the start of programming block 142B1 to the start of programming block 142B2. In other words, the programming time for two blocks (e.g., blocks 141B1 and 142B1) is determined based on the block with the larger programming pulse count rather than the block with the smaller programming pulse count. The block with the larger programming pulse count can be a defective or degraded block, while the block with the smaller programming pulse count can be a normal block.

[0037] Figure 5 This is a flowchart of a programming method 50 according to an embodiment of the present invention, the programming method 50 being used for programming... Figure 1 The storage device 10 shown is programmed. Programming method 50 can be compiled into program code.

[0038] Method 50 can be executed by control circuit 100 and includes the following steps:

[0039] Step S500: Begin.

[0040] Step S502: Apply programming pulse.

[0041] Step S504: Increase the programming pulse count Cp.

[0042] Step S506: Bypass at least one successfully programmed plane.

[0043] Step S508: Determine whether all planes have been bypassed. If yes, proceed to step S514; otherwise, proceed to step S510.

[0044] Step S510: Determine whether the programming pulse count Cp is less than the maximum programming pulse count Cpmax. If yes, proceed to step S502; otherwise, proceed to step S512.

[0045] Step S512: Indicates programming failure.

[0046] Step S514: End.

[0047] At the start of multi-plane programming, in step S500, planes 141 and 142 are initialized for programming. Control circuit 100 sets the programming pulse count Cp and verification count Cvf to values ​​such as 0 (i.e., Cp = 0, Cvf = 0). In step S502, control circuit 100 simultaneously begins programming the first memory cell of plane 141 (block 141B1 or page) and the second memory cell of plane 142 (block 142B1 or page). Word line driver 120 can apply programming pulses (e.g., programming pulse Vpp1) to selected word lines of planes 141 and 142. In step S504, control circuit 100 increments the programming pulse count Cp by 1 (Cp = 1).

[0048] Then, the control circuit 100 can verify whether the first memory cell of plane 141 and the second memory cell of plane 142 have been successfully programmed. In some embodiments, it can be... Figure 4A verification pulse is applied after each programming pulse shown to verify the threshold voltage of each memory cell. In some embodiments, the control circuit 100 can verify whether the first memory cell and the second memory cell have reached one or more programming states. In some embodiments, data can be read from the first memory cell and the second memory cell on selected bit lines, respectively. If the data read is incorrect, the control circuit 100 can verify the corresponding first memory cell or the corresponding second memory cell as unqualified. If the data read is correct, the control circuit 100 can verify the corresponding first memory cell or the corresponding second memory cell as qualified. After the verification of the first memory cell and the second memory cell, the control circuit 100 increments the verification count Cvf by 1 (Cvf = 1). In some embodiments, if more than a corresponding preset number of the first memory cells or the second memory cells fail to reach one of the programming states, the control circuit 100 will verify the first memory cell or the second memory cell as unqualified. If less than a corresponding preset number of the first memory cells or the second memory cells fail to reach the programming state, the control circuit 100 will verify planes 141 and 142 as qualified. In some embodiments, if for each programming state, the number of first or second memory cells that cannot be successfully programmed is less than a corresponding preset number, then the first or second memory cell is determined to be qualified.

[0049] To reduce programming interference, if any plane has been successfully programmed (and verified as qualified), the control circuit 100 bypasses the (successfully programmed) plane in subsequent programming in step S506. However, the control circuit 100 continues programming another plane that has not yet been successfully programmed in step S506. The control circuit 100 sets the pause signal (or suspend signal) Sss1 to logic low while keeping the main signal Smn to logic high to bypass plane 141 and continue programming plane 142. Once plane 141 passes all verifications, programming interference can be eliminated by suspending plane 141. In some embodiments, when less than a preset number of first memory cells have not yet been verified as qualified, but more than a preset number of second memory cells have been verified as unqualified, plane 141 is suspended and plane 142 is still programmed. The first memory cells of plane 141 will be bypassed and retained in subsequent programming, while the second memory cells of plane 142 will still be programmed in subsequent programming. In other words, the first programming process for the first memory cell of plane 141 and the second programming process for the second memory cell of plane 142 begin simultaneously but do not end simultaneously. By suspending plane 141 when the first memory cell of plane 141 is bypassed, programming interference in plane 141 can be eliminated.

[0050] In step S508, control circuit 100 determines whether all planes in planes 141 and 142 for the multi-plane programming scheme have been bypassed. If all planes in planes 141 and 142 have been bypassed, the multi-plane programming scheme is complete. If any plane in planes 141 and 142 has not been bypassed (or is suspended), in step S510, control circuit 100 determines whether the programming pulse count Cp is less than the maximum programming pulse count Cpmax. If the programming pulse count Cp (e.g., Cp = 1) is less than the maximum programming pulse count Cpmax (e.g., Cpmax = 6), control circuit 100 repeats steps S402 to S408 until the programming pulse count Cp reaches the maximum programming pulse count Cpmax. For example, in step S502, another programming pulse (e.g., programming pulses Vpp2, Vpp3, ..., or Vpp6 sequentially) is applied to the selected word line of the non-bypassed plane, and in step S504, control circuit 100 increments the programming pulse count Cp by 1 again.

[0051] If the first memory cell of plane 141 is bypassed after the application of programming pulse Vpp4, the programming pulse count Cp increases to 4 to be used as the first programming pulse count. Furthermore, the verification count Cvf may be not less than 4 to be used as the first number of times for the first memory cell to be verified. Similarly, if the second memory cell of plane 142 is bypassed after the application of programming pulse Vpp6, the programming pulse count Cp increases to 6 to be used as the second programming pulse count. Alternatively, if the second memory cell of plane 142 cannot be successfully programmed (and may therefore be disabled) after the application of the last programming pulse (i.e., programming pulse Vpp6), the programming pulse count Cp also increases to 6, which is equal to the maximum programming pulse count Cpmax. In these cases, the verification count Cvf may be not less than 6 to be used as the second number of times for the second memory cell to be verified. The first programming pulse count corresponding to the first memory cell is less than the second programming pulse count corresponding to the second memory cell. The first number of times for the first memory cell to be verified is less than the second number of times for the second memory cell to be verified.

[0052] Since the first memory cell has been successfully programmed before programming pulse Vpp5 is applied, it can be affected only by programming pulses Vpp1 to Vpp4, bypassing subsequent programming pulses Vpp5 and Vpp6. Therefore, the first memory cell will not suffer from the programming pressure of subsequent programming pulses Vpp5 and Vpp6, while the second memory cell needs to be programmed by more programming pulses Vpp5 and Vpp6 for a longer time, thereby eliminating or at least reducing programming interference in block 141B1.

[0053] If the programming pulse count Cp (or the second programming pulse count) is equal to or greater than the maximum programming pulse count Cpmax, a programming failure report is sent to the control circuit 100 in step S512 to report a programming failure (if any) for a non-bypass plane (e.g., plane 142). In other words, the second memory cell can be programmed until the maximum programming pulse count Cpmax is reached. In some embodiments, the control circuit 100 may stop programming the second memory cell when the programming pulse count Cp (or the second programming pulse count) equals the maximum programming pulse count Cpmax.

[0054] It is worth noting that those skilled in the art can easily make different substitutions and modifications. For example, in order to bypass plane 141 (the first memory cell), the plane select signal or the block select signal can be blocked. Alternatively, all word lines WL11 to WL1n or all bit lines BL11 to BL1m of plane 141 can be deselected to bypass plane 141 (the first memory cell). Figure 6 This is an embodiment of the present invention. Figure 1 The diagram illustrates the selected circuitry in the control circuitry 100. The control circuitry 100 may include AND gates 101 and 102 to control access to planes 141 and 142, respectively. AND gate 101 may receive a plane address signal Spr1, a disable signal Sdb1, a master signal Smn, or a pending signal Sss1 to generate a plane selection signal Ssp1. AND gate 102 may receive a plane address signal Spr2, a disable signal Sdb2, a master signal Smn, or a pending signal Sss2 to generate a plane selection signal Ssp2. In some embodiments, the control circuitry 100 may set the master signal Smn high to continue programming the memory device 10 and set the master signal Smn low to stop programming the memory device 10. In some embodiments, when a programming failure report is received, the control circuitry 100 may generate disable signals Sdb1 and Sdb2, which may indicate the programming result when exiting the programming verification operation. In some embodiments, the pending signals Sss1 and Sss2 may indicate whether the verification result is pass or fail.

[0055] In some embodiments, disable signals Sdb1 and Sdb2 may be associated with a programming state counter, a verification count Cvf, a programming pulse count Cp, or a maximum programming pulse count Cpmax. The maximum programming pulse count Cpmax may define the maximum number of programming pulses applied to planes 141 and 142. The programming state counter may be associated with a target programming state or a current programming state. Specifically, the first memory cell and the second memory cell may be initially set to an erase state, and subsequently, a series of programming verification operations may be performed on the first memory cell and the second memory cell to program the first memory cell and the second memory cell to their respective target programming states. This series of programming verification operations may start from the lowest programming state and progress to higher programming states until the threshold voltage of the selected memory cell reaches the corresponding verification voltage level of the corresponding target programming state. In some embodiments, the verification voltage may be selected as the minimum threshold voltage of the threshold voltage distribution curve of the programming state, respectively. Each programming verification operation may include a programming operation and a subsequent verification operation.

[0056] The control circuit 100 can generate a bit line address signal Scadr1 based on the plane selection signal Ssp1, a bit line address signal Scadr2 based on the plane selection signal Ssp2, and a word line address signal Sradr based on the plane selection signals Ssp1 and Ssp2. In some embodiments, when the suspended plane 141 is determined, the control circuit 100 can set the suspended signal Sss1 to logic low. The AND gate 101 can block the plane selection signal Ssp1 in response to the suspended signal Sss1 by setting the plane selection signal Ssp1 to logic low. The control circuit 100 can also generate the word line address signal Sradr and the bit line address signal Scadr1 to deselect word lines WL11 to WL1n and bit lines BL11 to BL1m of the plane 141. Similarly, when the suspended plane 142 is determined, the control circuit 100 can set the suspended signal Sss2 to logic low. The AND gate 102 can block the plane select signal Ssp2 in response to the suspended signal Sss2 by setting the plane select signal Ssp2 to logic low. Furthermore, the control circuit 100 can generate word line address signals Sradr and bit line address signals Scadr2 to deselect word lines WL21 to WL2n and bit lines BL21 to BL2m of plane 142. For example, word lines WL11 to WL1n, WL21 to WL2n or bit lines BL11 to BL1m, BL21 to BL2m can be in a floating state, subject to low voltage, or grounded to deselect word lines WL11 to WL1n, WL21 to WL2n or bit lines BL11 to BL1m, BL21 to BL2m.

[0057] In some embodiments, AND gate 101 may receive a first block address signal replacing the plane address signal Spr1 to generate a first block select signal (replacing the plane select signal Ssp1), and AND gate 102 may receive a second block address signal replacing the plane address signal Spr2 to generate a second select signal (replacing the plane select signal Ssp2). Control circuit 100 may generate a bit line address signal Scadr1 based on the first block select signal, a bit line address signal Scadr2 based on the second block select signal, and a word line address signal Sradr based on the first block select signal and the second select signal. In some embodiments, when a suspended block 141B1 is determined, control circuit 100 may set the suspended signal Sss1 to logic low. AND gate 101 may block the first block select signal in response to the suspended signal Sss1 by setting the first block select signal to logic low. Control circuit 100 may generate word line address signal Sradr and bit line address signal Scadr1 to deselect word lines WL11 to WL1n and bit lines BL11 to BL1m of plane 141. Similarly, when suspending block 142B1 is determined, control circuit 100 can set suspend signal Sss2 to logic low, and AND gate 102 can block the second block select signal in response to suspend signal Sss2 by setting the second block select signal to logic low. Control circuit 100 can also generate word line address signal Sradr and bit line address signal Scadr2 to deselect word lines WL21 to WL2n and bit lines BL21 to BL2m of plane 142.

[0058] In summary, this invention simultaneously programs at least two planes of a storage device to achieve a multi-plane programming scheme. When at least one plane has been successfully programmed but another plane has not, at least one plane is bypassed while the other plane continues to be programmed. Once the at least one plane passes all verifications, programming interference in that at least one plane can be eliminated by bypassing it.

[0059] It will be readily apparent to those skilled in the art that many modifications and alterations can be made to the devices and methods while maintaining the teachings of the present invention. Therefore, the foregoing disclosure should be construed as being limited only by the boundaries and limits of the appended claims.

Claims

1. A programming method for a storage device, the programming method comprising: Programming begins simultaneously on at least two planes in the storage device; When the first plane is successfully programmed but the second plane is not successfully programmed, bypass the first plane and continue programming the second plane until either of the second planes is successfully programmed and bypassed or the programming reaches a predetermined programming pulse count; Wherein, the first plane is one or more of the at least two planes; the second plane is the plane other than the first plane among the at least two planes; The simultaneous programming of at least two planes in the storage device includes: Simultaneously, programming begins on one or more first memory cells of the first plane and one or more second memory cells of the second plane; wherein a first programming process for the one or more first memory cells and a second programming process for the one or more second memory cells are started simultaneously but not ended simultaneously.

2. The programming method according to claim 1, wherein, The bypassing of the first plane includes at least one of the following: Block the plane selection signal of the first plane; Block the block selection signal of the storage block in the first plane; Cancel all word lines in the first plane; Cancel all bit lines in the first plane.

3. The programming method according to claim 2, wherein, The method of blocking the plane selection signal of the first plane or blocking the block selection signal of the storage block in the first plane includes: setting the plane selection signal to logic low to block the plane selection signal of the first plane; or setting the block selection signal to logic low to block the block selection signal of the storage block in the first plane.

4. The programming method according to claim 3, wherein, The plane selection signal or the block selection signal is logically consistent with the suspend signal of the first plane. Blocking the plane selection signal of the first plane or blocking the block selection signal of the storage block in the first plane includes: setting the suspend signal of the first plane to logic low, so that the plane selection signal is logic low, thereby blocking the plane selection signal of the first plane; or setting the suspend signal of the first plane to logic low, so that the block selection signal is logic low, thereby blocking the block selection signal of the storage block in the first plane.

5. The programming method according to claim 1, wherein, The method further includes: When less than a preset number of the one or more first memory cells have not been successfully programmed and more than the preset number of the one or more second memory cells have not been successfully programmed, the programming of the one or more first memory cells in the first plane is bypassed and the programming of the one or more second memory cells in the second plane is continued.

6. The programming method according to claim 1 further includes: After the first programming process and the second programming process are completed, programming begins simultaneously on one or more third memory cells of the first plane and one or more fourth memory cells of the second plane, wherein the one or more first memory cells are followed by the one or more third memory cells, and the one or more second memory cells are followed by the one or more fourth memory cells.

7. The programming method according to claim 1, wherein, The one or more first memory units correspond to a first programming pulse count, wherein the one or more second memory units correspond to a second programming pulse count, wherein the first programming pulse count is less than the second programming pulse count.

8. The programming method according to claim 7 further includes: When the second programming pulse count is greater than a predetermined programming pulse count, a programming failure for the second plane is reported.

9. The programming method according to claim 1, further comprising: Verify whether the one or more first memory cells and the one or more second memory cells have been successfully programmed, wherein a first number of times is used for the one or more first memory cells to be verified is less than a second number of times is used for the one or more second memory cells to be verified.

10. A storage device comprising: At least two planes; and control circuitry coupled to the at least two planes; wherein, The control circuit is configured to: simultaneously begin programming at least two planes in the storage device; when the first plane is successfully programmed and the second plane is not successfully programmed, bypass the first plane and continue programming the second plane until either of the second planes is successfully programmed and the programming reaches a predetermined programming pulse count; Wherein, the first plane is one or more of the at least two planes; the second plane is the plane other than the first plane among the at least two planes; The simultaneous programming of at least two planes in the storage device includes: Simultaneously, programming begins on one or more first memory cells of the first plane and one or more second memory cells of the second plane; wherein a first programming process for the one or more first memory cells and a second programming process for the one or more second memory cells are started simultaneously but not ended simultaneously.

11. The storage device according to claim 10, wherein, The bypassing of the first plane includes at least one of the following: Block the plane selection signal of the first plane; Block the block selection signal of the storage block in the first plane; Cancel all word lines in the first plane; Cancel all bit lines in the first plane.

12. The storage device according to claim 11, wherein, The method of blocking the plane selection signal of the first plane or blocking the block selection signal of the storage block in the first plane includes: setting the plane selection signal to logic low to block the plane selection signal of the first plane; or setting the block selection signal to logic low to block the block selection signal of the storage block in the first plane.

13. The storage device according to claim 12, wherein, The plane selection signal or the block selection signal is logically consistent with the suspend signal of the first plane. Blocking the plane selection signal of the first plane or blocking the block selection signal of the storage block in the first plane includes: setting the suspend signal of the first plane to logic low, so that the plane selection signal is logic low, thereby blocking the plane selection signal of the first plane; or setting the suspend signal of the first plane to logic low, so that the block selection signal is logic low, thereby blocking the block selection signal of the storage block in the first plane.

14. The storage device according to claim 10, wherein, The control circuit is also configured to: When less than a preset number of the one or more first memory cells have not been successfully programmed and more than the preset number of the one or more second memory cells have not been successfully programmed, the programming of the one or more first memory cells in the first plane is bypassed and the programming of the one or more second memory cells in the second plane is continued.

15. The storage device according to claim 10, wherein, The programming method also includes: After the first programming process and the second programming process are completed, programming begins simultaneously on one or more third memory cells of the first plane and one or more fourth memory cells of the second plane, wherein the one or more first memory cells are followed by the one or more third memory cells, and the one or more second memory cells are followed by the one or more fourth memory cells.

16. The storage device according to claim 10, wherein, The one or more first memory units correspond to a first programming pulse count, wherein the one or more second memory units correspond to a second programming pulse count, wherein the first programming pulse count is less than the second programming pulse count.

17. The storage device according to claim 16, wherein, When the second programming pulse count is greater than a predetermined programming pulse count, a programming failure for the second plane is reported.

18. The storage device according to claim 10, wherein, The control circuit is also configured to: Verify whether the one or more first memory cells and the one or more second memory cells have been successfully programmed, wherein a first number of times is used for the one or more first memory cells to be verified is less than a second number of times is used for the one or more second memory cells to be verified.

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