Read / write calibration method and circuit

Abstract

The application provides a read-write calibration method and circuit. The method comprises the following steps: verifying the read-write accuracy of a storage controller working at different first phases respectively according to read-write consistency data, the first phase being the phase of a first clock signal provided to the storage controller; when the verification is passed, taking the phase difference between the first phase and a second phase as a candidate phase difference, the second phase being the phase of a second clock signal provided to the storage controller; and selecting a target phase difference from the candidate phase difference according to a preset rule, and adjusting the first clock signal of the storage controller so that the storage controller works at the first phase corresponding to the target phase difference. The application verifies the read-write accuracy of the storage controller at different first phases by automatically adjusting the phase difference between the first phase and the second phase, finds the optimal phase difference, and automatically calibrates the read-write accuracy of the storage controller, thereby ensuring the correctness of read-write data.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of memory, in particular to a read-write calibration method and circuit. BACKGROUND

[0002] Memory is widely used in mobile phones, electronic dictionaries and other consumer electronic products due to its advantages in volume and power consumption. The read-write accuracy of the memory determines the performance of the electronic product. Therefore, during the design and production process of the memory chip, the memory particles need to be operated to ensure the correctness of the read-write of the memory. For a traditional memory controller, at different clock frequencies, the clock channel or data channel of the memory controller needs to be manually adjusted in time, and then the phase difference between the clock signal of the memory controller and the clock signal of the memory is adjusted to ensure the correctness of the read-write data, which is time-consuming and laborious, and is not flexible and reliable. SUMMARY

[0003] In order to solve the technical problems of manual adjustment, time-consuming and laborious and low accuracy in the prior art when adjusting the time delay of the memory. The present application provides a read-write calibration method and circuit, which mainly aims to automatically find the optimal phase difference between the memory controller and the memory module to calibrate the read-write accuracy of the memory controller.

[0004] To achieve the above-mentioned purpose, the present application provides a read-write calibration method, which comprises:

[0005] Verifying the read-write accuracy of the memory controller working at different first phases according to read-write consistency data, wherein the read-write consistency data comprises whether the data read from the same storage address of the memory module and the data written under the first phase are the same, and the first phase is the phase of the first clock signal provided to the memory controller;

[0006] When the read-write accuracy of the memory controller working at the first phase is verified, the phase difference between the first phase and the second phase of the memory module is taken as a candidate phase difference, wherein the second phase is the phase of the second clock signal provided to the memory module;

[0007] Selecting a target phase difference from the candidate phase difference according to a preset rule;

[0008] Adjusting the first phase of the first clock signal of the memory controller so that the memory controller works at the first phase corresponding to the target phase difference.

[0009] In addition, to achieve the above-mentioned purpose, the present application also provides a read-write calibration circuit, which comprises a clock module, a calibration module and a memory controller connected;

[0010] The clock module is configured to provide a first clock signal for the storage controller and the calibration module, and provide a second clock signal for the storage module, wherein a first phase of the first clock signal has a phase difference with a second phase of the second clock signal;

[0011] The storage controller is configured to operate under the first clock signal to read and write data to the storage module operating under the second clock signal;

[0012] The calibration module comprises:

[0013] The first adjusting module is configured to adjust the first phase of the first clock signal by the clock module to adjust the phase difference between the first phase and the second clock signal;

[0014] The verification module is configured to verify the read and write accuracy of the storage controller operating under different first phases respectively according to read and write consistency data, wherein the read and write consistency data comprises whether the data read from a same storage address of the storage module and the data written under the first phase are the same, and the first phase is the phase of the first clock signal provided to the storage controller;

[0015] The first screening module is configured to take the phase difference between the first phase and the second phase of the storage module as a candidate phase difference when the read and write accuracy of the storage controller operating under the first phase is verified to be correct, wherein the second phase is the phase of the second clock signal provided to the storage module;

[0016] The second screening module is configured to select a target phase difference from the candidate phase difference according to a preset rule;

[0017] The second adjusting module is configured to adjust the first phase of the first clock signal of the storage controller, so that the storage controller operates under the first phase corresponding to the target phase difference.

[0018] The read and write calibration method and circuit provided by the present application automatically adjust the phase difference between the storage controller and the storage module, verify the read and write accuracy of the storage controller operating under different first phases, find out the optimal phase difference from different phase differences corresponding to different first phases, and finally make the storage controller operate under the first phase corresponding to the optimal phase difference, thereby realizing automatic calibration of the read and write accuracy of the storage controller and ensuring the correctness of the read and write data. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 The figure is a flowchart of the read and write calibration method in an embodiment of the present application;

[0020] Figure 2 The figure is a structural block diagram of the read and write calibration circuit in an embodiment of the present application;

[0021] Figure 3 Figure 1 is a structure block diagram of a read-write calibration circuit according to an embodiment of the present application.

[0022] The purposes, functional features and advantages of the present application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0023] To make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application, and should not be used to limit the present application.

[0024] Figure 1 Figure 2 is a flowchart of a read-write calibration method according to an embodiment of the present application. Referring to Figure 1 The read-write calibration method is applied in a calibration module or a calibration device, for example. The read-write calibration method comprises the following steps S100-S400.

[0025] S100: verifying read-write accuracy of a storage controller working at different first phases respectively according to read-write consistency data, the read-write consistency data comprising: whether data read out from a same storage address of a storage module at the first phase and data written in are same, wherein the first phase is a phase of a first clock signal provided to the storage controller.

[0026] Specifically, the storage controller works at a first phase, and the storage module works at a second phase. The phase difference between the different first phase and the second phase is different. The second phase is a phase of a second clock signal provided to the storage module. The storage controller is used to perform read-write and other operations on storage grains in the storage module, i.e., write data into the storage grains of the storage module or read data from the storage grains of the storage module and other operations. The storage module is a kind of memory, which can be a kind of PSRAM (Pseudo static random access memory). The highest working clock of the PSRAM is 200MHZ, the bit width supports 4 / 8 / 16bit, and the read-write access is performed in a clock double-edge mode.

[0027] Data needs to be sampled by the up and down edges of the clock. To ensure the accuracy of the sampled data, the sampling clock needs to be adjusted to the appropriate state. Otherwise, it is easy to produce error code or metastability when reading data from the memory during the sampling process of the data. The clock module can provide a plurality of first clock signals with different first phases for the storage controller, and provide a second clock signal for the storage module. The first clock signal is the working clock of the storage controller, and the second clock signal is the working clock of the storage module. The storage controller controls the storage module to perform read and write operations of data according to the first clock signal. The storage module is controlled by and driven by the second clock signal. The phase difference between the first clock signal and the second clock signal is a key factor for the data to be correctly read from the storage module.

[0028] For each first phase, the corresponding read-write consistency data is whether the data read from the same storage address of the storage module by the storage controller working in the first phase is the same as the data written.

[0029] In one specific embodiment, before step S100, the calibration module is configured first, for example, the maximum number of cyclic detection and the scanning window are configured. The maximum number of cyclic detection is the preset verification number or the maximum verification number of read-write verification of the storage controller under each phase difference; the scanning window is the difference value of the adjacent two phase differences or the step length from the current phase difference to the next phase difference. The configuration provides the clock frequency of the clock module of the first clock signal and the second clock signal of the storage controller and the initial phase difference of the first clock signal and the second clock signal. For example, the clock frequency can be configured as any frequency point of 0-200MHZ, and the initial phase difference can be configured as 30°. The mode of read-write calibration is configured, for example, the automatic calibration mode and the manual calibration mode. The present application is realized in the automatic calibration mode.

[0030] The clock module provides a first clock signal with different first phases for the storage controller and a second clock signal with the same second phase for the storage module, and the storage controller controls the write and read operations of the storage module at different first phases. The calibration module compares the data written and read by the storage controller working at different first phases to verify the read and write accuracy of the storage controller at different first phases. The storage controller working at the first phase and the storage module working at the second phase have a phase difference, which is the difference between the first phase and the second phase. The first phase can be calculated according to the phase difference and the second phase, that is, the first phase has a corresponding relationship with the phase difference. For example, the calibration module compares the data read from the same storage address by the storage controller working at the initial phase with the data written before to determine whether the data read by the storage controller at the initial phase is the same as the data written. Specifically, the first phase is the sum of the second phase and the current phase difference, the current phase difference is the sum of the previous phase difference and the preset scanning window, the initial value of the current phase difference is the preset initial phase difference, the current phase difference is less than or equal to the cutoff phase difference, that is, the cutoff value of the current phase difference is the cutoff phase difference, and the cutoff value of the first phase is the sum of the second phase and the cutoff phase difference; wherein the initial phase difference is the starting point of the preset phase difference, and the cutoff phase difference is the ending point of the preset phase difference. Specifically, in an optional embodiment, the different first phases are respectively the initial phase, the initial phase+1*scanning window, the initial phase+2*scanning window, …, the initial phase+n*scanning window, …, and the cutoff phase, wherein n is a natural number.

[0031] In order to ensure the reliability and authenticity of the read and write accuracy verification, the calibration module can verify the read and write accuracy of the storage controller working at the same first phase multiple times. If the data read from the same storage address by the storage controller working at the same first phase is the same as the data written before in multiple verifications, it is determined that the read and write accuracy of the storage controller at the first phase is normal. If the data read from the same storage address by the storage controller working at the same first phase is different from the data written before in any one of the multiple verifications, it is determined that the read and write accuracy of the storage controller at the first phase is not normal.

[0032] The calibration module can be composed of an FPGA / CPLD device. FPGA / CPLD is a reconfigurable device, and the circuit is programmable. Different circuits can be generated by modifying the programming file. The traditional ASIC device, once the circuit is generated, it cannot be modified again. Therefore, using FPGA / CPLD device can realize the verification and calibration of the read and write accuracy of the storage controller working at different clock frequencies, different bit widths and different phases.

[0033] The clock module can be a PLL (Phase Locked Loop) or a phase-locked loop, which is used to unify the clock signal and make the high-frequency device work normally, such as accessing data of the memory.

[0034] The step realizes adjusting the first phase by adjusting the phase difference between the first phase and the second phase, and verifying the consistency of the data read from the same storage address and the data written by the read-write controller working at different first phases, so as to respectively verify the read-write of the read-write controller working at each first phase.

[0035] S200: When the read-write accuracy verification of the storage controller working at the first phase is passed, the phase difference between the first phase and the second phase of the storage module is taken as a candidate phase difference, wherein the second phase is the phase of the second clock signal provided to the storage module.

[0036] Specifically, if the read-write consistency data is that the storage controller works at the same first phase, and the data read from the same storage address is the same as the data written before, the phase difference between the first phase and the second phase of the storage module is the candidate phase difference.

[0037] S300: Select a target phase difference from the candidate phase differences according to a preset rule.

[0038] S400: Adjust the first phase of the first clock signal of the storage controller, so that the storage controller works at the first phase corresponding to the target phase difference.

[0039] Specifically, the target phase difference is the final target first phase and the second phase of the storage controller, which is the optimal phase difference in the candidate phase difference, or can be any candidate phase difference. For example, a candidate phase difference with an intermediate value in the candidate phase difference can be selected as the target phase difference. The target first phase is obtained according to the sum of the target phase difference and the second phase, and the first clock signal is adjusted by delay to adjust the first clock signal of the storage controller to the target first phase, so that the storage controller can work at the target first phase. The storage controller working at the target first phase can ensure the correctness of the read-write data.

[0040] The embodiment automatically selects the optimal phase difference between the first clock signal and the second clock signal of the storage controller and the storage module through the calibration module, and adjusts the first clock signal of the storage controller to the first phase corresponding to the optimal phase difference, so as to realize the read-write calibration of the storage controller at any working frequency or data bit width, and ensure the accuracy of the read-write data.

[0041] In one embodiment, step S100 specifically includes:

[0042] For the current first phase, verify the read-write accuracy of the storage controller working at any one of the first phases from the initial phase to the cutoff phase respectively:

[0043] Control the storage controller to write data to any available address of the storage module working at the second phase under the current first phase;

[0044] Wherein, the written data is the write result.

[0045] Control the storage controller to read data from the available address of the storage module working at the second phase under the current first phase;

[0046] Wherein, the read data is the read result.

[0047] Compare whether the data written by the storage controller under the current first phase and the data read by the storage controller under the current first phase are the same;

[0048] Wherein, compare whether the write result and the read result obtained in the previous two steps respectively are the same.

[0049] Accumulate the verification number of the read-write accuracy verification of the storage controller working at the current first phase;

[0050] If the data written by the storage controller under the current first phase and the data read by the storage controller under the current first phase are the same and the accumulated verification number does not reach the preset verification number, then looply execute the steps of controlling the storage controller to write data to any available address of the storage module working at the second phase under the current first phase to the step of accumulating the verification number of the read-write accuracy verification of the storage controller working at the current first phase;

[0051] If the data written by the storage controller under the current first phase and the data read by the storage controller under the current first phase are the same and the accumulated verification number reaches the preset verification number, then end the read-write accuracy verification of the storage controller working at the current first phase;

[0052] If the data written by the storage controller under the current first phase and the data read by the storage controller under the current first phase are different, then end the read-write accuracy verification of the storage controller working at the current first phase.

[0053] Specifically, as mentioned above, any one of the first phases between the initial phase and the cut-off phase is the sum of the corresponding phase difference and the second phase, therefore, the first phase and the phase difference have a corresponding relationship. The initial phase corresponds to the initial phase difference, and the cut-off phase corresponds to the cut-off phase difference. The cut-off phase difference is the end point of the pre-set phase difference. From the initial phase difference to the cut-off phase difference, there are a plurality of different phase differences, and the difference between adjacent phase differences is equal or the step from the current phase difference to the next phase difference is equal. The delay value of 1 step is 1 / 8 period of the VCO frequency in the configuration parameter of the clock module.

[0054] When the system where the storage controller and the calibration module are located is initialized, the calibration module enters an idle state (IDLE); when the calibration module detects that the initialization flag signal cfg_done sent by the storage controller is high, it indicates that the storage module (for example, the storage particles of the PSRAM) controlled by the storage controller has been initialized, and the calibration module enters a write data state WR_DATA.

[0055] The clock module provides a first clock signal for the storage controller and a second clock signal for the storage module, and the first clock signal and the second clock signal have a phase difference. The phase difference is a certain phase difference between the initial phase difference and the cut-off phase difference. The current phase difference is the phase difference between the current first phase of the storage controller and the second phase of the storage module.

[0056] In the write data state WR_DATA, the calibration module sends a write request wr_req to the storage controller working in the current first phase. After the storage controller working in the current first phase receives the write request wr_req, it returns a ready-to-write signal wr_rdy to the calibration module. The ready-to-write signal wr_req indicates that the storage controller working in the current first phase is in a ready-to-write state. After receiving the ready-to-write signal wr_rdy, the calibration module sends the data to be written wr_data and the address to be written wr_addr to the storage controller working in the current first phase. The storage controller working in the current first phase writes the data to be written wr_data into the storage module at the address to be written wr_addr. After writing is completed, the storage controller working in the current first phase sends a write completion signal wr_done to the calibration module.

[0057] The calibration module enters the read data state RD_DATA after receiving the write completion signal wr_done. In the read data state RD_DATA, the calibration module sends a read request red_req to the memory controller operating in the current first phase. The memory controller operating in the current first phase returns a read valid signal rd_valid to the calibration module after receiving the read request red_req, where the read valid signal rd_valid indicates that the memory controller operating in the current first phase can currently read data. The calibration module sends a read address rd_addr to the memory controller operating in the current first phase after receiving the read valid signal rd_valid. The memory controller operating in the current first phase reads data rd_data from the read address rd_addr of the memory module and returns the data rd_data to the calibration module. After reading the data rd_data, the memory controller operating in the current first phase sends a read completion signal rd_done to the calibration module.

[0058] The calibration module enters the SAMPLE state after receiving the read completion signal rd_done, and accumulates the verification times of the memory controller operating in the current first phase, i.e., the counter loop_cnt is incremented by 1. The counter loop_cnt is used to accumulate the verification times of the memory controller operating in the same first phase. When the memory controller operates in another first phase, the counter loop_cnt is cleared and then re-counted.

[0059] If the data written by the memory controller in the current first phase is the same as the data read by the memory controller in the current first phase, and the accumulated verification times do not reach the preset verification times, the above steps are repeatedly executed to re-enter the WR_DATA state. The memory controller operating in the current first phase writes data to a certain memory address of the memory module, and reads data from the same memory address. The written data and the read data are compared to verify the read-write function of the memory controller operating in the current first phase. The verification times are accumulated until the accumulated verification times reach the preset verification times or the data written by the memory controller in the current first phase is different from the data read by the memory controller in the current first phase. Then, the read-write accuracy verification of the memory controller operating in the current first phase is stopped.

[0060] If the data written by the memory controller in the current first phase is the same as the data read by the memory controller in the current first phase, and the accumulated verification times reach the preset verification times, or the data written by the memory controller in the current first phase is different from the data read by the memory controller in the current first phase, the read-write accuracy verification of the memory controller operating in the current first phase is ended.

[0061] That is, if the data written by the storage controller working in the current first phase is different from the data read and the accumulated verification times do not reach the preset verification times, the read-write accuracy verification of the storage controller working in the current first phase is ended; if the data written by the storage controller working in the current first phase is different from the data read and the accumulated verification times reach the preset verification times, the read-write accuracy verification of the storage controller working in the current first phase is ended.

[0062] The calibration module is provided with a register for storing the result of each verification. If the data written by the storage controller in the current first phase is different from the data read, the register corresponding to the error bit is high, indicating that the current verification stage has an error code, at this time the calibration module no longer performs the read-write accuracy verification on the storage controller working in the current first phase. Moreover, if the current first phase is not the cutoff phase, the storage controller works in the next first phase, and the calibration module performs the read-write accuracy verification on the storage controller working in the next first phase at least once according to the same method above.

[0063] The storage controller works in any first phase, and the verification times of the storage controller in the first phase are at least once, and the maximum verification times do not exceed the preset verification times. The greater the preset verification times, the more credible the verification of the storage controller. The preset verification times can be set in advance according to the actual situation, for example, 200 times, and the actual verification times do not exceed 200 times.

[0064] The embodiment realizes the automatic verification of the read-write accuracy of the storage controller working in different first phases.

[0065] In one embodiment, the initial phase is the sum of the second phase and the initial phase difference, and the cutoff phase is the sum of the second phase and the cutoff phase difference.

[0066] The step S100 further includes:

[0067] After the read-write accuracy verification of the storage controller working in the current first phase is ended, if the current phase difference between the current first phase and the second phase is not the cutoff phase difference, the current phase difference is scanned according to the scanning window to obtain the next phase difference.

[0068] The next first phase is obtained according to the sum of the next phase difference and the second phase, the first phase of the first clock signal is adjusted, the memory controller is operated in the next first phase, and the next first phase is taken as the current first phase; that is, the next first phase is obtained according to the sum of the next phase difference and the second phase, and the current first phase is updated according to the next first phase; the phase of the first clock signal is adjusted according to the updated current first phase, and the memory controller is operated in the updated current first phase.

[0069] After the read-write accuracy verification of the memory controller operating in the current first phase is completed, if the current phase difference between the current first phase and the second phase is the cutoff phase difference, the read-write accuracy verification of the memory controller operating in the different first phase is completed.

[0070] Specifically, if the data written by the memory controller in the current first phase is different from the data read out, at this time, the calibration module no longer performs the read-write accuracy verification on the memory controller operating in the current first phase, but adjusts the phase difference to adjust the first phase of the memory controller, so that the memory controller operates in the next first phase, and the read-write accuracy of the memory controller operating in the next phase is verified. The next first phase is the sum of the next phase difference and the second phase, and the next phase difference is obtained by scanning the current phase difference according to the scanning window.

[0071] After the read-write accuracy verification of the memory controller operating in the current first phase is completed, if the current phase difference between the current first phase and the second phase is the cutoff phase difference, the read-write accuracy verification of the memory controller operating in the different first phase is completed.

[0072] For example, the current phase difference is 30°, and the scanning window is 30°, so the next phase difference is 60°. Similarly, the same scanning window is 30°, if the current phase difference is 60°, then the next phase difference is 90°. The scanning window is pre-configured, and the scanning window or step length can also be limited by setting the maximum scanning step number. For example, the maximum scanning step number is limited to not more than 12 steps, and according to the initial phase difference and the cutoff phase difference, the value range of the scanning window can be obtained.

[0073] Further, if the current phase difference is the cut-off phase difference, the current phase difference is the last phase difference to be verified, and thus after the read-write accuracy verification of the storage controller operating in the current first phase is completed, the verification of all possible phase differences is completed, and the verification step can be stopped.

[0074] In one embodiment, step S200 specifically comprises:

[0075] When the accumulated verification times reach the preset verification times, and the data written and read by the storage controller in each verification are the same, the phase difference between the current first phase in which the storage controller operates and the second phase in which the storage module operates is taken as a candidate phase difference. That is, when the accumulated verification times reach the preset verification times and the data written and read by the storage controller in each verification are the same, the read-write accuracy verification of the storage controller operating in the first phase is passed.

[0076] Specifically, for example, the initial phase difference is 30°, the cut-off phase difference is 180°, and the scanning window is 30°, and all the phase differences include: 30°, 60°, 90°, 120°, 150°, and 180°. The first phase corresponding to each phase difference is obtained according to the sum of the six phase differences 30°, 60°, 90°, 120°, 150°, and 180° and the second phase, respectively. The read-write accuracy verification of the storage controller operating in each first phase is performed at most 200 times. After scanning 30°-180°, if only the storage controllers operating in the first phases corresponding to the three phase differences 90°, 120°, and 150° have the same data read from the same storage address and the data written before in each of the 200 read-write accuracy verifications, respectively, 90°, 120°, and 150° are taken as candidate phase differences.

[0077] In one embodiment, step S300 specifically comprises:

[0078] The candidate phase difference with the intermediate value in the candidate phase difference with the largest number and the most continuous candidate phase differences is taken as the target phase difference. Specifically, one or more continuous phase difference sequences are selected from the candidate phase differences, wherein the difference between each adjacent two candidate phase differences in the continuous phase difference sequence is the preset scanning window; the continuous phase difference sequence with the largest number of candidate phase differences is selected, and the candidate phase difference with the intermediate value in the selected continuous phase difference sequence is taken as the target phase difference.

[0079] Specifically, the target phase difference is the intermediate value of a continuous correct phase difference. For example, 90°, 120°, and 150° are taken as the candidate phase differences, and 120° is taken as the target phase difference.

[0080] For example, the scanning window is 10°, the candidate phase differences are 30°, 40°, 50°, 60°, 70°, 120°, 130°, and 140°, thus, the continuous phase difference sequence 1 is: [30°, 40°, 50°, 60°, 70°], the continuous phase difference sequence 2 is: [120°, 130°, 140°], the data of the candidate phase difference in the continuous phase difference sequence 1 is 5, the data of the candidate phase difference in the continuous phase difference sequence 2 is 3, and the middle value of the continuous phase difference sequence 1, i.e., 50°, is selected as the target phase difference. Further, if the continuous phase difference sequence 1 is: [30°, 40°, 50°, 60°], and the number of the candidate phase differences is even, the middle values are 40° and 50°, respectively, and both of the values can be used as the target phase difference.

[0081] In one embodiment, the method further comprises: comparing the data written by the storage controller at the current phase difference with the data read by the storage controller to determine whether the data written by the storage controller at the current phase difference is the same as the data read by the storage controller, including:

[0082] obtaining the read delay of the storage controller;

[0083] aligning the data written by the storage controller at the current first phase with the data read by the storage controller according to the read delay;

[0084] comparing the data written by the storage controller after the aligning with the data read by the storage controller to determine whether the data written by the storage controller after the aligning is the same as the data read by the storage controller.

[0085] Specifically, the read delay of the storage controller is an inherent attribute, which is generally related to the hardware performance of the system (for example, related to the frequency and the chip) and cannot be completely avoided. All the above states are to find the best clock sampling window and obtain the best phase difference. However, there may be a case where the high and low bytes are reversed or offset by one clock cycle, and automatic byte alignment is required.

[0086] obtaining the data written by the storage controller from the same storage address and the data read by the storage controller from the same storage address, aligning the data written by the storage controller from the same storage address with the data read by the storage controller from the same storage address, obtaining the alignment value in the aligning, and obtaining the read delay of the storage controller according to the alignment value. Since the read delay is an inherent attribute, the obtained read delay is applicable to each stage. The data written by the storage controller and the data read by the storage controller need to be aligned before the read-write accuracy of the storage controller is verified each time, so as to eliminate the interference of the read delay on the verification result.

[0087] In one embodiment, the method further comprises: obtaining the read delay of the storage controller; and aligning each read data of the storage controller working at the first phase corresponding to the target phase difference according to the read delay, and taking the read data after the aligning as the final read data.

[0088] Specifically, even if there is a read delay under the target phase difference, therefore, the data read by the storage controller working under the target phase difference also needs to be aligned to be the correct read data.

[0089] The application combines the traditional storage controller with the calibration module and the clock module, realizes the delay adjustment of the clock channel or the data channel under different clock frequencies and different bit widths, and does not need to manually adjust the delay of the clock channel or the data channel of the storage, which not only saves time and effort, but also has wide application, guarantees the correctness of the read and write data, is flexible and reliable.

[0090] It should be understood that the size of the serial number of each step in the above embodiment does not mean the order of execution, and the execution order of each process should be determined according to its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the application.

[0091] Figure 2 The structure block diagram of the read-write calibration circuit in an embodiment of the application is shown in FIG. 1. Figure 2 The read-write calibration circuit includes a clock module, a calibration module and a storage controller connected with each other.

[0092] The clock module is configured to provide a first clock signal for the storage controller and the calibration module, and provide a second clock signal for the storage module, wherein a first phase of the first clock signal and a second phase of the second clock signal have a phase difference.

[0093] The storage controller is configured to work under the first clock signal to read and write data from and to the storage module working under the second clock signal.

[0094] The calibration module includes:

[0095] The first adjustment module is configured to adjust the first phase of the first clock signal by the clock module to adjust the phase difference between the first phase and the second phase,

[0096] The verification module is configured to verify the read-write accuracy of the storage controller working under different first phases according to read-write consistency data, and the read-write consistency data includes whether the data read from the same storage address of the storage module under the first phase is the same as the data written, wherein the first phase is the phase of the first clock signal provided for the storage controller.

[0097] The first screening module is configured to take the phase difference between the first phase of the storage controller working under which the read-write accuracy is verified to pass and the second phase of the storage module working under which as a candidate phase difference when the read-write accuracy of the storage controller working under the first phase is verified to pass, wherein the second phase is the phase of the second clock signal provided for the storage module.

[0098] The second screening module is configured to select a target phase difference from the candidate phase differences according to a preset rule.

[0099] The second adjusting module is configured to adjust a first phase of the first clock signal of the storage controller, so that the storage controller works at the first phase corresponding to the target phase difference.

[0100] Reference Figure 2 The clock module provides a first clock signal for the storage controller and the calibration module, the first clock signal is a system working clock of the storage controller and the calibration module, and the second clock signal is provided for the storage module through an interface of the storage controller, and the second clock signal is used as a working clock of the storage module to drive the storage module. The storage controller controls the reading and writing of the storage module on the storage particles according to the first clock signal. The calibration module receives the first clock signal as the clock of the calibration module, and is also used to change the phase of the first clock signal by controlling the clock module, and then adjust the phase difference between the first clock signal and the second clock signal, so that the storage controller works at different first phases corresponding to different phase differences. Figure 3 The reading and writing calibration circuit in the embodiment adjusts the phase difference between the first clock signal and the second clock signal by changing one clock signal while keeping the other clock signal unchanged.

[0101] More specifically, the first clock signal and the second clock signal are respectively sclk clock signal and clk clock signal. The calibration module receives the sclk clock signal as the clock of the calibration module. The calibration module can also include a user interaction interface, through which the user can configure various parameters of the calibration module.

[0102] In one embodiment, the verification module is specifically configured to verify the reading and writing accuracy of the storage controller working at any one of the first phases from the initial phase to the cutoff phase by the following modules:

[0103] The write control module is configured to control the storage controller to write data to any available address of the storage module working at the second phase at the current first phase;

[0104] The read control module is configured to control the storage controller to read data from the available address of the storage module working at the second phase at the current first phase;

[0105] The comparison module is configured to compare whether the data written by the storage controller at the current first phase and the data read by the storage controller are the same;

[0106] The counting module is configured to accumulate the verification times of the reading and writing accuracy verification of the storage controller working at the current first phase;

[0107] The first cycle module is configured to cycle to the write control module to the counting module if the data written by the storage controller at the current first phase is the same as the read data and the accumulated verification times do not reach the preset verification times.

[0108] The first end module is configured to end the read-write accuracy verification of the storage controller working at the current first phase if the data written by the storage controller at the current first phase is the same as the read data and the accumulated verification times reach the preset verification times.

[0109] The second end module is configured to end the read-write accuracy verification of the storage controller working at the current first phase if the data written by the storage controller at the current first phase is different from the read data.

[0110] In an embodiment, the verification module further comprises:

[0111] The phase difference adjustment module is configured to, after ending the read-write accuracy verification of the storage controller working at the current first phase, scan the current phase difference according to a scanning window to obtain a next phase difference if the current phase difference between the current first phase and the second phase is not the cutoff phase difference.

[0112] The third adjustment module is configured to obtain a next first phase according to a sum of the next phase difference and the second phase, adjust the first phase of the first clock signal, make the storage controller work at the next first phase, and take the next first phase as the current first phase.

[0113] That is, the third adjustment module is configured to obtain a next first phase according to a sum of the next phase difference and the second phase, update the current first phase according to the next first phase, and adjust the phase of the first clock signal according to the updated current first phase, so that the storage controller works at the updated current first phase.

[0114] The third end module is configured to, after ending the read-write accuracy verification of the storage controller working at the current first phase, end the execution of the verification module if the current phase difference between the current first phase and the second phase is the cutoff phase difference.

[0115] In an embodiment, the first screening module is specifically configured to: when the read-write accuracy verification of the storage controller working at the first phase passes, take the phase difference between the first phase and the second phase of the storage module as a candidate phase difference, wherein the second phase is the phase of the second clock signal provided to the storage module.

[0116] In one embodiment, the second screening module is specifically configured to select, from the candidate phase differences, a candidate phase difference with an intermediate value as a target phase difference, the candidate phase difference being in a continuous candidate phase difference sequence with the largest number of candidate phase differences.

[0117] In one embodiment, the comparison module specifically comprises:

[0118] a delay obtaining module configured to obtain a read delay of the storage controller;

[0119] an alignment module configured to perform alignment processing on the data written and read by the storage controller at the current first phase according to the read delay;

[0120] a comparison module configured to compare the data written and the corresponding data read after the alignment processing to determine whether they are the same.

[0121] In one embodiment, the present application provides a read-write calibration device, which comprises:

[0122] a first adjusting module configured to adjust a first phase of a first clock signal by the clock module to adjust a phase difference between the first phase and a second phase,

[0123] a verification module configured to verify the read-write accuracy of the storage controller operating at different first phases according to read-write consistency data, the read-write consistency data comprising whether the data read and written from the same storage address of the storage module operating at the first phase are the same, wherein the first phase is the phase of the first clock signal provided to the storage controller

[0124] a first screening module configured to, when the read-write accuracy verification of the storage controller operating at the first phase passes, take the phase difference between the first phase and a second phase at which the storage module operates as a candidate phase difference, wherein the second phase is the phase of a second clock signal provided to the storage module;

[0125] a second screening module configured to select a target phase difference from the candidate phase differences according to a preset rule;

[0126] a second adjusting module configured to adjust the first phase of the first clock signal of the storage controller so that the storage controller operates at the first phase corresponding to the target phase difference.

[0127] Figure 1The structure block diagram of the read-write calibration circuit in an embodiment of the present application is shown in the figure. The clock module is a PLL phase-locked loop, the storage module is a PSRAM pseudo-random memory, and the storage controller is a PPSRAM storage controller. The calibration module, the PSRAM storage controller, and the clock module PLL are packaged as an FPGA / CPLD device for performing data read-write operations and read-write calibration operations on the PSRAM pseudo-random memory from PSRAM storage particles. The clock module PLL provides the PSRAM_sclk clock signal and the PSRAM_clk clock signal for the PSRAM storage controller, and simultaneously provides the PSRAM_sclk clock signal for the calibration module as the working clock signal of the calibration module. The calibration module controls the clock module PLL to adjust the PSRAM_sclk clock signal according to the PSRAM_sclk clock signal through the pll_adjust signal, so as to adjust the phase difference between the PSRAM_sclk clock signal and the PSRAM_clk clock signal. Because data is sampled by a clock, the delay adjustment of the PSRAM_sclk will affect the read-write of the data by the storage controller, and the PSRAM storage controller has different abilities of data read-write at different phase differences. The read-write accuracy of the PSRAM storage controller working at different phase differences is verified, so as to screen out the optimal phase difference as the final working phase difference of the PSRAM storage controller.

[0128] The specific implementation process of the read-write calibration circuit of the present application is the same as the read-write calibration method described above, and will not be described here.

[0129] The "first" and "second" in the above modules / units are only used to distinguish different modules / units, and are not used to limit the priority of which module / unit is higher or other limiting meanings. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device including a series of steps or modules does not have to be limited to only those steps or modules clearly listed, but can include other steps or modules not clearly listed or inherent to these processes, methods, products or devices. The division of modules in the present application is only a logical division, and other division methods can be used in actual application.

[0130] The specific limitations of the read-write calibration device can be referred to the limitations of the read-write calibration method described above, and will not be described here. The above modules of the read-write calibration device can be realized by software, hardware, and combinations thereof, in whole or in part. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to the above modules.

[0131] In one embodiment, a computer device is provided, which includes a memory, a processor, and computer readable instructions (e.g., a computer program) stored in the memory and executable on the processor, the processor implements the steps of the read-write calibration method in the above embodiments when executing the computer readable instructions, for example Figure 1 The steps S100 to S300 and other extensions and related steps of the method are shown. Alternatively, the processor implements the functions of each module / unit of the read-write calibration apparatus in the above embodiments when executing the computer readable instructions. To avoid repetition, it will not be repeated here.

[0132] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor and the like, and the processor is the control center of the computer device, which connects all parts of the computer device through various interfaces and lines.

[0133] The memory can be used to store computer readable instructions and / or modules, and the processor realizes various functions of the computer device by running or executing the computer readable instructions and / or modules stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application program required by a function (such as a sound playing function, an image playing function, etc.), etc.; and the data storage area can store data created according to the use of the mobile phone (such as audio data, video data, etc.), etc.

[0134] The memory can be integrated in the processor, or can be separately arranged from the processor.

[0135] Those skilled in the art can understand that the structure shown is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or less components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0136] In one embodiment, a computer readable storage medium is provided, having computer readable instructions stored thereon, which when executed by a processor implement the steps of the read-write calibration method in the above embodiments, for example Figure 1 The steps S100 to S300 and other extensions and related steps of the method are shown. Alternatively, the computer readable instructions are executed by the processor to implement the functions of each module / unit of the read-write calibration apparatus in the above embodiments. To avoid repetition, it will not be repeated here.

[0137] Those of ordinary skill in the art can understand that all or part of the processes in the above embodiments can be completed by computer readable instructions instructing related hardware, and the computer readable instructions can be stored in a computer readable storage medium, and when executed, can include the processes of the above embodiments. Any reference to memory, storage, database or other medium used in the embodiments provided in the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0138] It should be noted that in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusions, so that a process, device, article or method including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, device, article or method. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, device, article or method including the element.

[0139] The above application embodiment serial numbers are only for description, and do not represent the advantages and disadvantages of the embodiments. Through the above description of the embodiments, those skilled in the art can clearly understand that the above embodiment methods can be realized by means of software and the necessary general hardware platform, and of course, they can also be realized by hardware, but in many cases, the former is a better embodiment. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disc, optical disc) as described above, and includes a plurality of instructions for making a terminal device (which can be a mobile phone, computer, server, or network device, etc.) execute the methods described in various embodiments of the present application.

[0140] The above is only the preferred embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation using the content of the present application specification and drawings, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.

Claims

1. A read / write calibration method, applied to a calibration module, wherein the calibration module is connected to a storage controller, characterized in that, The method includes: The read / write accuracy of the storage controller operating under different first phases is verified based on read / write consistency data. The read / write consistency data includes whether the data read from the same storage address of the storage module and the data written are the same when operating under the first phase. The first phase is the phase of the first clock signal provided to the storage controller. The verification of the read / write accuracy of the storage controller operating under different first phases based on read / write consistency data includes: For the current first phase, control the storage controller to write data to any available address of the storage module operating in the second phase; The storage controller is controlled to read data from the available address of the storage module operating in the second phase under the current first phase; Compare whether the data written and read by the storage controller in the current first phase are the same; The number of verifications for the read / write accuracy of the storage controller operating under the current first phase is accumulated; If the data written by the storage controller under the current first phase is the same as the data read out and the accumulated verification count has not reached the preset verification count, then the step of controlling the storage controller to write data to any available address of the storage module operating under the second phase under the current first phase is executed repeatedly until the step of accumulating the verification count of the read and write accuracy verification of the storage controller operating under the current first phase is executed. If the data written by the storage controller under the current first phase is the same as the data read out and the accumulated number of verifications reaches the preset number of verifications, then the verification of the read and write accuracy of the storage controller operating under the current first phase ends. If the data written by the storage controller under the current first phase is different from the data read, then the verification of the read / write accuracy of the storage controller operating under the current first phase ends. When the read / write accuracy verification of the storage controller operating under the first phase is passed, the phase difference between the first phase and the second phase in which the storage module operates is taken as the candidate phase difference, wherein the second phase is the phase of the second clock signal provided to the storage module; A target phase difference is selected from the candidate phase differences according to a preset rule; The first phase of the first clock signal of the storage controller is adjusted so that the storage controller operates at the first phase corresponding to the target phase difference.

2. The method according to claim 1, characterized in that, The first phase is the sum of the second phase and the current phase difference, the current phase difference is the sum of the previous phase difference and the preset scanning window, the initial value of the current phase difference is the preset initial phase difference, and the current phase difference is less than or equal to the cutoff phase difference; After completing the verification of the read / write accuracy capability of the memory controller operating in the current first phase, the process further includes: If the current phase difference between the current first phase and the second phase is not the cutoff phase difference, then the current phase difference is scanned according to the scanning window to obtain the next phase difference; The next first phase is obtained based on the sum of the next phase difference and the second phase, and the current first phase is updated based on the next first phase; The phase of the first clock signal is adjusted according to the updated current first phase, so that the memory controller operates in the updated current first phase; If the current phase difference between the current first phase and the second phase is the cutoff phase difference, then the verification of the read / write accuracy of the storage controller operating under different first phases ends.

3. The method according to claim 1, characterized in that, When the read / write accuracy verification of the storage controller operating in the first phase passes, the phase difference between the first phase and the second phase in which the storage module operates is used as a candidate phase difference, including: When the accumulated number of verifications reaches the preset number of verifications and the data written and read by the storage controller are the same in each verification, the read and write accuracy verification of the storage controller operating in the first phase is passed; The phase difference between the current first phase in which the storage controller operates and the second phase in which the storage module operates is used as the candidate phase difference.

4. The method according to claim 3, characterized in that, The step of selecting a target phase difference from the candidate phase differences according to a preset rule includes: One or more consecutive phase difference sequences are selected from the candidate phase differences, wherein the difference between each two adjacent candidate phase differences in the consecutive phase difference sequence is a preset scanning window; Select the continuous phase difference sequence with the largest number of candidate phase differences, and take the candidate phase difference with the median phase difference in the selected continuous phase difference sequence as the target phase difference.

5. A read / write calibration circuit, characterized in that, The circuit includes a connected clock module, a calibration module, and a storage controller; The clock module is used to provide a first clock signal to the storage controller and the calibration module, and to provide a second clock signal to the storage module, wherein there is a phase difference between the first phase of the first clock signal and the second phase of the second clock signal; The storage controller is used to operate under the first clock signal to read and write data to the storage module operating under the second clock signal; The calibration module includes: The first adjustment module is used to adjust the first phase of the first clock signal through the clock module, so as to adjust the phase difference between the first phase and the second phase. The verification module is used to verify the read and write accuracy of the storage controller operating under different first phases based on read and write consistency data. The read and write consistency data includes whether the data read from the same storage address of the storage module and the data written are the same when operating under the first phase. The first phase is the phase of the first clock signal provided to the storage controller. The verification module includes: The write control module is used to control the storage controller to write data to any available address of the storage module operating in the second phase under the current first phase. A read control module is used to control the storage controller to read data from the available address of the storage module operating in the second phase under the current first phase; The comparison module is used to compare whether the data written and read by the storage controller in the current first phase are the same; The counting module is used to accumulate the number of verifications for the read / write accuracy verification of the storage controller operating under the current first phase; The first loop module is used to loop back to the write control module to the counting module if the data written by the storage controller under the current first phase is the same as the data read out and the accumulated number of verifications has not reached the preset number of verifications. The first termination module is used to terminate the read / write verification of the storage controller operating in the current first phase if the data written by the storage controller in the current first phase is the same as the data read out and the accumulated verification count reaches the preset verification count. The second termination module is used to terminate the read / write verification of the storage controller operating in the current first phase if the data written by the storage controller in the current first phase is different from the data read out. The first filtering module is used to select the phase difference between the first phase and the second phase in which the storage module operates as a candidate phase difference when the read / write accuracy verification of the storage controller operating under the first phase is passed, wherein the second phase is the phase of the second clock signal provided to the storage module; The second filtering module is used to select a target phase difference from the candidate phase differences according to preset rules. The second adjustment module adjusts the first phase of the first clock signal of the storage controller so that the storage controller operates under the first phase corresponding to the target phase difference.

6. The circuit according to claim 5, characterized in that, The verification module also includes: The phase difference adjustment module is used to scan the current phase difference according to the scanning window to obtain the next phase difference after the read / write accuracy verification of the memory controller operating under the current first phase is completed. The third adjustment module is used to obtain the next first phase based on the sum of the next phase difference and the second phase, update the current first phase based on the next first phase, and adjust the phase of the first clock signal based on the updated current first phase so that the memory controller operates at the updated current first phase. The third termination module is used to terminate the execution of the verification module if the current phase difference between the current first phase and the second phase is the cutoff phase difference after the verification of the read / write accuracy of the storage controller operating under the current first phase is completed.

7. The circuit according to claim 5, characterized in that, The first filtering module is specifically used for: when the accumulated number of verifications reaches the preset number of verifications and the data written and read by the storage controller are the same in each verification, the read and write accuracy verification of the storage controller operating in the first phase is passed; and the phase difference between the current first phase in which the storage controller is operating and the second phase in which the storage module is operating is used as the candidate phase difference.

8. The circuit according to claim 7, characterized in that, The second filtering module is specifically used to: select one or more continuous phase difference sequences from the candidate phase differences, wherein the difference between each two adjacent candidate phase differences in the continuous phase difference sequence is a preset scanning window; select the continuous phase difference sequence with the most candidate phase differences, and take the candidate phase difference with the median phase difference in the selected continuous phase difference sequence as the target phase difference.

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