Electrostatic Discharge Protection Structure and Method for Forming the Same

Abstract

An electrostatic discharge protection structure and a method for forming the same, comprising: a substrate including a first region and a plurality of second regions; a first well region located in the first region, having a first doping ion in the first well region; a second well region located in the second region, having a second doping ion in the second well region; a plurality of first gate structures located on the first region; a second gate structure located on the second region; a first doping layer in the substrate between adjacent first gate structures; a second doping layer and a third doping layer in the substrate on both sides of the second gate structure respectively. Since the electrical types of the second doping ion and the first doping ion are different, a reverse-biased junction is formed at the junction of the first well region and the second well region. Since the first gate structure is serially connected to the reverse-biased junction through the first well region, the resistance value of the branch formed by the first gate structure and the reverse-biased junction is increased, thereby reducing the risk of the first gate structure being broken down, and thus improving the performance of the finally formed semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and particularly to an electrostatic discharge protection structure and a method for forming the same. Background Art

[0002] Integrated circuits are vulnerable to electrostatic damage. Generally, protection circuits are designed at the input / output terminals or power protection devices of the circuit to prevent the internal circuit from being damaged by static electricity.

[0003] In existing integrated circuit designs, an electrostatic discharge (ESD) protection structure is often used to reduce electrostatic damage. The existing electrostatic discharge protection structures mainly include: a gate-grounded N-type field-effect transistor (Gate Grounded NMOS, abbreviated as GGNMOS) protection circuit, a silicon controlled rectifier (SCR) protection circuit, a lateral double-diffused MOSFET (LDMOS) protection circuit, a bipolar junction transistor (BJT) protection circuit, etc.

[0004] Among them, GGNMOS is a widely used electrostatic discharge protection structure. Its working mechanism is as follows: Since the power consumption on the MOS transistor is the product of the passing current and the voltage drop, at a certain ESD static current, if the voltage drop on the MOS transistor can be reduced, and then the junction temperature of the MOS transistor can be reduced, so as to achieve the purpose of protecting the MOS transistor. As an ESD device, GGNMOS relies on the parasitic NPN BJT to discharge the ESD current in the forward direction. The NPN is composed of the N+ active region of the drain, the P-type substrate, and the N+ active region of the source; the path for discharging the ESD current in the reverse direction is composed of a PN diode and an NMOS diode with the gate-source connected. The PN diode is composed of the P-type substrate and the N+ active region. In the ESD network of the entire chip, when the ESD time comes, GGNMOS may conduct in both the forward and reverse directions, which is determined by the potential ESD path, and the ESD current always flows to the low-resistance path. Therefore, it is necessary to consider the forward and reverse ESD performances of GGNMOS during design to ensure the reliability of the integrated circuit. As a BJT, GGNMOS has a breakdown device working mechanism, and relies on the avalanche breakdown between the drain and the substrate to trigger the formation of a low-resistance path to discharge the ESD current.

[0005] However, the performance of the electrostatic discharge protection structure formed by the prior art needs to be improved. Summary of the Invention

[0006] The technical problem solved by the present invention is to provide an electrostatic discharge protection structure and a method for forming the same, which can effectively improve the performance of the electrostatic discharge protection structure.

[0007] To solve the above problems, the present invention provides an electrostatic discharge protection structure, including: a substrate, the substrate includes a first region and a plurality of second regions arranged along a first direction, the first region is located between adjacent second regions; a first well region located in the first region, the first well region has a first doping ion; a second well region located in the second region, the second well region has a second doping ion, and the conductivity type of the second doping ion is different from that of the first doping ion; a plurality of first gate structures located on the first region; a second gate structure located on the second region; a first doping layer in the substrate between adjacent first gate structures, the first doping layer has the first doping ion, and the first doping layer is also located in the first well region; a second doping layer and a third doping layer in the substrate on both sides of the second gate structure respectively, the second doping layer and the third doping layer have the first doping ion, the second doping layer and the third doping layer are respectively located in the second well region, and the second doping layer is also in contact with the first well region.

[0008] Optionally, the first doping ion includes an N-type ion; the first doping ion includes: phosphorus or arsenic.

[0009] Optionally, the second doping ion includes a P-type ion; the second doping ion includes: boron or indium.

[0010] Optionally, the substrate includes: a substrate and fins located on the substrate, the fins have the first well region and the second well region, and the first doping layer, the second doping layer and the third doping layer are located in the fins.

[0011] Optionally, it further includes: an isolation structure located in the fins.

[0012] Optionally, the substrate includes: a substrate and a first fin and a second fin located on the substrate, the first fin has the first well region and the second well region, and the first doping layer, the second doping layer and the third doping layer are located in the first fin, and the second fin has the second well region.

[0013] Optionally, it further includes: an isolation structure located between the first fin and the second fin.

[0014] Optionally, it further includes: a heavily doped region formed in the second well region, the isolation structure being located between the heavily doped region and the third doped layer, the heavily doped region having a third doped ion, the third doped ion having the same electrical type as the second doped ion, and the concentration of the third doped ion in the heavily doped region being greater than the concentration of the second doped ion in the second well region.

[0015] Optionally, the first doped layer is connected to an electrostatic output terminal; the third doped layer, the second gate structure, and the heavily doped region are connected to an electrostatic input terminal.

[0016] Optionally, it further includes: a first conductive plug on the first doped layer at the middle position of the first region, the first conductive plug being connected to the electrostatic output terminal; second conductive plugs respectively on the third doped layer, the second gate structure, and the heavily doped region, the second conductive plugs being connected to the electrostatic input terminal.

[0017] Optionally, the first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

[0018] Correspondingly, the present invention further provides a method for forming an electrostatic discharge protection structure, including: providing a substrate, the substrate including a first region and a plurality of second regions arranged along a first direction, the first region being located between adjacent second regions; forming a first well region in the first region, the first well region having a first doped ion; forming a second well region in the second region, the second well region having a second doped ion, the second doped ion having a different electrical type from the first doped ion; forming a plurality of first gate structures on the first region; forming a second gate structure on the second region; forming a first doped layer in the substrate between adjacent first gate structures, the first doped layer having the first doped ion, and the first doped layer also being located in the first well region; respectively forming a second doped layer and a third doped layer in the substrate on both sides of the second gate structure, the second doped layer and the third doped layer having the first doped ion, the second doped layer and the third doped layer being respectively located in the second well region, and the second doped layer also being in contact with the first well region.

[0019] Optionally, the method for forming the first well region and the second well region includes: forming a first patterned layer on the substrate, the first patterned layer exposing the top surface of the first region; using the first patterned layer as a mask, performing an implantation process of a first doping ion on the first region to form the first well region in the first region; after forming the first well region, removing the first patterned layer; forming a second patterned layer on the substrate, the second patterned layer exposing the top surface of the second region; using the second patterned layer as a mask, performing an implantation process of a second doping ion on the second region to form the second well region in the second region.

[0020] Optionally, the first doping ion includes an N-type ion; the first doping ion includes: phosphorus or arsenic.

[0021] Optionally, the second doping ion includes a P-type ion; the second doping ion includes: boron or indium.

[0022] Optionally, the substrate includes: a substrate and fins located on the substrate, the first well region and the second well region are within the fins, and the first doping layer, the second doping layer, and the third doping layer are located within the fins.

[0023] Optionally, further includes: forming an isolation structure, the isolation structure is located within the fins.

[0024] Optionally, the substrate includes: a substrate and a first fin and a second fin located on the substrate, the first well region and the second well region are within the first fin, and the first doping layer, the second doping layer, and the third doping layer are located within the first fin, and the second well region is within the second fin.

[0025] Optionally, further includes: forming an isolation structure, the isolation structure is located between the first fin and the second fin.

[0026] Optionally, the method for forming the fins and the isolation structure includes: providing an initial substrate; forming a third patterned layer on the initial substrate, the third patterned layer exposing a part of the top surface of the initial substrate; etching the initial substrate using the third patterned layer as a mask to form a substrate and fins located on the substrate; etching a part of the fins to form an isolation opening within the fins; forming the isolation structure within the isolation opening.

[0027] Optionally, the method for forming the first fin portion, the second fin portion, and the isolation structure includes: providing an initial substrate; forming a third patterned layer on the initial substrate, the third patterned layer exposing a top surface of a part of the initial substrate; etching the initial substrate using the third patterned layer as a mask to form a base and the first fin portion and the second fin portion located on the base, with an isolation opening between the first fin portion and the second fin portion; and forming the isolation structure in the isolation opening.

[0028] Optionally, after forming the isolation structure, the method further includes: forming a heavily doped region in the second well region, the isolation structure being located between the heavily doped region and the third doped layer, the heavily doped region having a third doping ion, the third doping ion having the same electrical type as the second doping ion, and the concentration of the third doping ion in the heavily doped region being greater than the concentration of the second doping ion in the second well region.

[0029] Optionally, after forming the heavily doped region, the method further includes: connecting the first doped layer to an electrostatic output terminal; connecting the third doped layer, the second gate structure, and the heavily doped region to an electrostatic input terminal.

[0030] Optionally, the method for connecting the first doped layer to the electrostatic output terminal includes: forming a first conductive plug on the first doped layer at a middle position of the first region, the first conductive plug connecting to the electrostatic output terminal.

[0031] Optionally, the method for connecting the third doped layer, the second gate structure, and the heavily doped region to the electrostatic input terminal includes: forming second conductive plugs on the third doped layer, the second gate structure, and the heavily doped region respectively, the second conductive plugs connecting to the electrostatic input terminal.

[0032] Optionally, the first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

[0033] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0034] In the structure of the technical solution of the present invention, through the first well region located in the first region, the first well region has a first doping ion; the second well region located in the second region, the second well region has a second doping ion, and the electrical type of the second doping ion is different from that of the first doping ion, so that a reverse-biased junction is formed at the junction of the first well region and the second well region. Since the first gate structure and the reverse-biased junction are connected in series through the first well region, the resistance value of the branch formed by the first gate structure and the reverse-biased junction increases. During the electrostatic discharge process, the branch formed by the first gate structure and the reverse-biased structure is equivalent to an open circuit state. Therefore, the risk of the first gate structure being broken down is reduced, thereby improving the performance of the finally formed semiconductor structure.

[0035] In addition, there are several first gate structures on the first region. Subsequently, a first conductive plug is formed between adjacent first gate structures, so that the distance between the first conductive plug and the second gate structure increases. At the same time, the current path of the first conductive plug is also changed, preventing the second gate structure from being discharged and broken down, and improving the protection ability of the device. At the same time, it is not necessary to additionally increase the size of the first doping layer in the direction parallel to the top surface of the substrate, effectively reducing the difficulty of the process.

[0036] In the forming method of the technical solution of the present invention, a first well region is formed in the first region, and the first well region has a first doping ion; a second well region is formed in the second region, and the second well region has a second doping ion. The electrical type of the second doping ion is different from that of the first doping ion, so that a reverse-biased junction is formed at the junction of the first well region and the second well region. Since the first gate structure and the reverse-biased junction are connected in series through the first well region, the resistance value of the branch formed by the first gate structure and the reverse-biased junction increases. During the electrostatic discharge process, the branch formed by the first gate structure and the reverse-biased structure is equivalent to an open circuit state. Therefore, the risk of the first gate structure being broken down is reduced, thereby improving the performance of the finally formed semiconductor structure.

[0037] In addition, several first gate structures are formed on the first region. Subsequently, a first conductive plug is formed on the first doping layer between adjacent first gate structures, so that the distance between the first conductive plug and the second gate structure increases. At the same time, the current path of the first conductive plug is also changed, preventing the second gate structure from being discharged and broken down, and improving the protection ability of the device. At the same time, it is not necessary to additionally increase the size of the first doping layer in the direction parallel to the top surface of the substrate, effectively reducing the difficulty of the process. Description of the Drawings

[0038] Figure 1 andFigure 2 It is a schematic structural diagram of a semiconductor structure;

[0039] Figures 3 to 14 It is a schematic structural diagram of each step in an embodiment of the method for forming the semiconductor structure of the present invention. Detailed implementation manners

[0040] As described in the background art, the performance of the electrostatic discharge protection structure formed by the prior art needs to be improved. The following will be specifically described with reference to the accompanying drawings.

[0041] Please refer to Figure 1 , a substrate 100 is provided; a first well region 101 is formed in the substrate 100, and the first well region 101 has first doping ions; a first gate structure 102 and a plurality of second gate structures 103 are formed on the substrate 100, and the first gate structure 102 is located between adjacent second gate structures 103; a first epitaxial doping layer 104 and a second epitaxial doping layer 105 are respectively formed in the substrate 100 on both sides of the second gate structure 103, the first epitaxial doping layer 104 and the second epitaxial doping layer 105 have second doping ions, the second doping ions are different from the first doping ions, and the first epitaxial doping layer 104 is also located on both sides of the first gate structure 103.

[0042] Please refer to Figure 2 , a doping region 106 is formed in the first well region 101, the doping region 106 has the first doping ions, and the concentration of the first doping ions in the doping region 106 is greater than the concentration of the first doping ions in the first well region 101; first conductive plugs 107 are respectively formed on the first epitaxial doping layer 104, and the first conductive plugs 107 are electrically connected; second conductive plugs 108 are formed on the doping region 106, the second gate structure 103 and the second epitaxial doping layer 105, and the second conductive plugs 108 are electrically connected.

[0043] In this embodiment, the first conductive plug 107 needs to be arranged at a position far from the second gate structure 103 to improve the protection ability of the device. However, when the interval dimension D1 between the first conductive plug 107 and the second gate structure 103 is large, the interval dimension D2 between the first conductive plug 107 and the first gate structure 102 is small. At this time, the first gate structure 102 is easily damaged by breakdown and becomes a weak point of the device, resulting in a reduction in the overall electrostatic tolerance of the finally formed semiconductor structure.

[0044] In this embodiment, the first epitaxial doped layer 104 has a first dimension L1 in a direction parallel to the top surface of the substrate 100, and the second epitaxial doped layer 105 has a second dimension L2 in a direction parallel to the top surface of the substrate 100. In order to further increase the distance between the first conductive plug 107 and the second gate structure 103, generally the first dimension L1 is greater than the second dimension L2. However, under the process conditions of the global process, forming the first epitaxial doped layer 104 and the second epitaxial doped layer 105 with different dimensions will make the process complex and difficult.

[0045] On this basis, the present invention provides an electrostatic discharge protection structure and a method for forming the same, forming an anti - bias junction at the junction of the first well region and the second well region. The first gate structure is connected in series with the anti - bias junction, so that the resistance value of the branch formed by the first gate structure and the anti - bias junction increases, reducing the risk of breakdown of the first gate structure. In addition, a plurality of the first gate structures are formed on the first region, and then a first conductive plug is formed on the first doped layer between adjacent first gate structures, so that the distance between the first conductive plug and the second gate structure is increased, and at the same time, the current path of the first conductive plug is also changed, preventing the second gate structure from being discharged and broken down. At the same time, it is not necessary to additionally increase the dimension of the first doped layer in a direction parallel to the top surface of the substrate, effectively reducing the difficulty of the process.

[0046] To make the above - mentioned objects, features and advantages of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given with reference to the accompanying drawings.

[0047] Figures 3 to 14 It is a schematic structural diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0048] Please refer to Figure 3 , a substrate is provided, and the substrate includes a first region I arranged along a first direction X and a plurality of second regions II, and the first region I is located between adjacent second regions II.

[0049] In this embodiment, the material of the substrate is single - crystal silicon; in other embodiments, the material of the substrate may also be single - crystal germanium, silicon germanium, silicon carbide, or may be silicon - on - insulator (SOI), germanium - on - insulator (GOI); or the substrate may also be other materials, such as III - V compounds such as gallium arsenide.

[0050] In this embodiment, the substrate includes: a substrate 200, a first fin 201 and a second fin 202 located on the substrate 200; in other embodiments, the substrate may also include: a substrate and fins located on the substrate.

[0051] In this embodiment, the method for forming the first fin portion 201 and the second fin portion 202 includes: providing an initial substrate (not shown); forming a third patterned layer (not shown) on the initial substrate, the third patterned layer exposing a top surface of a part of the initial substrate; etching the initial substrate using the third patterned layer as a mask to form a base 200 and the first fin portion 201 and the second fin portion 202 located on the base 200.

[0052] In other embodiments, an initial substrate is provided; a third patterned layer is formed on the initial substrate, the third patterned layer exposing a top surface of a part of the initial substrate; the initial substrate is etched using the third patterned layer as a mask to form a base and fins located on the base.

[0053] Please refer to Figure 4 , after forming the first fin portion 201 and the second fin portion 202, an isolation structure 203 is formed between the first fin portion 201 and the second fin portion 202.

[0054] In this embodiment, the material of the isolation structure 203 is silicon oxide; in other embodiments, the material of the isolation structure may also be silicon oxynitride.

[0055] In other embodiments, the method for forming the isolation structure may further include: etching a part of the fins to form isolation openings in the fins; forming the isolation structure in the isolation openings.

[0056] Please refer to Figure 5 , after forming the isolation structure 203, a first well region 204 is formed in the first region I, and the first well region 204 has first doping ions.

[0057] In this embodiment, the method for forming the first well region 204 includes: forming a first patterned layer (not shown) on the substrate, the first patterned layer exposing a top surface of the first region I; performing an implantation process of first doping ions on the first region I using the first patterned layer as a mask to form the first well region 204 in the first region I.

[0058] The first doping ions include N-type ions; the first doping ions include: phosphorus or arsenic. In this embodiment, the first doping ions are phosphorus.

[0059] In this embodiment, after forming the first well region 204, the first patterned layer is removed.

[0060] In this embodiment, the first well region 204 is located in the first fin portion 201.

[0061] In other embodiments, the first well region is within the fin portion.

[0062] Please refer to Figure 6 , a second well region 205 is formed within the second region II. The second well region 205 has second doping ions, and the electrical type of the second doping ions is different from that of the first doping ions.

[0063] In this embodiment, the method for forming the second well region 205 includes: forming a second patterned layer (not shown) on the substrate, where the second patterned layer exposes the top surface of the second region II; using the second patterned layer as a mask to perform an implantation process of second doping ions on the second region II, so as to form the second well region 205 within the second region II.

[0064] In this embodiment, after forming the second well region 205, the second patterned layer is removed.

[0065] The second doping ions include P-type ions; the second doping ions include: boron or indium. In this embodiment, the second doping ions are boron.

[0066] In other embodiments, the second well region may be formed first, and after forming the second well region, the first well region is formed.

[0067] In this embodiment, the second well region 205 is respectively within the first fin portion 201 and the second fin portion 202.

[0068] In other embodiments, the second well region is within the fin portion.

[0069] Please refer to Figure 7 , after forming the first well region 204 and the second well region 205, an isolation layer 218 is formed on the substrate. The isolation layer 218 covers part of the first fin portion 201 and the second fin portion 202, and the top surface of the isolation layer 218 is lower than the top surfaces of the first fin portion 201 and the second fin portion 202.

[0070] In this embodiment, the method for forming the isolation layer 218 includes: forming an initial isolation layer (not shown) on the substrate; etching away part of the initial isolation layer to form the isolation layer 218, and the top surface of the isolation layer 218 is lower than the top surfaces of the first fin portion 201 and the second fin portion 202.

[0071] The material of the isolation layer 218 is an insulating material, and the insulating material includes silicon oxide or silicon oxynitride; in this embodiment, the material of the isolation layer 218 is silicon oxide.

[0072] After forming the isolation layer 218, the process further includes: forming a plurality of first gate structures on the first region I; forming a second gate structure on the second region II; forming a first doped layer in the substrate between adjacent first gate structures, the first doped layer having the first doped ions and also located within the first well region; forming a second doped layer and a third doped layer in the substrate on both sides of the second gate structure respectively, the second doped layer and the third doped layer having the first doped ions and located within the second well region respectively, and the second doped layer also contacting the first well region. For the specific forming process, please refer to Figures 8 to 12 。

[0073] Please refer to Figure 8 , forming a plurality of first dummy gate structures 206 on the first region I; forming a second dummy gate structure 207 on the second region II.

[0074] In this embodiment, the method for forming the first dummy gate structure 206 includes: forming a first dummy gate dielectric layer on the isolation layer 218 and the first well region 204; forming a first dummy gate layer on the first dummy gate dielectric layer; forming a first sidewall (not labeled) on the sidewalls of the first dummy gate dielectric layer and the first dummy gate layer.

[0075] In this embodiment, the material of the first dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer can also be silicon oxynitride.

[0076] In this embodiment, the material of the first dummy gate layer is silicon.

[0077] In this embodiment, the method for forming the second dummy gate structure 207 includes: forming a second dummy gate dielectric layer on the isolation layer 218 and the second well region 205; forming a second dummy gate layer on the second dummy gate dielectric layer; forming a second sidewall (not labeled) on the sidewalls of the second dummy gate dielectric layer and the second dummy gate layer.

[0078] In this embodiment, the materials of the second dummy gate dielectric layer and the first dummy gate dielectric layer are the same, and the materials of the second dummy gate layer and the first dummy gate layer are also the same.

[0079] In this embodiment, the first dummy gate structure 206 and the second dummy gate structure 207 are formed simultaneously, which can effectively improve the production efficiency.

[0080] Please refer to Figure 9, a first doped layer 208, a second doped layer 209, and a third doped layer 219 are formed in the substrate. The first doped layer 208, the second doped layer 209, and the third doped layer 219 respectively have first doped ions. The first doped layer is also located within the first well region, and the second doped layer 209 and the third doped layer 219 are respectively located within the second well region. Moreover, the second doped layer 209 is also in contact with the first well region I.

[0081] In this embodiment, the method of forming the first doped layer 208, the second doped layer 209, and the third doped layer 219 in the substrate includes: etching the first fin 201 using the first dummy gate structure 206 and the second dummy gate structure 207 as masks to form a first doping opening, a second doping opening, and a third doping opening (not labeled) in the first fin 201; forming the first doped layer 208 in the first doping opening; forming the second doped layer 209 in the second doping opening; and forming the third doped layer 219 in the third doping opening.

[0082] In this embodiment, the method of forming the first doped layer 208, the second doped layer 209, and the third doped layer 219 includes: forming a first epitaxial layer in the first doping opening, a second epitaxial layer in the second doping opening, and a third epitaxial layer (not shown) in the third doping opening by using an epitaxial growth process; performing in-situ doping on the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer during the epitaxial growth process, and doping the first doped ions into the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer to form the first doped layer 208, the second doped layer 209, and the third doped layer 219.

[0083] In other embodiments, the first doped layer, the second doped layer, and the third doped layer 219 can also be formed by using a first doped ion implantation process.

[0084] In this embodiment, the first doped layer 208, the second doped layer 209, and the third doped layer 219 are located within the first fin 201.

[0085] In other embodiments, the first doped layer, the second doped layer, and the third doped layer 219 are located within the fin.

[0086] Please refer to Figure 10 , after forming the first doped layer 208, the second doped layer 209, and the third doped layer 219, a dielectric layer 210 is formed on the substrate, and the dielectric layer 210 covers the sidewalls of the first dummy gate structure 206 and the second dummy gate structure 207.

[0087] In this embodiment, the material of the dielectric layer 210 is silicon oxide; in other embodiments, the material of the dielectric layer may also be a low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative dielectric constant lower than 2.5).

[0088] Please refer to Figure 11 , after forming the dielectric layer 210, remove the first dummy gate structure 206, and form a first opening 211 in the dielectric layer 210, where the first opening 211 is located on the first region I; remove the second dummy gate structure 207, and form a second opening 212 in the dielectric layer 210, where the second opening 212 is located on the second region II.

[0089] In this embodiment, specifically remove the first dummy gate dielectric layer and the first dummy gate layer of the first dummy gate structure 206; remove the second dummy gate dielectric layer and the second dummy gate layer of the second dummy gate structure 207.

[0090] Please refer to Figure 12 , form the first gate structure 213 in the first opening 211; form the second gate structure 214 in the second opening 212.

[0091] In this embodiment, the first gate structure 213 includes: a first gate dielectric layer and a first gate layer (not labeled) located on the first gate dielectric layer.

[0092] In this embodiment, the second gate structure 214 includes: a second gate dielectric layer and a second gate layer (not labeled) located on the second gate dielectric layer.

[0093] In this embodiment, by forming a first well region 204 in the first region I, the first well region 204 has first doping ions; form a second well region 205 in the second region II, the second well region 205 has second doping ions, and the second doping ions have a different conduction type from the first doping ions, so that a reverse-biased junction is formed at the junction of the first well region 204 and the second well region 205. Since the first gate structure 213 is connected in series with the reverse-biased junction through the first well region 204, the resistance value of the branch formed by the first gate structure 213 and the reverse-biased junction increases. During the electrostatic discharge process, the branch formed by the first gate structure 213 and the reverse-biased structure is equivalent to an open circuit state. Therefore, the risk of the first gate structure 213 being broken down is reduced, thereby improving the performance of the finally formed semiconductor structure.

[0094] Please refer to Figure 13, a heavily doped region 215 is formed in the second well region 205. The isolation structure 203 is located between the heavily doped region 215 and the third doped layer 219. The heavily doped region 215 contains a third doping ion, the third doping ion has the same electrical type as the second doping ion, and the concentration of the third doping ion in the heavily doped region 215 is greater than the concentration of the second doping ion in the second well region 205.

[0095] In this embodiment, the purpose of forming the heavily doped region 215 with high-concentration doping in the second well region 205 is to reduce the contact resistance between the subsequently formed second conductive plug and the second well region 205 by using the heavily doped region 215 with high-concentration doping.

[0096] Please refer to Figure 14 , after forming the heavily doped region 215, connect the first doped layer 208 to the electrostatic output terminal; connect the third doped layer 219, the second gate structure 214, and the heavily doped region 215 to the electrostatic input terminal.

[0097] In this embodiment, the method of connecting the first doped layer 208 to the electrostatic output terminal includes: forming a first conductive plug 216 on the first doped layer 208 at the middle position of the first region I, and the first conductive plug 216 is connected to the electrostatic output terminal.

[0098] It should be noted that in this embodiment, since the number of the first gate structures 213 is two and only one first doped layer 208 is formed, the first conductive plug 216 can only be located on this one first doped layer 208; when the number of the first gate structures 213 is greater than two, the number of the corresponding first doped layers 208 formed is also more than one. At this time, the middle position means that the midline position of the first doped layer 208 has a first spacing dimension s1 from one boundary line of the first region I along the first direction X, and the midline position of the first doped layer 208 has a second spacing dimension s2 from the other opposite boundary line of the first region I along the first direction X, and the second spacing dimension s1 is equal to the first spacing dimension s2.

[0099] In this embodiment, since a plurality of the first gate structures 213 are formed on the first region I, and the first conductive plugs 216 are formed on the first doping layer 208 between adjacent first gate structures 213, the distance between the first conductive plugs 216 and the second gate structure 214 is increased. At the same time, the current path of the first conductive plugs 216 is also changed, preventing the second gate structure 214 from being discharged and broken down, and improving the protection ability of the device. Meanwhile, it is not necessary to additionally increase the size of the first doping layer 208 in the direction parallel to the top surface of the substrate, effectively reducing the difficulty of the process.

[0100] In this embodiment, the method of connecting the third doping layer 219, the second gate structure 214, and the heavily doped region 215 to the electrostatic input terminal includes: forming second conductive plugs 217 on the third doping layer 219, the second gate structure 214, and the heavily doped region 215 respectively, and the second conductive plugs 217 are connected to the electrostatic input terminal.

[0101] In this embodiment, the materials of the first conductive plugs 216 and the second conductive plugs 217 are copper.

[0102] Correspondingly, the present invention also provides an electrostatic discharge protection structure. Please continue to refer to Figure 14 which includes: a substrate, the substrate includes a first region I and a plurality of second regions II arranged along the first direction X, and the first region I is located between adjacent second regions II; a first well region 204 located in the first region I, and the first well region 204 has first doping ions; a second well region 205 located in the second region II, and the second well region 205 has second doping ions, and the conductivity type of the second doping ions is different from that of the first doping ions; a plurality of first gate structures 213 located on the first region I; a second gate structure 214 located on the second region II; a first doping layer 208 in the substrate between adjacent first gate structures 213, and the first doping layer 208 has the first doping ions, and the first doping layer 208 is also located in the first well region I; a second doping layer 209 and a third doping layer 219 in the substrate on both sides of the second gate structure 214 respectively, and the second doping layer 209 and the third doping layer 219 have the first doping ions, and the second doping layer 209 and the third doping layer 219 are respectively located in the second well region II, and the second doping layer 209 is also in contact with the first well region I.

[0103] In this embodiment, through the first well region 204 located in the first region I, the first well region 204 has first doping ions; the second well region 205 located in the second region II, the second well region 205 has second doping ions, and the electrical types of the second doping ions and the first doping ions are different, so that a reverse-biased junction is formed at the junction of the first well region 204 and the second well region 205. Since the first gate structure 213 and the reverse-biased junction are connected in series through the first well region 204, the resistance value of the branch formed by the first gate structure 213 and the reverse-biased junction increases. During the electrostatic discharge process, the branch formed by the first gate structure 213 and the reverse-biased structure is equivalent to an open circuit state. Therefore, the risk of the first gate structure 213 being broken down is reduced, thereby improving the performance of the finally formed semiconductor structure.

[0104] The first doping ions include N-type ions; the first doping ions include: phosphorus or arsenic. In this embodiment, the first doping ions are phosphorus.

[0105] The second doping ions include P-type ions; the second doping ions include: boron or indium. In this embodiment, the second doping ions are boron.

[0106] In this embodiment, the substrate includes: a substrate 200, and a first fin 201 and a second fin 202 located on the substrate 200. The first well region 204 and the second well region 205 are located in the first fin 201, and the first doping layer 208 and the second doping layer 209 are located in the first fin 201. The second well region 205 is located in the second fin 202.

[0107] In other embodiments, the substrate includes: a substrate and fins located on the substrate. The first well region and the second well region are located in the fins, and the first doping layer and the second doping layer are located in the fins.

[0108] In this embodiment, it further includes: an isolation structure 203 located between the first fin 201 and the second fin 202.

[0109] In other embodiments, it further includes: an isolation structure located in the fins.

[0110] In this embodiment, it further includes: a heavily doped region 215 formed within the second well region 205, the isolation structure 203 being located between the heavily doped region 215 and the third doped layer 219. The heavily doped region 215 has third doping ions, the third doping ions having the same electrical type as the second doping ions, and the concentration of the third doping ions in the heavily doped region 215 being greater than the concentration of the second doping ions in the second well region 205.

[0111] In this embodiment, the first doped layer 208 is connected to the electrostatic output terminal; the third doped layer 219, the second gate structure 214, and the heavily doped region 215 are connected to the electrostatic input terminal.

[0112] In this embodiment, it further includes: a first conductive plug 216 on the first doped layer 208 at the middle position of the first region I, the first conductive plug 216 being connected to the electrostatic output terminal; second conductive plugs 217 respectively on the third doped layer 219, the second gate structure 214, and the heavily doped region 215, the second conductive plugs 217 being connected to the electrostatic input terminal.

[0113] In this embodiment, since there are a plurality of the first gate structures 213 on the first region I, the first conductive plug 216 is formed between adjacent first gate structures 213, increasing the distance between the first conductive plug 216 and the second gate structure 214. At the same time, it also changes the current path of the first conductive plug 216, preventing the second gate structure 214 from being discharged and broken down, and improving the protection ability of the device. At the same time, it is not necessary to additionally increase the size of the first doped layer 208 in the direction parallel to the top surface of the substrate, effectively reducing the difficulty of the process.

[0114] In this embodiment, the first gate structure 213 includes a first gate dielectric layer and a first gate layer (not labeled) on the first gate dielectric layer.

[0115] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. An electrostatic discharge protection structure, characterized in that, Comprising: A substrate, the substrate comprising a first region and a plurality of second regions arranged in a first direction, the first region being located between adjacent second regions; A first well region located in the first region, the first well region having first doping ions; A second well region located in the second region, the second well region having second doping ions, the second doping ions having a different conductivity type from the first doping ions; A plurality of first gate structures located on the first region; A second gate structure located on the second region; A first doping layer in the substrate between adjacent first gate structures, the first doping layer having the first doping ions, and the first doping layer also being located in the first well region; A second doping layer and a third doping layer in the substrate on both sides of the second gate structure respectively, the second doping layer and the third doping layer having the first doping ions, the second doping layer and the third doping layer being located in the second well region respectively, and the second doping layer also being in contact with the first well region.

2. The electrostatic discharge protection structure according to claim 1, wherein, The first doping ions include N-type ions; the first doping ions include: phosphorus or arsenic.

3. The electrostatic discharge protection structure according to claim 1, wherein, The second doping ions include P-type ions; The second doping ions include: boron or indium.

4. The electrostatic discharge protection structure according to claim 1, wherein The substrate includes: a substrate and fins located on the substrate, the fins having the first well region and the second well region, and the first doping layer, the second doping layer and the third doping layer being located in the fins.

5. The electrostatic discharge protection structure according to claim 4, wherein Further comprising: An isolation structure located in the fins.

6. The electrostatic discharge protection structure according to claim 1, wherein The substrate includes: a substrate and a first fin and a second fin located on the substrate, the first fin having the first well region and the second well region, and the first doping layer, the second doping layer and the third doping layer being located in the first fin, and the second fin having the second well region.

7. The electrostatic discharge protection structure according to claim 6, wherein Further comprising: An isolation structure located between the first fin and the second fin.

8. The electrostatic discharge protection structure according to claim 5 or 7, wherein Further comprising: A heavily doped region is formed in the second well region, the isolation structure is located between the heavily doped region and the third doping layer, the heavily doped region has third doping ions, the third doping ions have the same electrical type as the second doping ions, and the concentration of the third doping ions in the heavily doped region is greater than the concentration of the second doping ions in the second well region.

9. The electrostatic discharge protection structure according to claim 8, wherein, The first doping layer is connected to an electrostatic output terminal; the third doping layer, the second gate structure and the heavily doped region are connected to an electrostatic input terminal.

10. The electrostatic discharge protection structure according to claim 9, wherein, Further comprising: A first conductive plug on the first doping layer at the middle position of the first region, the first conductive plug being connected to the electrostatic output terminal; Second conductive plugs on the third doping layer, the second gate structure and the heavily doped region respectively, the second conductive plugs being connected to the electrostatic input terminal.

11. The electrostatic discharge protection structure according to claim 1, wherein, The first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

12. A method for forming an electrostatic discharge protection structure, characterized in that Comprising: Providing a substrate, the substrate comprising a first region and a plurality of second regions arranged in a first direction, the first region being located between adjacent second regions; Forming a first well region in the first region, the first well region having first doping ions; A second well region is formed in the second region, and the second well region has second doping ions, and the electrical type of the second doping ions is different from that of the first doping ions; A plurality of first gate structures are formed on the first region; A second gate structure is formed on the second region; A first doping layer is formed in the substrate between adjacent first gate structures, and the first doping layer has the first doping ions, and the first doping layer is also located in the first well region; A second doping layer and a third doping layer are respectively formed in the substrate on both sides of the second gate structure, and the second doping layer and the third doping layer have the first doping ions, and the second doping layer and the third doping layer are respectively located in the second well region, and the second doping layer is also in contact with the first well region.

13. The method for forming the electrostatic discharge protection structure according to claim 12, wherein, The forming method of the first well region and the second well region includes: forming a first patterned layer on the substrate, and the first patterned layer exposes the top surface of the first region; using the first patterned layer as a mask, performing an implantation process of the first doping ions on the first region to form the first well region in the first region; after forming the first well region, removing the first patterned layer; forming a second patterned layer on the substrate, and the second patterned layer exposes the top surface of the second region; using the second patterned layer as a mask, performing an implantation process of the second doping ions on the second region to form the second well region in the second region.

14. The method for forming the electrostatic discharge protection structure according to claim 12, wherein The first doping ions include N-type ions; the first doping ions include: phosphorus or arsenic.

15. The method for forming the electrostatic discharge protection structure according to claim 12, wherein, The second doping ions include P-type ions; The second doping ions include: boron or indium.

16. The method for forming the electrostatic discharge protection structure according to claim 12, wherein, The substrate includes: a substrate and fins located on the substrate, and the first well region and the second well region are in the fins, and the first doping layer, the second doping layer and the third doping layer are located in the fins.

17. The method for forming the electrostatic discharge protection structure according to claim 16, wherein, It further includes: Forming an isolation structure, and the isolation structure is located in the fins.

18. The method for forming the electrostatic discharge protection structure according to claim 12, wherein The substrate includes: a substrate and a first fin and a second fin located on the substrate, and the first well region and the second well region are in the first fin, and the first doping layer, the second doping layer and the third doping layer are located in the first fin, and the second well region is in the second fin.

19. The method for forming the electrostatic discharge protection structure according to claim 18, wherein, It further includes: Forming an isolation structure, and the isolation structure is located between the first fin and the second fin.

20. The method for forming the electrostatic discharge protection structure according to claim 17, wherein, The forming method of the fins and the isolation structure includes: providing an initial substrate; forming a third patterned layer on the initial substrate, and the third patterned layer exposes the top surface of a part of the initial substrate; etching the initial substrate using the third patterned layer as a mask to form a substrate and fins located on the substrate; etching a part of the fins to form isolation openings in the fins; forming the isolation structure in the isolation openings.

21. The method for forming the electrostatic discharge protection structure according to claim 19, wherein, The forming method of the first fin portion, the second fin portion and the isolation structure includes: providing an initial substrate; forming a third patterned layer on the initial substrate, the third patterned layer exposing a top surface of a part of the initial substrate; etching the initial substrate using the third patterned layer as a mask to form a base and a first fin portion and a second fin portion located on the base, with an isolation opening between the first fin portion and the second fin portion; forming the isolation structure in the isolation opening.

22. The method for forming the electrostatic discharge protection structure according to claim 17 or 19, wherein After forming the isolation structure, it further includes: forming a heavily doped region in the second well region, the isolation structure being located between the heavily doped region and the third doped layer, the heavily doped region having a third doping ion, the third doping ion having the same electrical type as the second doping ion, and the concentration of the third doping ion in the heavily doped region being greater than the concentration of the second doping ion in the second well region.

23. The method for forming the electrostatic discharge protection structure according to claim 22, wherein, After forming the heavily doped region, it further includes: connecting the first doped layer to an electrostatic output terminal; connecting the third doped layer, the second gate structure and the heavily doped region to an electrostatic input terminal.

24. The method for forming the electrostatic discharge protection structure according to claim 23, wherein The method of connecting the first doped layer to the electrostatic output terminal includes: forming a first conductive plug on the first doped layer at a middle position of the first region, the first conductive plug connecting the electrostatic output terminal.

25. The method for forming the electrostatic discharge protection structure according to claim 23, wherein, The method of connecting the third doped layer, the second gate structure and the heavily doped region to the electrostatic input terminal includes: forming second conductive plugs on the third doped layer, the second gate structure and the heavily doped region respectively, the second conductive plugs connecting the electrostatic input terminal.

26. The method for forming the electrostatic discharge protection structure according to claim 12, wherein, The first gate structure includes a first gate dielectric layer and a first gate layer located on the first gate dielectric layer.

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