An optimized TVS structure device

Abstract

The present invention discloses an optimized TVS structure device. The P-base region of the N-type semiconductor substrate forms a base region with three-layer superposed diffusion. The P1 base region of the P-base region forms a target voltage with the N-type semiconductor substrate. The P2 base region and the P3 base region of the P-base region form a voltage modulation region by diffusing two layers on the P1 base region. By arranging the P-base region with three-layer superposed diffusion on the N-type semiconductor substrate, after the P1 base region forms a target voltage with the N-type semiconductor substrate, through two high-concentration impurity dopings, that is, the two-layer diffusion of the P2 base region and the P3 base region, the P-base region as a whole has a higher impurity concentration gradient. When the PN junction undergoes avalanche breakdown, the high-concentration carriers in the regions of the P2 base region and the P3 base region will quickly drift to the space charge region of the PN junction and participate in the avalanche effect, improving the expansion speed of the avalanche breakdown area of the PN junction, effectively enabling the PN junction to enter the complete avalanche breakdown state in a shorter time, and thus discharging surge energy more quickly.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor chip design and manufacturing, and particularly to an optimized TVS structure device. Background Art

[0002] TVS (Transient Voltage Suppressor) tube is a new product developed on the basis of the zener diode process. When the two ends of the TVS tube are subjected to an instantaneous high-energy impact, it can reduce its impedance suddenly at an extremely high speed, and at the same time absorb a large current, clamping the voltage between its two ends at a predetermined value, so as to ensure that the subsequent circuit elements are not damaged by the transient high-energy impact. Due to its advantages of fast response time, high transient power, low capacitance, low leakage current, small breakdown voltage deviation, easy control of the clamping voltage, small volume, and easy installation, the TVS tube has been widely used in various fields such as computer systems, communication equipment, consumer electronics, power supplies, and household appliances. With the diversification of the application scenarios of IC chips, various spike pulses have continuously damaged the chips. The existing TVS devices have poor protection effects on some high di / dt destructive pulses, and there is an urgent need to upgrade the response speed of the current traditional TVS devices. Summary of the Invention

[0003] The purpose of the present invention is to provide an optimized TVS structure device. After the P1 base region forms a target voltage with the N-type semiconductor substrate, through two high-concentration impurity dopings, that is, two-layer diffusions of the P2 base region and the P3 base region, the overall P base region has a higher impurity concentration gradient. When the PN junction undergoes avalanche breakdown, the high-concentration carriers in the regions of the P2 base region and the P3 base region will quickly drift to the space charge region of the PN junction and participate in the avalanche effect, greatly improving the expansion speed of the avalanche breakdown area of the PN junction.

[0004] The technical problem to be solved by the present invention is:

[0005] How to improve the expansion speed of the breakdown region when the PN junction undergoes avalanche breakdown, so that the device has stronger current-carrying capacity under high di / dt conditions.

[0006] The purpose of the present invention can be achieved by the following technical solutions:

[0007] An optimized TVS structure device includes an N-type semiconductor substrate. The P base region of the N-type semiconductor substrate forms a base region with three-layer superimposed diffusion. The P1 base region of the P base region forms a target voltage with the N-type semiconductor substrate, and the P2 base region and the P3 base region of the P base region form a voltage modulation region through two-layer diffusion on the P1 base region.

[0008] As a further solution of the present invention: Metal layers are provided on the upper and lower surfaces of the N-type semiconductor substrate.

[0009] As a further solution of the present invention: the metal layer is a multi-layer metal stacked structure.

[0010] As a further solution of the present invention: masking layers are provided on both sides of the P-base region on the N-type semiconductor substrate.

[0011] As a further solution of the present invention: a manufacturing method of an optimized TVS structure device includes the following steps:

[0012] Step 1: Wafer preparation

[0013] Select an MCZ silicon single crystal wafer, 5-inch crystal orientation <111>, N-type, resistivity 0.03 - 0.04 Ω / cm, thickness 220 μm ± 10%;

[0014] Step 2: Primary oxidation

[0015] Fabricate a field oxide masking layer under the conditions of furnace temperature 1100 °C, oxygen 4 L / min, and hydrogen 5 L / min, with an oxide layer thickness of 1.5 μm ± 10%;

[0016] Step 3: Preparation of the P1 base region

[0017] Perform boron source deposition under the conditions of furnace temperature 1050 °C, oxygen 2 L / min, and nitrogen 3 L / min for a deposition time of 40 min. Perform boron source drive under the conditions of furnace temperature 1260 °C, oxygen 2 L / min, and nitrogen 3 L / min for a drive time of 1500 min, and use a four-probe to measure the diffusion sheet resistance of 22 Ω ± 10% and the junction depth of 25 μm ± 10%;

[0018] Step 4: Preparation of the P2 base region

[0019] Perform boron source deposition under the conditions of furnace temperature 1080 °C, oxygen 2 L / min, and nitrogen 3 L / min for a deposition time of 45 min; perform boron source drive under the conditions of furnace temperature 1240 °C, oxygen 2 L / min, and nitrogen 4 L / min for a drive time of 520 min, and use a four-probe to measure the diffusion sheet resistance of 12 Ω ± 10% and the junction depth of 17 μm ± 10%;

[0020] Step 5: Preparation of the P3 base region

[0021] Perform boron source deposition under the conditions of furnace temperature 1130 °C, oxygen 2 L / min, and nitrogen 3 L / min for a deposition time of 70 min; perform boron source drive under the conditions of furnace temperature 1250 °C, oxygen 2 L / min, and nitrogen 4 L / min for a drive time of 300 min, and use a four-probe to measure the diffusion sheet resistance of 5.5 Ω ± 10% and the junction depth of 11 μm ± 10%;

[0022] Step 6: Metal layer

[0023] Deposit the metal layer through the electron beam metallization evaporation platform process.

[0024] As a further solution of the present invention: For the preparation of the P1 base region, P2 base region, and P3 base region in Step 3, Step 4, and Step 5, the oxide layer on the wafer surface needs to be first rinsed clean, a spin-coated dopant is used as the diffusion source, and then boron pre-deposition diffusion doping is carried out.

[0025] As a further solution of the present invention: The metal layer consists of a contact layer and the first layer, a total of four layers, which are 1.5 μm of aluminum, 0.3 μm of titanium, 0.7 μm of nickel, and 1.5 μm of silver in sequence.

[0026] Advantages of the present invention:

[0027] In the present invention, by setting P base regions with three superimposed diffusions on the N-type semiconductor substrate, after the P1 base region forms the target voltage with the N-type semiconductor substrate, through two high-concentration impurity dopings, that is, two-layer diffusions of the P2 base region and the P3 base region, the P base region as a whole has a higher impurity concentration gradient. When the PN junction undergoes avalanche breakdown, the high-concentration carriers in the regions of the P2 base region and the P3 base region will quickly drift to the space charge region of the PN junction and participate in the avalanche effect, greatly increasing the expansion speed of the avalanche breakdown area of the PN junction, and effectively enabling the PN junction to enter the complete avalanche breakdown state in a shorter time, thereby discharging the surge energy more quickly. Brief description of the drawings

[0028] The present invention will be further described below in conjunction with the drawings.

[0029] Figure 1 is the front view of the present invention;

[0030] Figure 2 is the structural schematic diagram of the P1 base region in the present invention;

[0031] Figure 3 is the structural schematic diagram of the P2 base region in the present invention;

[0032] Figure 4 is the structural schematic diagram of the P3 base region in the present invention.

[0033] In the figure: 1, N-type semiconductor substrate; 2, P1 base region; 3, P2 base region; 4, P3 base region; 5, metal layer; 6, mask layer. Detailed implementation manners

[0034] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0035] Embodiment 1

[0036] Please refer to Figures 1 - 4 As shown, the present invention is an optimized TVS structure device, including an N-type semiconductor substrate 1. The P-base region of the N-type semiconductor substrate 1 forms a base region with three-layer superimposed diffusion. The P1 base region 2 of the P-base region forms a target voltage with the N-type semiconductor substrate 1. The P2 base region 3 and the P3 base region 4 of the P-base region are diffused in two layers on the P1 base region 2 to form a voltage modulation region.

[0037] During use, after the P1 base region 2 forms a target voltage with the N-type semiconductor substrate 1, through two high-concentration impurity dopings, that is, the two-layer diffusion of the P2 base region 3 and the P3 base region 4, the P-base region as a whole has a higher impurity concentration gradient. When the PN junction undergoes avalanche breakdown, the high-concentration carriers in the regions of the P2 base region 3 and the P3 base region 4 will quickly drift to the space charge region of the PN junction and participate in the avalanche effect, greatly increasing the expansion speed of the avalanche breakdown area of the PN junction, and effectively enabling the PN junction to enter the complete avalanche breakdown state in a shorter time, thereby discharging surge energy more quickly.

[0038] Specifically, taking the SMCJ series TVS of the 1500W version as an example, the original version of the chip needs to use a package with a size of 6.2*8.1*2.6mm. After optimization with this embodiment, under the condition of achieving the same performance as the original version, only a package with a size of 3.9*5.6*2.6mm needs to be used, and the volume of the finished product is only 43.5% of the original, greatly optimizing the overall machine layout space;

[0039] The solution of the present invention can also greatly improve the protection level without changing the layout of the overall machine design, so as to adapt to a wider application environment. Taking the ITU-T standard as an example, since its enhanced level includes two test levels of 4000V and 6000V, and two sets of protection layouts are required for the overall machine. After adopting the solution of the present invention, the same overall machine PCB layout can be compatible with the space requirements of these two protection levels, greatly simplifying the overall machine design, so that a set of layout design solutions can cover the two application standard environments of the enhanced level.

[0040] Refer to Figure 1, metal layers 5 are provided on the upper and lower surfaces of the N-type semiconductor substrate 1. The metal layer 5 is a multi-layer metal stack structure. The metal layer 5 consists of a contact layer, a total of four layers, which are 1.5 μm of aluminum, 0.3 μm of titanium, 0.7 μm of nickel, and 1.5 μm of silver in sequence, improving the durability and protection performance of the TVS structure device.

[0041] Among them, masking layers 6 are provided on both sides of the P-base region on the N-type semiconductor substrate 1 to protect the P-base region through the masking layers 6.

[0042] A manufacturing method for an optimized TVS structure device includes the following steps:

[0043] Step 1: Wafer preparation

[0044] Select an MCZ silicon single crystal wafer, 5 inches, crystal orientation <111>, N-type, resistivity 0.03 - 0.04 Ω / cm, thickness 220 μm ± 10%;

[0045] Step 2: Primary oxidation

[0046] Fabricate a field oxide masking layer under the working conditions of a furnace temperature of 1100 °C, oxygen of 4 L / min, and hydrogen of 5 L / min, with an oxide layer thickness of 1.5 μm ± 10%;

[0047] Step 3: Preparation of the P1 base region

[0048] Perform boron source deposition under the working conditions of a furnace temperature of 1050 °C, oxygen of 2 L / min, and nitrogen of 3 L / min for a deposition time of 40 min. Perform boron source push under the working conditions of a furnace temperature of 1260 °C, oxygen of 2 L / min, and nitrogen of 3 L / min for a push time of 1500 min, and use a four-probe to test the diffusion sheet resistance of 22 Ω ± 10% and the junction depth of 25 μm ± 10%;

[0049] Step 4: Preparation of the P2 base region

[0050] Perform boron source deposition under the working conditions of a furnace temperature of 1080 °C, oxygen of 2 L / min, and nitrogen of 3 L / min for a deposition time of 45 min; perform boron source push under the working conditions of a furnace temperature of 1240 °C, oxygen of 2 L / min, and nitrogen of 4 L / min for a push time of 520 min, and use a four-probe to test the diffusion sheet resistance of 12 Ω ± 10% and the junction depth of 17 μm ± 10%;

[0051] Step 5: Preparation of the P3 base region

[0052] Boron source deposition is carried out under the conditions of furnace temperature of 1130 °C, oxygen of 2 L / min, and nitrogen of 3 L / min, and the deposition time is 70 min; boron source push is carried out under the conditions of furnace temperature of 1250 °C, oxygen of 2 L / min, and nitrogen of 4 L / min, and the push time is 300 min. The diffusion sheet resistance is measured by four-probe to be 5.5 Ω ± 10%, and the junction depth is 11 μm ± 10%.

[0053] Step Six: Metallization layer

[0054] The metallization layer is deposited by electron beam metallization evaporation platform process.

[0055] As a further solution of the present invention: for the preparation of the P1 base region, P2 base region and P3 base region in Step Three, Step Four and Step Five, the oxide layer on the wafer surface needs to be cleaned first, spin-coated dopant is used as the diffusion source, and then boron pre-deposition diffusion doping is carried out.

[0056] The TVS structure devices manufactured by this method are tested. Five groups of TVS structure devices are selected for testing, and the test structures are shown in the following table:

[0057]

[0058] It can be seen from the table that on the basis of ensuring the functions and parameters of the original product, the peak value of the current-carrying capacity of this solution is increased by about 10%, and the TVS structure device has stronger current-carrying capacity under high di / dt conditions.

[0059] Example 2

[0060] The manufacturing method of this example is exactly the same as that of Example 1, except that the N-type semiconductor substrate 1 is replaced by a P-type semiconductor substrate, and the impurity types are opposite.

[0061] In summary, both Example 1 and Example 2 are based on the two theoretical models of "strong electric field effect" and "linear graded junction". Since the conventional TVS device forms a PN junction through a single impurity diffusion to reach the designed breakdown voltage, and then forms a diode to achieve the clamping protection function. Usually, the high-temperature and long-time thermal diffusion conforms to the "linear graded junction" model, and the impurity layer concentration formed by diffusion is continuously and gradually distributed. In the avalanche breakdown process formed by the strong electric field effect, it is necessary to rely on the doped impurities to affect the speed of avalanche breakdown. The higher the impurity concentration, the easier the avalanche phenomenon occurs, but the impurity concentration will also affect the designed breakdown voltage.

[0062] The present invention designs triple-doping diffusion with the doping concentration increasing layer by layer. Among them, the longitudinal structure P1 base region is the first doping region with a relatively low diffusion doping concentration to meet the designed breakdown voltage value. The diffusion boundaries of the subsequent two diffusions, the P2 base region and the P3 base region, are smaller than the first diffusion region, so the breakdown voltage value is not affected, but the doping concentration gradient of the entire doping region is increased, and the number of doped impurities is increased. According to the "strong electric field effect" model, the carrier density at the time of avalanche breakdown is increased, so that the PN junction reaching the designed breakdown voltage value can enter the avalanche breakdown state at a faster speed, thereby reducing the local maximum current density and enhancing the surge resistance of the device.

[0063] Combining Embodiment 1 and Embodiment 2, both take the planar structure PN junction as an example. The mesa structure PN junction is consistent with the key points of the present invention and will not be separately exemplified. Therefore, the structure of the present invention is also protected in mesa-type TVSs.

[0064] The above has described in detail one embodiment of the present invention, but the content described is only the preferred embodiment of the present invention and cannot be considered as limiting the scope of implementation of the present invention. All equivalent changes and improvements made according to the scope of the present invention application should still fall within the patent coverage scope of the present invention.

Claims

1. An optimized TVS structure device, including an N-type semiconductor substrate (1), characterized in that, The P-base region of the N-type semiconductor substrate (1) forms a base region with three-layer superposed diffusion. The P1 base region (2) of the P-base region and the N-type semiconductor substrate (1) form a target voltage. The P2 base region (3) and P3 base region (4) of the P-base region are diffused in two layers on the P1 base region (2) to form a voltage modulation region; Metal layers (5) are provided on the upper and lower surfaces of the N-type semiconductor substrate (1); Masking layers (6) are provided on both sides of the N-type semiconductor substrate (1) and located in the P-base region; The optimized TVS structure device is manufactured through the following steps: Step 1: Wafer preparation Select an MCZ silicon single crystal wafer, 5-inch crystal orientation <111>, N-type, resistivity 0.03 - 0.04 Ω / cm, thickness 220 μm ± 10%; Step 2: Primary oxidation Under the working conditions of a furnace temperature of 1100 °C, oxygen of 4 L / min, and hydrogen of 5 L / min, a field oxide masking layer is fabricated, and the thickness of the oxide layer is 1.5 μm ± 10%; Step 3: Preparation of the P1 base region Under the working conditions of a furnace temperature of 1050 °C, oxygen of 2 L / min, and nitrogen of 3 L / min, boron source deposition is carried out for a deposition time of 40 min. Under the working conditions of a furnace temperature of 1260 °C, oxygen of 2 L / min, and nitrogen of 3 L / min, boron source drive-in is carried out for a drive-in time of 1500 min, and the sheet resistance of the diffusion is measured using a four-probe to be 22 Ω ± 10%, and the junction depth is 25 μm ± 10%; Step 4: Preparation of the P2 base region Under the working conditions of a furnace temperature of 1080 °C, oxygen of 2 L / min, and nitrogen of 3 L / min, boron source deposition is carried out for a deposition time of 45 min; Under the working conditions of a furnace temperature of 1240 °C, oxygen of 2 L / min, and nitrogen of 4 L / min, boron source drive-in is carried out for a drive-in time of 520 min, and the sheet resistance of the diffusion is measured using a four-probe to be 12 Ω ± 10%, and the junction depth is 17 μm ± 10%; Step 5: Preparation of the P3 base region Under the working conditions of a furnace temperature of 1130 °C, oxygen of 2 L / min, and nitrogen of 3 L / min, boron source deposition is carried out for a deposition time of 70 min. Under the working conditions of a furnace temperature of 1250 °C, oxygen of 2 L / min, and nitrogen of 4 L / min, boron source drive-in is carried out for a drive-in time of 300 min, and the sheet resistance of the diffusion is measured using a four-probe to be 5.5 Ω ± 10%, and the junction depth is 11 μm ± 10%; Step 6: Metallization layer The metallization layer is deposited through an electron beam metal evaporation platform process.

2. An optimized TVS structure device according to claim 1, characterized in that, The metal layer (5) is a multi-layer metal superposed structure.

3. An optimized TVS structure device according to claim 1, characterized in that The metal layer (5) consists of a contact layer and three other layers, a total of four layers, which are 1.5 μm of aluminum, 0.3 μm of titanium, 0.7 μm of nickel, and 1.5 μm of silver in sequence.

4. An optimized TVS structure device according to claim 1, characterized in that, In the preparation of the P1 base region, P2 base region, and P3 base region in Step 3, Step 4, and Step 5, the oxide layer on the wafer surface needs to be cleaned first, and a spin-coated dopant is used as the diffusion source, and then boron pre-deposition diffusion doping is carried out.

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