A Split Pipeline-Successive Approximation Analog-to-Digital Converter

Abstract

The present invention discloses a split-pipeline successive approximation analog-to-digital converter. The analog-to-digital converter circuit of the present invention is composed of a coarse successive approximation analog-to-digital converter, an encoder, a digital calibration module and two symmetrical half-channels; each half-channel circuit includes a first-stage fine successive approximation analog-to-digital converter, a dynamic amplifier, and a second-stage successive approximation analog-to-digital converter; the coarse analog-to-digital converter samples the input signal, quantizes it through the first-stage converter to generate an output code value; the encoder encodes the output and controls the flipping of the capacitor arrays of the first-stage converters of the two half-channels; the first-stage residual is amplified by the dynamic amplifier and sampled by the second-stage converter to generate respective second-stage output digital code values; the front and back stages work in a pipeline manner; the outputs of the first and second stages of the two half-channels pass through the digital calibration module to obtain the output of the entire ADC. The present invention has low power consumption, high efficiency and low hardware overhead.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a split-pipeline-successive approximation analog-to-digital converter with a single-coarse double-fine structure. Background Art

[0002] As data requirements increase, high-speed and high-resolution analog-to-digital converters are essential. Pipelined-SAR ADCs are more energy-efficient than traditional pipeline ADCs and outperform SAR ADCs in speed, resolution, and linearity. Therefore, they offer significant advantages in the field of high-performance, high-speed, and high-resolution ADCs.

[0003] As process nodes continue to advance, high-performance ADC designs increasingly rely on various correction techniques to correct errors and improve performance. The split-ADC architecture is a physical architecture that offers low hardware overhead, low power consumption, ease of digital modeling, and robust digital background correction. Figure 1 A schematic diagram of the Split-ADC architecture is provided. The ADC is split in half, resulting in two half-channels that sample the same signal. Each half-channel has half the passive capacitance and active transconductance of the original ADC. Consequently, each half-channel consumes half the area and power of the original ADC, making the total area and power consumption essentially the same as the original ADC. The split-ADC's final output is the average of the quantization results from the two half-channels, resulting in consistent noise performance with the original ADC. Figure 2 The implementation of Pipelined-SAR ADC under a traditional Split architecture is demonstrated.

[0004] The core idea of ​​the Split-ADC correction method is based on the basic mathematical property of linearity, which is an approximate expression of translation invariance:

[0005] h(x+Δ)=h(x)+c, (1)

[0006] As a criterion for determining whether the quantization transfer function of the channel is a straight line, for the two half-channels, each has a corrected overall transfer function h A (·) and h B (·). Therefore, equation (1) can be indirectly realized through the following relationship:

[0007] h A (x)-h B (x) = a, (2)

[0008] h A (x+Δ)-h B(x) = b, (3)

[0009] It can be seen that if (2) and (3) can be satisfied simultaneously, it is equivalent to satisfying (1). These two equations represent that: in the two half-channels A and B of the Split-ADC, if channel A operates in two modes, mode I is normal sampling x, and mode II samples x+Δ; while channel B always samples normally. According to the error extraction method described above, the quantization differences a and b of the two channels are always two constants that are independent of the input signal, which can be used to prove that channels A and B are linear. Obviously, this judgment condition is independent of the specific structure of the ADC, so this method is universal and can be extended to various ADC designs and correction structures, which has great promotion significance. This correction idea requires that the ADC actually implements two different margin curves under the same input. The switching between the two curves is controlled by the pseudo-random number PN. Figure 3 The figure shows the difference between the two different margin curves of a 3-bit ADC. Traditionally, to generate two different margin curves, additional analog signals need to be injected during ADC sampling based on PN.

[0010] High-precision ADCs require large capacitor arrays and long voltage settling times, which limits the ADC's speed. A coarse-fine architecture ADC consists of a coarse ADC and a fine ADC. During sampling, the input signal is sampled simultaneously by both the coarse and fine ADCs. After sampling, the coarse ADC first quantizes the MSBs of the input signal. Its rapidly generated quantization results control the high-bit flipping of the Fine ADC's capacitor array, which then completes the low-bit quantization. Because the coarse ADC's sampling capacitor is much smaller than that of the fine ADC, the voltage settling time is significantly reduced, and the noise requirements for the comparator are also significantly lowered, further accelerating the ADC's operating speed.

[0011] Furthermore, traditional pipelined-SAR ADCs rely on high-performance operational transconductance amplifiers (OTAs) in switched-capacitor circuits to accurately amplify the margin, resulting in high power consumption. Dynamic amplifiers, which eliminate DC power consumption, offer significant advantages, but their lower gain makes it difficult to achieve the required multiples for inter-stage margin amplification. Summary of the Invention

[0012] The object of the present invention is to provide a split-pipeline-successive approximation analog-to-digital converter with a single-coarse double-fine structure and low power consumption and high efficiency.

[0013] The split-pipeline-successive approximation analog-to-digital converter proposed in the present invention is based on the Split-ADC architecture and has a single-coarse double-fine structure. The overall circuit consists of a shared coarse successive approximation analog-to-digital converter (Coarse Sub-ADC), an encoder, a digital calibration module (Calibration), and two completely symmetrical half-channels (CHA and CHB). Figure 4 As shown. Among them:

[0014] The shared coarse successive approximation analog-to-digital converter includes a sampling capacitor array with a relatively small capacitance, a comparator with high noise and low power consumption, and a relatively fast successive approximation logic. The capacitance of the capacitor array, the noise of the comparator, and the power consumption only need to meet the minimum requirements of the ADC resolution. The input signal is quantized by the shared coarse analog-to-digital converter to generate an output code value D R .

[0015] The two completely symmetrical half-channels (CHA, CHB), each half-channel circuit includes: a first-stage fine successive approximation analog-to-digital converter (ADC) with a large capacitor, a dynamic amplifier (DA) with a gain boost, and a second-stage successive approximation analog-to-digital converter (ADC); wherein the first-stage fine successive approximation analog-to-digital converter with a large capacitor samples the input signal at the same time as the shared coarse successive approximation analog-to-digital converter, but does not compare and quantize, but waits for the output result D of the encoder. A / B1 The capacitor array is directly flipped. After the flipping is completed and the establishment accuracy of the residual voltage meets the requirements of the half-channel ADC, the gain-boosted dynamic amplifier (DA) amplifies the residual signal. The amplified signal is sampled and quantized by the second-stage successive approximation analog-to-digital converter to generate a second-stage digital code value.

[0016] In the present invention, the first-stage fine SAR ADC with large capacitance has the same resolution as the common coarse SAR ADC, but the circuit only includes a sampling capacitor array with a larger capacitance, and the capacitance of the array is determined by the noise limit required by the half-channel ADC resolution.

[0017] The encoder input is the output code value D of the above-mentioned common coarse successive approximation analog-to-digital converter R And 4 1-bit control signals PN_A, PN_B, SHUFF_A, SHUFF_B, where PN_A and PN_B control the margin mode of the two completely symmetrical half channels (CHA and CHB) respectively. R For example, the encoding methods of its two margin modes are:

[0018]

[0019] PN controls the margin mode selection for the two fully symmetrical half-channels CHA and CHB. If PN_A / B = 0, the encoder operates in NRM mode. This means the original output code values ​​are not modified, and the CHA and CHB capacitor arrays are directly flipped. The ADC quantizes the input signal Vin normally, and the margin curve is the same as a traditional ADC. If PN_A / B = 1, the encoder operates in DRM mode, re-encoding the original output code values. The generated capacitor array flip control signal shifts the margin curve up or down, causing the ADC to quantize Vin+Δ or Vin-Δ.

[0020] SHUFF controls the last bit capacitor linking mode of the first-stage sub-ADC in the two completely symmetrical half-channels CHA and CHB. The control mode is shown in the attached figure. Figure 4 If SHUFF_A / B=0, we can get D from formula (1) A / B1 Directly control the flipping of the capacitor array so that the first stage of the two symmetrical half channels generates their own residual signals. If SHUFF_A / B=1, D obtained by formula (1) A / B1 If the last two code values ​​are swapped, the flipping modes of the last two capacitors in the capacitor array with equal values ​​and weights representing the smallest weight 1 and the second smallest weight 2 are swapped.

[0021] The digital calibration module adopts a calibration method based on a split analog-to-digital converter, and mainly completes the calibration based on the split analog-to-digital converter through an adaptive filter: its working process is: input the digital output code values ​​generated by the two channels and the control signals PN_A, PN_B, SHUFF_A, SHUFF_B, and adjust the weights corresponding to each bit output through the adaptive filter to compensate for the non-ideal factors in the channel; when the output expectation obtained by subtracting the transfer functions of the two channels is 0, the transfer functions of the two channels become the same linear function, thereby completing the calibration of the system.

[0022] The split-pipeline-successive approximation analog-to-digital converter of the present invention has the following working process: a shared coarse successive approximation analog-to-digital converter samples an input signal, performs first-stage quantization, and generates an output code value; an encoder encodes this output according to pseudo-random numbers PN and SHUFF selected in a control mode, and the generated new code value directly controls the flipping of capacitor arrays of two half channels (CHA and CHB); the two half channels (CHA and CHB) sample the input signal but do not perform quantization. Instead, after the encoder output controls the flipping of their capacitor arrays, they directly generate their respective first-stage residuals; the residual information is amplified by a gain-boosted dynamic amplifier (DA) and sampled by a second-stage successive approximation analog-to-digital converter to generate their respective second-stage output digital code values; the two stages operate in a pipeline manner; after data synchronization, the output code values ​​of the first and second stages of the two half channels are subtracted and input to a digital calibration module (calibration) for digital background calibration of the ADC; the output code values ​​are summed and divided by two to serve as the output of the entire ADC.

[0023] Furthermore, the gain-boosted dynamic amplifier of the present invention is as shown in the attached Figure 6 As shown, it includes common mode level detection module, input pair tube M N1 、M N2 、M P5 and M P6 , cross-coupled load tube M N3 and M N4 , tail current tube M N0 , load capacitance C 1N 、C 1P and C 2N 、C 2P , 7 control switches S0-S6; among them, the M N1 、M N2 、M P5 and M P6 The gates of M are connected to the differential input signals respectively; N1 、M N2 The source and tail current tube M N0 The drain of M N0 The source of the M is connected to the ground by the switch S0. N0 The gate of M is connected to a bias voltage to control the tail current of the dynamic amplifier circuit; N1 、M N2 The drain level and M N3 、M N4 Source level, capacitive load C 2N and C 2P The top plate, and switches S1 and S2 are connected and connected to the power supply; C 2N and C 2P The bottom plate is connected to ground; M N3 、MN4 The gates are connected to M N4 、M N3 The source level forms a cross-coupling connection mode; M N4 、M N3 The source level is the output end of the dynamic amplifier, and is connected to the detection end of the common mode level detection module and the input pair tube M P5 and M P6 The drain of the capacitor is connected to the load capacitor C through switches S3 and S4. 1N 、C 1P The top plate is connected to the power supply through switches S5 and S6; C 1N and C 1P The bottom plate is connected to the ground; the input to tube M P5 and M P6 The source stage is connected to the power supply.

[0024] Furthermore, the gain-boosted dynamic amplifier operates in open loop and has two working phases: reset Φ RST With the magnification Φ AMP , where, in the reset phase, switches S1-S6 are closed, S0 is open, and the load capacitor C 1N 、C 1P and C 2N 、C 2P The top plate ends of the transistors are charged to the power supply. In the amplification phase, switches S1, S2, S5, and S6 are disconnected, and switches S0, S3, and S4 are closed. N1 、M N2 、M P5 and M P6 Receive the input signal, the common mode level detection module detects the change of the output common mode voltage. When the output common mode voltage drops to the set common mode voltage, switches S3 and S4 are disconnected, and the load capacitor C 1N 、C 1P The voltage on the top plate is the output.

[0025] Furthermore, the gain-boosted dynamic amplifier, wherein the load capacitor C 1N 、C 1P 、C 2N 、C 2P , whose value includes the parasitic capacitance and actual capacitance of the connected nodes, where C 1N 、C 1P It also includes the sampling capacitor of the subsequent ADC.

[0026] Unlike conventional methods that inject analog signals to achieve two margin modes, this invention uses an encoder to encode the output code values ​​of the coarse ADC, directly enabling the fine first-stage ADC to obtain two different margin curves, thus providing a digital input for the offset. Furthermore, the increased speed of the coarse ADC effectively reduces the time required for first-stage quantization.

[0027] The foregoing briefly describes the features and technical advantages of the present invention. The following uses a Pipelined-SAR ADC based on a Split-ADC architecture with a 200MS / s sampling rate and 14-bit resolution as an example to more clearly illustrate the concept of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 Schematic diagram of the split analog-to-digital converter architecture.

[0029] Figure 2 Schematic diagram of the traditional split-analog-to-digital converter-based calibration architecture.

[0030] Figure 3 Schematic diagram of two margin modes for a 3-bit ADC based on the split ADC calibration method.

[0031] Figure 4 This is a schematic diagram of a split-pipeline-successive approximation analog-to-digital converter with a single-coarse double-fine structure proposed by the present invention.

[0032] Figure 5 Schematic diagram of the PN and SHUFF signals controlling a 6-bit capacitor array.

[0033] Figure 6 Schematic diagram of a dynamic amplifier with gain boost.

[0034] Figure 7 The following is a 200MS / s 14-bit Pipelined-SAR ADC example and its timing diagram. DETAILED DESCRIPTION

[0035] The following, in conjunction with the accompanying drawings, describes a split-pipeline-successive-approximation analog-to-digital converter (ADC) with a single-coarse, double-fine structure proposed by the present invention. It is noteworthy that the ADC provided by the present invention can have many different performance indicators and implementation methods, and the gain-boosted dynamic amplifier and digital injection margin encoding methods of the present invention can also have a variety of application scenarios. The following implementation only provides a typical implementation circuit for the present invention and is intended only to illustrate the formation and use of the present invention and is not intended to limit the present invention.

[0036] The present invention provides a split-pipeline-successive approximation analog-to-digital converter with a single-coarse double-fine structure and its internal module circuit. An implementation example is a two-stage Pipelined-SAR ADC with a sampling rate of 200MS / s and a 14-bit resolution. According to the requirements of the Split-ADC architecture, the single channel of the ADC is split into two half-channels A and B, and the front and back stages work in a pipeline manner. The specific implementation method is as follows: Figure 7 In this example, the power supply voltage is 0.9V, and the actual gain of the dynamic amplifier with increased gain is 16 times.

[0037] In this example, the first stage is a 6-bit resolution SAR ADC. The coarse sub-ADC has a capacitor array, a comparator, and a successive approximation logic circuit, while the first-stage analog-to-digital converters of CHA and CHB only have a capacitor array. S Phase, the three capacitor arrays sample the input signal simultaneously, CK1 is the comparator clock of the Coarse Sub-ADC; the encoder receives the external control signals PN_A / B and SHUFF_A / B. After the Ready signal comes, the 6-bit output code of the Coarse Sub-ADC is encoded by the encoder to control the flip of the first-stage capacitor arrays of CHA and CHB respectively. During this period, the dynamic amplifier with gain boost is in Φ RST After the margin is generated, the dynamic amplifier enters Φ AMP , margin amplification begins, while the second-stage ADC samples simultaneously. CK2 is the clock signal for the second-stage comparator. CHA and CHB each have different control signals, PN and SHUFF, randomly assigning different margin modes for digital calibration. The pipelined operation of the previous and next stages within each channel achieves high speed.

[0038] Although the contents and advantages of the present invention have been disclosed in detail as above, it must be noted that the scope of the present invention is not limited to the specific embodiments such as the methods and steps described in the specification. Without departing from the spirit and scope of the present invention, any person skilled in the art can make many variations and modifications based on the contents disclosed by the present invention, which should also be regarded as the scope of protection of the present invention.

Claims

1. A split-pipeline-successive approximation analog-to-digital converter, characterized in that: Based on the Split-ADC architecture, it has a single-coarse double-fine structure. The overall circuit consists of a shared coarse successive approximation analog-to-digital converter, an encoder, a digital calibration module, and two fully symmetrical half-channels (CHA and CHB). The shared coarse successive approximation analog-to-digital converter includes a sampling capacitor array, a comparator, and successive approximation logic; wherein the capacitance of the sampling capacitor array, the noise of the comparator, the power consumption, etc., meet the minimum requirements of the ADC resolution; the input signal is quantized by the shared coarse analog-to-digital converter to generate an output code value D R ; The two completely symmetrical half-channels (CHA, CHB), each half-channel circuit includes: a first-stage fine successive approximation analog-to-digital converter (ADC), a gain-boosted dynamic amplifier (DA), and a second-stage successive approximation analog-to-digital converter (ADC); wherein the first-stage fine successive approximation analog-to-digital converter samples the input signal at the same time as the shared coarse successive approximation analog-to-digital converter, but does not compare and quantize, but waits for the output result of the encoder. DA / B1 The capacitor array is directly flipped. After the flipping is completed and the margin voltage establishment accuracy meets the requirements of the half-channel ADC, the gain-boosted dynamic amplifier (DA) amplifies the margin signal. The amplified signal is sampled and quantized by the second-stage successive approximation analog-to-digital converter to generate a second-stage digital code value. The encoder input is the output code value D of the above-mentioned common coarse successive approximation analog-to-digital converter R and four 1-bit control signals PN_A, PN_B, SHUFF_A, and SHUFF_B, wherein PN_A and PN_B respectively control the margin modes of the two fully symmetrical half channels (CHA and CHB); The digital calibration module adopts a calibration method based on a split analog-to-digital converter and completes the calibration based on the split analog-to-digital converter through an adaptive filter: its working process is: input the digital output code values ​​generated by the two channels and the control signals PN_A, PN_B, SHUFF_A, SHUFF_B, and adjust the weight corresponding to each bit output through the adaptive filter to compensate for the non-ideal factors in the channel; when the output expectation obtained by subtracting the transfer functions of the two channels is 0, the transfer functions of the two channels become the same linear function, thereby completing the calibration of the system.

2. The split-pipeline-successive approximation analog-to-digital converter according to claim 1, wherein: The resolution of the first-stage fine successive approximation analog-to-digital converter is the same as that of the shared coarse successive approximation analog-to-digital converter, but the circuit only includes one sampling capacitor array, and the capacitance of the capacitor array is determined by the noise limit required by the half-channel ADC resolution.

3. The split-pipeline-successive approximation analog-to-digital converter according to claim 1, wherein: In the encoder, for the 6-bit first-level output code D R , the encoding methods of its two margin modes are:

4. The split-pipeline-successive approximation analog-to-digital converter according to claim 3, wherein: In the encoder, PN controls the margin mode selection of the two completely symmetrical half-channels CHA and CHB. If PN_A / B = 0, the encoder operates in NRM mode, that is, the original output code value is not modified, and this is directly used to control the flipping of the CHA and CHB capacitor arrays. The ADC normally quantizes the input signal Vin, and the margin curve is the same as that of a traditional ADC. If PN_A / B = 1, the encoder operates in DRM mode, re-encoding the original output code value. The generated capacitor array flip control signal will shift the margin curve up and down, causing the ADC to quantize Vin+Δ or Vin-Δ.

5. The split-pipeline-successive approximation analog-to-digital converter according to claim 3, wherein: In the encoder, SHUFF controls the last bit capacitor linking mode of the first-stage sub-ADC in the two completely symmetrical half-channels CHA and CHB; if SHUFF_A / B=0, D is obtained from formula (1): A / B1 Directly control the flipping of the capacitor array so that the first stage of the two symmetrical half channels generates their own residual signals. If SHUFF_A / B=1, D obtained by formula (1) A / B1 If the last two code values ​​are swapped, the flipping modes of the last two capacitors in the capacitor array with equal values ​​and weights representing the smallest weight 1 and the second smallest weight 2 are swapped.

6. The split-pipeline-successive approximation analog-to-digital converter according to claim 5, wherein: Its workflow is as follows: a shared coarse successive approximation analog-to-digital converter samples the input signal, performs first-stage quantization, and generates an output code value; the encoder encodes this output according to the pseudo-random numbers PN and SHUFF selected in the control mode, and the generated new code value directly controls the flipping of the capacitor arrays of the two half-channels (CHA and CHB); the two half-channels (CHA and CHB) sample the input signal but do not quantize it. Instead, after the encoder output controls the flipping of their capacitor arrays, they directly generate their own first-stage residuals; the residual information is amplified by a gain-boosted dynamic amplifier (DA) and sampled by a second-stage successive approximation analog-to-digital converter to generate their own second-stage output digital code values; the two stages operate in a pipelined manner. After data synchronization, the output code values ​​of the first and second stages of the two half-channels are subtracted and input into the digital calibration module for digital background calibration of the ADC. The output code values ​​are summed and divided by 2 to be used as the output of the entire ADC.

7. The split-pipeline-successive approximation analog-to-digital converter according to any one of claims 1 to 6, wherein: The gain-boosted dynamic amplifier circuit includes a common-mode level detection module, an input pair tube M N1 、M N2 、M P5 and M P6 , cross-coupled load tube M N3 and M N4 , tail current tube M N0 , load capacitance C 1N 、C 1P and C 2N 、C 2P , 7 control switches S0-S6; in: Pair M N1 、M N2 、M P5 and M P6 The gates of M are connected to the differential input signals respectively; N1 、M N2 The source and tail current tube M N0 The drain of M N0 The source of the M is connected to the ground by the switch S0. N0 The gate of M is connected to a bias voltage to control the tail current of the dynamic amplifier circuit; N1 、M N2 The drain level and M N3 、M N4 Source level, capacitive load C 2N and C 2P The top plate, and switches S1 and S2 are connected and connected to the power supply; C 2N and C 2P The bottom plate is connected to ground; M N3 、M N4 The gates are connected to M N4 、M N3 The source level forms a cross-coupling connection mode; M N4 、M N3 The source level is the output end of the dynamic amplifier, and is connected to the detection end of the common mode level detection module and the input pair tube M P5 and M P6 The drain of the capacitor is connected to the load capacitor C through switches S3 and S4. 1N 、C 1P The top plate is connected to the power supply through switches S5 and S6; C 1N and C 1P The bottom plate is connected to the ground; the input to tube M P5 and M P6 The source stage is connected to the power supply.

8. The split-pipeline-successive approximation analog-to-digital converter according to claim 7, wherein: The gain-boosted dynamic amplifier operates in an open-loop circuit and has two working phases: resetting Φ RST With the magnification Φ AMP ,in: In the reset phase, switches S1-S6 are closed, S0 is open, and the load capacitor C 1N 、C 1P and C 2N 、C 2P The top plate ends of the transistors are charged to the power supply. In the amplification phase, switches S1, S2, S5, and S6 are disconnected, and switches S0, S3, and S4 are closed. N1 、M N2 、M P5 and M P6 Receive the input signal, the common mode level detection module detects the change of the output common mode voltage. When the output common mode voltage drops to the set common mode voltage, switches S3 and S4 are disconnected, and the load capacitor C 1N 、C 1P The voltage on the top plate is the output.

9. The split-pipeline-successive approximation analog-to-digital converter according to claim 8, wherein: In the gain-boosted dynamic amplifier, the load capacitor C 1N 、C 1P 、C 2N 、C 2P , whose value includes the parasitic capacitance and actual capacitance of the connected node, where C 1N 、C 1P It also includes the sampling capacitor of the subsequent ADC.

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