Method and apparatus for memory device mode selection

Abstract

A method and apparatus for selecting a memory device mode in a serial memory device are provided. Memory device configuration information may be retrieved in response to a memory device initialization condition, and a configuration register bit mask included in the memory device configuration information may then be written to a configuration register of the memory device. The configuration bit mask may be written to the configuration register using a write command, which may also be included in the memory device configuration information. The serial memory device may be a serial flash memory. The configuration register bit mask may include an I / O mode bit setting indicating that the memory is enabled to operate in a four-bit I / O mode or other multi-bit serial I / O mode instead of a single-bit serial I / O mode.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. non-provisional patent application No. 16 / 523,429, filed on July 26, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to serial memory devices, and more particularly to methods and apparatus for enabling or selecting a multi-bit serial input / output (I / O) mode rather than a single-bit serial I / O mode in a serial memory device. Background Art

[0004] A computing device (e.g., a laptop computer, a mobile phone, etc.) may include one or more processors to perform various functions, such as telephony, wireless data access, camera / video functions, etc. The processor may be coupled to a memory in which processor instructions and data may be stored. The memory may be embedded with the processor on a semiconductor die, or may be part of a different semiconductor die. The memory may perform various functions. For example, the memory may be used as a cache, a register file, or a storage device. The memory may be any of a variety of types. For example, the memory may be a static random access memory (SRAM), a dynamic random access memory (DRAM), a magnetic random access memory (MRAM), a NAND flash memory, or a NOR flash memory, etc. Some types of flash memory devices only provide serial data access, rather than parallel data access. Such flash memory devices are generally referred to as serial flash memory devices.

[0005] Some types of serial flash memory devices can be configured to operate in a selected mode of multiple serial I / O modes, such as a single-bit serial I / O mode and a four-bit serial I / O mode. In the single-bit I / O mode, data bits are input to the flash memory device in a serial format on a single input line and read from the flash memory device in a serial format on a single output line. In the four-bit I / O mode, data is input and output on four serial I / O lines. The I / O mode can be selected using a configuration register in the flash memory device. Several methods for selecting an I / O mode are known, and the method used may depend on the characteristics of the flash memory device, such as whether the configuration register is volatile or non-volatile. One method of selecting an I / O mode involves: upon booting a system incorporating a flash memory device, using a single-bit I / O mode to read configuration information from a file in the flash memory device itself, and writing the value of the I / O mode enable bit (e.g., a quad enable bit or "QE" bit) indicated in the configuration information to the configuration register. In response to setting the QE bit value in this manner, the flash memory device configures itself to operate in a four-bit serial I / O mode rather than a single-bit serial I / O mode.

[0006] Using configuration registers to select I / O modes may present a number of challenges to manufacturers of devices incorporating serial flash memory devices. For example, the manner in which configuration registers are used to select I / O modes may not be the same in all serial flash memory devices, such as those produced by different memory device manufacturers. It is desirable to provide improved methods and apparatus related to serial flash memory I / O mode selection. Summary of the invention

[0007] This summary identifies features of some exemplary aspects and is not an exclusive or exhaustive description of the disclosed subject matter. Additional features and aspects are described and will become apparent to those skilled in the art upon reading the following detailed description and viewing the accompanying drawings which form a part hereof.

[0008] A method for memory device mode selection according to at least one embodiment includes: retrieving memory device configuration information in response to a memory device initialization condition, and writing a configuration register bit mask included in the memory device configuration information to a configuration register of the memory device. A write command can be used to write the configuration bit mask to the configuration register, and the write command can also be included in the memory device configuration information. The memory device can be a serial flash memory. The configuration register bit mask can include an I / O mode bit setting, which indicates that the memory can operate in a multi-bit I / O mode such as a four-bit I / O mode.

[0009] According to at least one embodiment, a device for selecting a memory device mode includes a host coupled to a memory device via a link. The host may include a processor system configured to retrieve memory device configuration information in response to a memory device initialization condition, and write a configuration register bit mask included in the memory device configuration information to a configuration register of the memory device. A write command may be used to write a configuration bit mask to a configuration register, which may also be included in the memory device configuration information. The memory device may be a serial flash memory. The configuration register bit mask may include an I / O mode bit setting, which indicates that the memory can operate in a multi-bit I / O mode such as a four-bit I / O mode.

[0010] According to another apparatus for selecting a memory device mode according to at least one embodiment, the apparatus comprises a memory device and a processor system, the processor system being configured to retrieve memory device configuration information in response to a memory device initialization condition, and write a configuration register bit mask included in the memory device configuration information to a configuration register of the memory device. A write command may be used to write a configuration bit mask to a configuration register, which may also be included in the memory device configuration information. The memory device may be a serial flash memory. The configuration register bit mask may include an I / O mode bit setting, which indicates that the memory can operate in a multi-bit I / O mode such as a four-bit I / O mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Various aspects of the apparatus and method will now be presented in a detailed description by way of example and not limitation, with reference to the accompanying drawings, in which:

[0012] Figure 1 Apparatus for memory device mode selection in accordance with certain aspects of the present disclosure are shown.

[0013] Figure 2A An example of normal operation of a serial flash memory in single-bit I / O mode is shown.

[0014] Figure 2B An example of normal operation of a serial flash memory in four-bit I / O mode is shown.

[0015] Figure 3 An example of a configuration register of a conventional serial flash memory device that is configurable to operate in one of a single-bit I / O mode and a four-bit I / O mode is shown.

[0016] Figure 4 Examples of configuration information in accordance with certain aspects of the present disclosure are shown.

[0017] Figure 5 is a flow chart illustrating a method for memory device mode selection according to certain aspects of the present disclosure.

[0018] Figure 6 is a flow chart illustrating another method for memory device mode selection in accordance with certain aspects of the present disclosure.

[0019] Figure 7 is a flow chart illustrating yet another method for memory device mode selection in accordance with certain aspects of the present disclosure.

[0020] Figure 8 A system for memory device mode selection in accordance with certain aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0021] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of various configurations and is not intended to represent the only configuration in which the concepts described herein may be practiced. The detailed description includes specific details for providing a thorough understanding of the various concepts. However, it is clear to those skilled in the art that these concepts may be practiced without these specific details. In some cases, well-known structures and components are shown in block diagram form to avoid confusing such concepts.

[0022] As used herein, the term "coupled to" in various tenses of the verb "couple" may mean that element A is directly connected to element B or that other elements may be connected between elements A and B (i.e., element A is indirectly connected to element B) to operate certain intended functions. In the case of electrical components, the term "coupled to" may also be used herein to mean the use of wires, traces, or other conductive materials to electrically connect elements A and B (and any components electrically connected therebetween). In some examples, the term "coupled to" may mean the transfer of electrical energy between elements A and B to operate certain intended functions.

[0023] In some examples, the term "electrically connected" can mean having current or being configurable to have current flow between elements A and B. For example, elements A and B can be connected via resistors, transistors, or inductors, as well as wires, traces, or other conductive materials and components. In addition, for radio frequency functions, elements A and B can be "electrically connected" via capacitors.

[0024] The terms "first", "second", "third", etc. may be adopted for ease of reference and may not have substantive meaning. Similarly, the names of components / modules may be adopted for ease of reference and may not limit the components / modules. The modules and components presented in this disclosure may be implemented in hardware, software, or a combination of hardware and software.

[0025] The term "bus system" may specify that elements coupled to the "bus system" may exchange information between them directly or indirectly. In this manner, a "bus system" may contain multiple physical connections, as well as intermediate levels such as buffers, latches, registers, etc. Modules may be implemented in hardware, software, or a combination of hardware and software. The terms "software" and "firmware" are used synonymously in this disclosure.

[0026] A method and apparatus for input / output (I / O) mode selection in a serial flash memory device are proposed. A serial flash memory is typically a compact, low-power device that provides only serial access to data (i.e., no parallel access). Rather than being configured to address a single byte, a serial flash memory device is configured to read or write a group of consecutive bytes in an address space by receiving a serial format bit to be written as input and providing a serial format bit that has been read as output. Conventional flash memory devices can typically operate in a single-bit I / O mode, in which all bits to be written are received on a single input data line and all bits that have been read are provided on a single output data line. Due to the operation in the single-bit I / O mode, a serial peripheral interface (SPI) protocol is typically used to access the flash memory device. However, in addition to the single-bit I / O mode, some flash memory devices can also operate in one or more multi-bit I / O modes. A common multi-bit I / O mode is a four-bit I / O mode, in which data is input and output on four I / O lines (i.e., four bits per clock cycle). Dual-bit I / O mode is another common multi-bit I / O mode in which data is input and output on two I / O lines (i.e., two bits per clock cycle).

[0027] As described below, the I / O mode in which the serial flash memory device is to operate can be selected by setting a bit value in a configuration register in the device. For example, one of the configuration register bits can be a quad enable bit or "QE" bit. When the flash memory device is initially powered on, the QE bit of the configuration register can be set to a default value, such as "0", to indicate that the flash memory device can operate in single-bit I / O mode. If a "1" is subsequently written to the QE bit, the flash memory device can respond by becoming operable in four-bit I / O mode. The QE bit can be set to indicate four-bit I / O mode operation as part of a boot process for a device (e.g., a computing system, a mobile computing device, etc.) that includes or contains flash memory.

[0028] While aspects of single-bit I / O mode are somewhat standardized (e.g., per the SPI protocol), aspects of multi-bit I / O mode in serial flash memory devices that provide such mode are not standardized. For example, the location of the multi-bit I / O mode enable bit (e.g., QE) in the configuration register, whether the configuration register is volatile or non-volatile, and the manner in which data is read and written in multi-bit I / O mode (e.g., read and write commands, wait time specifications, etc.) may differ between flash memory devices produced by different manufacturers, or may even differ between different flash memory device products from the same manufacturer. For simplicity, flash memory devices that are functionally different from each other in these or other related aspects described below are referred to in this disclosure as "different memories," or as "another memory" or "other memories" in the context of a particular or exemplary memory device.

[0029] Figure 1 An apparatus 100 according to certain aspects of the present disclosure is shown, comprising a processor system or host 102, a memory 104, and a link 106 coupling the host 102 and the memory 104. The memory 104 may be, for example, a serial flash memory having a feature by which the memory 104 can selectively operate in one of a single-bit I / O mode and a multi-bit (e.g., four-bit) I / O mode. As described below, the memory 104 bit operates in an I / O mode indicated by a bit setting in a configuration register 108 (also commonly referred to as a status register).

[0030] The apparatus 100 may be, for example, one of the following: a computing system (e.g., a server, a data center, a desktop computer), a mobile computing device (e.g., a laptop, a mobile phone, a vehicle, etc.), an Internet of Things (IoT) device, a virtual reality (VR) system, an augmented reality (AR) system, etc. The host 102 may include at least one processor 110 (e.g., a central processing unit (CPU), a digital signal processor (DSP), a graphics processing unit (GPU), etc.), which is coupled to the memory 104 via a link 106 to perform one or more computing functions, such as data processing, data communication, graphic display, camera operation, AR or VR rendering, image processing, etc. For example, the memory 104 may store instructions or data (e.g., application 112) for at least one processor 110 to perform one or more of the above computing functions. The host 102 may be implemented as a system on a chip (SoC), which includes multiple processors and other devices interconnected by a data bus or other interconnection (not shown for clarity). In some examples, link 106 can be a chip-to-chip or die-to-die link between host 102 and memory 104, with host 102 and flash memory 104 being on separate dies. In other examples, link 106 can be an intra-die link, with host 102 and memory 104 being on the same die.

[0031] Host 102 may communicate data and commands with memory 104 via link 106, either directly under the control of processor 110, or indirectly by processor 110 via memory controller 114 or other intermediary devices. Processor 110 may operate under the control of firmware, which may include loader 116 associated with the multi-bit I / O mode configuration method described below. Although in Figure 1 In the present invention, for the sake of clarity, loader 116 is conceptually shown as residing in processor 110, but it is understood by those of ordinary skill in the art that loader (firmware) 116 may be stored or reside in any storage location accessible to processor 110, such as, for example, in a read-only memory (not shown) in or connected to host 102. Loader 116 may be executed on processor 110 in a conventional manner, which may include processor 110 retrieving instructions from such firmware memory as needed. Processor 110 may execute loader 116 to perform the following description of Figure 5-Figure 7 The method (or part thereof) described herein.

[0032] Figure 2AAn example of a waveform representing a signal that can be transmitted via corresponding signal lines of a link 106 between a host 102 and a memory 104 when the memory 104 operates in a single-bit I / O mode is shown. The signals (and corresponding signal lines) may include, for example, a clock (SCLK), a serial data output (MOSI), a serial data input (MISO), and a chip enable (SS2). Since such signals and their operation are well known to those of ordinary skill in the art, this aspect is not described herein. Note that in this example, four signal lines of the link 106 are used in single-bit I / O mode.

[0033] Figure 2B An example of a waveform representing signals that may be transmitted via corresponding signal lines of a link 106 between a host 102 and a memory 104 when the memory 104 operates in a four-bit I / O mode is shown. The signals may include, for example, a chip enable signal (SS), a clock signal (SCLK), a first-bit serial data signal (DQ0), a second-bit serial data signal (DQ1), a third-bit serial data signal (DQ2), and a fourth-bit serial data signal (DQ3). Since such signals and their operation are well known to those of ordinary skill in the art, this aspect is not described herein. Note that in this example, six signal lines of the link 106 are used in the four-bit I / O mode. Also note that the two signal lines used to transmit the DQ0 and DQ1 signals in the four-bit I / O mode are also used to transmit the MOSI and MISO signals in the single-bit I / O mode ( Figure 2A ). Some signal lines of link 106 may be reused for alternate functions when a different I / O mode is selected.

[0034] Figure 3 The configuration register 108 of the memory 104 is shown. Figure 1 Configuration register 108 may be composed of, for example, 16 bits (in Figure 3 15). The memory 104 configures itself to operate in various aspects based on the 16-bit word that can be written to the configuration register 108. One of ordinary skill in the art understands the functions of the various bits of the configuration register 108 as described in documentation published by the manufacturer of the memory 104 (commonly referred to as a data sheet). Since the memory 104 can be of a commercially available type, such documentation is readily available to one of ordinary skill in the art. Of the bits in the configuration register 108, only the QE bit (in this example at the S9 bit position, and for clarity, at the Figure 3 Therefore, for the sake of brevity, the functions of the bits other than the QE bit of the configuration register 108 are not described in the present disclosure.

[0035] It should be understood that Figure 3The structure of the configuration register 108 shown (i.e., the bit functions and corresponding bit positions) is by way of example only, and different memories (such as memories provided by other manufacturers, or even different products of the same manufacturer) may have different structures. Regardless of such possible differences in structure, at least one bit is an I / O mode bit that relates to enabling a multi-bit serial I / O mode, or more generally, to selecting one of a plurality of serial I / Os. An I / O mode bit setting of one or more I / O mode bits may indicate one of a first I / O mode and a second I / O mode. For example, an I / O mode bit setting may indicate one of a single-bit serial I / O mode and a multi-bit (e.g., dual-bit, quad-bit, etc.) serial I / O mode. In Figure 3 In the example shown, the QE bit (S9) can be set to "0" or "1" by performing a write operation on the configuration register 108. For example, in response to the QE bit being set to "0", the memory 104 can configure itself to operate in the above-mentioned single-bit I / O mode, and in response to the QE bit being set to "1", the memory 104 can configure itself to operate in the above-mentioned four-bit I / O mode. The memory 104 can have a default I / O mode in which it begins operating at power-up (i.e., before any write operation to the configuration register 108). For example, at power-up, the memory 104 can default to the single-bit I / O mode.

[0036] Figure 4 4 shows an exemplary structure of memory device configuration information 400. The memory device configuration information 400 may include a configuration register bit mask indicating the bit position of the above-mentioned I / O mode bit and the value to which the I / O mode bit is set to indicate a multi-bit I / O mode. Figure 4 1, the configuration register bit mask (QE bit mask) of the memory device configuration information 400 may indicate that the QE bit is at the S9 bit position of the configuration register 108 and is set to "1" to enable the four-bit I / O mode. The length of the QE bit mask may be, for example, one byte. It should be understood that the configuration register bit mask may be different between different memories because, as described above, the configuration register bit position of the I / O mode bit may be different between different memories. For example, in different memories (different from those having Figure 3 104), the QE bit may be located at a bit position other than S9.

[0037] The memory device configuration information 400 may include a write command, which is an instruction or command to which the memory 104 responds by performing a write operation. Similarly, the memory device configuration information 400 may include a read command, which is an instruction or command to which the memory 104 responds by performing a read operation. It should be understood that the write command and the read command may be different between different memories.

[0038] The memory device configuration information 400 may also include a latency. The latency is the minimum amount of time between: after a write operation is performed, before the newly written data is designated as readable. It should be understood that the latency may be different between different memories.

[0039] The memory device configuration information 400 may also include device identification (ID) information that uniquely identifies the memory 104 from a variety of different memories (eg, produced by different manufacturers). The device ID information may include, for example, a manufacturer ID and a memory ID that jointly identify a specific product of a specific manufacturer.

[0040] The memory device configuration information 400 may have Figure 4 The exemplary structure shown or any other structure. Regardless of the structure, the same structure can be used to store the memory device configuration information 400 of any memory in a plurality of different memories. For example, Figure 4 The exemplary structure shown indicates that the memory device configuration information 400 may consist of eight consecutive bytes: manufacturer ID (one byte), memory ID (two bytes), QE bit mask (one byte), write command (one byte), read command (one byte), and wait time (two bytes). This structure may be used to store not only Figure 3 The memory device configuration information 400 of the memory 104 of the exemplary configuration information 108 shown may also be used to store memory device configuration information 400 of other (ie, different) memories having other configuration register structures. However, it should be understood that Figure 4 The structure shown is exemplary only. In other examples (not shown), the memory device configuration information 400 may include more or less information than in the example shown, and each field or information item may be represented by more or less bits / bytes than in the example shown. In addition, in other examples, the various fields or items of the memory device configuration information 400 may be organized in a different order than in the example shown, or may be stored non-contiguously.

[0041] Figure 5 A method 500 for selecting a memory I / O mode is shown. Figure 5 The described operations may be performed by, for example, the apparatus 100 ( Figure 1) or under its control. More specifically, the operation may be implemented by, for example, the processor 110 executing the loader 116 or under its control.

[0042] As shown in block 502, method 500 may include retrieving memory device configuration information in response to a memory device initialization condition. The memory device configuration information may include a configuration register bit mask. The configuration register bit mask may include an I / O mode bit setting indicating the enablement of a four-bit I / O mode or other multi-bit I / O mode. The memory device initialization condition may be, for example, where apparatus 100( Figure 1 ) is started, powered on, or otherwise initialized to prepare for operation.

[0043] As indicated at block 504, method 500 may further include writing the configuration register bit mask to a configuration register of a memory device, such as configuration register 108 ( Figure 1 ). The write command indicated in the retrieved memory device configuration information may be used to write the configuration register bit mask to the configuration register. For example, the write operation may include writing a value to the QE bit of the configuration register 108 indicating that the operation of the four-bit I / O mode is enabled. Figure 3 In the described example, "1" may be written to the S9 bit (i.e., the QE bit) of the configuration register 108 to enable operation in the four-bit I / O mode. Note that before a value indicating that operation in the four-bit I / O mode is enabled is written to the QE bit of the configuration register 108, the memory 104 may be operated in the single-bit I / O mode and not in the four-bit I / O mode. However, in response to writing the value to the QE bit, the memory 104 may configure itself to subsequently operate in the four-bit I / O mode. That is, the memory 104 may switch or change from operating in the single-bit I / O mode to operating in the four-bit I / O mode. Although not described in Figure 5 , but after enabling the four-bit I / O mode in this manner, additional write and read operations can be performed using the four-bit I / O mode.

[0044] Figure 6 A method 600 for selecting a memory I / O mode is shown. The method 600 may be a method 500 ( Figure 5 ). The operations described below with respect to method 600 may be implemented by, for example, processor 110 or under its control. Processor 110 may execute method 600 under the control of loader 116 (e.g., part of the processor's firmware). In this exemplary method 600, the memory device configuration information 400 ( Figure 4 ) is pre-stored in the boot sector 118 ( Figure 1). Prior to performing method 600, an entity such as a manufacturer of apparatus 100 (i.e., an original equipment manufacturer or “OEM”) may store memory device configuration information 400 in boot sector 118. The entity may store memory device configuration information 400 in boot sector 118 using any means, such as, for example, a computer-based tool (not shown) to which memory 104 may be connected to configure memory 104 prior to incorporating memory 104 into apparatus 100.

[0045] As indicated at block 602, the method 600 may include, in response to the booting of the device 100 including the memory 104, booting the boot sector 118 ( Figure 1 ) reads the memory device configuration information 400( Figure 4 Since the reading of the memory device configuration information 400 may be implemented by the processor 110 or under its control, the arrow 120 ( Figure 1 ) conceptually indicates that the memory device configuration information 400 is retrieved from the boot sector 118 by the processor 110. It should be noted that the memory 104 can operate in a single-bit I / O mode as a default mode in which the memory 104 is powered on. Therefore, the processor 110 can use the single-bit I / O mode to read the memory device configuration information 400. The processor 110 does not have to use a read command to read the memory device configuration information 400 from the boot sector 118 because the read and write operations using the single-bit I / O mode are standardized between various different memories. As understood by those of ordinary skill in the art, the command for performing a read operation in the single-bit I / O mode is "standard" because the same command can be used in the same manner for different memories. When reading and writing data in the four-bit I / O mode, the standard read and write commands can be used instead of the read and write commands indicated in the memory device configuration information 400.

[0046] As shown in block 604, the method 600 may also include reading the device ID information 122 ( Figure 1 Since the reading device ID information 122 can be implemented by the processor 110 or under its control, the arrow 124 ( Figure 1) conceptually indicates that the device ID information 122 is retrieved by the processor 110 from a location in the memory 104. The processor 110 can use a standard command (e.g., according to the JEDEC standard) to read the device ID information. As understood by those of ordinary skill in the art, the (e.g., JEDEC) command for reading the device ID is "standard" because the same command can be used in the same way for different memories. The location where the device ID information 122 is read from the memory 104 can be clear to the processor 110. That is, the JEDEC command does not require the processor 110 to provide an address or otherwise specify the source from which the requested device ID information is read. When the retrieval is expected to be performed using the standard JEDEC command, the location where the device ID information is stored can be different between different memories. The memory manufacturer can select the location in the memory where the device ID information is stored, and store the device ID information therein so that it can be retrieved in a manner that is clear to the requester (e.g., the processor). Therefore, when the manufacturer of the device 100 incorporates the memory 104 into the device 100, the device ID information may already be stored in the memory 104 (i.e., it can be pre-stored).

[0047] As shown in block 606, the method 600 may then include comparing the device ID information 122 read from the memory 104 using a standard (e.g., JEDEC) command with the device ID information including the manufacturer ID portion and the memory ID portion of the memory device configuration information 400 read from the boot sector 118 of the memory 104 using a single-bit I / O mode to determine if they match. If they do not match, an error handling step (not shown) may be performed.

[0048] As shown in block 608, if the comparison (block 606) does not indicate an error, the method 600 may continue to write the configuration register bit mask portion of the memory device configuration information 400 to the configuration register 108 of the memory 104. The write command indicated in the retrieved memory device configuration information 400 may be used. Alternatively, a standard command may be used. The write operation may include writing a value to the QE bit of the configuration register 108 indicating that the operation of the four-bit I / O mode is enabled. Figure 3 In the example depicted, a "1" may be written to the S9 bit (ie, QE bit) of the configuration register 108 to enable operation in the four-bit I / O mode. Arrow 126 ( Figure 1 ) conceptually indicates that a configuration register bit mask including a QE bit is written by processor 110 to configuration register 108 of memory 104. In response to writing the QE bit value, memory 104 may configure itself to operate in four-bit I / O mode instead of single-bit I / O mode.

[0049] The processor 110 may then confirm that the QE bit was written correctly. However, before reading the contents of the configuration register 108 as shown in block 612, the processor 110 may ensure that a delay time of at least the latency indicated in the memory device configuration information 400 has elapsed as shown in block 610. The processor 110 may read the configuration register 108 using a single-bit I / O mode.

[0050] As shown in block 614, the method 600 may then include comparing the value of the QE bit read from the configuration register 108 (per block 612) with the value of the QE bit written (per block 608) to the configuration register 108. If they do not match, an error handling step (not shown) may be performed. If the comparison (block 614) does not indicate an error, the method 600 is complete and additional memory access operations may be performed using the four-bit I / O mode. Such additional memory access operations may include reading or writing data under the control of, for example, one or more applications 112.

[0051] Figure 7 A method 700 for selecting a memory I / O mode is shown. The method 700 may be a method 500 ( Figure 5 ). The operations described below with respect to method 700 may be implemented by, for example, processor 110 or under its control. Processor 110 may not only Figure 1 In the Figure 8 The system 800 in the embodiment further includes (except Figure 1 104) is a remote network-accessible data storage source or "cloud" 802. As one of ordinary skill in the art will appreciate, the cloud 802 may include, for example, one or more server computer systems with associated data storage devices that are typically used to store and retrieve data in response to queries from remote clients via a network. In the exemplary method 700, the memory device configuration information 400 ( Figure 4 ) may be pre-stored in the cloud 802. The processor 110 may execute the method 700 under the control of the loader 116.

[0052] As shown in block 702, method 700 may include reading device ID information 122 ( Figure 1 ). The device ID information 122 may be provided under the control of the processor 110 in the manner described above with respect to the method 600 ( Figure 6 ) is read in the manner described.

[0053] As shown in block 704, the method 700 may also include obtaining a network data storage address, such as enabling the host 102 to access the cloud 802 via a data network ( Figure 8 The network data storage address may be stored in, for example, a one-time programmable (OTP) memory (not shown) in the host 102 or other memory accessible to the processor 110.

[0054] As shown in block 706, the method 700 may include obtaining from the cloud 802 ( Figure 8 ) to retrieve the memory device configuration information 400( Figure 4 Since the reading of the memory device configuration information 400 may be implemented by the processor 110 or under its control, the arrow 804 ( Figure 8 ) conceptually indicates that memory device configuration information 400 is retrieved from cloud 802 by processor 110. A table or other data structure or database (not shown) stored in cloud 802 may contain a plurality of entries, each of which associates device configuration information with corresponding unique device ID information (e.g., a unique combination of manufacturer ID and memory ID) of a plurality of different memories. Thus, each device configuration information stored in cloud 802 corresponds to a different memory, of which memory 104 may be an example. Thus, for example, cloud 802 may provide exemplary memory device configuration information 400 in response to a query received from host 102 identifying memory 104 by its unique device ID information 122.

[0055] As shown in block 708, the method 700 may also include transferring the memory device configuration information 400 ( Figure 4 ) is stored in the boot sector 118 ( Figure 8 ). The processor 110 may write the memory device configuration information 400 to the boot sector 118 using a single-bit I / O mode. A write command indicated in the retrieved memory device configuration information 400 may be used. Alternatively, a standard command may be used. Since storing the memory device configuration information 400 in the boot sector 118 may be implemented by the processor 110 or under its control, arrow 806 conceptually indicates that the memory device configuration information 400 is stored in the boot sector 118 by the processor 110. Although not shown for clarity, the aforementioned operations indicated by blocks 702-708 may be adjusted when the processor 110 determines that the memory device configuration information 400 is not yet stored in the boot sector 118 when the apparatus 100 is started. In addition, although not shown for clarity, the operations indicated by block 708 may be performed in the same manner as described above with respect to blocks 604-606 ( Figure 6 ) as a conditional.

[0056] As shown in block 710, the method 600 may include reading the memory device configuration information 400 from the boot sector 118 in response to a subsequent startup of the device 100. The subsequent startup follows or is after the initial startup, in response to which the memory device configuration information 400 is retrieved from the cloud 802 and stored in the boot sector 118, as described above with respect to blocks 702-708. Between the initial startup and the subsequent startup, other operations may occur, and any amount of time may pass. Such possible other operations, time passing, etc. are indicated by the ellipsis ("...") between blocks 708 and 710. Therefore, if the processor 110 determines that the memory device configuration information 400 has been stored in the boot sector 118 when the device 100 is started, the method proceeds to block 710.

[0057] As indicated at block 712, the method 600 may continue by writing the configuration register bit mask portion of the memory device configuration information 400 to the configuration register 108 of the memory 104. The processor 110 may write to the configuration register 108 using the single-bit I / O mode. The write command indicated in the retrieved memory device configuration information 400 may be used. The write operation may include writing a value to the QE bit of the configuration register 108 indicating that the operation in the four-bit I / O mode is enabled. Figure 3 In the depicted example, a "1" may be written to the S9 bit (ie, QE bit) of the configuration register 108 to enable operation in the four-bit I / O mode. Arrow 808 ( Figure 8 ) conceptually indicates that a configuration register bit mask including a QE bit is written to memory 104 by processor 110. In response to writing a value indicating operation in four-bit I / O mode to the QE bit, memory 104 may configure itself to operate in four-bit I / O mode instead of single-bit I / O mode.

[0058] After enabling or selecting the four-bit I / O mode as described above, additional memory access operations may be performed using the four-bit I / O mode. Such additional memory access operations may include, for example, reading or writing data under the control of one or more applications 112. Although not shown for clarity, additional read and write operations using the four-bit I / O mode may be performed in a manner similar to that described above with respect to blocks 612-614 ( Figure 6 ) describes the error check as a condition.

[0059] As shown in block 714, the network data storage address may also be used to retrieve software from the cloud 802, such as one or more applications 112 or updates to such applications 112. Although not shown separately for clarity, the applications 112 may include not only end-user applications, but also lower-level configuration software that may be involved in the operation of the device 100.

[0060] In a case where two or more business entities (such as an original equipment manufacturer (OEM) that builds the device 100 for an original design manufacturer (ODM)) participate in the device 100 ( Figure 1 ), the ODM can use cloud 802 to isolate software that the ODM considers confidential from direct access by the OEM. Obviously, system 800 and method 700 can enable such a manufacturer to include any of a plurality of different memories without requiring different host (e.g., SoC) firmware, such as loader 116. Additional production runs including different memories can be accommodated by uploading new entries associated with new device ID information and corresponding device configuration information to cloud 802.

[0061] The previous description is provided to enable those skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be clear to those skilled in the art, and the general principles defined herein can be applied to other aspects. Therefore, the claims are not intended to be limited to the aspects shown herein, but to the full range consistent with the language of the claims, wherein unless otherwise specifically stated, references to elements in the singular form are not intended to mean "one and only one", but to mean "one or more". The word "exemplary" is used herein to mean "used as an example, instance or illustration". Any aspect described as "exemplary" herein is not necessarily interpreted as being preferred or superior to other aspects. Unless otherwise specifically stated, the term "some" refers to one or more. Combinations such as "at least one of A, B or C", "one or more of A, B or C", "at least one of A, B and C", "one or more of A, B and C" and "A, B, C or any combination thereof" include any combination of A, B and / or C, and may include multiple A, multiple B or multiple C. Specifically, combinations such as "at least one of A, B, or C," "one or more of A, B, or C," "at least one of A, B and C," "one or more of A, B, and C," and "A, B, C, or any combination thereof" may be A only, B only, C only, A and B, A and C, B and C, or A and B and C, wherein any such combination may include one or more members of A, B, or C. All structural and functional equivalents of the elements of the various aspects described in this disclosure that are known or later known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be covered by the claims. In addition, nothing disclosed herein is intended to be exclusive to the public, regardless of whether such disclosure is explicitly cited in the claims. Words such as "module," "mechanism," "element," "device," and the like may not replace the word "means." Therefore, no claim element shall be interpreted as means plus function unless the element is expressly recited using the phrase "means for..."

Claims

1. A method for selecting a memory device mode, comprising: retrieving, by the processor system in response to a memory device initialization condition, memory device configuration information including a configuration register bit mask, the configuration register bit mask including an input / output (I / O) mode bit setting indicating that a memory multi-bit I / O mode is enabled, the memory device configuration information also including a write command; and writing, by the processor system, the configuration register bit mask into a configuration register of a serial memory device using the write command, The memory device configuration information further includes a wait time, and the method further includes: after writing the configuration register bit mask to the configuration register and the wait time has passed, determining whether an I / O mode bit of the configuration register is set to the I / O mode bit setting.

2. The method according to claim 1, wherein: The memory device initialization condition includes: starting up an apparatus incorporating the memory device and the processor system; and Retrieving the memory device configuration information includes reading the memory device configuration information from a boot sector of the memory device.

3. The method of claim 2, wherein reading the memory device configuration information from the boot sector of the memory device comprises: Use memory single bit I / O mode to read.

4. The method according to claim 1, further comprising: Reading device identification information from the memory device; determining whether the device identification information matches an identification portion of the memory device configuration information; as well as Wherein writing the configuration register bit mask into the configuration register comprises: writing the configuration register bit mask into the configuration register, and determining that the identification information matches the identification portion of the memory device configuration information.

5. The method of claim 1 , wherein retrieving the memory device configuration information comprises: Acquiring, by the processor system, the memory device configuration information from a remote data storage source via a data communications network; storing, by the processor system, the memory device configuration information in a boot sector of the memory device; as well as The memory device configuration information is read from the boot sector of the memory device by the processor system in response to the memory device initialization condition.

6. The method of claim 5, wherein reading the memory device configuration information from the boot sector of the memory device comprises: Use single-bit I / O mode to read.

7. The method of claim 5, wherein storing the memory device configuration information in the boot sector of the memory device comprises: Use single-bit I / O mode to write.

8. An apparatus for selecting a memory device mode, comprising: A host coupled to the serial memory device via a link, wherein the host includes a processor system configured to: retrieving memory device configuration information in response to a memory device initialization condition, the memory device configuration information comprising a configuration register bit mask, the configuration register bit mask comprising an input / output (I / O) mode bit setting, the I / O mode bit setting indicating that a memory multi-bit I / O mode is enabled, the memory device configuration information further comprising a write command; and writing the configuration register bit mask to a configuration register of the memory device using the write command, The memory device configuration information further includes a wait time, and the processor system is further configured to determine whether an I / O mode bit of the configuration register is set to the I / O mode bit setting after the configuration register bit mask is written to the configuration register and the wait time has passed.

9. The apparatus of claim 8, further comprising one of: a computing system, a mobile computing system, an Internet of Things (IoT) device, a virtual reality system, or an augmented reality system incorporating the host, the memory, and the link, wherein the processor system is configured to perform computing functions of the one of the computing system, the mobile computing system, the IoT device, the virtual reality system, or the augmented reality system.

10. The device according to claim 8, wherein: The memory device initialization condition includes: starting up an apparatus incorporating the memory device and the processor system; and Retrieving the memory device configuration information includes reading the memory device configuration information from a boot sector of the memory device.

11. The apparatus of claim 10, wherein reading the memory device configuration information from the boot sector of the memory device comprises: Use memory single bit I / O mode to read.

12. The apparatus according to claim 8, further comprising: Reading device identification information from the memory device; determining whether the device identification information matches an identification portion of the memory device configuration information; as well as Wherein writing the configuration register bit mask into the configuration register comprises: writing the configuration register bit mask into the configuration register, and determining that the identification information matches the identification portion of the memory device configuration information.

13. The apparatus of claim 8, wherein retrieving the memory device configuration information comprises: Acquiring, by the processor system, the memory device configuration information from a remote data storage source via a data communications network; storing, by the processor system, the memory device configuration information in a boot sector of the memory device; as well as The memory device configuration information is read from the boot sector of the memory device by the processor system in response to the memory device initialization condition.

14. The apparatus of claim 13, wherein reading the memory device configuration information from the boot sector of the memory device comprises: Use single-bit I / O mode to read.

15. The apparatus of claim 13, wherein storing the memory device configuration information in the boot sector of the memory device comprises: Use single-bit I / O mode to write.

16. An apparatus for selecting a memory device mode, comprising: Serial memory devices; as well as a processor system configured to retrieve memory device configuration information in response to a memory device initialization condition, the memory device configuration information comprising a configuration register bit mask, the configuration register bit mask comprising an input / output (I / O) mode bit setting, the I / O mode bit setting indicating that a memory multi-bit I / O mode is enabled, the memory device configuration information further comprising a write command, the processor system further configured to write the configuration register bit mask to a configuration register of the memory device using the write command, The memory device configuration information further includes a wait time, and the processor system is further configured to determine whether an I / O mode bit of the configuration register is set to the I / O mode bit setting after the configuration register bit mask is written to the configuration register and the wait time has passed.

17. The device according to claim 16, wherein: The memory device initialization condition includes: starting up an apparatus incorporating the memory device and the processor system; and The processor system is configured to retrieve the memory device configuration information by being configured to read the memory device configuration information from a boot sector of the memory device.

18. The apparatus of claim 17, wherein the processor system is configured to retrieve the memory device configuration information by being configured to: obtaining the memory device configuration information from a remote data storage source via a data communications network; storing the memory device configuration information in a boot sector of the memory device; and The memory device configuration information is read from the boot sector of the memory device in response to the memory device initialization condition.

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