Test circuit and method for simulated neural memory in artificial neural network

Abstract

This article discloses a test circuit and method for an emulated neural memory in a deep learning artificial neural network. The emulated neural memory includes one or more non-volatile memory cell arrays. The test circuit and method can be used to verify the programming operation of one or more cells during sorting tests, quality qualification tests, and other tests.

Description

[0001] Priority declaration

[0002] This patent application claims priority from U.S. Provisional Patent Application No. 62 / 876,515, filed on July 19, 2019, and entitled “Testing Circuitry and Methods for Analog Neural Memory in Artificial Neural Network,” and U.S. Patent Application No. 16 / 569,647, filed on September 12, 2019, and entitled “Testing Circuitry and Methods for Analog Neural Memory in Artificial Neural Network.” Technical Field

[0003] The present invention discloses a test circuit and method for a simulated neural memory in a deep learning artificial neural network. The simulated neural memory includes one or more non-volatile flash memory cell arrays. Background Art

[0004] Artificial neural networks simulate biological neural networks (the central nervous system of animals, especially the brain), and are used to estimate or approximate functions that may depend on a large number of inputs and are generally unknown. Artificial neural networks typically consist of layers of interconnected "neurons" that exchange messages with each other.

[0005] Figure 1 An artificial neural network is shown, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be adjusted based on experience. This allows the neural network to adapt to the input and be able to learn. Typically, a neural network includes multiple layers of inputs. There are typically one or more intermediate layers of neurons, and an output layer of neurons that provide the output of the neural network. Neurons at each level make decisions based on data received from the synapses, either individually or collectively.

[0006] One of the main challenges in developing artificial neural networks for high-performance information processing is the lack of adequate hardware technology. In fact, practical neural networks rely on a large number of synapses to achieve high connectivity between neurons, that is, very high computational parallelism. In principle, such complexity can be achieved by digital supercomputers or clusters of dedicated graphics processing units. However, in addition to being high cost, these approaches are also mediocre in energy efficiency compared to biological networks, which consume less energy mainly due to the low-precision analog calculations they perform. CMOS analog circuits have been used for artificial neural networks, but due to the large number of neurons and synapses required, the synapses of most CMOS implementations are too large.

[0007] Applicant previously disclosed an artificial (simulated) neural network utilizing one or more non-volatile memory arrays as synapses in U.S. Patent Application 15 / 594,439 (published as U.S. Patent Publication 2017 / 0337466), which is incorporated herein by reference. The non-volatile memory array operates as a simulated neural memory. The neural network device includes a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs therefrom, and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a spaced-apart source region and a drain region formed in a semiconductor substrate, wherein a channel region extends between the source region and the drain region; a floating gate disposed over a first portion of the channel region and insulated from the first portion; and a non-floating gate disposed over a second portion of the channel region and insulated from the second portion. Each of the plurality of memory cells is configured to store a weight value corresponding to a plurality of electrons on the floating gate. The plurality of memory cells are configured to multiply the first plurality of inputs by the stored weight values ​​to generate a first plurality of outputs. An array of memory cells used in this manner may be referred to as a vector-matrix multiplication (VMM) array.

[0008] Each nonvolatile memory cell used in an analog neural memory system must be erased and programmed to hold a very specific and precise amount of charge (i.e., number of electrons) in the floating gate. For example, each floating gate must hold one of N different values, where N is the number of different weights that can be indicated by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0009] Precision and accuracy are very important in operations involving VMM arrays because each individual memory cell can store one of N different levels, where N can be greater than 2, rather than a traditional memory cell where N is always 2. This makes testing a very important operation. For example, programming operations need to be verified to ensure that each individual cell or column of cells is accurately programmed to the expected value. As another example, it is critical to identify bad cells or groups of cells so that they can be removed from a group of cells used to store data during operation of the VMM array.

[0010] There is a need for improved testing circuits and methods for VMM arrays. Summary of the invention

[0011] Disclosed herein is a test circuit and method for an emulated neural memory in a deep learning artificial neural network. The emulated neural memory includes one or more arrays of non-volatile flash memory cells. The test circuit and method can be utilized during sorting tests, cycle tests, high temperature operating life (HTOL) tests, quality qualification tests, and other tests to verify the characteristics and operability of one or more cells.

[0012] One embodiment includes a method of verifying values ​​programmed into a plurality of nonvolatile memory cells in an array of analog neural nonvolatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, a bit line in the array; sensing, by a sense amplifier, a current received from the bit line; and comparing the current to a reference current to determine whether the nonvolatile memory cell coupled to the bit line contains an expected value.

[0013] Another embodiment includes a method of measuring current consumed by a plurality of nonvolatile memory cells in an array of analog neural nonvolatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, a bit line in the array; and measuring the current received from the bit line.

[0014] Another method includes a method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: asserting all word lines in the array by the row decoder; asserting all bit lines in the array by the column decoder; performing a deep programming operation on all non-volatile memory cells in the array; and measuring a total current received from the bit lines.

[0015] Another embodiment includes a method for testing an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, the method comprising: programming a plurality of cells coupled to the bit lines; measuring a current consumed by the plurality of cells at K different times and storing a measurement value at each of the K different times, wherein K is an integer; calculating an average value based on the K measurement values; and identifying the bit line as a bad bit line if any of the K measurement values ​​is less than the average value by more than a first threshold or greater than the average value by more than a second threshold.

[0016] Another embodiment includes a method for testing an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, the method comprising: programming a plurality of cells coupled to the bit lines; measuring a voltage on a control gate line coupled to a control gate terminal of the plurality of cells at K different times and storing a measurement value at each of the K different times, wherein K is an integer; calculating an average value based on the K measurement values; and identifying the bit line as a bad bit line if any of the K measurement values ​​is less than the average value by more than a first threshold or greater than the average value by more than a second threshold.

[0017] Another embodiment includes a method of testing an analog neural non-volatile memory cell for storing N different values, where N is an integer, the method comprising: programming the cell to a target value representing one of the N values; verifying whether the value stored in the cell is within an acceptable value window surrounding the target value; repeating the programming step and the reading step for each of the N values; and identifying the cell as bad if any of the verification steps indicates that the value stored in the cell is outside the acceptable value window surrounding the target value.

[0018] Another embodiment includes a method of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, the method comprising: measuring leakage of a column of non-volatile memory cells coupled to the bit lines; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of non-volatile memory cells to compensate for the leakage.

[0019] Another embodiment includes a method of testing a selected nonvolatile memory cell in an analog neural nonvolatile memory cell array, the method comprising: determining a logarithmic slope factor of the selected nonvolatile memory cell when the selected nonvolatile memory cell operates in a subthreshold region; storing the logarithmic slope factor; determining a linear slope factor of the selected nonvolatile memory cell when the selected nonvolatile memory cell operates in a linear region; storing the linear slope factor; and utilizing one or more of the logarithmic slope factor and the linear slope factor when programming the selected cell to a target current.

[0020] Another embodiment includes a method of measuring current consumed by a column of nonvolatile memory cells in an array of analog neural nonvolatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: asserting, by the row decoder, all word lines in the array; asserting, by the column decoder, a bit line in the array to select a column of nonvolatile memory cells; and measuring the current received from the bit line.

[0021] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, the method comprising: erasing non-volatile memory cells in the array by applying a series of voltages to terminals of each non-volatile memory cell in the array, wherein the voltages in the series of voltages increase over time in fixed steps; and reading all non-volatile memory cells to determine the effectiveness of the erasing step.

[0022] Another embodiment includes a method of testing an array of analog neural non-volatile memory cells, the method comprising: programming non-volatile memory cells in the array by applying a series of voltages to terminals of each non-volatile memory cell in the array, wherein the voltages in the series of voltages increase over time in fixed steps; and reading all non-volatile memory cells to determine the validity of the programming step.

[0023] Another embodiment includes a method of testing a plurality of analog neural non-volatile memory cells in an array of non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: programming the plurality of non-volatile memory cells to store one of N different values, wherein N is the number of different levels that can be stored in any non-volatile memory cell; measuring current consumed by the plurality of non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of non-volatile memory cells as bad if a difference between the measured value and the target value exceeds a threshold.

[0024] Another embodiment includes a method of testing multiple analog neural non-volatile memory cells in a non-volatile memory cell array, wherein the memory array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, and wherein each word line is selectively coupled to a row decoder and each bit line is selectively coupled to a column decoder, the method comprising: programming a first selected cell among the multiple non-volatile memory cells using a level among N levels corresponding to a minimum cell current; programming a second selected cell among the multiple non-volatile memory cells using a level among the N levels corresponding to a maximum cell current, wherein each of the second selected cells is adjacent to one or more of the first selected cells; measuring current consumed by the multiple non-volatile memory cells; comparing the measured current to a target value; and identifying the multiple non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 FIG. 1 is a schematic diagram showing an artificial neural network of the prior art.

[0026] Figure 2 A prior art split gate flash memory cell is shown.

[0027] Figure 3 Another prior art split gate flash memory cell is shown.

[0028] Figure 4 Another prior art split gate flash memory cell is shown.

[0029] Figure 5 Another prior art split gate flash memory cell is shown.

[0030] Figure 6 Another prior art split gate flash memory cell is shown.

[0031] Figure 7 A prior art stacked gate flash memory cell is shown.

[0032] Figure 8 A schematic diagram showing different levels of an exemplary artificial neural network using one or more non-volatile memory arrays.

[0033] Fig. 9 is a block diagram showing a vector-matrix multiplication system.

[0034] Fig.10 is a block diagram illustrating an exemplary artificial neural network using one or more vector-matrix multiplication systems.

[0035] Fig.11 Another embodiment of a vector-matrix multiplication system is shown.

[0036] Fig.12 Another embodiment of a vector-matrix multiplication system is shown.

[0037] Fig.13 Another embodiment of a vector-matrix multiplication system is shown.

[0038] Fig.14 Another embodiment of a vector-matrix multiplication system is shown.

[0039] Fig.15 Another embodiment of a vector-matrix multiplication system is shown.

[0040] Fig.16 Another embodiment of a vector-matrix multiplication system is shown.

[0041] Fig.17 Another embodiment of a vector-matrix multiplication system is shown.

[0042] Fig.18 Another embodiment of a vector-matrix multiplication system is shown.

[0043] Fig.19 Another embodiment of a vector-matrix multiplication system is shown.

[0044] Fig. 20 Another embodiment of a vector-matrix multiplication system is shown.

[0045] Fig.21 Another embodiment of a vector-matrix multiplication system is shown.

[0046] Fig. 22 Another embodiment of a vector-matrix multiplication system is shown.

[0047] Fig.23Another embodiment of a vector-matrix multiplication system is shown.

[0048] Fig.24 Another embodiment of a vector-matrix multiplication system is shown.

[0049] Fig.25 One embodiment of a vector-matrix multiplication system including test control logic is shown.

[0050] Fig.26 A reference current source is shown.

[0051] Fig. 27 Shown in Fig.26 The reference subcircuit used in the reference current source.

[0052] Fig.28 A sense amplifier is shown.

[0053] Fig.29A A verification analog-to-digital converter is shown.

[0054] Fig.29B A verification analog-to-digital converter is shown.

[0055] Fig.30 A high voltage generating circuit is shown.

[0056] Fig.31 An exemplary test algorithm implemented by test control logic in a vector-matrix multiplication system is shown.

[0057] Fig.32 One embodiment of a bitline neural read test is shown.

[0058] Fig.33 One embodiment of a bitline neurometric test is shown.

[0059] Fig.34 One embodiment of an LSB screening test is shown.

[0060] Fig.35 One embodiment of a bit line sampling screening test is shown.

[0061] Fig.36 Another implementation of the bit line sampling screening test is shown.

[0062] Fig.37 One implementation of a read window check test is shown.

[0063] Fig.38 One embodiment of a read calibration test is shown.

[0064] Fig.39 One embodiment of a read slope test is shown.

[0065] Fig.40 One embodiment of a read neuron quality qualification test is shown.

[0066] Fig.41 One embodiment of a soft erase test is shown.

[0067] Fig.42 One implementation of a soft programming test is shown.

[0068] Fig.43 One embodiment of a verification test is shown.

[0069] Fig.44 One implementation of a checkerboard validation test is shown. DETAILED DESCRIPTION

[0070] The artificial neural network of the present invention utilizes a combination of CMOS technology and non-volatile memory arrays.

[0071] Non-volatile memory cell

[0072] Digital non-volatile memory is well known. For example, U.S. Pat. No. 5,029,130 ​​(the "'130 patent"), which is incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, which is a type of flash memory cell. Such a memory cell 210 is Figure 2 . Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 therebetween. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is formed over a portion of the source region 14. A word line terminal 22 (which is typically coupled to a word line) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward and located over the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. A bit line terminal 24 is coupled to the drain region 16.

[0073] Memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on word line terminal 22, which causes the electrons on floating gate 20 to tunnel through the intervening insulator via Fowler-Nordheim tunneling from floating gate 20 to word line terminal 22.

[0074] The memory cell 210 is programmed by placing a positive voltage on the word line terminal 22 and a positive voltage on the source region 14 (where electrons are placed on the floating gate). Electron current will flow from the source region 14 (source line terminal) to the drain region 16. When the electrons reach the gap between the word line terminal 22 and the floating gate 20, the electrons will accelerate and become hot. Due to the electrostatic attraction from the floating gate 20, some of the heated electrons will be injected through the gate oxide onto the floating gate 20.

[0075] The memory cell 210 is read by placing a positive read voltage on the drain region 16 and the word line terminal 22 (which turns on the portion of the channel region 18 below the word line terminal). If the floating gate 20 is positively charged (i.e., the electrons are erased), the portion of the channel region 18 below the floating gate 20 is also turned on, and current will flow through the channel region 18, which is sensed as an erased state or a "1" state. If the floating gate 20 is negatively charged (i.e., programmed by electrons), the portion of the channel region below the floating gate 20 is mostly or completely turned off, and no current (or very little current) will flow through the channel region 18, which is sensed as a programmed state or a "0" state.

[0076] Table 1 shows typical voltage ranges that may be applied to the terminals of the memory cell 110 for performing read, erase, and program operations:

[0077] Table 1: Figure 2 Operation of the flash memory unit 210

[0078] WL BL SL Read 1 0.5-3V 0.1-2V 0V Read 2 0.5-3V 0-2V 2-0.1V Erase About 11-13V 0V 0V programming 1V-2V 1-3μA 9-10V

[0079] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0080] Figure 3 A memory cell 310 is shown, which is connected to Figure 2 The memory cell 210 is similar to the memory cell 210 of FIG. 1 , but with the addition of a control gate (CG) terminal 28. The control gate terminal 28 is biased at a high voltage (e.g., 10V) during programming, at a low voltage or negative voltage (e.g., 0v / -8V) during erasing, and at a low voltage or medium voltage (e.g., 0v / 2.5V) during reading. The other terminals are similar to Figure 2 That's biased.

[0081] Figure 4A quad-gate memory cell 410 is shown, which includes a source region 14, a drain region 16, a floating gate 20 over a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) over a second portion of the channel region 18, a control gate 28 over the floating gate 20, and an erase gate 30 over the source region 14. This configuration is described in U.S. Pat. No. 6,747,310, which is incorporated herein by reference for all purposes. Here, except for the floating gate 20, all gates are non-floating gates, meaning that they are electrically connected or capable of being electrically connected to a voltage source. Programming is performed by heated electrons from the channel region 18 that inject themselves into the floating gate 20. Erasing is performed by electrons tunneling from the floating gate 20 to the erase gate 30.

[0082] Table 2 shows typical voltage ranges that may be applied to the terminals of the memory cell 410 for performing read, erase, and program operations:

[0083] Table 2: Figure 4 Operation of the flash memory unit 410

[0084] WL / SG BL CG EG SL Read 1 0.5-2V 0.1-2V 0-2.6V 0-2.6V 0V Read 2 0.5-2V 0-2V 0-2.6V 0-2.6V 2-0.1V Erase -0.5V / 0V 0V 0V / -8V 8-12V 0V programming 1V 1μA 8-11V 4.5-9V 4.5-5V

[0085] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0086] Figure 5 Memory cell 510 is shown, except that the erase gate EG terminal is not included. Memory cell 510 is similar to Figure 4 Erasing is performed by biasing the substrate 18 to a high voltage and biasing the control gate CG terminal 28 to a low or negative voltage. Alternatively, erasing is performed by biasing the word line terminal 22 to a positive voltage and biasing the control gate terminal 28 to a negative voltage. Programming and reading are similar to Figure 4 Like that.

[0087] Figure 6 6 is another type of flash memory cell. Figure 4 The memory cell 410 is the same as the memory cell 610 except that the memory cell 610 does not have a separate control gate terminal. Except that no control gate bias is applied, the erase operation (erasing by using the erase gate terminal) and the read operation are similar to Figure 4 The programming operation is also completed without a control gate bias, and as a result, a higher voltage must be applied on the source line terminal during the programming operation to compensate for the lack of control gate bias.

[0088] Table 3 shows typical voltage ranges that may be applied to the terminals of the memory cell 610 for performing read, erase, and program operations:

[0089] Table 3: Figure 6 Operation of the flash memory unit 610

[0090] WL / SG BL EG SL Read 1 0.5-2.2V 0.1-2V 0-2.6V 0V Read 2 0.5-2.2V 0-2V 0-2.6V 2-0.1V Erase -0.5V / 0V 0V 11.5V 0V programming 1V 2-3μA 4.5V 7-9V

[0091] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal.

[0092] Figure 7 7 is another type of flash memory cell. Figure 2 1 is similar to the memory cell 210 of 1, except that the floating gate 20 extends over the entire channel region 18, and the control gate terminal 22 (which here will be coupled to the word line) extends over the floating gate 20, separated by an insulating layer (not shown). Erase, program and read operations operate in a similar manner as previously described for the memory cell 210.

[0093] Table 4 shows typical voltage ranges that may be applied to the terminals of the memory cell 710 and the substrate 12 for performing read, erase, and program operations:

[0094] Table 4: Figure 7 Operation of the flash memory unit 710

[0095] CG BL SL Substrate Read 1 0-5V 0.1-2V 0-2V 0V Read 2 0.5-2V 0-2V 2-0.1V 0V Erase -8 to -10V / 0V FLT FLT 8-10V / 15-20V programming 8-12V 3-5V / 0V 0V / 3-5V 0V

[0096] "Read 1" is a read mode in which the cell current is output on the bit line. "Read 2" is a read mode in which the cell current is output on the source line terminal. Optionally, in an array including rows and columns of memory cells 210, 310, 410, 510, 610, or 710, the source line can be coupled to a row of memory cells or two adjacent rows of memory cells. That is, the source line terminal can be shared by memory cells in adjacent rows.

[0097] In order to utilize a memory array comprising one of the above-described types of non-volatile memory cells in an artificial neural network, two modifications are made. First, the circuitry is configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory states of other memory cells in the array, as further explained below. Second, continuous (analog) programming of the memory cells is provided.

[0098] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully erased state to a fully programmed state independently and with minimal disturbance to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be changed continuously from a fully programmed state to a fully erased state, and vice versa, independently and with minimal disturbance to other memory cells. This means that the cell storage device is analog, or at least can store one of many discrete values ​​(such as 16 or 64 different values), which allows very precise and individual tuning of all cells in the memory array, and this makes the memory array ideal for storing and fine-tuning the synaptic weights of a neural network.

[0099] The methods and apparatus described herein can be applied to other non-volatile memory technologies, such as but not limited to SONOS (silicon-oxide-nitride-oxide-silicon, charge trapped in nitride), MONOS (metal-oxide-nitride-oxide-silicon, metal charge trapped in nitride), ReRAM (resistive ram), PCM (phase change memory), MRAM (magnetic ram), FeRAM (ferroelectric ram), OTP (two-layer or multi-layer one-time programmable), and CeRAM (correlated electron ram), etc. The methods and apparatus described herein can be applied to volatile memory technologies for neural networks, such as but not limited to SRAM, DRAM, and / or volatile synaptic cells.

[0100] Neural Network Using Non-Volatile Memory Cell Array

[0101] Figure 8 A non-limiting example of a neural network using a non-volatile memory array of the present embodiment is conceptually illustrated. This example uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application may also be implemented using a neural network based on a non-volatile memory array.

[0102] For this example, S0 is the input layer, which is a 32x32 pixel RGB image with 5 bits of precision (i.e., three 32x32 pixel arrays, one for each color R, G, and B, with 5 bits of precision per pixel). Synapse CB1 from input layer S0 to layer C1 applies different sets of weights in some cases and shared weights in other cases, and scans the input image with a 3x3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel as dictated by the model). Specifically, the values ​​of 9 pixels in the 3x3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these 9 input values ​​are multiplied by the appropriate weights, and after summing the outputs of this multiplication, a single output value is determined and provided by the first synapse of CB1 for use in generating a feature map for one of the pixels of layer C1. The 3x3 filter is then shifted right by one pixel within the input layer S0 (i.e., a column of three pixels on the right is added, and a column of three pixels on the left is released), whereby the 9 pixel values ​​in this newly positioned filter are provided to the synapse CB1, where they are multiplied by the same weights and a second single output value is determined by the associated synapse. This process continues until the 3x3 filter has scanned all three colors and all bits (precision values) over the entire 32x32 pixel image of the input layer S0. The process is then repeated using different sets of weights to generate different feature maps for C1 until all feature maps for layer C1 are calculated.

[0103] At layer C1, in this example, there are 16 feature maps, each with 30x30 pixels. Each pixel is a new feature pixel extracted from the product of the input and the kernel, so each feature map is a two-dimensional array, so in this example, layer C1 consists of a two-dimensional array of 16 layers (remember that the layers and arrays referred to in this article are logical relationships, not necessarily physical relationships, that is, arrays do not have to be oriented to physical two-dimensional arrays). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synaptic weights applied to the filter scan. The C1 feature maps can all relate to different aspects of the same image features, such as boundary identification. For example, a first map (generated using a first set of weights, shared for all scans used to generate the first map) can identify circular edges, a second map (generated using a second set of weights different from the first set of weights) can identify rectangular edges, or the aspect ratio of certain features, and so on.

[0104] Before passing from layer C1 to layer S1, an activation function P1 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. The purpose of the pooling function is to average neighboring positions (or a max function can also be used) to, for example, reduce the dependency of edge positions and reduce the data size before entering the next stage. At layer S1, there are 16 15x15 feature maps (i.e., sixteen different arrays of 15x15 pixels per feature map). The synapse CB2 from layer S1 to layer C2 scans the map in S1 using a 4x4 filter, where the filter is shifted by 1 pixel. At layer C2, there are 22 12x12 feature maps. Before passing from layer C2 to layer S2, an activation function P2 (pooling) is applied, which pools the values ​​from consecutive non-overlapping 2x2 regions in each feature map. At layer S2, there are 22 6x6 feature maps. An activation function (pooling) is applied to the synapse CB3 from layer S2 to layer C3, where each neuron in layer C3 is connected to each map in layer S2 via a corresponding synapse of CB3. At layer C3, there are 64 neurons. Synapse CB4 from layer C3 to output layer S3 completely connects C3 to S3, i.e., each neuron in layer C3 is connected to each neuron in layer S3. The output at S3 includes 10 neurons, where the highest output neuron determines the class. For example, the output may indicate recognition or classification of the content of the original image.

[0105] The synapses at each layer are implemented using an array or a portion of an array of non-volatile memory cells.

[0106] Fig. 9 is a block diagram of a system that can be used for this purpose. The vector-matrix multiplication (VMM) system 32 includes a non-volatile memory unit and serves as a synapse between one layer and the next layer (such as Figure 6 CB1, CB2, CB3 and CB4 in FIG. 3 ). Specifically, the VMM system 32 includes a VMM array 33 (including non-volatile memory cells arranged in rows and columns), an erase gate and word line gate decoder 34, a control gate decoder 35, a bit line decoder 36 and a source line decoder 37, which decode the corresponding inputs of the non-volatile memory cell array 33. The input to the VMM array 33 may come from the erase gate and word line gate decoder 34 or from the control gate decoder 35. In this example, the source line decoder 37 also decodes the output of the VMM array 33. Alternatively, the bit line decoder 36 may decode the output of the VMM array 33.

[0107] The VMM array 33 serves two purposes. First, it stores weights to be used by the VMM system 32. Second, the VMM array 33 effectively multiplies the inputs with the weights stored in the VMM array 33 and each output line (source line or bit line) adds them together to produce an output that will serve as the input to the next layer or the final layer. By performing multiplication and addition functions, the VMM array 33 eliminates the need for separate multiplication and addition logic circuits and is also power efficient due to its in-situ memory calculations.

[0108] The output of the VMM array 33 is provided to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the VMM array 33 to create a single value for the convolution. The differential summer 38 is arranged to perform a summation of both the positive weight input and the negative weight input to output a single value.

[0109] The output values ​​of the difference summer 38 are then summed and provided to the activation function circuit 39, which corrects the output. The activation function circuit 39 can provide a sigmoid, tanh, ReLU function or any other nonlinear function. The corrected output value of the activation function circuit 39 becomes the next layer (for example, Figure 8 The elements of the feature map of layer C1 in the image are then applied to the next synapse to produce the next feature map layer or the final layer. Thus, in this example, the VMM array 33 constitutes a plurality of synapses (which receive their inputs from an existing neuron layer or from an input layer such as an image database), and the summer 38 and activation function circuit 39 constitute a plurality of neurons.

[0110] Fig. 9 The inputs to the VMM system 32 (WLx, EGx, CGx, and optionally BLx and SLx) may be analog levels, binary levels, digital pulses (in which case a pulse-to-analog converter PAC may be required to convert the pulses to suitable input analog levels), or digital bits (in which case a DAC is provided to convert the digital bits to suitable input analog levels); the outputs may be analog levels, binary levels, digital pulses, or digital bits (in which case an output ADC is provided to convert the output analog levels into digital bits).

[0111] Fig.10 2 is a block diagram illustrating the use of multiple layers of VMM systems 32 (here labeled VMM systems 32a, 32b, 32c, 32d, and 32e). Fig.10As shown, the input (denoted as Inputx) is converted from digital to analog by a digital-to-analog converter 31 and provided to the input VMM system 32a. The converted analog input can be a voltage or a current. The first level of input D / A conversion can be accomplished by using a function or LUT (lookup table) that maps the input Inputx to the appropriate analog level of the matrix multiplier of the input VMM system 32a. The input conversion can also be accomplished by an analog-to-analog (A / A) converter to convert the external analog input into a mapped analog input to the input VMM system 32a. The input conversion can also be accomplished by a digital-to-digital pulse (D / P) converter to convert the external digital input into one or more digital pulses mapped to the input VMM system 32a.

[0112] The output generated by the input VMM system 32a is provided as an input to the next VMM system (hidden level 1) 32b, which in turn generates an output provided as an input to the next VMM system (hidden level 2) 32c, and so on. The layers of the VMM system 32 serve as different layers of synapses and neurons of a convolutional neural network (CNN). Each VMM system 32a, 32b, 32c, 32d and 32e can be an independent physical system including a corresponding non-volatile memory array, or multiple VMM systems can utilize different parts of the same physical non-volatile memory array, or multiple VMM systems can utilize overlapping parts of the same physical non-volatile memory array. Each VMM system 32a, 32b, 32c, 32d and 32e can also be time-division multiplexed for different parts of its array or neurons. Fig.10 The example shown includes five layers (32a, 32b, 32c, 32d, 32e): one input layer (32a), two hidden layers (32b, 32c) and two fully connected layers (32d, 32e). Those of ordinary skill in the art will appreciate that this is merely exemplary and that, on the contrary, the system may include more than two hidden layers and more than two fully connected layers.

[0113] VMM Array

[0114] Fig.11 A neuron VMM array 1100 is shown, which is particularly suitable for Figure 3 The memory cells 310 shown are used as synapses and components of neurons between the input layer and the next layer. The VMM array 1100 includes a memory array 1101 of nonvolatile memory cells and a reference array 1102 of nonvolatile reference memory cells (at the top of the array). Alternatively, another reference array can be placed at the bottom.

[0115] In the VMM array 1100, control gate lines (such as control gate line 1103) extend in the vertical direction (so reference array 1102 is orthogonal to control gate line 1103 in the row direction), and erase gate lines (such as erase gate line 1104) extend in the horizontal direction. Here, the inputs of the VMM array 1100 are set on the control gate lines (CG0, CG1, CG2, CG3), and the outputs of the VMM array 1100 appear on the source lines (SL0, SL1). In one embodiment, only even rows are used, and in another embodiment, only odd rows are used. The current placed on each source line (SL0, SL1, respectively) performs a summing function of all currents from the memory cells connected to that particular source line.

[0116] As described herein for neural networks, the non-volatile memory cells of VMM array 1100 (ie, the flash memory of VMM array 1100) are preferably configured to operate in a sub-threshold region.

[0117] Biasing the nonvolatile reference memory cell and the nonvolatile memory cell described herein in weak inversion:

[0118] Ids=Io*e (Vg-Vth) / nVt =w*Io*e (Vg) / nVt ,

[0119] where w = e (-Vth) / nVt

[0120] Where Ids is the drain to source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the temperature in Kelvin, and q is the electron charge; n is the slope factor = 1+(Cdep / Cox), where Cdep = the capacitance of the depletion layer, and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is related to (Wt / L)*u*Cox*(n-1)*Vt 2 is proportional to , where u is the carrier mobility, and Wt and L are the width and length of the memory cell, respectively.

[0121] For an I to V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert an input current Ids to an input voltage Vg:

[0122] Vg=n*Vt*log[Ids / wp*Io]

[0123] Here, wp is w of a reference memory cell or a peripheral memory cell.

[0124] For an I to V logarithmic converter that uses a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor to convert an input current Ids to an input voltage Vg:

[0125] Vg=n*Vt*log[Ids / wp*Io]

[0126] Here, wp is w of a reference memory cell or a peripheral memory cell.

[0127] For a memory array used as a vector matrix multiplier VMM array, the output current is:

[0128] Iout=wa*Io*e (Vg) / nVt ,Right now

[0129] Iout=(wa / wp)*Iin=W*Iin

[0130] W=e (Vthp-Vtha) / nVt

[0131] Iin=wp*Io*e (Vg) / nVt

[0132] Here, wa = w for each memory cell in the memory array.

[0133] The word line or control gate may be used as the input of the memory cell for the input voltage.

[0134] Alternatively, the non-volatile memory cells of the VMM array described herein may be configured to operate in the linear region:

[0135] Ids=β*(Vgs-Vth)*Vds; β=u*Cox*Wt / L,

[0136] Wα(Vgs-Vth),

[0137] This means that the weight W in the linear region is proportional to (Vgs-Vth)

[0138] The word line or control gate or bit line or source line can be used as the input of the memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0139] For an I to V linear converter, a memory cell (eg, a reference memory cell or a peripheral memory cell) or a transistor or a resistor operating in a linear region may be used to linearly convert an input / output current into an input / output voltage.

[0140] Alternatively, the memory cells of the VMM array described herein may be configured to operate in the saturation region:

[0141] Ids=1 / 2*β*(Vgs-Vth)2 ; β=u*Cox*Wt / L

[0142] Wα(Vgs-Vth) 2 , which means weight W and (Vgs-Vth) 2 Proportional

[0143] The word line, control gate, or erase gate can be used as the input of the memory cell operating in the saturation region. The bit line or source line can be used as the output of the output neuron.

[0144] Alternatively, the memory cells of the VMM arrays described herein may be used in all regions or a combination thereof (subthreshold, linear, or saturation regions).

[0145] U.S. Patent Application 15 / 826,345 describes Fig. 9 Other embodiments of the VMM array 33 of , which is incorporated herein by reference. As described herein, source lines or bit lines can be used as neuron outputs (current summing outputs).

[0146] Fig.12 A neuron VMM array 1200 is shown, which is particularly suitable for Figure 2 1 and 2. The memory cell 210 shown in FIG. 1 is a memory cell 210 of FIG. 1 , and serves as a synapse between an input layer and a next layer. The VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of a first nonvolatile reference memory cell, and a reference array 1202 of a second nonvolatile reference memory cell. The reference arrays 1201 and 1202 arranged along the column direction of the array are used to convert the current input flowing into the terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected through a multiplexer 1214 (only partially shown), in which the current input flows. The reference cells are tuned (e.g., programmed) to a target reference level. The target reference level is provided by a reference microarray matrix (not shown).

[0147] The memory array 1203 serves two purposes. First, it stores the weights that the VMM array 1200 will use on its corresponding memory cells. Second, the memory array 1203 effectively multiplies the inputs (i.e., the current inputs provided in the terminals BLR0, BLR1, BLR2, and BLR3, which the reference arrays 1201 and 1202 convert into input voltages to provide to the word lines WL0, WL1, WL2, and WL3) by the weights stored in the memory array 1203, and then adds all the results (memory cell currents) to produce an output on the corresponding bit lines (BL0-BLN), which will be the input of the next layer or the input of the final layer. By performing multiplication and addition functions, the memory array 1203 eliminates the need for separate multiplication and addition logic circuits and is also highly power-efficient. Here, the voltage inputs are provided on the word lines (WL0, WL1, WL2, and WL3), and the outputs appear on the corresponding bit lines (BL0-BLN) during the read (inference) operation. The current placed on each of the bit lines BL0-BLN performs a summing function of the currents from all of the nonvolatile memory cells connected to that particular bit line.

[0148] Table 5 shows the operating voltages for the VMM array 1200. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell, where FLT indicates floating, i.e., no voltage is applied. The rows indicate read, erase, and program operations.

[0149] Table 5: Fig.12 Operation of the VMM array 1200

[0150] WL WL-Not selected BL BL-Not selected SL SL-Not selected Read 0.5-3.5V -0.5V / 0V 0.1-2V(Ineuron) 0.6V-2V / FLT 0V 0V Erase About 5-13V 0V 0V 0V 0V 0V programming 1V-2V -0.5V / 0V 0.1-3uA Vinh about 2.5V 4-10V 0-1V / FLT

[0151] Fig.13 A neuron VMM array 1300 is shown, which is particularly suitable for Figure 21 and 2. The memory cell 210 shown in FIG. 1 is a memory cell 210, and serves as a synapse and component of a neuron between an input layer and a next layer. The VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of a first nonvolatile reference memory cell, and a reference array 1302 of a second nonvolatile reference memory cell. The reference arrays 1301 and 1302 extend in the row direction of the VMM array 1300. The VMM array is similar to the VMM 1000, except that in the VMM array 1300, the word lines extend in the vertical direction. Here, the input is set on the word lines (WLA0, WLB0, WLA1, WLB2, WLA2, WLB2, WLA3, WLB3), and the output appears on the source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summing function of all currents from the memory cells connected to that particular source line.

[0152] Table 6 shows the operating voltages for the VMM array 1300. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0153] Table 6: Fig.13 Operation of the VMM array 1300

[0154] WL WL-Not selected BL BL-Not selected SL SL-Not selected Read 0.5-3.5V -0.5V / 0V 0.1-2V 0.1V-2V / FLT About 0.3-1V (Ineuron) 0V Erase About 5-13V 0V 0V 0V 0V SL-Prohibit (about 4-8V) programming 1V-2V -0.5V / 0V 0.1-3uA Vinh about 2.5V 4-10V 0-1V / FLT

[0155] Fig.14 A neuron VMM array 1400 is shown, which is particularly suitable for Figure 3 Memory cell 310 shown, and used as a synapse and component of neurons between the input layer and the next layer. VMM array 1400 includes a memory array 1403 of nonvolatile memory cells, a reference array 1401 of a first nonvolatile reference memory cell, and a reference array 1402 of a second nonvolatile reference memory cell. Reference arrays 1401 and 1402 are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first nonvolatile reference memory cell and the second nonvolatile reference memory cell are diode-connected through a multiplexer 1412 (only partially shown), wherein the current input flows into them through BLR0, BLR1, BLR2, and BLR3. Multiplexers 1412 each include a respective multiplexer 1405 and cascode transistor 1404 to ensure a constant voltage on a bit line (such as BLR0) of each of the first and second nonvolatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0156] The memory array 1403 serves two purposes. First, it stores weights to be used by the VMM array 1400. Second, the memory array 1403 effectively multiplies the inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which are converted by reference arrays 1401 and 1402 into input voltages to be provided to control gates CG0, CG1, CG2, and CG3) by the weights stored in the memory array, and then adds all the results (cell currents) to produce an output, which appears in BL0-BLN and will be the input to the next layer or the input to the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also highly power-efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear on the bit lines (BL0-BLN) during a read operation. The current placed on each bit line performs a summing function of all currents from the memory cells connected to that particular bit line.

[0157] The VMM array 1400 implements unidirectional tuning for the non-volatile memory cells in the memory array 1403. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. This can be performed, for example, using the precision programming techniques described below. If too much charge is placed on the floating gate (causing the wrong value to be stored in the cell), the cell must be erased and the sequence of partial programming operations must be restarted. As shown, two rows sharing the same erase gate (such as EG0 or EG1) need to be erased together (which is called a page erase), and thereafter, each cell is partially programmed until the desired charge on the floating gate is reached.

[0158] Table 7 shows the operating voltages for the VMM array 1400. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0159] Table 7: Fig.14 Operation of the VMM array 1400

[0160]

[0161] Fig.15 A neuron VMM array 1500 is shown, which is particularly suitable for Figure 3The memory cell 310 shown is used as a synapse and component of the neurons between the input layer and the next layer. The VMM array 1500 includes a memory array 1503 of nonvolatile memory cells, a reference array 1501 of a first nonvolatile reference memory cell, and a reference array 1502 of a second nonvolatile reference memory cell. The EG lines EGR0, EG0, EG1, and EGR1 extend vertically, while the CG lines CG0, CG1, CG2, and CG3 and the SL lines WL0, WL1, WL2, and WL3 extend horizontally. The VMM array 1500 is similar to the VMM array 1400, except that the VMM array 1500 implements bidirectional tuning, where each individual cell can be fully erased, partially programmed, and partially erased as needed to achieve a desired amount of charge on the floating gate due to the use of a separate EG line. As shown, reference arrays 1501 and 1502 convert input currents in terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the row direction (through the action of the reference cells connected via the diodes of multiplexer 1514). The current outputs (neurons) are in bit lines BL0-BLN, where each bit line sums all currents from the non-volatile memory cells connected to that particular bit line.

[0162] Table 8 shows the operating voltages for the VMM array 1500. The columns in the table indicate the voltages placed on the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector than the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, the source line for an unselected cell. The rows indicate read, erase, and program operations.

[0163] Table 8: Fig.15 Operation of the VMM Array 1500

[0164]

[0165] Fig.16 A neuron VMM array 1600 is shown, which is particularly suitable for Figure 2 The memory cell 210 shown in FIG. 1 is used as a synapse and component of neurons between the input layer and the next layer. In the VMM array 1600, the inputs INPUT0, ..., INPUT N On bit lines BL0, BL N The signals are received on the source lines SL0, SL1, SL2 and SL3, and outputs OUTPUT1, OUTPUT2, OUTPUT3 and OUTPUT4 are generated on the source lines SL0, SL1, SL2 and SL3, respectively.

[0166] Fig.17 A neuron VMM array 1700 is shown, which is particularly suitable for Figure 2 The memory cell 210 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, inputs INPUT0, INPUT1, INPUT2 and INPUT3 are received on source lines SL0, SL1, SL2 and SL3, respectively, and outputs OUTPUT0, ... OUTPUT N On bit lines BL0, ..., BL N Generate on.

[0167] Fig.18 A neuron VMM array 1800 is shown, which is particularly suitable for Figure 2 The memory unit 210 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, inputs INPUT0, ..., INPUT M On word lines WL0,…,WL M is received and output OUTPUT0,…OUTPUT N On bit lines BL0, ..., BL N Generate on.

[0168] Fig.19 A neuron VMM array 1900 is shown, which is particularly suitable for Figure 3 The memory unit 310 shown in FIG. 1 is used as a synapse and a component of a neuron between an input layer and a next layer. In this example, inputs INPUT0, ..., INPUT M On word lines WL0,…,WL M is received and output OUTPUT0,…OUTPUT N On bit lines BL0, ..., BL N Generate on.

[0169] Fig. 20 A neuron VMM array 2000 is shown, which is particularly suitable for Figure 4 The memory unit 410 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the input INPUT0, ..., INPUT n On the vertical control gate lines CG0,...,CG N The signals are received on the source lines SL0 and SL1, and outputs OUTPUT1 and OUTPUT2 are generated on the source lines SL0 and SL1.

[0170] Fig.21 A neuron VMM array 2100 is shown, which is particularly suitable for Figure 4 The memory unit 410 shown in FIG. 4 is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the input INPUT0 to INPUT N are received at the gates of bit line control gates 2901-1, 2901-2 to 2901-(N-1), and 2901-N, which are coupled to bit lines BL0 to BL N Exemplary outputs OUTPUT1 and OUTPUT2 are generated on source lines SL0 and SL1.

[0171] Fig. 22 A neuron VMM array 2200 is shown, which is particularly suitable for Figure 3 The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7 The memory unit 710 shown is used as a synapse and component of the neurons between the input layer and the next layer. In this example, the inputs INPUT0, ..., INPUT M On word lines WL0, ..., WL M are received and output OUTPUT0,…,OUTPUT N On bit lines BL0, ..., BL N Generate on.

[0172] Fig.23 A neuron VMM array 2300 is shown, which is particularly suitable for Figure 3 The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7 The memory cell 710 shown in FIG. 1 is used as a synapse and component of neurons between the input layer and the next layer. In this example, the input INPUT0 to INPUT M On the control gate lines CG0 to CG M The outputs OUTPUT0, ..., OUTPUT N On the vertical source lines SL0, ..., SL N Each source line SL i The source line coupled to all memory cells in column i.

[0173] Fig.24 A neuron VMM array 2400 is shown, which is particularly suitable for Figure 3 The memory unit 310 shown, Figure 5 The memory cell 510 and Figure 7The memory cell 710 shown in FIG. 1 is used as a synapse and component of neurons between the input layer and the next layer. In this example, the input INPUT0 to INPUT M On the control gate lines CG0 to CG M The outputs OUTPUT0, ..., OUTPUT N On the vertical bit lines BL0, ..., BL N On generation, each bit line BL i The bit line coupled to all memory cells in column i.

[0174] Test circuit and method

[0175] Fig.25 A VMM system 2500 is shown. The VMM system 2500 includes a VMM array 2501 (which may be based on any of the previously discussed VMM array designs, such as VMM arrays 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900, 2000, 2100, 2200, 2300, and 2400 or other VMM array designs), a low voltage row decoder 2502, a high voltage row decoder 2503, a column decoder 2504, a column driver 2505, control logic 2506, a bias circuit 2507, an output circuit block 2508, an input VMM circuit block 2509, an algorithm controller 2510, a high voltage generator block 2511, an analog circuit block 2515, a control logic 2516, and a test control logic 2517.

[0176] The input circuit block 2509 is used as an interface for input from the outside to the input terminal of the memory array 2501. The input circuit block 2509 may include, but is not limited to, a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter), an APC (analog-to-pulse converter), an IVC (current-to-voltage converter), an AAC (analog-to-analog converter, such as a voltage-to-voltage scaler), or a FAC (frequency-to-analog converter). The output circuit block 2508 is used as an interface for output from the memory array to an external interface (not shown). The output circuit block 2508 may include, but is not limited to, an ADC (analog-to-digital converter), an APC (analog-to-pulse converter), a DPC (digital-to-pulse converter), an IVC (current-to-voltage converter), or an IFC (current-to-frequency converter). The output circuit block 2508 may include, but is not limited to, an activation function, a normalization circuit, and / or a rescaling circuit.

[0177] The low voltage row decoder 2502 provides a bias voltage for a read operation and a program operation, and provides a decoding signal for the high voltage row decoder 2503. The high voltage row decoder 2503 provides a high voltage bias signal for a program operation and an erase operation.

[0178] The algorithm controller 2510 provides control functions for the bit lines during programming, verifying, and erasing operations.

[0179] The high voltage generator block 2511 includes a charge pump 2512, a charge pump regulator 2513, and a high voltage generating circuit 2514, which provides multiple voltages required for various programming, erasing, program verification, and reading operations.

[0180] Test control logic 2517 includes the following references for executing Figure 26 to Figure 31 Various test control circuits for the tests described.

[0181] Fig.26 A reference current source 2600 is shown for use during a verify operation following a programming operation of one or more nonvolatile memory cells, or during other types of testing. For example, the reference current source 2600 can be used for a verify operation of a single nonvolatile memory cell, or for a verify operation of a column of nonvolatile memory cells (e.g., all cells connected to a particular bit line), or some other grouping of nonvolatile memory cells.

[0182] The reference current source 2600 includes a buffer mirror 2601 (the buffer mirror includes an output I REF 2607), an adjustable bias source 2604, and a two-dimensional array 2605, which includes an array of i rows and j columns of devices 2606, where a particular device 2606 is labeled by the label 2606-(row)(column). Here, various combinations of devices 2606 can be activated so that the reference current I output by the buffer mirror 2601 can be adjusted. REF 2607. As shown, there are 16 devices 2606 in array 2605, each of which can be implemented by a current mirror. Reference current source 2600 basically converts the 4 digital inputs into a reference current bias whose value is 1 to 16 times Ibiasunit, where Ibiasunit is provided from bias source 2604. Reference current source 2600 is basically a thermometer-coded digital-to-current converter whose buffered output I REF The value of 2607 corresponds to 1 of 16 levels, the particular level being responsive to the 4 digital inputs, which may be stored by a memory cell in any of the VMM arrays discussed previously.

[0183] For example, bias source 2604 can provide a 1 nA current Ibiasunit, which is mirrored into device 2606. Here, the first row consists of devices 2606-11 to 2606-1j, and are enabled sequentially from left to right, one device 2606 at a time. The next row is then enabled in a sequential manner from left to right to add to the first row, which means that 5, then 6, then 7, then 8 devices 2606 are enabled. By enabling devices 2606 sequentially, transistor mismatch issues associated with conventional binary decoding can be avoided. The sum of enabled devices 2606 is then mirrored by buffer mirror 2601, and the output is a current I REF 2607. The bias source 2604 may provide a finely adjustable current Ibiasunit range, such as 50pA / 100pA / 200pA / ... / 100nA. Here, the array 2605 is shown as a 4×4 array, but it should be understood that the array 2605 may have other sizes, such as 32×32 or 8×32.

[0184] Fig. 27 A reference subcircuit 2700 is shown, which can be used to Fig.26 The reference subcircuit 2700 includes NMOS transistors 2701 and 2702 configured as shown. Transistor 2702 is a current mirror bias transistor that receives a current Ibiasunit (described above with reference to FIG. 1 ) at its gate. Fig.26 Discussion), and transistor 2701 is an enable transistor (to enable current mirror bias transistor 2702 to be connected to output node OUTPUT). Current Ibiasunit is provided, such as from a diode-connected NMOS transistor (similar to transistor 2702) (not shown).

[0185] Fig.28 Sense amplifier 2800 is shown used with reference current source 2600 during a verify operation following a programming operation of a nonvolatile memory cell, a column of nonvolatile memory cells, or some other grouping of nonvolatile memory cells, or during another type of testing. Sense amplifier 2800 receives reference current source 2600 as described above. Fig.26 The current I discussed REF 2607.I REF 2607 can be modeled as a PMOS transistor 2813, where the gate is composed of VI REF2814 controls. The sense amplifier 2800 further includes an inverter 2801, a current source 2802 (the current source is used to limit the current in the inverter 2801), switches 2803 and 2806, a capacitor 2804, and a cascaded NMOS transistor 2805 (to apply a fixed voltage on the memory bit line). The sense amplifier 2800 receives a current I from the reference current source 2600. REF 2607, which may be one of sixteen possible levels stored in a nonvolatile memory cell of a VMM array, for example. Sense amplifier 2800 is coupled to cell 2808, which is a nonvolatile memory cell whose contents are to be verified. When NMOS transistor 2805 is turned on, cell 2808 consumes current I CELL Alternatively, cell 2808 may be replaced by column 2809 (which, for the sake of convenience in the drawing, will consume the memory and will still be referred to as I CELL current, which should be the neuronal current consumed by column 2809).

[0186] In one embodiment, I REF 2607 starts at the lowest possible value (e.g., the lowest value of 16 possible levels that can be stored in cell 2808 or in column 2809), and then increases to each subsequent level in sequence for the verification operation. Switch 2806 can be closed to create an initial state for capacitor 2804 (such as ground or a precharge voltage to provide offset cancellation). Switch 2803 can be closed to equalize the input and output of inverter 2801, thereby removing the offset from inverter 2801 for comparison in the verification operation. During the verification operation, switches 2806 and 2803 are opened. If I CELL >=I REF 2607, the voltage on node 2810 will decrease, which in turn is capacitively coupled through capacitor 2804, causing the voltage on node 2811 to decrease, thereby causing the inverter output to switch to "1", which means that the input of inverter 2801 will be a "0" value and the output of inverter 2801 will be a "1" value. If I CELL REF 2607, the voltage on node 2810 will increase, which in turn is capacitively coupled through capacitor 2804, causing the voltage on node 2811 to increase, causing the inverter output to switch to "0", which means that the input of inverter 2801 will switch to a "1" value and the output of inverter 2801 will switch to a "0" value. REF The value of 2807 corresponds to the value stored in unit 2808.

[0187] Fig.29A ​A verification ramp analog-to-digital converter (ADC) 2900 is shown used with a reference current source 2600 during a verification operation of a nonvolatile memory cell 2930 or column 2931 following a programming pulse operation (such as to verify that the memory cell has reached a target current during a weight tuning process) or during another type of testing (such as to verify a truncated memory bit (e.g., an abnormal bit) in a memory array that fails to meet cell current requirements). CELL 2906 is the output current from cell 2930 or column 2931. Verify that ADC 2900 converts I CELL 2906 is converted into a series of digital output bits that are output as output 2940, where output 2940 indicates the value stored in cell 2930 or column 2931.

[0188] Verification ADC 2900 includes an operational amplifier 2901, an adjustable capacitor 2902, an operational amplifier 2904, a counter 2920, and switches 2908, 2909, and 2910. Adjustable capacitor 2902 CELL 2906 is relative to the current I provided by the adjustable current source 2807 REF During the initialization phase, switch 2908 is closed. Vout 2903 of op amp 2901 and the input to the inverting input of op amp 2901 will become equal to the value of reference voltage VREF applied to the non-inverting input of op amp 2901. Thereafter, switch 2908 is opened, and during a fixed time period tref, switch 2910 is closed, and the neuron current I CELL 2906 is integrated up. During the fixed time period tref, Vout 2903 increases, and its slope reflects I CELL Thereafter, during the time period tmeas, by opening the switch 2910 and closing the switch 2909, the constant reference current I provided by the adjustable current source 2807 is REF is integrated down (during which Vout falls), where tmeas is the time required to integrate Vout down to VREF.

[0189] When VOUT 2903>VREF, the output EC 2905 of the operational amplifier 2904 will be high, otherwise it will be low. EC 2905 thus generates a pulse whose width reflects the time period tmeas, which in turn is related to the current I CELL 2906 in proportion.

[0190] Optionally, output EC 2905 is input to counter 2920 which counts the number of clock pulses 2921 received while output EC 2905 is high and will generate output 2940 which will be a set of digital bits representing a digital count of the number of clock pulses 2921 that occurred while EC 2905 was high, which is the same as the I corresponding to the value stored in cell 2930 or column 2931. CELL Directly proportional to 2906.

[0191] Fig.29B A verification ramp analog-to-digital converter 2950 is shown, which includes a current source 2953 (which represents the received neuron current Ineu or a single memory cell current), a switch 2954, a variable capacitor 2952, and a comparator 2951, which receives a voltage (denoted as Vneu) formed across the variable capacitor 2952 at its non-inverting input and receives a configurable reference voltage Vreframp at its inverting input, and generates an output Cout. The circuit for clearing the voltage across the variable capacitor 2952 is not shown. Vreframp ramps up (increases) at a discrete level with each comparison clock cycle. Comparator 2951 compares Vneu with Vreframp, and therefore when Vneu>Vreframp, the output Cout will be "1", and otherwise it will be "0". Therefore, the output Cout will be a pulse whose width varies in response to the value of Ineu. A larger Ineu will cause Cout to be "1" for a longer period of time, that is, the pulse of the output Cout is wider. The digital counter 2960 converts the output Cout into digital output bits DO[n:0] 2970, which reflect the number of clock cycles 2961 during which Cout is a "1" value. Alternatively, the ramp voltage Vreframp is a continuous ramp voltage. A multi-slope implementation scheme for reducing conversion time by utilizing a coarse-fine ramp conversion algorithm can be implemented. The first coarse reference ramp reference voltage is ramped in a fast manner to figure out each sub-range of Ineu. Next, a fine reference ramp reference voltage is used for each sub-range to convert the Ineu current within the corresponding sub-range. More than two coarse / fine steps or more than two sub-ranges are possible.

[0192] Other ADC architectures may be used as the verification ADC, such as, but not limited to, Flash ADC, SAR (Successive Approximation Register) ADC, Algorithmic ADC, Pipeline ADC, Sigma Delta ADC.

[0193] Fig.30 Show previous reference Fig.253003. The high voltage generation circuit 2511 described above is an embodiment of a high voltage generation circuit 2511. The high voltage generation circuit 2511 can be used with any of the VMM arrays previously discussed. The high voltage generation circuit 2511 includes a charge pump 2512 and a high voltage generation circuit 2514. The charge pump 2512 receives an input 3004 and generates a high voltage 3005, which is then provided to high voltage generators 3002 and 3003. The high voltage (HV) generator (HVDAC_EG) 3002 is a HV digital-to-analog converter that provides a voltage (denoted as V EG 3008), such as an incremental voltage suitable for application to the erase gate terminal of the split-gate flash memory cell in response to the digital bit 3006 and the received high voltage 3005. The high voltage generator (HVDAC CGSL) 3003 is a HV digital-to-analog converter that provides voltages (represented as V CG 3009 and V SL 3010), such as an incremental voltage suitable for being applied to the control gate terminal and source line terminal of the split gate flash memory cell in response to the digital bit 3007 and the received high voltage 3005.

[0194] Fig.31 Show previous reference Fig.25 The VMM system 2500 described above but shown here in a test configuration. Test control logic 2517 provides control logic to other components of the VMM system 2500 (in Fig.25 shown in Fig.31 2504, an input block 2509, a high voltage decoder 2503, a column driver 2505, a high voltage generation block 2511, an analog block 2515, an algorithm controller 2510, and an output circuit block 2508. The VMM array 2501 receives control signals from the row decoder 2502, whereby one or more rows are asserted within the VMM array 2501. The VMM array 2501 provides signals from one or more bit lines to the column decoder 2504, and then provides outputs from the one or more bit lines to the output circuit block 2508. The output circuit block 2508 may include an analog-to-digital converter block (such as previously described). Fig.29A Verification of ADC 2900 as described or previously referenced Fig.29B Verification ramp ADC 2950 described above), which provides a digital output representing the analog current received by output circuit block 2508 from VMM array 2501.

[0195] Table 9 contains exemplary values ​​for word lines, control gate lines, erase gate lines, source gate lines, and bit lines within the VMM array 2501 during the following operations, including: program, erase, read, and verify operations performed on individual memory cells; verify neuron and read neuron operations performed on selected bit lines coupled to columns of memory cells; and read array operations whereby each bit line is read (where each bit line is coupled to a column of memory cells).

[0196] Table 9: Example values ​​for operations within VMM array 2501

[0197] WL CG EG SL BL Selected Unselected Selected Unselected Selected Unselected Selected Unselected Selected Unselected programming 0.9V 0v Up to 10.5V 0v Up to 4.5V 0v Up to 4.5V About 0.5v Iprog Vinh Erase 0v 0v 0v 0v 6V-11.5V 0v 0v 0v 0v 0v Read 1.1V 0v 2.5V 2.5V 2.5V 2.5V 0v 0v 0.6V 0v Verify Neuron 1.1V 0v 0V-1.5V 0v 0V 0v 0v 0v 0.6V 0v Reading neurons 1.1V 1.1V 0V-1.5V 0V-1.5V 0V 0V 0v 0V 0.6V 0.6V Reading array 1.1V 1.1V 0V-1.5V 0V-1.5V 0V 0V 0v 0V 0.6V 0v

[0198] Now we will provide reference Fig.31 The test algorithm 3100 shown in FIG. 31 is executed and Figures 32 to 44 The tests are implemented by test control logic 2517 and other components of VMM system 2500, with further details on the types of tests further described in detail in FIG. 25 .

[0199] refer to Fig.32 , the bit line neural read test 3101 measures the values ​​in all memory cells coupled to the bit line simultaneously. That is, the bit line neural read test 3101 reads the neurons in the VMM array. First, the row decoder 2502 asserts all word lines in the array (step 3201). Second, the bit line is selected (asserted) by the column decoder 2504 (step 3202). Third, a read is performed on the bit line, such as by sensing the current received from the bit line by the sense amplifier 2800 (step 3203). Fourth, the value of the selected bit line can be determined by comparing the reference current generated by the reference current source 2600 to determine whether the non-volatile memory cell (i.e., neuron) coupled to the selected bit line contains the expected value (step 3204).

[0200] refer to Fig.33 , the bit line neural measurement test 3102 is similar to the bit line neural read test 3101. The row decoder 2502 asserts all word lines (step 3301). A bit line is selected by the column decoder 2504 (step 3302). The current consumed by the bit line during the read operation is measured (step 3303). Here, unlike the bit line neural read test 3101, the current from the selected bit line is measured without comparison to a reference current.

[0201] refer to Fig.34, during the LSB screening test 3103, the row decoder 2502 asserts all word lines (step 3401), and the column decoder 2504 asserts all bit lines (step 3402). Deep programming is performed on all memory cells in the VMM array 2501 (step 3403). Deep programming will program all memory cells that are beyond the normal programming state used to infer the reading. This deep programming is done with a longer programming time or a higher programming voltage than is typically used in normal operation. The total current received from all bit lines is then measured (step 3404). It is expected that the total current of the deeply programmed array will be much less than the LSB value. In addition, each individual cell is checked to ensure that the current from the individual cell is also below the LSB value, such as 50-100pA. This type of test is suitable for testing during the manufacturing process to quickly identify bad dies.

[0202] refer to Fig.35 During the bit line sampling screening test 3104, a memory cell or a group of memory cells are programmed to a specific level, such as Lx, where x ranges from 1 to N, where N is the total number of levels that can be stored in the cell (e.g., N=16) (step 3501). The bit line current (the current consumed by a cell or a group of cells in the selected bit line, referred to as I BL )K times (step 3502). For example, if K=8, the bit line current is measured 8 times. Then, based on the K measured values ​​(i.e., I BL1 …I BLK )Calculate the average value (I AVG )(Step 3503).

[0203] Next, relative to I AVG Check K current measurements I BL1 …I BLK Each measurement value in (step 3504). If I BLi (where i ranges from i to K)>(I AVG +Threshold 3505) or I BLi <(I AVG -threshold 3506), then the bit line is considered bad. Each cell in the bad bit line is then checked and the bad cell is replaced with a redundant cell (such a cell from a redundant row or redundant column).

[0204] Fig.36 Another embodiment of the bit line sampling screening test 3104 is shown. The voltage V is measured by forcing the current Iref into the bit line at K different times. CG (Step 3601). For example, the voltage V CG until the bit line current matches the fixed Iref and that particular VCG The fixed Iref may be provided by the reference current source 2600, and the operation of verifying whether the bit line current matches the fixed Iref may be performed by the sense amplifier 2800. Then, according to K different V CG The average value V AVG Next, relative to V AVG Check K measured V CG voltages (step 3603). If V CGi (where i ranges from i to K)>(V AVG +Threshold 3604) or V CGi <(V AVG -threshold 3605), the bit line is considered bad. Each cell in the bad bit line is then checked and the bad cell is replaced with a redundant cell (redundant row or redundant column).

[0205] During the read trip point test 3105, coarse and fine read reference current trimming is performed using different levels of Iref in the read operation. The purpose of the read trip point test 3105 is to find out whether the selected memory cell can pass a predetermined current percentage target, such as about 40% of fully erased cells for erased cells or about 5% of fully programmed cells for programmed cells. This ensures that the memory cells are within the main distribution and not within the clipped memory cells or clipped bits (i.e., statistical outliers) that may cause potential reliability issues over the operating lifetime.

[0206] refer to Fig.37 During the read window check test 3107, the cell is tested to ensure that it can store each of the N possible levels. First, the cell is programmed to a target value representing one of the N values ​​(step 3701). Next, a verification operation is performed to determine whether the value stored in the cell is within an acceptable value window 3710 around the target value (step 3702). Steps 3701 and 3702 are repeated for each of the N values ​​(step 3703). For each N value, the acceptable window 3710 can be different. If any instance of step 3702 being performed indicates that the value stored in the cell is outside the acceptable value window around the target value, the cell is identified as bad. The read window check test 3107 can be performed by the sense amplifier 2800, the ADC 2900, the ADC2950, ​​or another component. This may be useful for performing weight tuning on the memory cell. While the above has been explained in an embodiment in which a fixed window is used for each of N values ​​centered around a nominal value, it will be appreciated that in another embodiment, a higher threshold and a lower threshold are used for each of the N values, and these thresholds need not be the same between all N values, yet not be out of range.

[0207] refer to Fig.38 During a read calibration test 3108, leakage of a cell or a group of cells (such as cells coupled to a bit line) is measured (step 3801), and the measured leakage value is stored (I LEAKAGE )(step 3802), and later during a read operation the measured leakage values ​​are used to compensate for leakage under various combinations of process / voltage / temperature (PVT) (step 3803). In one embodiment, multiple cells are programmed separately with known values. The word lines and control gate lines are set to ground, and the bit lines are set to a read bias voltage. A series of different reference currents are injected into the array, and the resulting data reads are read by a sense amplifier, such as ADC circuit 2900 or 2950 or sense amplifier 2800. The injected current that produces the best result (compared to the known value programmed into the cell) is stored as I LEAKAGE Then, during a read operation on the same cell, I is applied LEAKAGE , for example by subtracting the stored leakage level from the conversion data during a read operation to compensate for leakage occurring within the selected cell.

[0208] refer to Fig.39 , during the read slope test 3109, the IV slope factor of the control gate voltage relative to two reference currents, CG1 at current IR1 and CG2 at current IR2, is determined. The first step is to determine the logarithmic slope factor of the selected nonvolatile memory cell when the selected nonvolatile memory cell operates in the subthreshold region (step 3901). The second step is to store the logarithmic slope factor (step 3902). The third step is to determine the linear slope factor of the selected nonvolatile memory cell when the selected nonvolatile memory cell operates in the linear region (step 3903). The fourth step is to store the linear slope factor (step 3904). The fifth step is to utilize one or more of the logarithmic slope factor and the linear slope factor when programming the selected cell to the target current (step 3905).

[0209] refer to Fig.40 , during the read neuron quality qualification test 3110, neurons (bit lines) are read without checking the value relative to an expected value. The first step is to measure the current in the bit line and store the measured value (step 4001). The second step is to perform the read virtual neuron test 4010 as described below within a predetermined amount of time, such as a burn-in time during the quality qualification process. The third step is to measure the current from the bit line (step 4003). The fourth step is to compare the measured current to the stored measured current from step 4001 (step 4004). If the difference is greater or less than a certain amount, then the bit line is considered a bad bit line.

[0210] The read virtual neuron test 4010 includes a series of steps. The first step is to assert all word lines in the array by the row decoder (step 4011). The second step is to assert all bit lines in the array by the column decoder to select all columns of non-volatile memory cells (step 4012). The third step is to perform a read operation (read condition) on the array without checking the read output (step 4013). The read virtual neuron test 4010 is used as a read stress on the array for burn-in purposes.

[0211] refer to Fig.41 During the soft erase test 3111, the entire array or a sector is tested to check the erase performance of the memory array. The first step is to erase the non-volatile memory cells in the array by applying a series of voltages to the terminals of each non-volatile memory cell in the array, wherein the voltage in the series of voltages increases over time in fixed steps (step 4101). This erases the cells in an incremental manner, for example, by increasing the voltage on the erase gate in a stepwise manner between 5 volts and 12.5 volts in steps of, for example, 0.5 volts or 1 volt. Erasing in this manner reduces the stress on the memory cells. The second step is to read all non-volatile memory cells to determine the effectiveness of the erase step (step 4102), for example by determining that the cell current after the erase step 4101 is within an acceptable window around the nominal value. Optionally, an endurance test can be performed to determine how many program / erase cycles can be maintained, or a background test can be performed to transition the array to an erased state.

[0212] refer to Fig.42 During the soft programming test 3112, the entire array or a row or a cell is tested. The first step is to program the non-volatile memory cells in the array by applying a series of voltages to the terminals of each non-volatile memory cell in the array, where the voltage in the series of voltages increases over time in fixed steps (step 4201). The cells are programmed in an incremental manner, for example, in steps of 10mV or 0.3V or 1V between 3 volts and 10 volts to check the programming performance of the memory array. Programming in this manner reduces the stress on the memory cells. The second step is to read all non-volatile memory cells to determine the effectiveness of the programming step (step 4202), for example by determining that the cell current after the programming step 4201 is within an acceptable window around the nominal value. Optionally, a durability test or background test can be utilized.

[0213] refer to Fig.43, a read verification test 3106 may be performed. The first step is to program a plurality of non-volatile memory cells to store one of N different values, where N is the number of different levels that can be stored in any non-volatile memory cell (step 4301). The second step is to measure the current consumed by the plurality of non-volatile memory cells (step 4302). The third step is to compare the measured current to a target value (step 4303). The fourth step is to identify the plurality of non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold factor (step 4304).

[0214] refer to Fig.44 , a checkerboard verification test 3113 may be performed whereby a checkerboard or pseudo-checkerboard pattern is used to implement the test pattern and sample levels are measured instead of all possible levels (e.g., 4 levels, L0, Ln, Ln / 4, Ln*3 / 4, instead of all N levels). For example, the pattern may be used to check for worst case electric field stress within a memory array (meaning one cell is at a high electric field level and an adjacent cell is at a low electric field level).

[0215] In one embodiment, the first step is to program a first group of cells among a plurality of non-volatile memory cells using a level corresponding to a minimum cell current among the N levels (step 4401). The second step is to program a second group of cells among a plurality of non-volatile memory cells using a level corresponding to a maximum cell current among the N levels (step 4402). Each cell in the second group of cells is adjacent to one or more cells in the first group of cells. The third step is to measure the current consumed by the plurality of non-volatile memory cells (step 4403). The fourth step is to compare the measured current with a target value (step 4404). The fifth step is to identify the plurality of non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold value (step 4405).

[0216] Table 10 contains other exemplary test patterns of physical array mapping that may be used during checkerboard verification test 3113:

[0217] Table 10: Exemplary test patterns

[0218]

[0219] Sorting test 3114, final test 3115, qualification test 3116, and data retention test 3117 are test suites that may be performed during the manufacturing and qualification process of a wafer, die, or packaged device that includes the VMM system disclosed herein.

[0220] A sorting test 3114 may be performed on the wafer during the manufacturing process. In one embodiment, the sorting test 3114 includes the following test suite: First, relatively fast tests are performed to quickly identify bad wafers or dies, such as soft erase test 3111, soft programming test 3112, and various stress mode tests (such as erase gate oxide gox, coupled gate oxide cox, source line oxide sol, reverse disturbance tunneling rtst (tunneling from floating gate to word line, disturbance to unselected rows), massive punch-through mpt (disturbance from source to drain of unselected rows), read disturbance rdist (disturbance from read conditions)). Second, neural test modes are performed on the top and bottom sectors, such as LSB screening test 3103 and bit line sampling screening 3104. The neural test mode is much more time-consuming than the tests performed during the first step, and some time is saved because bad wafers or dies are screened or identified during the first set of less time-consuming tests.

[0221] A final test 3115 may be performed on the packaged device. In one embodiment, the final test 3115 includes the execution of a soft erase test 3111 and a soft program test 3112. Optionally, test patterns for neural applications may be utilized to reduce test time instead of a comprehensive test, such as testing K of N levels for M sectors, or testing all N levels for certain sectors, such as the top and bottom sectors.

[0222] During the qualification test 3116, a dummy bit line read cycle is performed (which is the execution of a read action without actually determining the content of the read data), and the endurance test is completed by applying a soft erase test 3111 and a soft programming test 3112. The bit line test is performed instead of individual memory cell tests because bit line reads are used during the neural memory application instead of individual memory reads.

[0223] The data retention test 3117 can include, for example, baking the programmed wafer at an elevated temperature (such as 250 degrees Celsius) for 24-72 hours. In one embodiment, a checkerboard or pseudo-checkerboard test pattern is applied rather than performing a full test as with digital memory testing. Data retention on the bit line current is checked in both the neural mode and the read bit line current mode (rather than checking each memory cell as with digital memory). For example, one query is to check if ΔIBL is <+ / -p%, where ΔIBL is defined as the difference between the measured bit line current and the expected bit line current. (WholeBLmeas mode, software neural network modeling allows a percentage error of p% for a target accuracy of the neural network). ΔIBL for neural mode is tested to identify if the bit line output current exceeds or falls below a target, which is defined herein as a predetermined percentage "p" of the target. Alternatively, each cell can be checked / tested with + / -Δ of the target.

[0224] Other tests may be performed using the hardware and algorithms described herein.

[0225] It should be noted that, as used herein, the terms "above" and "on" both inclusively include "directly on" (no intermediate material, element, or space is provided between) and "indirectly on" (intermediate material, element, or space is provided between). Similarly, the term "adjacent" includes "directly adjacent" (no intermediate material, element, or space is provided between) and "indirectly adjacent" (intermediate material, element, or space is provided between), "mounted to" includes "directly mounted to" (no intermediate material, element, or space is provided between) and "indirectly mounted to" (intermediate material, element, or space is provided between), and "electrically coupled to" includes "directly electrically coupled to" (no intermediate material or element electrically connecting the elements together between) and "indirectly electrically coupled to" (intermediate material or element electrically connecting the elements together between). For example, forming an element "above a substrate" may include directly forming the element on the substrate without intermediate materials / elements between the two, and indirectly forming the element on the substrate with one or more intermediate materials / elements between the two.

Claims

1. A method of testing an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, the method comprising: programming a plurality of cells coupled to the bit lines; measuring the current consumed by the plurality of cells at K different times and storing the measured value at each of the K different times, where K is an integer; Calculating an average value based on the K measured values; and If any of the K measured values ​​is less than the average value by more than a first threshold or greater than the average value by more than a second threshold, the bit line is identified as a bad bit line. 2 . The method of claim 1 , wherein each of the nonvolatile memory cells is a stacked-gate flash memory cell.

3. The method of claim 1, wherein each of the non-volatile memory cells is a split-gate flash memory.

4. The method of claim 1, wherein the array is part of a neural network.

5. A method of testing an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bit line, the method comprising: programming a plurality of cells coupled to the bit lines; measuring a voltage on a control gate line coupled to control gate terminals of a plurality of cells at K different times and storing a measured value at each of the K different times, wherein K is an integer; Calculating an average value based on the K measured values; and If any of the K measured values ​​is less than the average value by more than a first threshold or greater than the average value by more than a second threshold, the bit line is identified as a bad bit line.

6. The method of claim 5, wherein each of the non-volatile memory cells is a stacked-gate flash memory cell.

7. The method of claim 5, wherein each of the non-volatile memory cells is a split gate flash memory cell.

8. The method of claim 5, wherein the array is part of a neural network.

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