Display panel and display device

Abstract

A display panel and a display device. The display panel comprises: a base substrate (1); a plurality of pixel units (P2), the plurality of pixel units (P2) being arranged in an array on the base substrate (1), each pixel unit (P2) comprising a pixel driving circuit and a light-emitting device, the pixel driving circuit being used to drive the light-emitting device; a plurality of signal lines (61, 62, 63, 64, 65, 66, 67), the plurality of signal lines (61, 62, 63, 64, 65, 66, 67) being electrically connected to the pixel driving circuit respectively; and a light shielding portion (100) arranged on the base substrate (1). Orthographic projections of at least two signal lines (61, 62, 63, 64, 65, 66, 67) among a plurality of signal lines (61, 62, 63, 64, 65, 66, 67) on the base substrate (1) are separated from each other by a gap (71, 72); the gap (71, 72) causes at least one of interference and diffraction to occur when at least a portion of imaging light passes through the gap (71, 72); and the orthographic projection of the light shielding portion (100) on the base substrate (1) at least covers the orthographic projection of the gap (71, 72) on the base substrate (1).

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display panel and a display device. Background Art

[0002] With increasing user demand for diversified display device usage and the emergence of design requirements for high screen-to-body ratios, the "under-screen camera" solution has emerged. In this "under-screen camera" solution, an imaging module, such as a camera, is embedded within the display area to reduce the size of the display's border area, thereby increasing the screen-to-body ratio. Currently, in this "under-screen camera" solution, while increasing the screen-to-body ratio of the display device, how to ensure the light transmittance and display quality at the location on the display panel corresponding to the imaging module has become a major concern for R&D personnel.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the Invention

[0004] In one aspect, a display panel is provided, comprising:

[0005] substrate;

[0006] A plurality of pixel units, wherein the plurality of pixel units are arranged in an array on the substrate, each of the pixel units includes a pixel driving circuit and a light-emitting device, and the driving circuit structure is used to drive the light-emitting device;

[0007] a plurality of signal lines, each of which is electrically connected to the pixel driving circuit; and

[0008] A light shielding portion is provided on the base substrate,

[0009] The orthographic projections of at least two of the multiple signal lines on the substrate are separated from each other by a gap, and the gap causes at least one of interference and diffraction to occur when at least a portion of the light passes through the gap, and the orthographic projection of the shading portion on the substrate at least covers the orthographic projection of the gap on the substrate.

[0010] According to some exemplary embodiments, the display panel includes a first display area and a second display area, the first display area has a first pixel density, the second display area has a second pixel density, and the first pixel density is greater than the second pixel density;

[0011] The orthographic projection of the light shielding portion on the base substrate is at least located within the orthographic projection of the second display area on the base substrate.

[0012] According to some exemplary embodiments, the gap includes a first gap and a second gap, the first gap is located within the pixel unit in the second display area, and the second gap is located between a plurality of pixel units in the second display area;

[0013] An orthographic projection of the light shielding portion on the base substrate covers an orthographic projection of each of the first gap and the second gap on the base substrate.

[0014] According to some exemplary embodiments, the pixel driving circuit includes a storage capacitor and at least one thin film transistor, each of the thin film transistors includes an active layer, a gate, a source electrode, and a drain electrode, the storage capacitor includes a first capacitor electrode and a second capacitor electrode; the light emitting device includes an anode; the display panel further includes a connecting conductive portion, the connecting conductive portion being configured to electrically connect one of the source electrode and the drain electrode to the anode;

[0015] And the display panel includes:

[0016] a first conductive layer disposed on a side of the active layer away from the base substrate, wherein the gate and the second capacitor electrode are located in the first conductive layer;

[0017] a second conductive layer disposed on a side of the first conductive layer away from the base substrate, wherein the first capacitor electrode is located on the second conductive layer;

[0018] a third conductive layer disposed on a side of the second conductive layer away from the base substrate, wherein the source and the drain are located in the third conductive layer; and

[0019] A fourth conductive layer is provided on a side of the third conductive layer away from the base substrate, and the connecting conductive portion is located in the fourth conductive layer.

[0020] According to some exemplary embodiments, the light shielding portion is located at a layer different from the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer.

[0021] According to some exemplary embodiments, the plurality of signal lines include at least a driving voltage line for supplying a power voltage signal, the driving voltage line is located in the third conductive layer, and the light shielding portion is electrically connected to the driving voltage line.

[0022] According to some exemplary embodiments, the display panel further includes:

[0023] a gate insulating layer disposed between the active layer and the first conductive layer;

[0024] a first interlayer insulating layer disposed between the first conductive layer and the second conductive layer;

[0025] a second interlayer insulating layer disposed between the second conductive layer and the third conductive layer;

[0026] a first planarization layer disposed between the third conductive layer and the fourth conductive layer; and

[0027] A second planarization layer is disposed between the fourth conductive layer and the anode.

[0028] According to some exemplary embodiments, the light shielding portion is located between the active layer and the base substrate.

[0029] According to some exemplary embodiments, the orthographic projection of the light shielding portion on the base substrate covers the orthographic projection of each pixel unit located in the second display area on the base substrate, and also covers the orthographic projection of the portion of the multiple signal lines located in the second display area on the base substrate.

[0030] According to some exemplary embodiments, the light shielding portion extends continuously in the second display area.

[0031] According to some exemplary embodiments, the outline of the orthographic projection of the light shielding portion on the base substrate has an arc-shaped boundary line; and / or the outline of the orthographic projection of the light shielding portion on the base substrate has an arc-shaped transition portion at a corner.

[0032] According to some exemplary embodiments, the display panel further includes a plurality of light-transmitting areas located in the second display area, the orthographic projections of the plurality of light-transmitting areas on the base substrate do not overlap with the orthographic projections of the light-shielding portion on the base substrate, and the orthographic projection of each of the plurality of light-transmitting areas on the base substrate has the shape of a rounded rectangle.

[0033] According to some exemplary embodiments, the light shielding portion for shielding a portion of each pixel unit located in the second display area has an outline of an orthographic projection on the substrate that is approximately rectangular, and arc-shaped transitions are formed at the four corners of the approximately rectangular shape.

[0034] According to some exemplary embodiments, the display panel includes:

[0035] a first buffer layer disposed on the base substrate;

[0036] a second buffer layer disposed between the first buffer layer and the active layer,

[0037] Wherein, the light shielding portion is located between the first buffer layer and the second buffer layer.

[0038] According to some exemplary embodiments, the light shielding portion is located in the fourth conductive layer.

[0039] According to some exemplary embodiments, an orthographic projection of the light shielding portion on the base substrate is spaced apart from an orthographic projection of the connecting conductive portion on the base substrate.

[0040] According to some exemplary embodiments, the orthographic projection of the light shielding portion on the base substrate surrounds the orthographic projection of the anode on the base substrate, and the orthographic projection of the light shielding portion on the base substrate is spaced apart from the orthographic projection of the anode on the base substrate.

[0041] According to some exemplary embodiments, the light shielding portion includes a first light shielding portion and a second light shielding portion, the first light shielding portion is located between the active layer and the base substrate, and the second light shielding portion is located in the fourth conductive layer.

[0042] According to some exemplary embodiments, the display panel further includes a transfer conductive portion, wherein the transfer conductive portion is located in the first conductive layer;

[0043] The driving voltage line is electrically connected to the transfer conductive portion through a first via hole penetrating the first interlayer insulating layer and the second interlayer insulating layer; and

[0044] The switching conductive portion is electrically connected to the light shielding portion through a second via hole penetrating the gate insulating layer and the second buffer layer.

[0045] According to some exemplary embodiments, the light shielding portion is electrically connected to the driving voltage line through a third via hole penetrating the first planarization layer.

[0046] According to some exemplary embodiments, the plurality of signal lines include scan signal lines, light emitting control lines, data lines, driving voltage lines, initialization voltage lines, and power lines.

[0047] According to some exemplary embodiments, the scanning signal lines, the light-emitting control lines and the initialization voltage lines are arranged along the row direction, the data lines and the driving voltage lines are arranged along the column direction, each of the scanning signal lines, the light-emitting control lines, the initialization voltage lines, the data lines and the driving voltage lines includes a first portion located within the pixel unit and a second portion located between two adjacent pixel units, the gap includes a first gap, the first portion of each of the scanning signal lines, the light-emitting control lines, the initialization voltage lines, the data lines and the driving voltage lines has the first gap between each other, and the orthographic projection of the light-shielding portion on the base substrate at least covers the orthographic projection of the first gap on the base substrate.

[0048] According to some exemplary embodiments, the scanning signal line for the pixel unit located in the first display area includes an extended signal line portion that passes through the second display area in the row direction, the second portion of each of the scanning signal line, the light-emitting control line, and the initialization voltage line, and the extended signal line portion have the second gap between each other, and the orthographic projection of the light-shielding portion on the base substrate also covers at least the orthographic projection of the second gap on the base substrate.

[0049] In another aspect, a display device is provided, comprising:

[0050] According to the display panel as described above; and

[0051] An image sensor is located on a side of the base substrate away from the light shielding portion, and an orthographic projection of the image sensor on the base substrate is located within an orthographic projection of the second display area on the base substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0053] Figure 1 is a schematic plan view of a display panel according to some exemplary embodiments of the present disclosure;

[0054] Figure 2 The display panel according to some exemplary embodiments of the present disclosure is Figure 1 A schematic cross-sectional view taken along line EE';

[0055] Figure 3 yes Figure 1 A partial enlarged schematic diagram of the display panel in FIG. 1 , wherein each rectangle in the figure represents a pixel unit;

[0056] Figure 4 is a schematic diagram of a second display area of ​​a display panel in the related art, schematically showing a plurality of (for example, five) pixel units;

[0057] Figure 5 yes Figure 4 A partial enlarged view of part I in FIG;

[0058] Figure 6 is an equivalent circuit diagram of a pixel driving circuit of a display panel according to some exemplary embodiments of the present disclosure;

[0059] Figure 7 is a schematic diagram of a second display area of ​​a display panel according to some exemplary embodiments of the present disclosure, wherein several (for example, five) pixel units are schematically shown;

[0060] Figure 8 yes Figure 7 A partial enlarged schematic diagram of part II in FIG.

[0061] Figure 9 is a plan view illustrating an exemplary embodiment of a sub-pixel in the second display area AA2 of a display panel according to some exemplary embodiments of the present disclosure.

[0062] Figures 10 to 14 It shows Figure 9 A plan view of some film layers of an exemplary embodiment of a sub-pixel in FIG.

[0063] Figure 15 The display panel according to some exemplary embodiments of the present disclosure is Figure 9 A schematic cross-sectional view taken along line AA';

[0064] Figure 16 The display panel according to some exemplary embodiments of the present disclosure is Figure 9 A schematic cross-sectional view taken along line BB';

[0065] Figures 17 to 20 Schematic plan views of light shielding portions included in a display panel according to some exemplary embodiments of the present disclosure;

[0066] Figure 21 The display panel according to some exemplary embodiments of the present disclosure is Figure 8 A schematic cross-sectional view taken along line CC';

[0067] Figure 22 The display panel according to some exemplary embodiments of the present disclosure is Figure 8 A schematic cross-sectional view taken along line DD';

[0068] Figure 23 is a partial enlarged view of a portion of a display panel between two sub-pixel units according to some exemplary embodiments of the present disclosure;

[0069] Figure 24 The display panel according to some exemplary embodiments of the present disclosure is Figure 8 A schematic cross-sectional view taken along line CC' in FIG.

[0070] Figure 25 The display panel according to some exemplary embodiments of the present disclosure is Figure 8 Schematic cross-sectional view taken along line DD'. DETAILED DESCRIPTION

[0071] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0072] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0073] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, the element may be directly on the other element, directly connected to the other element, or directly coupled to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly coupled to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between..." versus "directly between...", "adjacent" versus "directly adjacent," or "on..." versus "directly on...", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0074] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0075] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0076] Those skilled in the art should understand that, in this document, unless otherwise specified, the expression "height" or "thickness" refers to the dimension along the surface of each film layer arranged perpendicular to the display panel, that is, the dimension along the light emitting direction of the display panel, or the dimension along the normal direction of the display device, or the dimension along the Z direction in the accompanying drawings.

[0077] Herein, the expression “pixel density” refers to the number of pixel units or sub-pixel units within a unit area.

[0078] In this article, the expressions "row direction" and "column direction" represent the two directions in which pixel units or sub-pixels are arranged in an array. It should be understood that the "row direction" and the "column direction" are two intersecting directions, which can be two directions perpendicular to each other or two directions at an angle different from 90° to each other.

[0079] Embodiments of the present disclosure provide at least one display panel, comprising: a substrate; a plurality of pixel units arranged in an array on the substrate, each pixel unit including a pixel driving circuit and a light-emitting device, the driving circuit structure being configured to drive the light-emitting device; a plurality of signal lines electrically connected to the pixel driving circuit; and a light shielding portion disposed on the substrate, wherein the orthographic projections of at least two of the plurality of signal lines on the substrate are separated by a gap, the gap causing at least a portion of imaging light to undergo at least one of interference and diffraction when passing through the gap, and the orthographic projection of the light shielding portion on the substrate at least covers the orthographic projection of the gap on the substrate. The provision of the light shielding portion prevents diffraction and interference of the imaging light, thereby reducing brightness variations in local areas within the field of view and improving object visibility. This effectively eliminates glare from under-screen cameras, thereby improving imaging quality.

[0080] Figure 1 is a schematic plan view of a display panel according to some exemplary embodiments of the present disclosure. Figure 2 The display panel according to some exemplary embodiments of the present disclosure is Figure 1 Schematic cross-sectional view taken along line EE'. Figure 3 yes Figure 1 A partial enlarged schematic diagram of the display panel in FIG. 1 is shown, where each rectangle represents a pixel unit.

[0081] Reference Figures 1 to 3 The display panel includes a first display area AA1 and a second display area AA2 at least partially surrounded by the first display area AA1. The first display area AA1 includes a plurality of first pixel units P1 arranged in an array, and the second display area AA2 includes a plurality of second pixel units P2 arranged in an array. The first pixel unit P1 may further include a plurality of sub-pixel units, such as a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit; similarly, the second pixel unit P2 may further include a plurality of sub-pixel units, such as a red sub-pixel unit, a green sub-pixel unit, and a blue sub-pixel unit.

[0082] like Figure 3 As shown, the first display area AA1 has a first pixel density, and the second display area AA2 has a second pixel density smaller than the first pixel density.

[0083] In the second display area AA2, the blank areas between the second pixel units P2 allow more light to pass through, thereby improving the light transmittance of the area. Therefore, compared with the first display area AA1, the second display area AA2 has a higher light transmittance.

[0084] It should be noted that, in this document, the blank area between the plurality of second pixel units P2 may be referred to as a light-transmitting area TRA.

[0085] like Figure 2 As shown, the display panel may include a substrate 1. The image sensor 2 may be provided on the back side of the substrate 1 located at the second display area AA2 (in the Figure 2 The second display area AA2 can meet the imaging requirements of the image sensor 2 for light transmittance.

[0086] exist Figures 1 to 3 The display panel shown in the figure can use OLED display technology. Due to the advantages of OLED display panels such as wide viewing angle, high contrast, fast response, low power consumption, foldability, and flexibility, they are increasingly widely used in display products. With the development and in-depth application of OLED display technology, the demand for high screen-to-body ratio displays is becoming increasingly strong. Figures 1 to 3 The display panel shown uses an under-screen camera solution, which eliminates the notch area, avoids digging a hole in the display, and increases the screen-to-body ratio, providing a better visual experience.

[0087] In addition, the display panel may further include a driving circuit layer, a light emitting device layer and an encapsulation layer provided on the base substrate 1. For example, Figure 2 The figure schematically illustrates a drive circuit layer 3, a light-emitting device layer 4, and an encapsulation layer 5. The drive circuit layer 3 includes a drive circuit structure, and the light-emitting device layer 4 includes light-emitting devices, such as OLEDs. The drive circuit structure controls the light-emitting devices in each sub-pixel unit to emit light, thereby achieving a display function. The drive circuit structure includes thin-film transistors, storage capacitors, and various signal lines. These various signal lines include scan signal lines, data lines, ELVDD power lines, and ELVSS power lines, etc., to provide various signals such as control signals, data signals, and power supply voltages to the pixel drive circuit in each sub-pixel unit in the pixel unit.

[0088] Figure 4 FIG. 2 is a schematic diagram of a second display area AA2 of a display panel in the related art, in which several (eg, 5) pixel units are schematically shown.

[0089] like Figure 4As shown, the second display area AA2 includes a plurality of second pixel units P2 arranged in an array. For example, each second pixel unit P2 may further include a plurality of sub-pixel units, such as a red sub-pixel unit SP1, a green sub-pixel unit SP2, and a blue sub-pixel unit SP3. A light-transmitting region TRA is defined between the pixel units P2 in the second display area AA2, allowing imaging light to pass through and enter the image sensor 2 disposed in the second display area AA2.

[0090] It should be noted that, in the accompanying drawings, the pixel units and sub-pixel units are schematically illustrated as rectangular shapes. However, this does not limit the shapes of the pixel units and sub-pixel units included in the display panel provided by the embodiments of the present disclosure. Furthermore, in the accompanying drawings, the three sub-pixel units SP1, SP2, and SP3 included in each pixel unit SP are arranged in a herringbone shape. This arrangement does not limit the display panel provided by the embodiments of the present disclosure.

[0091] Herein, the imaging light may include at least one of visible light or infrared light, but the embodiments of the present disclosure are not limited thereto.

[0092] Figure 5 yes Figure 4 A partial enlarged view of part I in FIG. Figure 4 and Figure 5 The display panel includes various signal lines that provide control signals, data signals, power supply voltages, and other signals to each sub-pixel unit. For example, the signal lines may include scan signal lines, data lines, ELVDD power lines, ELVSS power lines, reset lines, and light-emitting control lines. These signal lines may be formed in different layers. For example, the scan signal lines may be located in the same layer as the gate electrodes of thin-film transistors (e.g., formed by the same patterning process), and the data lines may be located in the same layer as the source and drain electrodes of the thin-film transistors (e.g., formed by the same patterning process).

[0093] Reference Figure 4 and Figure 5 As mentioned above, various signal lines extend inside and between each pixel unit. In the second display area AA2, relatively small gaps are formed between various signal lines. These gaps may appear inside each pixel unit, such as Figure 5 The gap 51 shown in FIG can also appear between each pixel unit, such as Figure 5The gaps 52 shown in FIG. During imaging, incident light passing through these gaps can undergo single-slit diffraction or double-slit interference, producing diffraction or interference fringes. This results in uneven brightness when the incident light reaches the camera, causing glare (i.e., excessive brightness in a certain area of ​​the field of view or large brightness variations), reducing object visibility and hindering imaging. In other words, these diffraction or interference effects reduce the imaging quality of image sensor 2 located below second display area AA2.

[0094] Hereinafter, some exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0095] For example, the display panel according to some exemplary embodiments of the present disclosure may be an organic light-emitting diode (OLED) display panel. The display panel may include a plurality of sub-pixel units, each of which may have a pixel driving circuit for controlling the sub-pixel unit to emit light for display.

[0096] Below, the structure of the pixel driving circuit is described in detail by taking the 7T1C pixel driving circuit as an example. However, the embodiments of the present disclosure are not limited to the 7T1C pixel driving circuit. Other known pixel driving circuit structures can be applied to the embodiments of the present disclosure unless there is a conflict.

[0097] Figure 6 FIG. 1 is an equivalent circuit diagram of a pixel driving circuit of a display panel according to some exemplary embodiments of the present disclosure. Figure 6 As shown, the pixel driving circuit may include: a plurality of signal lines 61, 62, 63, 64, 65, 66 and 67, a plurality of thin film transistors T1, T2, T3, T4, T5, T6 and T7, and a storage capacitor Cst. The pixel driving circuit is used to drive an organic light emitting diode (OLED).

[0098] The plurality of thin film transistors include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , an initialization thin film transistor T4 , an operation control thin film transistor T5 , a light emission control thin film transistor T6 and a bypass thin film transistor T7 .

[0099] The multiple signal lines include: a scanning signal line 61 for transmitting a scanning signal Sn, a previous scanning signal line 62 for transmitting a previous scanning signal Sn-1 to the initialization thin film transistor T4, a light emitting control line 63 for transmitting a light emitting control signal En to the operation control thin film transistor T5 and the light emitting control thin film transistor T6, a data line 64 for transmitting a data signal Dm, a driving voltage line 65 for transmitting a driving voltage ELVDD, an initialization voltage line 66 for transmitting an initialization voltage Vint for initializing the driving thin film transistor T1, and a power supply line 67 for transmitting an ELVSS voltage.

[0100] The gate electrode G1 of the driving thin film transistor T1 is electrically connected to one end Cst1 of the storage capacitor Cst (hereinafter referred to as the first capacitor electrode). The source electrode S1 of the driving thin film transistor T1 is electrically connected to the driving voltage line 65 via the operation control thin film transistor T5. The drain electrode D1 of the driving thin film transistor T1 is electrically connected to the anode of the OLED via the light emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 to supply the driving current Id to the OLED.

[0101] The gate electrode G2 of the switching thin film transistor T2 is electrically connected to the scan signal line 61, the source electrode S2 of the switching thin film transistor T2 is electrically connected to the data line 64, and the drain electrode D2 of the switching thin film transistor T2 is electrically connected to the drive voltage line 65 via the operation control thin film transistor T5, and is also electrically connected to the source electrode S1 of the driving thin film transistor T1. The switching thin film transistor T2 is turned on in response to the scan signal Sn transmitted via the scan signal line 64 to perform a switching operation to transmit the data signal Dm transmitted to the data line 64 to the source electrode S1 of the driving thin film transistor T1.

[0102] The gate electrode G3 of the compensation thin-film transistor T3 is electrically connected to the scan signal line 61. The source electrode S3 of the compensation thin-film transistor T3 is electrically connected to the anode of the OLED via the light-emission control thin-film transistor T6, and is also electrically connected to the drain electrode D1 of the drive thin-film transistor T1. Furthermore, the drain electrode D3 of the compensation thin-film transistor T3 is electrically connected to one end (i.e., the first capacitor electrode) Cst1 of the storage capacitor Cst, the drain electrode D4 of the initialization thin-film transistor T4, and the gate electrode G1 of the drive thin-film transistor T1. The compensation thin-film transistor T3 is turned on in response to the scan signal Sn transmitted via the scan signal line 61, thereby connecting the gate electrode G1 and the drain electrode D1 of the drive thin-film transistor T1 to each other, thereby implementing a diode connection for the drive thin-film transistor T1.

[0103] The gate electrode G4 of the initialization thin film transistor T4 is electrically connected to the previous scan signal line 62, and the source electrode S4 of the initialization thin film transistor T4 is electrically connected to the initialization voltage line 66. Furthermore, the drain electrode D4 of the initialization thin film transistor T4 is electrically connected to one end Cst1 of the storage capacitor Cst, the drain electrode D3 of the compensation thin film transistor T3, and the gate electrode G1 of the driving thin film transistor T1. The initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1 transmitted via the previous scan signal line 62 to transmit the initialization voltage Vint to the gate electrode G1 of the driving thin film transistor T1, thereby performing an initialization operation to initialize the voltage of the gate electrode G1 of the driving thin film transistor T1.

[0104] The gate electrode G5 of the operation control thin film transistor T5 is electrically connected to the light emission control line 63, and the source electrode S5 of the operation control thin film transistor T5 is electrically connected to the driving voltage line 65. The drain electrode D5 of the operation control thin film transistor T5 is electrically connected to the source electrode S1 of the driving thin film transistor T1 and the drain electrode D2 of the switching thin film transistor T2.

[0105] The gate electrode G6 of the emission control thin film transistor T6 is electrically connected to the emission control line 63. The source electrode S6 of the emission control thin film transistor T6 is electrically connected to the drain electrode D1 of the drive thin film transistor T1 and to the source electrode S3 of the compensation thin film transistor T3. Furthermore, the drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the anode electrode of the OLED. The operation control thin film transistor T5 and the emission control thin film transistor T6 are concurrently (e.g., simultaneously) turned on in response to the emission control signal En transmitted via the emission control line 63 to transmit the drive voltage ELVDD to the OLED, thereby allowing the drive current Id to flow into the OLED.

[0106] The bypass thin-film transistor T7 includes a gate G7 connected to the previous scan signal line 62; a source S7 connected to the drain D6 of the light-emission control thin-film transistor T6 and the anode of the OLED; and a drain D7 connected to the initialization voltage line 66. The bypass thin-film transistor T7 transmits the previous scan signal Sn-1 from the previous scan signal line 62 to the gate G7.

[0107] The other end of the storage capacitor Cst (hereinafter referred to as the second capacitor electrode) Cst2 is electrically connected to the driving voltage line 65, and the cathode of the OLED is electrically connected to the power supply line 67 to receive the common voltage ELVSS. Accordingly, the OLED receives the driving current Id from the driving thin film transistor T1 to emit light, thereby displaying an image.

[0108] It should be noted that in Figure 6In the embodiment, each thin film transistor T1, T2, T3, T4, T5, T6 and T7 has a single gate structure, but the embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 may have a double gate structure. Figure 6 , each thin film transistor T1, T2, T3, T4, T5, T6 and T7 is a p-channel field effect transistor, but the embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6 and T7 may be an n-channel field effect transistor.

[0109] In operation, during the initialization phase, a previous scan signal Sn-1 having a low level is supplied through the previous scan signal line 62. Subsequently, the initialization thin film transistor T4 is turned on based on the low level of the previous scan signal Sn-1, and the initialization voltage Vint from the initialization voltage line 66 is transmitted to the gate G1 of the driving thin film transistor T1 through the initialization thin film transistor T4. Therefore, the driving thin film transistor T1 is initialized due to the initialization voltage Vint.

[0110] During the data programming phase, a scan signal Sn having a low level is supplied through the scan signal line 61. Subsequently, the switching thin film transistor T2 and the compensation thin film transistor T3 are turned on based on the low level of the scan signal Sn. Therefore, the driving thin film transistor T1 is placed in a diode connection state through the turned-on compensation thin film transistor T3 and is biased in the forward direction.

[0111] Subsequently, a compensation voltage Dm+Vth (for example, Vth is a negative value) obtained by subtracting the threshold voltage Vth of the driving thin film transistor T1 from the data signal Dm supplied via the data line 64 is applied to the gate G1 of the driving thin film transistor T1. Subsequently, the driving voltage ELVDD and the compensation voltage Dm+Vth are applied to both terminals of the storage capacitor Cst, so that charges corresponding to the voltage difference between the corresponding terminals are stored in the storage capacitor Cst.

[0112] During the light emission period, the light emission control signal En from the light emission control line 63 changes from high level to low level. Subsequently, during the light emission period, the operation control thin film transistor T5 and the light emission control thin film transistor T6 are turned on based on the low level of the light emission control signal En.

[0113] Then, a driving current is generated based on the difference between the voltage of the gate G1 of the driving thin film transistor T1 and the driving voltage ELVDD. A driving current Id corresponding to the difference between the driving current and the bypass current is supplied to the OLED through the emission control thin film transistor T6.

[0114] During the light emitting phase, based on the current-voltage relationship of the driving thin film transistor T1, the gate-source voltage of the driving thin film transistor T1 is maintained at (Dm+Vth)-ELVDD due to the storage capacitor Cst. 2 Therefore, the driving current Id may not be affected by the change in the threshold voltage Vth of the driving thin film transistor T1.

[0115] Figure 7 2 is a schematic diagram of a second display area AA2 of a display panel according to some exemplary embodiments of the present disclosure, wherein several (for example, 5) pixel units are schematically shown. Figure 8 yes Figure 7 A locally enlarged schematic diagram of part II.

[0116] In an embodiment of the present disclosure, the display panel includes a plurality of signal lines disposed on a base substrate 1 , for example, the signal lines 61 , 62 , 63 , 64 , 65 , 66 and 67 described above.

[0117] like Figure 7 As shown, the second display area AA2 includes a plurality of second pixel units P2 arranged in an array. For example, each second pixel unit P2 may further include a plurality of sub-pixel units, such as a red sub-pixel unit SP1, a green sub-pixel unit SP2, and a blue sub-pixel unit SP3. A light-transmitting region TRA is defined between the pixel units P2 in the second display area AA2, allowing imaging light to pass through and enter the image sensor 2 disposed in the second display area AA2.

[0118] Herein, the imaging light may include at least one of visible light or infrared light, but the embodiments of the present disclosure are not limited thereto.

[0119] Reference Figure 7 and Figure 8 As described above, the various signal lines 61, 62, 63, 64, 65, 66 and 67 extend inside and between the pixel units. In the second display area AA2, relatively small gaps are formed between the various signal lines. These gaps may appear inside the pixel units, such as Figure 8 The gap 71 (hereinafter referred to as the first gap) in FIG. 1 may also appear between each pixel unit, as shown in FIG. Figure 8 As shown in FIG. 7A and 7B , gaps 72 (hereinafter referred to as second gaps) are provided in FIG. Exemplarily, gaps 71 appear between a plurality of signal lines within a pixel unit, and gaps 72 appear between a plurality of signal lines extending between pixel units.

[0120] In some exemplary embodiments of the present disclosure, the display panel further includes a light shielding portion 100 disposed on the base substrate 1 .

[0121] The light shielding portion 100 is made of a material capable of blocking imaging light, for example, the material has a transmittance of less than 10%, such as less than 5%, or less than 1% to imaging light (such as infrared light or visible light).

[0122] Reference Figure 7 and Figure 8 The orthographic projection of the light shielding portion 100 on the base substrate 1 at least covers the orthographic projection of each of the gaps 71 and 72 on the base substrate 1 .

[0123] By providing the light shield, diffraction and interference of imaging light can be avoided, thereby reducing brightness variations in local areas of the field of view and improving object visibility. This effectively eliminates glare from the under-screen camera, thereby improving imaging quality.

[0124] Figure 7 and Figure 8 The distribution of sub-pixels in the second display area AA2 of the display panel according to some exemplary embodiments of the present disclosure is schematically shown. Below, an exemplary embodiment of the distribution of sub-pixels and signal lines in the second display area AA2 of the display panel according to some exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings.

[0125] Figure 9 is a plan view illustrating an exemplary embodiment of a sub-pixel in the second display area AA2 of a display panel according to some exemplary embodiments of the present disclosure. Figures 10 to 14 It shows Figure 9 It should be noted that in order to clearly show the positional relationship between each film layer or wiring, Figures 9 to 14 Not all film layer structures within the sub-pixel are shown, that is, some structures are omitted. Figures 9 to 13 Shown is Figure 7 and Figure 8 A partial plan view of a sub-pixel included in a pixel unit, Figure 14 Shown is the corresponding Figure 7 and Figure 8 A plan view of the light shielding portion of a pixel unit.

[0126] Specifically, Figures 10 to 14A schematic plan view of the active layer, first conductive layer, second conductive layer, third conductive layer, and light shielding portion within a subpixel is shown. The first conductive layer, second conductive layer, and third conductive layer are described in further detail below. It should be understood that an insulating layer may be provided between any two adjacent active layers, conductive layers, and light shielding portions, and vias may be provided in the insulating layer to electrically connect structures between different layers.

[0127] Combined with reference Figure 6 as well as Figures 9 to 14 The subpixel includes a scan signal line 61, a previous scan signal line 62, a light emission control line 63, and an initialization voltage line 66 arranged along the row direction to apply a scan signal Sn, a previous scan signal Sn-1, a light emission control signal En, and an initialization voltage Vint to the subpixel, respectively. The subpixel may also include a data line 64 and a drive voltage line 65 that intersect the scan signal line 61, the previous scan signal line 62, the light emission control line 63, and the initialization voltage line 66 to apply a data signal Dm and a drive voltage ELVDD to the subpixel, respectively. The subpixel may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, an initialization thin film transistor T4, an operation control thin film transistor T5, a light emission control thin film transistor T6, a bypass thin film transistor T7, a storage capacitor Cst, and an organic light emitting diode OLED.

[0128] The driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the initialization thin film transistor T4, the operation control thin film transistor T5, the light emitting control thin film transistor T6 and the bypass thin film transistor T7 can be connected along the following lines: Figure 10 The active layer may have a curved or bent shape and may include a driving active layer 20a corresponding to the driving thin film transistor T1, a switching active layer 20b corresponding to the switching thin film transistor T2, a compensation active layer 20c corresponding to the compensation thin film transistor T3, an initialization active layer 20d corresponding to the initialization thin film transistor T4, an operation control active layer 20e corresponding to the operation control thin film transistor T5, a light emission control active layer 20f corresponding to the light emission control thin film transistor T6, and a bypass active layer 20g corresponding to the bypass thin film transistor T7.

[0129] The active layer may include, for example, polycrystalline silicon and, for example, includes a channel region, a source region, and a drain region. The channel region may not be doped with impurities and therefore has semiconductor properties. The source region and the drain region are located on either side of the channel region, respectively, and are doped with impurities and therefore have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0130] The driving thin film transistor T1 includes a driving active layer 20a and a driving gate G1. The driving active layer 20a includes a driving source region 203a, a driving drain region 205a, and a driving channel region 201a connecting the driving source region 203a and the driving drain region 205a. The driving source region 203a and the driving drain region 205a extend in two directions relative to the driving channel region 201a. The driving source region 203a of the driving thin film transistor T1 is connected to the switching drain region 205b and the operation control drain region 205e. The driving drain region 205a is connected to the compensation source region 203c and the light emission control source region 203f. The gate G1 of the driving thin film transistor T1 is connected to the compensation gate G3 of the compensation thin film transistor T3 through vias VAH1 and VAH2.

[0131] The switching thin film transistor T2 includes a switching active layer 20b and a switching gate G2. The switching active layer 20b includes a switching channel region 201b, a switching source region 203b, and a switching drain region 205b. The switching thin film transistor T2 serves as a switching device for selecting a target sub-pixel for light emission. The switching gate G2 is connected to the scan signal line 61, the switching source region 203b is connected to the data line 64 through the via VAH4, and the switching drain region 205b is connected to the driving thin film transistor T1 and the operation control thin film transistor T5.

[0132] The compensation thin film transistor T3 includes a compensation active layer 20c and a compensation gate G3. The compensation active layer 20c includes a compensation channel region 201c, a compensation source region 203c and a compensation drain region 205c.

[0133] The initialization thin film transistor T4 includes an initialization active layer 20d and an initialization gate G4. The initialization active layer 20d includes an initialization channel region 201d, an initialization source region 203d, and an initialization drain region 205d. The initialization source region 203d is connected to the initialization voltage line 66 through a via VAH5.

[0134] The operation control thin film transistor T5 includes an operation control active layer 20e and an operation control gate G5. The operation control active layer 20e includes an operation control channel region 201e, an operation control source region 203e, and an operation control drain region 205e. The operation control source region 203e can be connected to the driving voltage line 65 through a via VAH6.

[0135] The emission control thin film transistor T6 includes an emission control active layer 20f and an emission control gate G6. The emission control active layer 20f includes an emission control channel region 201f, an emission control source region 203f, and an emission control drain region 205f. The emission control drain region 205f can be connected to the anode of the OLED through a via VAH7.

[0136] The bypass thin-film transistor T7 includes a bypass active layer 20g and a bypass gate G7. The bypass active layer 20g includes a bypass source region 203g, a bypass drain region 205g, and a bypass channel region 201g. The bypass drain region 205g is connected to the initialization source region 203d of the initialization thin-film transistor T4. The bypass drain region 205g can be connected to the initialization voltage line 66 through a via VAH8.

[0137] The second storage capacitor plate Cst2 may be connected to the driving voltage line 65 through a via hole VAH9 located in the insulating layer.

[0138] like Figure 9 As shown in the figure, some signal lines are schematically shown, for example, the scanning signal line 61, the previous scanning signal line 62, the light-emitting control line 63 and the initialization voltage line 66 arranged along the row direction to apply the scanning signal Sn, the previous scanning signal Sn-1, the light-emitting control signal En and the initialization voltage Vint to the sub-pixels respectively, and the data line 64 and the driving voltage line 65 that cross the scanning signal line 61, the previous scanning signal line 62, the light-emitting control line 63 and the initialization voltage line 66 to apply the data signal Dm and the driving voltage ELVDD to the sub-pixels respectively.

[0139] For example, a portion and another portion of the previous scan signal line 62 may be located in different layers and connected through the via VAH3 .

[0140] Figure 15 The display panel according to some exemplary embodiments of the present disclosure is Figure 9 Schematic cross-sectional view taken along line AA'. Figure 16 The display panel according to some exemplary embodiments of the present disclosure is Figure 9 It should be noted that, in order to clearly show the relative position relationship of the light shielding portion, Figure 15 and Figure 16 The cross-sectional view omits some structures and layers, for example, Figure 15 Only one thin film transistor is shown in FIG. Figure 6 The light emission control thin film transistor T6 is shown in FIG.

[0141] Reference Figure 15 The insulating layer may include at least some of the gate insulating layer 30 , the first interlayer insulating layer 40 , the second interlayer insulating layer 41 , the first planarizing layer 50 , and the second planarizing layer 51 .

[0142] Combined with reference Figure 15 and Figure 16The display panel may include: an active layer 20 disposed on a base substrate 1; a gate insulating layer 30 disposed on a side of the active layer 20 away from the base substrate 1; a gate G6 and a second capacitor electrode Cst2 disposed on a side of the gate insulating layer 30 away from the base substrate 1; a first interlayer insulating layer 40 disposed on a side of the gate G6 and the second capacitor electrode Cst2 away from the base substrate 1; a first capacitor electrode Cst1 disposed on a side of the first interlayer insulating layer 40 away from the base substrate 1; a second interlayer insulating layer 41 disposed on a side of the first capacitor electrode Cst1 away from the base substrate 1; a source electrode S6 and a drain electrode D6 disposed on a side of the second interlayer insulating layer 41 away from the base substrate 1; and a first planarization layer 50 covering the source electrode S6 and the drain electrode D6. The source electrode S6 and the drain electrode D6 are respectively connected to the active layer 20 through vias.

[0143] It should be understood that the active layer 20 may be, for example, Figure 10 The film layers shown in FIG. 2 may include active layers 20 a , 20 b , 20 c , 20 d , 20 e , 20 f and 20 g of respective thin film transistors.

[0144] The active layer 20 , the gate G6 , the source S6 and the drain D6 form a light emission control thin film transistor T6 . The first capacitor electrode Cst1 and the second capacitor electrode Cst2 face each other and are spaced apart by the first interlayer insulating layer 40 to form a storage capacitor Cst.

[0145] The display panel may further include: a connecting conductive portion 70 disposed on the side of the first planarization layer 50 away from the base substrate 1, a second planarization layer 51 disposed on the side of the connecting conductive portion 70 away from the base substrate 1, an anode 81 of the OLED disposed on the side of the second planarization layer 51 away from the base substrate 1, and a pixel defining layer 90 disposed on the side of the anode 81 away from the base substrate 1. It should be understood that the OLED may further include an organic light-emitting layer and a cathode disposed on the side of the anode 81 away from the base substrate 1. The anode 81 is electrically connected to the connecting conductive portion 70 through a via 811, and the connecting conductive portion 70 is electrically connected to the drain electrode D6 through a via 701. In other words, the anode 81 is electrically connected to the drain electrode D6 through the connecting conductive portion 70.

[0146] In the example shown in the figure, the second capacitor electrode Cst2 and the gate G6 are located in the same layer, for example, formed by the same patterning process. For convenience of description, the layer where the second capacitor electrode Cst2 and the gate G6 are located can be referred to as the first conductive layer. The first capacitor electrode Cst1 is between the first conductive layer and the conductive layer where the source S6 and the drain D6 are located. For convenience of description, the layer where the first capacitor electrode Cst1 is located can be referred to as the second conductive layer, and the layer where the source S6 and the drain D6 are located can be referred to as the third conductive layer. The connecting conductive portion 70 is located on the side of the third conductive layer away from the base substrate 1. For convenience of description, the layer where the connecting conductive portion 70 is located can be referred to as the fourth conductive layer.

[0147] In the embodiment of the present disclosure, the various signal lines 61, 62, 63, 64, 65, 66, and 67 described above may be located in at least one conductive layer selected from the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, respectively. For example, the scan signal line 61 and the previous scan signal line 62 may be located in the first conductive layer, the light emitting control line 63 may be located in the second conductive layer, the data line 64 and the drive voltage line 65 may be located in the third conductive layer, and the initialization voltage line 66 may be located in the fourth conductive layer. However, the embodiment of the present disclosure is not limited thereto, and a signal line may also be located in multiple conductive layers. For example, some drive voltage lines 65 may be located in the third conductive layer, and other drive voltage lines 65 may be located in the fourth conductive layer.

[0148] For example, the first conductive layer and the second conductive layer may be conductive layers made of gate materials, and the third conductive layer and the fourth conductive layer may be conductive layers made of source and drain materials.

[0149] For example, the gate material may include a metal material, such as Mo, Al, Cu, and their alloys. The source and drain materials may include a metal material, such as Mo, Al, Cu, and their alloys. The semiconductor material constituting the active layer may include, for example, amorphous silicon, polycrystalline silicon, an oxide semiconductor, and the like. Oxide semiconductor materials may include, for example, IGZO (indium gallium zinc oxide), ZnO (zinc oxide), and the like.

[0150] In some embodiments of the present disclosure, the light shielding portion 100 may be a separate film layer. Figure 15 and Figure 16 The light shielding portion 100 is disposed below the active layer 20, that is, on the side of the active layer 20 close to the base substrate 1. In other words, the light shielding portion 100 is not located on the same layer as the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, but is a separate film layer.

[0151] For example, the light shielding portion 100 may be made of a metal light shielding material, which may be the same material as the gate material or the source / drain material, or a material different from the gate material or the source / drain material.

[0152] It should be noted that in Figure 7 and Figure 8 In the plan view, the light shielding portion 100 is shown in gray. Figures 9 to 16 In the following drawings, the light shielding portion 100 is shown in an image with oblique hatching lines, which is only for the purpose of making the drawings clear.

[0153] Optionally, the display panel may include a first buffer layer 11 and a second buffer layer 12 disposed on the base substrate 1. The first buffer layer 11 may be located between the base substrate 1 and the light shielding portion 100. The second buffer layer 12 may be located between the light shielding portion 100 and the active layer 20.

[0154] Reference Figures 7 to 16 The orthographic projection of the light shielding portion 100 on the base substrate 1 at least covers the orthographic projection of the gaps between the plurality of signal lines (including the above-mentioned gaps 71 and 72 ) on the base substrate 1 .

[0155] For example, refer to Figure 9 The orthographic projections of the driving thin-film transistor T1, the switching thin-film transistor T2, the compensation thin-film transistor T3, the initialization thin-film transistor T4, the operation control thin-film transistor T5, the emission control thin-film transistor T6, the bypass thin-film transistor T7, and the various signal lines 61, 62, 63, 64, 65, 66, and 67 on the substrate 1 do not completely cover the substrate 1, thereby forming some gaps. The gaps within each pixel unit are the first gaps 71, and the gaps between each pixel unit are the second gaps 72.

[0156] Specifically, the scan signal lines 61, the previous scan signal lines 62, the emission control lines 63, and the initialization voltage lines 66 arranged along the row direction have first portions located within the subpixels. The data lines 64 and the drive voltage lines 65 that intersect the scan signal lines 61, the previous scan signal lines 62, the emission control lines 63, and the initialization voltage lines 66 also have first portions located within the subpixels. The first portions of each of the scan signal lines 61, the previous scan signal lines 62, the emission control lines 63, the initialization voltage lines 66, the data lines 64, and the drive voltage lines 65 have first gaps 71 between them. The scan signal lines 61, the previous scan signal lines 62, the emission control lines 63, and the initialization voltage lines 66 also extend along the row direction to adjacent pixel units. That is, the scan signal lines 61, the previous scan signal lines 62, the emission control lines 63, and the initialization voltage lines 66 arranged along the row direction have second portions located between the respective pixel units. In addition, the pixel density in the first display area AA1 is higher than that in the second display area AA2, and the scanning signal lines in the first display area AA1 need to pass through the second display area AA2 along the row direction. Figure 9 As shown in the extended signal line portion 120. That is, Figure 9 The extended signal line portion 120 is the portion of the scan signal line in the first display area AA1 that extends to the second display area AA2. A second gap 72 is formed between the second portion of each of the scan signal line 61, the previous scan signal line 62, the light emission control line 63, and the initialization voltage line 66, as well as the extended signal line portion 120.

[0157] The orthographic projection of the light shielding portion 100 on the base substrate 1 at least covers the orthographic projection of each of the first gap 71 and the second gap 72 on the base substrate 1 .

[0158] Optionally, refer to Figure 9 and Figure 14 The orthographic projection of the light shielding portion 100 on the base substrate 1 covers the orthographic projection of the portion of the multiple signal lines in the second display area AA2 on the base substrate 1, and the orthographic projection of the light shielding portion 100 on the base substrate 1 also covers the orthographic projection of the multiple thin film transistors T1 to T7 and the storage capacitor Cst located in the second display area AA2 on the base substrate 1.

[0159] By means of the separately provided light shielding portion, it is possible to ensure that the gaps within each pixel unit and the gaps between the signal lines between the pixel units are shielded, thereby reliably avoiding the diffraction and interference of the imaging light.

[0160] It should be understood that the orthographic projection of the light shielding portion 100 on the base substrate 1 does not overlap with the orthographic projection of the light-transmitting region TRA between the pixel units P2 in the second display area AA2 on the base substrate 1 for the most part. Thus, a large area of ​​light-transmitting region TRA still exists between the pixel units P2 in the second display area AA2, allowing imaging light to pass through the light-transmitting region TRA and enter the image sensor 2 disposed in the second display area AA2.

[0161] Continue to refer to Figure 15 , the light shielding portion 100 is electrically connected to the driving voltage line 65. Figure 6 and Figure 15 The driving voltage line 65 is used to supply the ELVDD voltage signal. In other words, the light shielding portion 100 is also used to supply the ELVDD voltage signal.

[0162] Specifically, refer to Figure 15 , the driving voltage line 65 is electrically connected to the transition conductive part 110 through the via 651, and the transition conductive part 110 is electrically connected to the light shielding part 100 through the via 1101. Since the driving voltage line 65 and the light shielding part 100 are relatively far apart in the direction perpendicular to the base substrate 1, the provision of the transition conductive part 110 is conducive to electrically connecting the light shielding part 100 to the driving voltage line 65. For example, the transition conductive part 110 can be located in the above-mentioned first conductive layer, that is, the transition conductive part 110 is located in the same layer as the gate G6 and the second capacitor electrode Cst2. Among them, the via 651 penetrates the first interlayer insulating layer 40 and the second interlayer insulating layer 41 to expose a portion of the transition conductive part 110. The via 1101 penetrates the gate insulating layer 30 and the second buffer layer 12 to expose a portion of the light shielding part 100.

[0163] Combined with reference Figure 6 and Figure 15 The driving voltage line 65 is also electrically connected to the second capacitor electrode Cst2. For example, the driving voltage line 65 is electrically connected to the second capacitor electrode Cst2 through a via 652. The via 652 may penetrate the first interlayer insulating layer 40, the first capacitor electrode Cst1, and the second interlayer insulating layer 41 to expose a portion of the second capacitor electrode Cst2.

[0164] In this way, the light shielding portion 100 is electrically connected to a stable DC voltage signal, preventing charges generated by the floating light shielding portion 100 and thus preventing ESD. Furthermore, both the light shielding portion 100 and the driving voltage line 65 function as signal lines supplying the ELVDD voltage signal, effectively reducing the IR drop effect and improving brightness uniformity.

[0165] Figures 17 to 20They are respectively schematic plan views of light shielding portions included in a display panel according to some exemplary embodiments of the present disclosure. Figures 17 to 20 Since the light shielding portion 100 is a separately provided film layer, it will not interfere with the position of other film layers such as the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer, so the shape of the orthographic projection of the light shielding portion 100 on the base substrate 1 can be designed.

[0166] For example, the orthographic projection of the light shielding portion 100 on the substrate 1 can extend continuously, that is, the portion 101 of the light shielding portion 100 used to shield the gap 71 within each pixel unit and the portion 102 of the light shielding portion 100 used to shield the gap 72 between each sub-pixel unit can be connected together. In this way, the light shielding portion 100 is easily formed.

[0167] For example, the orthographic projection of the light shielding portion 100 on the substrate 1 can cover the orthographic projection of each pixel unit in the second display area AA2 on the substrate 1, and the area of ​​the orthographic projection of the light shielding portion 100 on the substrate 1 can be larger than the area of ​​the orthographic projection of each pixel unit in the second display area AA2 on the substrate 1. Furthermore, the orthographic projection of the light shielding portion 100 on the substrate 1 can cover the orthographic projection of the portions of the multiple signal lines between the pixel units located in the second display area AA2 on the substrate 1, and the area of ​​the orthographic projection of the light shielding portion 100 on the substrate 1 can be larger than the area of ​​the orthographic projection of the portions of the multiple signal lines between the pixel units located in the second display area AA2 on the substrate 1. In this way, the light shielding portion 100 can effectively cover the edges of each pixel unit and the multiple signal lines between the pixel units, thereby improving the light shielding portion's shielding effect on each gap.

[0168] The shape of the orthographic projection of the light shielding portion 100 on the base substrate 1 can be designed. Figures 17 to 20 In the embodiment, the outline of the orthographic projection of the light shielding portion 100 on the base substrate 1 may have an arc shape at the corners or boundaries. In this way, the arc-shaped corners or boundaries can reduce the diffraction effect when the imaging light passes through, thereby further improving the imaging quality.

[0169] Specifically, refer to Figure 17In the second display area AA2, the boundary 100S of the outline of the orthographic projection of the light shielding portion 100 on the substrate 1 is closely attached to the boundaries of the orthographic projections of the various pixel units and the multiple signal lines between the pixel units on the substrate 1. The "closely attached" here can be understood as follows: in the second display area AA2, the orthographic projection of the light shielding portion 100 on the substrate 1 can cover the orthographic projections of the various pixel units and the multiple signal lines between the pixel units on the substrate 1, and the area of ​​the orthographic projection of the light shielding portion 100 on the substrate 1 can be slightly larger than the area of ​​the orthographic projections of the various pixel units and the multiple signal lines between the pixel units on the substrate 1. In this way, while ensuring the light shielding effect, the area of ​​the light-transmitting area can be made as large as possible, thereby further improving the imaging quality.

[0170] like Figure 17 As shown, the boundaries 100S of the outline of the orthographic projection of the light shielding portion 100 on the base substrate 1 are at various corners (eg Figure 17 The corners 103 and 104 shown in the figure are arc-shaped, that is, arc-shaped transitions are made at each corner. In this way, the arc-shaped corners or boundaries can reduce the diffraction effect when the imaging light passes through, thereby further improving the imaging quality.

[0171] Reference Figure 18 The outline of the orthographic projection of the light shielding portion 100 on the base substrate 1 has an arc-shaped boundary 100S. In this way, the arc-shaped outline can reduce the diffraction effect when the imaging light passes through, thereby further improving the imaging quality.

[0172] Reference Figure 19 The outline 100S of the orthographic projection of the light shielding portion 100 on the base substrate 1 is formed at each corner (eg Figure 19 The corners 105 and 106 shown in the figure are arc-shaped, that is, arc-shaped transitions are formed. In this way, the arc-shaped corners can reduce the diffraction effect when the imaging light passes through, thereby further improving the imaging quality.

[0173] exist Figure 19 In the embodiment shown, the orthographic projection of each light-transmitting region TRA on the base substrate 1 has a rounded rectangular shape. This forms a relatively regular pattern, which is beneficial for forming the light-shielding portion and also helps improve the uniformity of the imaging light incident on the imaging module.

[0174] Reference Figure 20 The outline of the positive projection of the light shielding portion 100 for shielding the gaps within each pixel unit 101 on the substrate 1 has an approximately rectangular shape, and the four corners of the rectangle form arc transitions to reduce the diffraction effect of the imaging light when passing through.

[0175] The outline of the orthographic projection of a portion 102 of the light shielding portion 100 for shielding the gaps between the pixel units on the base substrate 1 closely follows the outline of the orthographic projection of the plurality of signal lines between the sub-pixel units on the base substrate 1 .

[0176] Alternatively or additionally, in some embodiments of the present disclosure, the light shielding portion 100 may be located in at least one layer selected from the first conductive layer, the second conductive layer, the third conductive layer, or the fourth conductive layer.

[0177] Figure 21 The display panel according to some exemplary embodiments of the present disclosure is Figure 8 Schematic cross-sectional view taken along line CC'. Figure 22 The display panel according to some exemplary embodiments of the present disclosure is Figure 8 Schematic cross-sectional view taken along line DD'. Figure 23 is a partially enlarged view of a portion of a display panel between two sub-pixel units according to some exemplary embodiments of the present disclosure.

[0178] It should be noted that, in order to clearly show the relative positional relationship of the light shielding parts, Figures 21 to 23 Some structures and membrane layers are omitted, for example, Figure 21 Only one thin film transistor is shown in FIG. Figure 6 The light emission control thin film transistor T6 is shown in FIG.

[0179] Combined with reference Figure 21 and Figure 22 The display panel may include: an active layer 20 disposed on a base substrate 1; a gate insulating layer 30 disposed on a side of the active layer 20 away from the base substrate 1; a gate G6 and a second capacitor electrode Cst2 disposed on a side of the gate insulating layer 30 away from the base substrate 1; a first interlayer insulating layer 40 disposed on a side of the gate G6 and the second capacitor electrode Cst2 away from the base substrate 1; a first capacitor electrode Cst1 disposed on a side of the first interlayer insulating layer 40 away from the base substrate 1; a second interlayer insulating layer 41 disposed on a side of the first capacitor electrode Cst1 away from the base substrate 1; a source electrode S6 and a drain electrode D6 disposed on a side of the second interlayer insulating layer 41 away from the base substrate 1; and a first planarization layer 50 covering the source electrode S6 and the drain electrode D6. The source electrode S6 and the drain electrode D6 are respectively connected to the active layer 20 through vias.

[0180] The active layer 20 , the gate G6 , the source S6 and the drain D6 form a light emission control thin film transistor T6 . The first capacitor electrode Cst1 and the second capacitor electrode Cst2 face each other and are spaced apart by the first interlayer insulating layer 40 to form a storage capacitor Cst.

[0181] The display panel may further include: a connecting conductive portion 70 disposed on the side of the first planarization layer 50 away from the base substrate 1, a second planarization layer 51 disposed on the side of the connecting conductive portion 70 away from the base substrate 1, an anode 81 of the OLED disposed on the side of the second planarization layer 51 away from the base substrate 1, and a pixel defining layer 90 disposed on the side of the anode 81 away from the base substrate 1. It should be understood that the OLED may further include an organic light-emitting layer and a cathode disposed on the side of the anode 81 away from the base substrate 1. The anode 81 is electrically connected to the connecting conductive portion 70 through a via 811, and the connecting conductive portion 70 is electrically connected to the drain electrode D6 through a via 701. In other words, the anode 81 is electrically connected to the drain electrode D6 through the connecting conductive portion 70.

[0182] In the example shown in the figure, the second capacitor electrode Cst2 and the gate G6 are located in the same layer, for example, formed by the same patterning process. For convenience of description, the layer where the second capacitor electrode Cst2 and the gate G6 are located can be referred to as the first conductive layer. The first capacitor electrode Cst1 is between the first conductive layer and the conductive layer where the source S6 and the drain D6 are located. For convenience of description, the layer where the first capacitor electrode Cst1 is located can be referred to as the second conductive layer, and the layer where the source S6 and the drain D6 are located can be referred to as the third conductive layer. The connecting conductive portion 70 is located on the side of the third conductive layer away from the base substrate 1. For convenience of description, the layer where the connecting conductive portion 70 is located can be referred to as the fourth conductive layer.

[0183] In the embodiment of the present disclosure, the various signal lines 61, 62, 63, 64, 65, 66, and 67 described above may be located in at least one conductive layer selected from the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer, respectively. For example, the scan signal line 61 and the previous scan signal line 62 may be located in the first conductive layer, the light emitting control line 63 may be located in the second conductive layer, the data line 64 and the drive voltage line 65 may be located in the third conductive layer, and the initialization voltage line 66 may be located in the fourth conductive layer. However, the embodiment of the present disclosure is not limited thereto, and a signal line may also be located in multiple conductive layers. For example, some drive voltage lines 65 may be located in the third conductive layer, and other drive voltage lines 65 may be located in the fourth conductive layer.

[0184] For example, the first conductive layer and the second conductive layer may be conductive layers made of gate materials, and the third conductive layer and the fourth conductive layer may be conductive layers made of source and drain materials.

[0185] For example, the gate material may include a metal material, such as Mo, Al, Cu, and their alloys. The source and drain materials may include a metal material, such as Mo, Al, Cu, and their alloys. The semiconductor material constituting the active layer may include, for example, amorphous silicon, polycrystalline silicon, an oxide semiconductor, and the like. Oxide semiconductor materials may include, for example, IGZO (indium gallium zinc oxide), ZnO (zinc oxide), and the like.

[0186] In the illustrated embodiment, the light shielding portion 100 is disposed in the fourth conductive layer, that is, the light shielding portion 100 is located in the same layer as the connecting conductive portion 70. For example, the light shielding portion 100 and the connecting conductive portion 70 can both be made of source and drain materials and formed by the same patterning process.

[0187] In this way, in order to form the light shielding portion, no additional film layer needs to be added, and no additional patterning process needs to be added, which is beneficial to process production and saves manufacturing costs.

[0188] It should be understood that the light shielding portions 100 disposed in the fourth conductive layer are not disposed continuously to avoid other structures in the fourth conductive layer, such as the connecting conductive portion 70 and some signal lines in the fourth conductive layer.

[0189] Optionally, the display panel may include a first buffer layer 11 disposed on the base substrate 1. The first buffer layer 11 may be located between the base substrate 1 and the active layer 20.

[0190] Reference Figure 8 as well as Figures 21 to 23 The orthographic projection of the light shielding portion 100 on the base substrate 1 at least covers the orthographic projection of the gaps between the plurality of signal lines (including the above-mentioned gaps 71 and 72 ) on the base substrate 1 .

[0191] Optionally, the orthographic projection of the light-shielding portion 100 on the base substrate 1 overlaps with the orthographic projection of the portion of the multiple signal lines located in the second display area AA2 on the base substrate 1, and the orthographic projection of the light-shielding portion 100 on the base substrate 1 also overlaps with the orthographic projection of the multiple thin-film transistors T1 to T7 and the storage capacitor Cst located in the second display area AA2 on the base substrate 1.

[0192] By providing the light shielding portion located in the fourth conductive layer, the gaps within each sub-pixel unit and the gaps between signal lines between sub-pixel units can be shielded, thereby avoiding diffraction and interference of imaging light.

[0193] Optionally, refer to Figure 21 and Figure 23The orthographic projection of the light shielding portion 100 on the base substrate 1 does not overlap with the orthographic projection of the anode 81 on the base substrate 1. For example, the anode 81 can be made of a light shielding material such as Ag, that is, the anode 81 can also serve as a light shield. In this way, the area occupied by the light shielding portion 100 can be reduced.

[0194] Continue to refer to Figure 21 and Figure 23 The orthographic projection of the light shielding portion 100 on the base substrate 1 is spaced apart from the orthographic projection of the anode 81 on the base substrate 1. That is, there is a certain distance between the orthographic projection of the light shielding portion 100 on the base substrate 1 and the orthographic projection of the anode 81 on the base substrate 1. In this way, the light shielding portion 100 and the anode 81 are prevented from overlapping, thereby reducing or avoiding crosstalk caused by the overlap between the two.

[0195] It should be understood that the orthographic projection of the light shielding portion 100 on the base substrate 1 does not overlap with the orthographic projection of the light-transmitting region TRA between the pixel units P2 in the second display area AA2 on the base substrate 1 for the most part. Thus, a large area of ​​light-transmitting region TRA still exists between the pixel units P2 in the second display area AA2, allowing imaging light to pass through the light-transmitting region TRA and enter the image sensor 2 disposed in the second display area AA2.

[0196] Continue to refer to Figure 21 , the light shielding portion 100 is electrically connected to the driving voltage line 65. Figure 6 and Figure 21 The driving voltage line 65 is used to supply the ELVDD voltage signal. In other words, the light shielding portion 100 is also used to supply the ELVDD voltage signal.

[0197] Specifically, refer to Figure 21 , the driving voltage line 65 is electrically connected to the light shielding portion 100 through the via hole 653. Figure 6 and Figure 21 The driving voltage line 65 is also electrically connected to the second capacitor electrode Cst2. For example, the driving voltage line 65 is electrically connected to the second capacitor electrode Cst2 through a via 652. The via 653 may penetrate the first planarization layer 50 to expose a portion of the driving voltage line 65. The via 652 may penetrate the first interlayer insulating layer 40, the first capacitor electrode Cst1, and the second interlayer insulating layer 41 to expose a portion of the second capacitor electrode Cst2.

[0198] In this way, the light shielding portion 100 is electrically connected to a stable DC voltage signal, preventing charges generated by the floating light shielding portion 100 and thus preventing ESD. Furthermore, both the light shielding portion 100 and the driving voltage line 65 function as signal lines supplying the ELVDD voltage signal, effectively reducing the IR drop effect and improving brightness uniformity.

[0199] Figure 24 The display panel according to some exemplary embodiments of the present disclosure is Figure 8 Schematic cross-sectional view taken along line CC'. Figure 25 The display panel according to some exemplary embodiments of the present disclosure is Figure 8 Schematic diagram of the cross section taken along line DD'. Figure 24 and Figure 25 The display substrate may include two light shielding portions, namely a first light shielding portion 100A and a second light shielding portion 100B. The first light shielding portion 100A may be Figure 15 and Figure 16 In the embodiment shown, the second light shielding portion 100B may be Figure 21 and Figure 22 That is, the light shielding parts in the above embodiments can be used in combination to ensure a better light shielding effect.

[0200] like Figure 24 and Figure 25 As shown, the first light shielding portion 100A may be a separate film layer, which is disposed below the active layer 20 and between the first buffer layer 11 and the second buffer layer 12. The second light shielding portion 100B may be located in the fourth conductive layer, that is, in the same layer as the connecting conductive portion 70.

[0201] Both the first light shielding portion 100A and the second light shielding portion 100B may be electrically connected to the driving voltage line 65 .

[0202] It should be understood that Figure 24 and Figure 25 The film layers, positions and connection relationships shown in the figure can be referred to the above description and will not be repeated here.

[0203] Return to reference Figure 2 At least some embodiments of the present disclosure further provide a display device. The display device may include the display panel described above and an image sensor 2 (eg, a camera).

[0204] As described above, the display panel has a first display area and a second display area, with the pixel density of the first display area being greater than that of the second display area. The image sensor 2 is located on the side of the base substrate 1 facing away from the pixel array, with the photosensitive surface of the image sensor 2 facing the display panel. The orthographic projection of the image sensor 2 on the base substrate 1 overlaps with the orthographic projection of the second display area on the base substrate 1, for example, being located within the orthographic projection of the second display area on the base substrate 1. This allows imaging using light passing through the second display area, thereby realizing an under-screen camera function.

[0205] The image sensor 2 can adopt a structure known in the art, for example, including a complementary metal oxide semiconductor (CMOS) image sensor or a charge coupled device (CCD) image sensor. The image sensor 2 can be electrically connected to an image processor. In addition to the image sensor, in order to achieve better imaging effects, the imaging module including the image sensor can also include a lens assembly, for example. The lens assembly and the image sensor can be arranged in sequence along the optical axis of the lens assembly in a direction perpendicular to the substrate 1.

[0206] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0207] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display panel, comprising: substrate; A plurality of pixel units, wherein the plurality of pixel units are arranged in an array on the substrate, each of the pixel units comprising a pixel driving circuit and a light-emitting device, wherein the pixel driving circuit is used to drive the light-emitting device; a plurality of signal lines, each of which is electrically connected to the pixel driving circuit; as well as A light shielding portion is provided on the base substrate, The orthographic projections of at least two of the plurality of signal lines on the base substrate are separated from each other by a gap, wherein the gap causes at least one of interference and diffraction to occur when at least a portion of light passes through the gap, and the orthographic projection of the light shielding portion on the base substrate at least covers the orthographic projection of the gap on the base substrate; The plurality of signal lines include scanning signal lines, light emitting control lines, data lines, driving voltage lines, initialization voltage lines and power lines; The scanning signal line, the light-emitting control line, and the initialization voltage line are arranged along the row direction, and the data line and the driving voltage line are arranged along the column direction. Each of the scanning signal line, the light-emitting control line, the initialization voltage line, the data line, and the driving voltage line includes a first portion located within the pixel unit. The gap includes a first gap. The first portion of each of the scanning signal line, the light-emitting control line, the initialization voltage line, the data line, and the driving voltage line has the first gap between each other. The orthographic projection of the light-shielding portion on the base substrate at least covers the orthographic projection of the first gap on the base substrate.

2. The display panel according to claim 1, wherein: The display panel includes a first display area and a second display area, the first display area has a first pixel density, the second display area has a second pixel density, and the first pixel density is greater than the second pixel density; The orthographic projection of the light shielding portion on the base substrate is at least located within the orthographic projection of the second display area on the base substrate.

3. The display panel according to claim 2, wherein: The gap further includes a second gap, the first gap is located within the pixel unit in the second display area, and the second gap is located between multiple pixel units in the second display area; An orthographic projection of the light shielding portion on the base substrate covers an orthographic projection of each of the first gap and the second gap on the base substrate.

4. The display panel according to claim 2 or 3, wherein: The pixel driving circuit includes a storage capacitor and at least one thin film transistor, each of the thin film transistors includes an active layer, a gate, a source electrode, and a drain electrode, and the storage capacitor includes a first capacitor electrode and a second capacitor electrode; the light emitting device includes an anode; the display panel further includes a connecting conductive portion, the connecting conductive portion being used to electrically connect one of the source electrode and the drain electrode to the anode; And wherein, the display panel comprises: a first conductive layer disposed on a side of the active layer away from the base substrate, wherein the gate and the second capacitor electrode are located in the first conductive layer; a second conductive layer disposed on a side of the first conductive layer away from the base substrate, wherein the first capacitor electrode is located on the second conductive layer; a third conductive layer disposed on a side of the second conductive layer away from the base substrate, wherein the source and the drain are located in the third conductive layer; and A fourth conductive layer is provided on a side of the third conductive layer away from the base substrate, and the connecting conductive portion is located in the fourth conductive layer.

5. The display panel according to claim 4, wherein: The light shielding portion is located in a layer different from the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer. The display panel according to claim 4 , wherein: The driving voltage line is used to supply a power voltage signal. The driving voltage line is located in the third conductive layer. The light shielding portion is electrically connected to the driving voltage line.

7. The display panel according to claim 6, wherein: The display panel further includes: a gate insulating layer disposed between the active layer and the first conductive layer; a first interlayer insulating layer disposed between the first conductive layer and the second conductive layer; a second interlayer insulating layer disposed between the second conductive layer and the third conductive layer; a first planarization layer disposed between the third conductive layer and the fourth conductive layer; and A second planarization layer is disposed between the fourth conductive layer and the anode.

8. The display panel according to any one of claims 2-3 and 5-7, wherein: The light shielding portion is located between the active layer and the base substrate.

9. The display panel according to claim 8, wherein: The orthographic projection of the light shielding portion on the base substrate covers the orthographic projection of each pixel unit in the second display area on the base substrate, and also covers the orthographic projection of the portion of the plurality of signal lines in the second display area on the base substrate.

10. The display panel according to claim 8, wherein: The light shielding portion extends continuously in the second display area.

11. The display panel according to claim 8, wherein: The outline of the orthographic projection of the light shielding portion on the base substrate has an arc-shaped boundary line; and / or the outline of the orthographic projection of the light shielding portion on the base substrate has an arc-shaped transition portion at a corner.

12. The display panel according to claim 11, wherein: The display panel also includes a plurality of light-transmitting areas located in the second display area, the orthographic projections of the plurality of light-transmitting areas on the base substrate do not overlap with the orthographic projections of the light-shielding portion on the base substrate, and the orthographic projections of each of the plurality of light-transmitting areas on the base substrate have the shape of a rounded rectangle.

13. The display panel according to claim 11, wherein: The light shielding portion is used to shield a portion of each pixel unit located in the second display area. The outline of the orthographic projection on the base substrate has an approximately rectangular shape, and arc transitions are formed at the four corners of the approximately rectangular shape.

14. The display panel according to claim 7, wherein: The display panel includes: a first buffer layer disposed on the base substrate; a second buffer layer disposed between the first buffer layer and the active layer, Wherein, the light shielding portion is located between the first buffer layer and the second buffer layer.

15. The display panel according to claim 4, wherein: The light shielding portion is located in the fourth conductive layer.

16. The display panel according to claim 15, wherein: The orthographic projection of the light shielding portion on the base substrate is spaced apart from the orthographic projection of the connecting conductive portion on the base substrate.

17. The display panel according to claim 15 or 16, wherein: The orthographic projection of the light shielding portion on the base substrate surrounds the orthographic projection of the anode on the base substrate, and the orthographic projection of the light shielding portion on the base substrate is spaced apart from the orthographic projection of the anode on the base substrate.

18. The display panel according to claim 4, wherein: The light shielding portion includes a first light shielding portion and a second light shielding portion, the first light shielding portion is located between the active layer and the base substrate, and the second light shielding portion is located in the fourth conductive layer.

19. The display panel according to claim 14, wherein: The display panel further includes a transfer conductive portion, and the transfer conductive portion is located in the first conductive layer; The driving voltage line is electrically connected to the transfer conductive portion through a first via hole penetrating the first interlayer insulating layer and the second interlayer insulating layer; as well as The switching conductive portion is electrically connected to the light shielding portion through a second via hole penetrating the gate insulating layer and the second buffer layer.

20. The display panel according to claim 7, wherein: The light shielding portion is electrically connected to the driving voltage line through a third via hole penetrating the first planarization layer.

21. The display panel according to claim 2, wherein: Each of the scan signal line, the light emitting control line, the initialization voltage line, the data line, and the driving voltage line includes a second portion located between two adjacent pixel units.

22. The display panel according to claim 21, wherein: The scanning signal line for the pixel unit located in the first display area includes an extended signal line portion that passes through the second display area in the row direction, the second portion of each of the scanning signal line, the light-emitting control line, and the initialization voltage line, and the extended signal line portion have a second gap therebetween, and the orthographic projection of the light-shielding portion on the base substrate also covers at least the orthographic projection of the second gap on the base substrate.

23. A display device comprising: The display panel according to any one of claims 2 to 22; as well as An image sensor is located on a side of the base substrate away from the light shielding portion, and an orthographic projection of the image sensor on the base substrate is located within an orthographic projection of the second display area on the base substrate.

Images