Phase synchronization of round-trip delay estimation

Abstract

Phase variations between a transmitter (TX) waveform and a receiver (RX) waveform generated by a transmitter (TX) phase-locked loop (PLL) and a receiver (RX) phase-locked loop (PLL), respectively, are an error source in processing delay calibration used, for example, in round-trip time (RTT) estimation. While the TX waveform and the RX waveform have constant phase delays under steady-state conditions, during transients, for example at start-up or reset, the phase delays can vary up to ±180°, which at a baseband frequency of 50 MHz introduces random delay variations up to ±10 nanoseconds, which is undesirable for fine position estimation using RTT. Using a phase correction signal generated using output signals of the TX PLL and the RX PLL, the phase delay variations between the TX waveform and the RX waveform can be reduced or eliminated.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefits of U.S. Provisional Application 62 / 884,634, filed August 8, 2019, entitled “Phase synchronization for round-trip delay estimation,” and U.S. Non-Provisional Application 16 / 683,162, filed November 13, 2019, entitled “Phase synchronization for round-trip delay estimation,” both of which have been assigned to their assignees and whose entire contents are expressly incorporated herein by reference. Technical Field Background Technology

[0003] Wireless communication systems have evolved through several generations, including first-generation analog wireless telephony (1G), second-generation (2G) digital wireless telephony (including temporary 2.5G and 2.75G networks), third-generation (3G) high-speed data, wireless services supporting the internet, and fourth-generation (4G) services (such as LTE or WiMax). The fifth-generation (5G) mobile standard demands even higher data transmission speeds, more connections, and better coverage, among other improvements. According to the Next Generation Mobile Networks Alliance, the 5G standard aims to provide tens of megabits per second of data rate for each of tens of thousands of users, and 1 gigabits per second for dozens of employees on an office floor.

[0004] Obtaining the location of a mobile device accessing a wireless (e.g., 5G) network can be useful for many applications, including emergency calls, personal navigation, asset tracking, locating friends or family members, etc. One type of location method is round-trip time (RTT), which is the time it takes for a signal to travel from one entity to another (e.g., from a base station to a user equipment (UE) or vice versa), plus the time it takes for a return signal (e.g., an acknowledgment of that signal) to be received. Time delay includes the propagation time of the path between two communication endpoints, which is proportional to the distance between the two endpoints. Time delay also includes processing delays within the endpoints, such as receiving, processing, and responding to signals. Processing delay is calibrated in addition to the RTT measurement to obtain an accurate location measurement. Improving the calibration of processing delay is desired to achieve more accurate location estimation. Summary of the Invention

[0005] The phase delay variation between the TX and RX waveforms generated by the transmitter (TX) phase-locked loop (PLL) and receiver (RX) PLL, respectively, is a source of error in processing delay calibration used, for example, in positioning procedures such as RTT measurements. While the TX PLL and RX PLL have a constant phase relationship under steady-state conditions, during transients, such as during startup or reset, the phase relationship between them is uncertain. At a baseband waveform frequency of 50 MHz, this can introduce random delay variations of up to ±10 nanoseconds, which is undesirable for fine position estimation using RTT. The phase delay variation between the TX and RX waveforms can be reduced or eliminated by using a phase correction signal generated from the output signals of the TX and RX PLLs.

[0006] In one embodiment, an entity in a wireless network, which is a mobile device or a base station, includes: a transmitter (TX) phase-locked loop (PLL) configured to receive a first clock signal from a reference clock and generate a TX waveform; and a receiver (RX) phase-locked loop (PLL) configured to receive a second clock signal from a reference clock and generate an RX waveform; wherein one or both of the transmitter PLL and the receiver PLL are configured to receive a phase correction signal and adjust the phase relationship between the TX waveform and the RX waveform based on the phase correction signal, such that the TX waveform and the RX waveform have the same phase relationship whenever the transmitter PLL and the receiver PLL reach a steady-state condition.

[0007] In one embodiment, a method for calibrating an entity in a wireless network, the entity being a mobile device or a base station, the method comprising: providing a first clock signal from a reference clock to a transmitter (TX) phase-locked loop (PLL), the transmitter PLL generating a TX waveform; providing a second clock signal from the reference clock to a receiver (RX) phase-locked loop (PLL), the receiver PLL generating an RX waveform; generating a phase correction signal received by the transmitter PLL and the receiver PLL; and adjusting the phase relationship between the TX waveform and the RX waveform based on the phase correction signal such that the TX waveform and the RX waveform have the same phase relationship each time the transmitter PLL and the receiver PLL reach a steady-state condition.

[0008] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0009] The accompanying drawings are provided to help describe various aspects of this disclosure, and are provided merely to illustrate these aspects and not to limit them.

[0010] Figure 1A simplified environment and exemplary techniques for determining the round-trip time (RTT) between a user equipment and a base station are shown.

[0011] Figure 2 This is a diagram illustrating exemplary timing within an RTT measurement that occurs during a wireless probe request and response initiated by a first entity and received by a second entity.

[0012] Figure 3 This is a timing diagram illustrating the RX and TX baseband signals generated by the receiver (RX) phase-locked loop (PLL) and the transmitter (TX) PLL after reaching steady-state conditions.

[0013] Figure 4 This is a graph showing the cycle slip error that may occur due to a lack of synchronization between the RX analog-to-digital converter (ADC) and the TX digital-to-analog converter (DAC).

[0014] Figure 5 This is a diagram showing the PLL that receives the phase correction signal.

[0015] Figure 6 This is a schematic diagram illustrating the generation of a phase correction signal based on the output signals from the RX PLL and TX PLL and a reference clock.

[0016] Figure 7 A block diagram is shown showing phase delay correction in the RX PLL and TX PLL using a phase correction signal.

[0017] Figure 8 This is a block diagram illustrating the synchronization between the TX DAC and RX ADC using a clock signal from a digital reference sampling clock.

[0018] Figure 9 The timing diagram of the digital clock signal and the sampling clock signal received by the TX DAC and RX ADC is shown.

[0019] Figure 10 This is a block diagram illustrating the synchronization between the TX DAC and RX ADC using a clock signal from a digital reference sampling clock controlled by a phase correction signal.

[0020] Figure 11 An exemplary method for physical calibration in a wireless network is shown. Detailed Implementation

[0021] Round-Trip Time (RTT) positioning of User Equipment (UE) uses bidirectional time-of-arrival measurements to determine the estimated distance between the UE and the base station. These measurements include processing delays within the endpoints, such as the reception, processing, and response of signals. To accurately estimate the location, these processing delays are calibrated and removed from the RTT measurements. Techniques for calibrating processing delays are disclosed, particularly techniques for calibrating delays caused by hardware within the UE or base station.

[0022] These techniques and other aspects are disclosed in the following description and related drawings with respect to specific aspects of this disclosure. Alternative aspects may be designed without departing from the scope of this disclosure. Furthermore, well-known elements of this disclosure will not be described in detail or will be omitted so as not to obscure relevant details of this disclosure.

[0023] The terms “exemplary” and / or “example” are used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” and / or “example” is not necessarily to be construed as being better than or superior to the others. Similarly, the term “aspects of this disclosure” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed.

[0024] A mobile device, also referred to herein as a UE, may be mobile or may (e.g., at certain times) be fixed and may communicate with a radio access network (RAN). As used herein, the term “UE” may be interchangeably referred to as “access terminal” or “AT”, “client device”, “wireless device”, “subscriber device”, “subscriber terminal”, “subscriber station”, “user terminal” or “UT”, “mobile terminal”, “mobile station”, or variations thereof. Typically, a UE can communicate with the core network via the RAN, and through the core network, the UE can connect to external networks (e.g., the Internet) and other UEs. Of course, other mechanisms for connecting to the core network and / or the Internet are also possible for the UE, such as via a wired access network, a WiFi network (e.g., based on IEEE 802.11, etc.), and so on. A UE can be implemented by any of a variety of types of devices, including but not limited to printed circuit (PC) cards, small flash memory devices, external or internal modems, wireless or wired telephones, smartphones, tablets, tracking devices, asset tags, etc. The communication link through which the UE sends signals to the RAN is referred to as an uplink channel (e.g., reverse traffic channel, reverse control channel, access channel, etc.). The communication links through which the RAN can send signals to the UE are called downlink or forward link channels (e.g., paging channels, control channels, broadcast channels, forward traffic channels, etc.). The term traffic channel (TCH) used here can refer to uplink / reverse or downlink / forward traffic channels.

[0025] Figure 1A simplified environment 100 and exemplary techniques for determining the round-trip time (RTT) between UE 102 and base station 110 are illustrated. UE 102 can wirelessly communicate with base station 110 using radio frequency (RF) signals and standardized protocols for RF signal modulation and packet switching. By extracting different types of information from the exchanged signals and utilizing the network layout (i.e., the network geometry including additional base stations (not shown), the location of UE 102 can be determined in a predefined reference coordinate system. For example, the determined RTT between UE 102 and base station 110 is proportional to the distance between the two communication endpoints. Using the known location of base station 110, the location of UE 102 can be determined to be on a circle (or sphere) surrounding base station 110. Using similar measurements of multiple base stations with known locations, the location of UE 102 can be determined based on the intersection of the circle (or sphere).

[0026] As shown in the figure, in phase 1 of determining the RTT between UE 102 and base station 110, base station 110 may send an RTT measurement signal (or message) 122 to UE 102. In phase 2, processor 103 in UE 102 receives the RTT measurement signal 122 and processes the signal to determine that a response message will be returned. In phase 3, UE 102 sends an RTT response signal (or message) 124 to base station 110. The total time between sending the RTT measurement signal 122 and receiving the RTT response signal 124 is the round-trip time of the measurement, i.e., the RTT measurement. In phase 4, location server 112 may receive the RTT measurement based on the time between sending the RTT measurement signal 122 from base station 110 and receiving the RTT response signal 124, and may use the RTT measurement to determine the estimated distance between UE 102 and base station 110. Location server 112 may use similar RTT measurements for UE 102 from multiple base stations and then use known geometric techniques (e.g., trilateration) to determine the estimated location of the UE.

[0027] UE 102 may include and / or be referred to as a device, mobile device, wireless device, mobile terminal, terminal, mobile station (MS), Secure User Plane Positioning (SUPL) enabled terminal (SET), or other names. Furthermore, UE 102 may correspond to a mobile phone, smartphone, laptop, tablet, PDA, tracking device, navigation device, Internet of Things (IoT) device, or some other portable or mobile device. Typically, although not required, UE 102 may support wireless communication using one or more Radio Access Technologies (RATs), such as Global System for Mobile Communications (GSM), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), LTE, High-Speed ​​Packet Data (HRPD), IEEE 802.11 WiFi (also known as WiFi). (BT), Global Microwave Access Interoperability (WiMAX), 5G New Radio Network (NR), etc. UE 102 can also support wireless communication using a Wireless Local Area Network (WLAN), which can be connected to other networks (such as the Internet) using, for example, Digital Subscriber Line (DSL) or packet cable. Using one or more of these RATs can allow UE 102 to communicate with external clients and / or allow external clients to receive location information about UE 102.

[0028] The estimation of the location of UE 102 may be referred to as location, location estimate, location positioning, positioning, location, location estimation, or location positioning, and may be geographic, thus providing the location coordinates of UE 102 (e.g., latitude and longitude), which may or may not include an altitude component (e.g., altitude above sea level, altitude above or below ground level, floor height, or basement height). Optionally, the location of UE 102 may be represented as a city location (e.g., as a postal address or designation of a point or small area within a building, such as a specific room or floor). The location of UE 102 may also be represented as an area or volume in which UE 102 is expected to be located with a certain probability or confidence level (e.g., 67%, 95%, etc.) (defined in geographic or urban form). The location of UE 102 may also be a relative location, including, for example, distance and direction defined relative to an origin at a known location, which may be defined geographicly, in urban terms, or by reference to a point, area, or space indicated on a map, floor plan, or building plan. In the description contained herein, unless otherwise stated, the use of the term “location” may include any of these variations. When calculating the location of a UE, local x, y, and possibly z coordinates are typically solved, and then, if necessary, the local coordinates are converted to absolute coordinates (e.g., latitude, longitude, and altitude above or below mean sea level).

[0029] Base station 110 can be part of a fifth-generation (5G) network, which includes a next-generation (NG) radio access network (RAN) (NG-RAN) and a 5G core network (5GC). A 5G network can also be called a new radio (NR) network; NG-RAN can be called 5G RAN or NR RAN; and 5GC can be called NG core network (NGC). Standardization of NG-RAN and 5GC is underway within the 3rd Generation Partnership Project (3GPP). Base station 110 can be referred to as an NR Node B, also known as a gNB. Base station 110 can also be part of other types of networks, such as 3G, Long Term Evolution (LTE), etc., and can be referred to as a Node B, Evolved Node B, eNodeB, etc.

[0030] During RTT measurement, various hardware components within UE 102 are necessary for receiving and transmitting signals used for RTT measurement. For example, UE 102 includes a receiver (RX) phase-locked loop (PLL) 104 and a transmitter (TX) PLL 105, a receiver (RX) analog-to-digital converter (ADC) 106, and a transmitter (TX) digital-to-analog converter (DAC) 107. UE 102 also includes one or more reference clocks 108, as well as other necessary hardware components as described above, which can be used to ensure proper calibration of any hardware delays during RTT measurement. Base station 110 may include the same or similar components for receiving and transmitting signals used for RTT measurement.

[0031] It should be understood that, although Figure 1 A general illustrative procedure is provided for RTT measurement, but other similar procedures known in the art can be used to generate RTT measurements. For example, base station 110 itself can use RTT measurements to determine the estimated distance to UE 102 and can provide the estimated distance to location server 112 instead of RTT measurements. Furthermore, instead of base station 110, UE 102 can determine RTT measurements; for example, UE 102 will send an RTT measurement signal 122 in phase 1 and receive an RTT response signal 124 from base station 110 in phase 3. UE 102 can use RTT measurements to determine the estimated distance between UE 102 and base station 110 and can determine the estimated location of UE 102. Alternatively, UE 102 can communicate with location server 112, and the location server can determine the estimated distance and / or estimated location of UE 102.

[0032] Determining the distance between UE 102 and base station 110 involves utilizing timing information from the radio frequency (RF) signals between them. For example, assuming no delay in phase 3 (i.e., no delay between receiving the RTT measurement signal 122 and sending the RTT response signal 124 in phase 1), the total time between sending the signal and receiving the acknowledgment is related to the signal propagation time, and assuming the signal is line-of-sight (LOS), the distance between entities can be easily converted by multiplying by the signal speed, i.e., the speed of light. However, in reality, processing delays affecting RTT measurements exist in both UE 102 and base station 110. Through calibration, these processing delays can be identified and removed from the RTT measurement to more accurately estimate the UE's location.

[0033] Figure 2This is a diagram illustrating exemplary timing within an RTT measurement occurring during a radio probe request and response initiated by a first entity 202 and received by a second entity 204. For example, the first entity 202 may be a base station, such as base station 110, and the second entity 204 may be a UE, such as UE 102; however, if desired, the first entity 202 may be a UE and the second entity 204 may be a base station. In one aspect, the RTT response may take the form of an acknowledgment packet (ACK); however, any type of response packet may be used.

[0034] As shown in the figure, in order to measure the RTT relative to the second entity 204, the first entity 202 can send a directional probe request, such as a downlink RTT reference signal, to the second entity 204, and record the time (timestamp) when the probe request packet is sent (t). TX (Grouped), as shown on the timeline of the first entity 202. During the propagation time t from the first entity 202 to the second entity 204... P Subsequently, the second entity 204 will receive the packet. The second entity 204 can then process the directional probe request and, after a certain processing time, such as after a processing delay, can send an acknowledgment (acknowledgment) back to the first entity 202, for example, an uplink RTT reference signal, as shown on the timeline of the second entity 204. At the second propagation time t p Subsequently, the first entity 202 can record the time (timestamp) of receiving the ACK packet (tRX ACK), as shown on the timeline of the first entity 202. It should be understood that within the first entity 202, there may be some processing delay between receiving the ACK packet and timestamping the ACK packet. The first entity 202, or other entities such as the second entity 204 or a location server, can determine the total RTT as the time difference t. RX ACK-t TX Packet. Net RTT, i.e., bidirectional propagation time (2*t). p The processing latency can be determined based on the difference between the total RTT and the processing delay. Therefore, calibrating the processing latency is very important.

[0035] like Figure 2As shown, the processing latency includes latency caused by the hardware (HW) within the second entity 204. Furthermore, as indicated by arrow 206, the amount of hardware-induced latency can be variable. The first entity 202 similarly suffers from hardware-induced processing latency. Currently, location estimation based on round-trip time is coarse enough that any variation in hardware latency is considered negligible. However, if more accurate location estimation is desired, for example, under 5G mobile standards considering wideband waveforms based on millimeter-wave carrier frequencies (e.g., FR2, FR4, etc.), then variations in hardware latency in entities such as the second entity 204 and the first entity 202 are no longer negligible and must be properly calibrated or controlled. For example, location estimation currently considered under the 5G Rel 17 3GPP standard requires a hardware calibration process that estimates electrical latency of less than 1 nanosecond.

[0036] One reason for the variation in hardware latency is due to Figure 1 The RX PLL104 and TX PLL105 shown lack synchronization. The RX PLL104 and TX PLL105 control the timing of UE 102 (or a similar component that controls the timing of signal reception and transmission in base station 110) to receive and transmit signals.

[0037] For example, Figure 3 This is a timing diagram illustrating the RX and TX baseband signals generated by RX PLL104 and TX PLL105, respectively. The RX and TX baseband signals are shown to have the same frequency, but it should be understood that they can have different frequencies. Once the RX PLL and TX PLL are in steady-state conditions, the RX baseband waveform and the TX baseband waveform have a fixed phase relationship. For example, the RX baseband signal (i.e., the RX waveform) and the TX baseband signal (i.e., the TX waveform) can be described as follows.

[0038]

[0039]

[0040] The phase difference δφ between the RX and TX signals is the difference This phase difference δφ causes the receive and transmit clocks to misalign, and is therefore a source of hardware delay in UE 102 and base station 110 during RTT measurements.

[0041] As long as the RX PLL and TX PLL maintain steady-state conditions, the phase difference δφ between the TX and RX waveforms will remain constant. However, during transients of the RX PLL, TX PLL, or both, the phase difference δφ does not remain constant and may change by up to ±180° until the PLL reaches steady-state conditions. This locks the resulting phase difference δφ between the TX and RX waveforms until the next transient occurs. At a baseband frequency of 50 MHz, this uncertainty introduces random delay variations of up to ±10 nanoseconds. Whenever one or more of the RX PLL and TX PLL experience a transient, such as during startup or reset, the phase difference δφ between the baseband waveforms will change. Therefore, the hardware delay caused by the phase difference δφ between the TX and RX waveforms is variable and is a source of error in handling delay calibration.

[0042] Therefore, in order to accurately determine and eliminate the processing delay in RTT measurements, it is necessary to perform phase calibration on the RX PLL and TX PLL to address the variable phase difference δφ between the RX and TX waveforms.

[0043] Another source of hardware latency during RTT measurements is the lack of synchronization between the RX ADC 106 and TX DAC 107, such as... Figure 1 As shown, the lack of synchronization between RX ADC 106 and TX DAC 107 causes cycle slip errors. To accurately identify and eliminate processing delays in RTT measurements, the lack of synchronization between RX ADC 106 and TX DAC 107 (or similar components in base station 110) needs to be addressed.

[0044] For example, Figure 4 It is shown that due to Figure 1 The graph shows the cycle slip error that may occur due to the lack of synchronization between the RX ADC 106 and TX DAC 107. The cycle slip between the RX ADC 106 and TX DAC 107 is due to these systems operating asynchronously with an unreasonable sampling clock ratio. For example, for every N clock cycles of the RX ADC 106, the TX DAC 107 may have M clock cycles. Due to frequency drift and the unreasonable clock ratio, for every N cycles of the RX ADC 106, the TX DAC 107 will occasionally have M+1 cycles or M-1 cycles, resulting in a cycle slip error that will generate positioning errors.

[0045] Figure 5 This is a diagram of a PLL 500. A PLL 500 can be... Figure 1 The RX PLL 104 or TXTPLL 105 shown in UE 102, or may be Figure 1A similar RX PLL or TX PLL is used in base station 110. PLL 500 receives a clock signal from a reference clock (REFCLK) 502, which can be a digitally controlled crystal oscillator (DCXO). The clock signal is divided by a reference divider 504. PLL 500 includes a phase frequency detector (PFD) 506, which can be a time-to-digital converter (TDC). PFD 506 also receives a feedback signal from a feedback divider 516 and provides an output signal representing the time interval (e.g., error) between the reference clock and the feedback signal. A digital loop filter 508, which can function as a low-pass filter, receives the output signal from PFD 506. The output of digital loop filter 508 is received by a digitally controlled oscillator (DCO) model 510 circuit, shown as including a digital-to-analog converter (DAC) 512 and a voltage-controlled oscillator (VCO) 514 that generates the output signal VCO. The output signal VCO from DCO model 510 is also divided by feedback divider 516 and provided to PFD 506 in the feedback loop. Feedback divider 516 can be controlled by the frequency control word (FCW) of ΣΔ modulator 518.

[0046] Digital and fractional PLLs utilize various divider ratios, such as in reference divider 504 and feedback divider 516, to select the desired output frequency. The division ratio is programmable and is sometimes driven by a ΣΔ modulator, such as ΣΔ modulator 518, to provide fine frequency resolution. However, calibrating the phase delay of the center frequencies of all PLL channels and the loop filter bandwidth is impractical. Therefore, single-point calibration is desirable. A phase difference δφ can be achieved using phase synchronization between multiple PLLs; this phase difference is constant and does not change even after transient times, such as during startup or reset.

[0047] Most signal delays in a digital PLL (such as PLL 500) are predictable and unaffected by uncertainties or variations during transients, such as the power-on state. For example, the output phase of PFD 506 is always aligned with the received reference clock. The filter delay from digital loop filter 508 is fixed and predictable. The phase delay generated by feedback divider 516 varies with a known division ratio. However, the phase delay from DCO model 510 varies with the initial state of DAC 512 and is therefore a source of uncertainty in PLL signal delay.

[0048] like Figure 5As shown, a phase correction signal can be provided to the digital loop filter 508 and / or the ΣΔ modulator 518. The phase correction signal can be used to ensure that the phase of the output VCO generated by the PLL 500 is constant relative to the output VCO generated by another PLL. The phase correction signal alters the response of the digital loop filter 508 to introduce a delay as needed. For example, a delay can be introduced by recalculating the coefficients of the digital loop filter or by turning an additional time delay on / off. If the phase correction signal is provided to the ΣΔ modulator 518, it can cause the ΣΔ modulator 518 to adjust the feedback divider 516 to introduce a delay as needed.

[0049] Figure 6 This diagram illustrates a phase matching estimation circuit 600, which generates phase correction signals to be provided to the RX PLL and TX PLL in UE 102 or base station 110. The phase matching estimation circuit 600 determines the phase / time delay between two sampled versions of a reference clock, e.g., a reference clock sampled simultaneously by the RX PLL and TX PLL, and calculates a single-point discrete Fourier transform (DFT).

[0050] As shown in the figure, in the first branch, the first differential ADC driver 602 receives a reference clock signal and a frequency sample (Fs) from the output signal VCO of the RX PLL. A rotator circuit 604 rotates the output signal from the differential ADC driver 602 and then averages it using an averaging circuit 606. The resulting signal is provided to the phase estimation circuit 620 as input A. The phase-matching estimation circuit 600 can use a Fast Fourier Transform (FFT) to calculate the DFT of the sampled reference clock. The important FFT bin is located at the reference clock frequency. By rotating the data with the rotator circuit 604, the bin of interest is shifted down to DC. The averaging circuit 606 calculates a windowed average of the amplitude and phase of the sampled reference clock in the frequency domain. Phase information captures the phase delay of the sampled clock of the ADC (not shown) in the phase estimation circuit 620. Similarly, in the second branch, the second differential ADC driver 612 receives a reference clock signal and a frequency sample (Fs) from the output signal VCO of the TX PLL. A rotator circuit 614 rotates the output signal from the differential ADC driver 612 and then averages it using an averaging circuit 616. The resulting signal is provided to the phase estimation circuit 620 as input B. The phase estimation circuit 620 receives inputs A and B and performs complex division to calculate the phase difference between the two inputs A and B. The phase difference information is then used to calculate the phase correction signal to be sent to the two PLLs. For example, the phase correction signal can be derived from the phase difference by calculating the group delay that needs to be applied to the digital loop filter 508 of the PLL or the time delay that needs to be applied to the digital divider (e.g., in the ΣΔ modulator 518 and the feedback divider 516).

[0051] Figure 7 A block diagram illustrating phase delay correction in RX PLL 702 and TX PLL 704 is shown, which can be in a UE such as UE 102, or in a base station such as base station 110. As shown, reference clock 706 provides a reference clock signal to RX PLL 702 and TX PLL 704, as well as phase matching estimation circuit 708. RX PLL 702 and TX PLL 704 can be similar to... Figure 5 The PLL 500 shown. One or both of the RX PLL 702 and TX PLL 704 can receive a phase correction signal from the phase matching estimation circuit 708 and adjust the phase relationship between the TX waveform (TX VCO) and the RX waveform (RX VCO) based on the phase correction signal, so that the TX waveform and the RX waveform have the same phase relationship whenever the transmitter PLL and the receiver PLL reach steady-state conditions. Figure 7The diagram shows that RX PLL 702 and TX PLL 704 receive the phase correction signal and generate RX VCO and TX VCO signals, respectively. The phase matching estimation circuit 708 can be similar to... Figure 6 The phase matching estimation circuit 600 shown can receive the RX VCO and TX VCO signals in addition to the reference clock signal, and generate the phase correction signal as discussed here.

[0052] By using the phase matching estimation circuit 708, the RX VCO and TXVCO signals generated by RX PLL 702 and TX PLL 704 are guaranteed to have a phase difference δφ between the TX waveform and the RX waveform. This phase difference is constant and will not change even after the transient time of one or both of RX PLL 702 and TX PLL 704, such as during startup or reset.

[0053] Figure 8 This is a block diagram illustrating the synchronization between TX DAC 802 and RX ADC 804, which can be in a UE such as UE 102, or in a base station such as base station 110. Traditionally, the TX DAC and RX ADC use independent clocks for various reasons, including: power saving (e.g., sometimes neither TX nor RX needs to be turned on during standby), using a variable sampling clock for TX to avoid spurious signals; and different phase noise requirements between the TX DAC and RX ADC clocks. However, as... Figure 8 As shown, both the TX DAC 802 and RX ADC 804 use the same digital reference clock 806. The TX DAC 802 receives the clock signal after it passes through divider 808, which divides the sampling clock by N. The RX ADC 804 receives the clock signal after it passes through a second divider 810, which divides the sampling clock by M. The TX and RX sampling clock ratio (N / M) is a rational number. Using the same clock 806 for both the TX DAC 802 and RX ADC 804, with a rational sampling clock ratio (N / M), enables clock synchronization between the TX DAC 802 and RX ADC 804, preventing cycle slip errors. Figure 4 As shown.

[0054] For example, Figure 9The timing diagram shows the digital clock signal CLK, the sampled clock signal TX CLK received by TX DAC 802 after the clock signal is divided by N by frequency divider 808 (where N = 2), and the sampled clock signal RX CLK received by RX ADC 804 after the clock signal is divided by M by frequency divider 808 (where M = 3). It can be seen that for a rational sampling clock ratio (N / M = 2 / 3), for every two TX CLK cycles of TX DAC 802, RX ADC 804 has exactly three RX CLK cycles, thus avoiding cycle slip error.

[0055] Figure 10 This is a block diagram illustrating another implementation of clock synchronization between the TX DAC 802 and the RX ADC 804. Figure 10 The system shown is similar to Figure 8 The system shown has the same specified components. However, as Figure 10 As shown, the digital clock 1006 can receive a phase correction signal, such as from a phase matching estimation circuit, like... Figure 6 and 7 As shown, the phase correction signal can control the digital clock 1006, causing the TX DAC 802 and RX ADC 804 to receive clock signals aligned with the TX VCO and RX VCO signals generated by the TX PLL704 and RX PLL702, thereby eliminating another possible source of variable hardware delay.

[0056] Figure 11 An exemplary method 1100 for calibrating an entity in a wireless network, such as a mobile device like UE 102 or a base station like base station 110, is illustrated. As shown in block 1102, a first clock signal is provided from a reference clock to a transmitter (TX) phase-locked loop (PLL), such as TX PLL 704, which generates the TX waveform. In block 1104, a second clock signal is provided from the reference clock to a receiver (RX) PLL (e.g., RX PLL 702) that generates the RX waveform. In block 1106, a phase correction signal is generated, which is received by both the transmitter PLL and the receiver PLL. In block 1108, the phase relationship between the TX and RX waveforms is adjusted based on the phase correction signal such that the TX and RX waveforms have the same phase relationship whenever the transmitter PLL and the receiver PLL reach a steady-state condition.

[0057] In some implementations, a phase correction signal can be generated by receiving a third clock signal from a reference clock; receiving a TX waveform; receiving an RX waveform; determining the phase relationship between the TX waveform and the RX waveform; and generating a phase correction signal based on the phase relationship between the TX waveform and the RX waveform.

[0058] In some implementations, the phase relationship between the TX and RX waveforms is adjusted based on a phase correction signal by adjusting at least one of the transmitter loop filter or transmitter ΣΔ modulator in the transmitter feedback divider of the transmitter PLL to change the phase delay in the TX waveform, and by adjusting one of the receiver loop filter or receiver ΣΔ modulator in the receiver feedback divider of the receiver PLL to change the phase delay in the RX waveform.

[0059] In some embodiments, the method may further include: providing a third clock signal from a digital reference sampling clock to a transmitter digital-to-analog converter; and providing a fourth clock signal from the digital reference sampling clock to a receiver analog-to-digital converter; wherein the ratio of the third clock signal to the fourth clock signal is a rational number. For example, the method may further include: generating the third clock signal by dividing the clock signal from the digital reference sampling clock by N, where N is an integer; and generating the fourth clock signal by dividing the clock signal from the digital reference sampling clock by M, where M is an integer, and the ratio N / M is a rational number. Furthermore, the clock signal may be generated from the digital reference sampling clock based on a phase correction signal.

[0060] Depending on the application, the methods described herein can be implemented in various ways. For example, these methods can be implemented in hardware, firmware, software, or any combination thereof. For hardware implementation, one or more processors can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, electronic devices, other electronic units designed to perform the functions described herein, or combinations thereof.

[0061] For implementations involving firmware and / or software, the methods can be implemented using modules (e.g., procedures, functions, etc.) that perform the individual functions described herein. Any machine-readable medium with tangibly embedded instructions can be used to implement the methods described herein. For example, software code can be stored in memory and executed by one or more processors, such that the one or more processors operate as a dedicated computer programmed to perform the techniques disclosed herein. Memory can be implemented within one or more processors or external to one or more processors. As used herein, the term "memory" refers to any type of long-term, short-term, volatile, non-volatile, or other memory, and is not limited to any particular type or number of memories, or the type of medium on which the memory is stored.

[0062] If implemented in firmware and / or software, the functions performed can be stored as one or more instructions or code on a non-transitory computer-readable storage medium. Examples of storage media include computer-readable media encoded with data structures and computer-readable media encoded with computer programs. Computer-readable media include physical computer storage media. Storage media can be any available medium accessible to a computer. By way of example and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices, semiconductor storage devices or other storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and is accessible to a computer; disks and discs as used herein include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0063] In addition to storage on a computer-readable storage medium, instructions and / or data can be provided as signals on a transmission medium included in the communication device. For example, an apparatus may include a transceiver having signals indicating instructions and data. Instructions and data are stored on a non-transitory computer-readable medium, such as memory, and configured to cause one or more processors to operate as a dedicated computer programmed to perform the techniques disclosed herein. That is, the communication device includes a transmission medium having signals indicating information to perform the disclosed functions. At a first time, the transmission medium included in the communication device may include a first portion of information to perform the disclosed functions, and at a second time, the transmission medium included in the communication device may include a second portion of information to perform the disclosed functions.

[0064] Therefore, entities in a wireless network, such as mobile devices or base stations, may include means for providing a first clock signal from a reference clock to a transmitter (TX) phase-locked loop (PLL) that generates TX waveforms, which may be, for example... Figure 7 The reference clock 706 and TX PLL 704 are shown. The means for providing a second clock signal from the reference clock to the receiver PLL that generates the RX waveform can be, for example, as... Figure 7 The reference clock 706 and RX PLL 702 are shown. The means for generating the phase correction signal received by the transmitter PLL and receiver PLL can be, for example... Figure 6 The phase matching estimation circuit 600 shown is or Figure 7The phase matching estimation circuit 708 shown is used to adjust the phase relationship between the TX and RX waveforms based on the phase correction signal, so that the TX and RX waveforms have the same phase relationship each time the transmitter PLL and receiver PLL reach steady-state conditions. The means for this purpose can be, for example... Figure 5 The digital loop filter 508 and / or ΣΔ modulator 518 in the PLL 500 shown.

[0065] In some embodiments, the means for generating the phase correction signal may include: means for receiving a third clock signal from a reference clock, the reference clock being, for example... Figure 6 The reference clock (REFCLCK) shown; the device for receiving the Tx waveform, which can be, for example... Figure 6 In this context, Fs = Tx VCO; the device used to receive the Rx waveform can be, for example... Figure 6 In this context, Fs = Rx VCO; the device used to determine the phase relationship between the TX and RX waveforms can be, for example... Figure 6 The phase estimation circuit 620 in the middle; and the means for generating a phase correction signal based on the phase relationship between the TX waveform and the RX waveform, which may be, for example, Figure 6 The phase estimation circuit 620 in the middle.

[0066] In some embodiments, the means for adjusting the phase relationship between the TX and RX waveforms based on a phase correction signal may include: means for adjusting at least one of the transmitter loop filter or the transmitter ΣΔ modulator in the transmitter feedback divider of the transmitter PLL to change the phase delay in the TX waveform, which may be, for example... Figure 5 The phase correction signal inputs to the digital loop filter 508 and / or ΣΔ modulator 518 in the PLL 500 shown; and means for adjusting one of the receiver loop filter or receiver ΣΔ modulator in the receiver feedback divider of the control receiver PLL based on the phase correction signal to change the phase delay in the RX waveform, which may be, for example... Figure 5 The phase correction signal inputs are the digital loop filter 508 and / or the ΣΔ modulator 518 in the PLL 500 shown.

[0067] In some embodiments, the entity may further include means for providing a fourth clock signal from the digital reference sampling clock to a transmitter digital-to-analog converter, which may be, for example... Figure 8 The connection between the digital clock 806 and the TXDAC 802 is shown. The means for providing a fifth clock signal from the digital reference sampling clock to the receiver analog-to-digital converter can be, for example... Figure 8The connection between the digital clock 806 and the RX ADC 804 is shown. The ratio of the fourth clock signal to the fifth clock signal can be a rational number. In one implementation, the entity may further include means for generating the fourth clock signal by dividing the clock signal from the digital reference sampling clock by N, where N is an integer, which can be, for example... Figure 8 The frequency divider 808 shown; and means for generating a fifth clock signal by dividing the clock signal from the digital reference sampling clock by M, where M is an integer, and where the ratio N / M is a rational number, which can be, for example... Figure 8 The frequency divider 808 is shown.

[0068] In one embodiment, the entity may further include means for generating a clock signal from a digital reference sampling clock based on a phase correction signal, the phase correction signal being, for example, input to... Figure 10 The phase correction signal of the digital clock 1006 is shown. Although the foregoing disclosure illustrates illustrative aspects of the disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of the disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims according to the aspects of the disclosure described herein do not need to be performed in any particular order. Furthermore, although elements of this disclosure may be described or claimed in the singular, the plural form is also contemplated unless a limitation on the singular is explicitly stated.

Claims

1. An entity in a wireless network, said entity being either a mobile device or a base station, said entity comprising: The transmitter TX phase-locked loop (PLL) is configured to receive a first clock signal from a reference clock and generate a TX waveform. The receiver RX phase-locked loop (PLL) is configured to receive a second clock signal from the reference clock and generate an RX waveform. One or both of the transmitter PLL and the receiver PLL are configured to receive a phase correction signal and adjust the phase relationship between the TX waveform and the RX waveform based on the phase correction signal, such that the TX waveform and the RX waveform have the same phase relationship whenever the transmitter PLL and the receiver PLL reach a steady state condition; The transmitter digital-to-analog converter is configured to receive a third clock signal from a digital reference sampling clock; and The receiver analog-to-digital converter is configured to receive a fourth clock signal from the digital reference sampling clock; The ratio of the third clock signal to the fourth clock signal is a rational number.

2. The entity according to claim 1, further comprising: A phase-matching estimation circuit is configured to receive a fifth clock signal from the reference clock, the TX waveform, and the RX waveform. The phase-matching estimation circuit is configured to determine the phase relationship between the TX waveform and the RX waveform, and generate the phase correction signal to generate the phase relationship between the reference clock and the TX waveform.

3. The entity of claim 1, wherein the transmitter loop filter or transmitter controlling the transmitter feedback divider in the transmitter PLL One of the modulators is configured to receive the phase correction signal and adjust the phase delay in the TX waveform, and wherein the receiver loop filter or receiver in the receiver feedback divider of the receiver PLL controls the receiver loop filter. One of the modulators is configured to receive the phase correction signal and adjust the phase delay in the RX waveform.

4. The entity according to claim 1, further comprising: A first divider coupled to the digital reference sampling clock divides the clock signal from the digital reference sampling clock by N to generate the third clock signal received by the transmitter digital-to-analog converter, where N is an integer; and A second divider coupled to the digital reference sampling clock divides the clock signal from the digital reference sampling clock by M to generate the fourth clock signal received by the receiver analog-to-digital converter, where M is an integer and the ratio N / M is a rational number.

5. The entity of claim 1, wherein the digital reference sampling clock is configured to receive the phase correction signal and generate a digital clock signal based on the phase correction signal.

6. A method for calibrating an entity in a wireless network, said entity being either a mobile device or a base station, the method comprising: A first clock signal is provided from a reference clock to the transmitter TX phase-locked loop PLL, and the transmitter PLL generates the TX waveform; A second clock signal is provided from the reference clock to the receiver RX phase-locked loop PLL, and the receiver PLL generates the RX waveform; Generate a phase correction signal received by the transmitter PLL and the receiver PLL; The phase relationship between the TX waveform and the RX waveform is adjusted based on the phase correction signal, so that the TX waveform and the RX waveform have the same phase relationship whenever the transmitter PLL and the receiver PLL reach the steady state condition; A third clock signal is provided from the digital reference sampling clock to the transmitter digital-to-analog converter; as well as A fourth clock signal is provided from the digital reference sampling clock to the receiver analog-to-digital converter; The ratio of the third clock signal to the fourth clock signal is a rational number.

7. The method of claim 6, wherein generating the phase correction signal comprises: Receive a fifth clock signal from the reference clock; Receive the TX waveform; Receive the RX waveform; Determine the phase relationship between the TX waveform and the RX waveform; and The phase correction signal is generated based on the phase relationship between the TX waveform and the RX waveform.

8. The method of claim 6, wherein adjusting the phase relationship between the TX waveform and the RX waveform based on the phase correction signal comprises: Based on the phase correction signal, adjust the transmitter loop filter or transmitter in the transmitter feedback divider of the transmitter PLL to control the transmitter loop filter or transmitter. At least one of the modulators, to change the phase delay in the TX waveform; and Based on the phase correction signal, adjust the receiver loop filter or receiver in the receiver feedback divider of the receiver PLL to control the receiver loop filter or receiver. One of the modulators is used to change the phase delay in the RX waveform.

9. The method of claim 6, further comprising: The third clock signal is generated by dividing the clock signal from the digital reference sampling clock by N, where N is an integer; and The fourth clock signal is generated by dividing the clock signal from the digital reference sampling clock by M, where M is an integer and the ratio N / M is a rational number.

10. The method of claim 6, further comprising generating a clock signal from the digital reference sampling clock based on the phase correction signal.

11. An entity in a wireless network, said entity being either a mobile device or a base station, said entity comprising: A means for providing a first clock signal from a reference clock to a transmitter TX phase-locked loop (PLL) that generates the TX waveform; A means for providing a second clock signal from the reference clock to the receiver RX PLL that generates the RX waveform; A means for generating a phase correction signal received by the transmitter PLL and the receiver PLL; A device for adjusting the phase relationship between the TX waveform and the RX waveform based on the phase correction signal, such that the TX waveform and the RX waveform have the same phase relationship whenever the transmitter PLL and the receiver PLL reach a steady state condition; A means for providing a third clock signal from a digital reference sampling clock to a transmitter digital-to-analog converter; and A means for providing a fourth clock signal from the digital reference sampling clock to the receiver analog-to-digital converter; The ratio of the third clock signal to the fourth clock signal is a rational number.

12. The entity of claim 11, wherein the means for generating the phase correction signal comprises: A means for receiving a fifth clock signal from the reference clock; A device for receiving the TX waveform; A means for receiving the RX waveform; A means for determining the phase relationship between the TX waveform and the RX waveform; and A means for generating the phase correction signal based on the phase relationship between the TX waveform and the RX waveform.

13. The entity according to claim 11, wherein, The apparatus for adjusting the phase relationship between the TX waveform and the RX waveform based on the phase correction signal includes: Transmitter loop filter or transmitter used to adjust and control the transmitter feedback divider in the transmitter PLL based on the phase correction signal. At least one of the modulators is used to change the phase delay in the TX waveform; and The receiver loop filter or receiver used to adjust and control the receiver feedback divider in the receiver PLL based on the phase correction signal. One of the modulators is a device for changing the phase delay in the RX waveform.

14. The entity according to claim 11, further comprising: A means for generating the third clock signal by dividing the clock signal from the digital reference sampling clock by N, where N is an integer; and A means for generating the fourth clock signal by dividing the clock signal from the digital reference sampling clock by M, where M is an integer and the ratio N / M is a rational number.

15. The entity of claim 11, further comprising means for generating a clock signal from the digital reference sampling clock based on the phase correction signal.

16. A non-transitory storage medium including program code stored thereon, the program code being operable to control at least one processor in an entity in a wireless network, the entity being either a mobile device or a base station, comprising: The first clock signal is provided from the reference clock to the transmitter TX phase-locked loop PLL that generates the TX waveform, and the second clock signal is provided from the reference clock to the receiver RX PLL that generates the RX waveform. Program code for generating phase correction signals received by the transmitter PLL and the receiver PLL; and Program code for adjusting the phase relationship between the TX waveform and the RX waveform based on the phase correction signal, such that the TX waveform and the RX waveform have the same phase relationship whenever the transmitter PLL and the receiver PLL reach a steady state condition; Program code used to provide a third clock signal from the digital reference sampling clock to the transmitter digital-to-analog converter; as well as Program code for providing a fourth clock signal from the digital reference sampling clock to the receiver analog-to-digital converter; The ratio of the third clock signal to the fourth clock signal is a rational number.

17. The non-transitory storage medium of claim 16, wherein the program code for generating the phase correction signal comprises: Program code for receiving a fifth clock signal from the reference clock; Program code for receiving the TX waveform; Program code for receiving the RX waveform; Program code used to determine the phase relationship between the TX waveform and the RX waveform; and Program code for generating the phase correction signal based on the phase relationship between the TX waveform and the RX waveform.

18. The non-transitory storage medium according to claim 16, wherein, The program code for adjusting the phase relationship between the TX waveform and the RX waveform based on the phase correction signal includes: Transmitter loop filter or transmitter used to adjust and control the transmitter feedback divider in the transmitter PLL based on the phase correction signal. Program code for at least one of the modulators to change the phase delay in the TX waveform; and The receiver loop filter or receiver used to adjust and control the receiver feedback divider in the receiver PLL based on the phase correction signal. The program code for one of the modulators to change the phase delay in the RX waveform.

19. The non-transitory storage medium according to claim 16, further comprising: Program code for generating the third clock signal by dividing the clock signal from the digital reference sampling clock by N, where N is an integer; and Program code for generating the fourth clock signal by dividing the clock signal from the digital reference sampling clock by M, where M is an integer and the ratio N / M is a rational number.

20. The non-transitory storage medium of claim 16, further comprising program code for generating a clock signal from the digital reference sampling clock based on the phase correction signal.

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