Integrated circuits and semiconductor devices

Abstract

This invention provides an integrated circuit capable of detecting switch faults without using a complex structure. The integrated circuit includes: a first line connected to the drain electrode of a first MOS transistor and the drain electrode of a second MOS transistor, the source electrode of the first MOS transistor being connected to a first terminal to which a power supply voltage is applied, and the source electrode of the second MOS transistor being connected to a second terminal to which a load is connected; a second line to which a first voltage lower than the power supply voltage is applied; a first element connecting the first line and the second line such that the first line is not in a floating state; and a detection circuit that, when the first MOS transistor and the second MOS transistor are turned off, detects at least whether an abnormality exists in the first MOS transistor based on the voltage level of the first line.

Description

Technical Field

[0001] This invention relates to integrated circuits and semiconductor devices. Background Technology

[0002] The ECU (Electronic Control Unit), located between the vehicle's battery and loads such as the electric motor, typically includes a switch for supplying power from the battery to the load. Alternatively, as a switch for supplying power to the load, two MOS transistors connected in series are sometimes used (e.g., Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-54384 Summary of the Invention

[0006] The technical problem that the invention aims to solve

[0007] However, if the two MOS transistors are repeatedly switched on and off, they may malfunction. Patent Document 1 detects malfunctions by changing the voltage applied to a predetermined node connecting the two MOS transistors. However, this technique complicates the detection circuitry because it requires detecting voltage changes at the predetermined node.

[0008] The present invention was made in view of the aforementioned problems, and its object is to provide an integrated circuit capable of detecting switch faults without using a complex structure.

[0009] Technical means for solving technical problems

[0010] The integrated circuit of the present invention, primarily used to solve the above-mentioned problems, includes: a first line connected to the drain electrode of a first MOS transistor and the drain electrode of a second MOS transistor, wherein the source electrode of the first MOS transistor is connected to a first terminal to which a power supply voltage is applied, and the source electrode of the second MOS transistor is connected to a second terminal to which a load is connected; a second line to which a first voltage lower than the power supply voltage is applied; a first element connected to the first line and the second line such that the first line is not in a floating state; and a detection circuit that, when the first MOS transistor and the second MOS transistor are turned off, detects at least whether there is an abnormality in the first MOS transistor based on the voltage level of the first line.

[0011] The semiconductor device of the present invention, primarily used to solve the above-mentioned problems, includes: a first MOS transistor and a second MOS transistor, the drain electrodes of which are connected between a first terminal to which a power supply voltage is applied and a second terminal to which a load is connected; a first line connected to the drain electrodes of the transistors; a second line to which a first voltage lower than the power supply voltage is applied; a first element connecting the first line and the second line such that the first line is not in a floating state; and a detection circuit that, when the first MOS transistor and the second MOS transistor are turned off, detects at least whether an abnormality exists in the first MOS transistor based on the voltage level of the first line.

[0012] Invention Effects

[0013] According to the present invention, an integrated circuit capable of detecting switch faults can be provided without using a complex structure. Attached Figure Description

[0014] Figure 1 This is a diagram showing an example of an electric motor control device 10.

[0015] Figure 2 This is a diagram representing an example of IPS 21.

[0016] Figure 3 This is a diagram showing an example of a voltage generation circuit 70.

[0017] Figure 4 This is a diagram showing an example of a voltage generation circuit 71.

[0018] Figure 5 This is a diagram showing an example of the discharge circuit 77.

[0019] Figure 6 This is a diagram used to illustrate the operation of the detection circuit 78.

[0020] Figure 7 This diagram illustrates the state where the power supply voltage Vcc is stopped from being supplied to the NMOS transistor M1.

[0021] Figure 8 This is a diagram showing the state of coil 12 when it is disconnected from the OUT terminal. Detailed Implementation

[0022] Based on the description in this specification and the accompanying drawings, at least the following matters are clearly defined.

[0023] This implementation method

[0024] Figure 1FIG. 0 is a diagram showing the structure of a motor control device 10 according to an embodiment of the present invention. The motor control device 10 is a device that controls a coil 12 of a motor provided in a vehicle using power from a battery 11, and includes an ECU 13. The battery 11 is, for example, a lithium-ion battery for a vehicle, and outputs a power supply voltage Vcc of 12V.

[0025] The ECU 13 is a device for controlling the coil 12, and includes a microcomputer 20, an IPS (Intelligent Power Switch) 21, and a switch 22.

[0026] The microcomputer 20 controls the IPS 21 and the switch 22 based on an instruction (not shown) input from the outside. Further, when a signal indicating an abnormality in a circuit or the like inside the IPS 21 is output from the IPS 21, the microcomputer 20, for example, stops the operation of the IPS 21 and opens the switch 22.

[0027] The IPS 21 is a "semiconductor device" that switches whether to supply the power supply voltage Vcc of the battery 11 to the coil 12 based on a signal Sin output from the microcomputer 20. Further, the IPS 21 outputs a signal So indicating whether there is an abnormality in the internal circuit or the like. The IPS 21 includes terminals VCC, GND, IN, ST, and OUT. The power supply voltage Vcc of the battery 11 is applied to the terminal VCC, and the terminal GND is grounded. Further, the signal Sin from the microcomputer 30 is input to the terminal IN, and the signal So indicating whether there is an abnormality in the internal circuit or the like is output from the terminal ST. Further, the terminal OUT is a terminal connected to the coil 12 as a load through the switch 22. When a switch (described later) inside the IPS 21 is turned on, the voltage Vcc is output from the terminal OUT. In the present embodiment, the voltage of the terminal GND is set to the ground voltage Vgnd (0V).

[0028] Further, the IPS 21切实 protects the coil 12 and the ECU 13 when the battery 11 is reversely connected, which will be specifically described later. Hereinafter, in the present embodiment, for convenience, it is assumed that the microcomputer 20 turns on the switch 22 for explanation. Further, in the present embodiment, "connected" means electrically connected between two nodes through wiring or electrical components.

[0029] <<<Structure of IPS21>>>

[0030] Figure 2 FIG. 19 is a diagram showing an example of the structure of the IPS 21. The IPS 21 includes an IC (Integrated Circuit) 50 in which a switch (described later) is formed and an IC 51 having a circuit for turning on and off the switch.

[0031] ===IC50===

[0032] IC50 includes two MOS transistors that constitute a switch (hereinafter referred to as "switch X") for toggling whether to output the power supply voltage Vcc from terminal OUT. In particular, in this embodiment, the two transistors are NMOS transistors M1 and M2.

[0033] In NMOS transistor M1, the source electrode S1 is connected to the terminal VCC to which the power supply voltage Vcc is applied. Furthermore, a diode 60 is formed between the source electrode S1 and the drain electrode D1 of NMOS transistor M1 as a body diode.

[0034] In NMOS transistor M2, the source electrode S2 is connected to terminal OUT, and the drain electrode D2 is connected to the drain electrode D1 of NMOS transistor M1. Furthermore, a diode 61 is formed between the source electrode S2 and the drain electrode D2 of NMOS transistor M2 as a body diode.

[0035] Here, the drain electrodes D1 and D2 of NMOS transistors M1 and M2 are connected in series. Therefore, when both NMOS transistors M1 and M2 are turned on, the power supply voltage Vcc of terminal VCC is output from terminal OUT, and coil 12 is driven. On the other hand, when both NMOS transistors M1 and M2 are turned off, the current supplied to coil 12 connected to terminal OUT stops, and thus the driving of coil 12 also stops.

[0036] Furthermore, the anode of diode 60 is connected to terminal VCC, and the cathode of diode 60 is connected to the cathode of diode 61. Moreover, the anode of diode 61 is connected to terminal OUT. Therefore, the cathodes of diodes 60 and 61, located between terminals VCC and OUT, are connected facing each other.

[0037] Therefore, when both NMOS transistors M1 and M2 are turned off, for example, the power supply voltage Vcc applied to terminal VCC is cut off by diode 61. On the other hand, for example, when battery 11 is reverse-connected and the power supply voltage Vcc is applied to terminal OUT, the power supply voltage Vcc at terminal OUT is cut off by diode 60.

[0038] Here, "reverse connection" refers to a state where the positive terminal of battery 11 is connected to the ground side terminal (e.g., terminal GND) and the negative terminal of battery 11 is connected to the power supply side terminal (e.g., terminal VCC). Therefore, when battery 11 is reverse connected, IPS21 can reliably protect coil 12 and ECU13.

[0039] In this embodiment, NMOS transistor M1 is equivalent to a "first MOS transistor", and NMOS transistor M2 is equivalent to a "second MOS transistor". Additionally, terminal VCC is equivalent to a "first terminal", and terminal VCC is equivalent to a "second terminal".

[0040] ===IC51===

[0041] Figure 2 IC 51 is a circuit that turns "switch X" on and off based on the signal Sin, and includes voltage generation circuits 70 and 71, control circuit 72, charge pump circuit 73, resistors 74 and 75, NMOS transistor 76 and discharge circuit 77.

[0042] <<Voltage Generation Circuit 70>>>

[0043] The voltage generation circuit 70 generates a voltage V1 based on the power supply voltage Vcc from the battery 11, which serves as a reference for a specified logic circuit (not shown) within the detection circuit 78, and applies it to the line La. Figure 3 This is a diagram illustrating an example of a voltage generation circuit 70. The voltage generation circuit 70 includes a Zener diode 100, diodes 101 and 102, a resistor 103, and a PMOS transistor 104. The voltage generation circuit 70 is equivalent to a "first voltage generation circuit," and the voltage V1 is equivalent to a "first voltage."

[0044] Zener diode 100, diodes 101 and 102, and resistor 103 are connected in series. Therefore, at the node where diode 102 and resistor 103 are connected, a voltage is generated that is lower than the power supply voltage Vcc by the breakdown voltage Vz of Zener diode 100 and the forward voltage Vf of diodes 101 and 102.

[0045] Here, if the breakdown voltage Vz of Zener diode 100 is set to, for example, 5.6V, and the forward voltage Vf of diodes 101 and 102 is set to 0.7V, then the voltage Vb1 becomes, for example, Vcc-7V (=5.6V+1.4V).

[0046] Furthermore, since the drain electrode of the PMOS transistor 104 is grounded, the PMOS transistor 104 operates as a source follower, outputting a voltage V1 from the source electrode corresponding to the voltage Vb1 applied to the gate electrode. In this embodiment, for example, the threshold voltage of the PMOS transistor 104 is 1.5V, so the voltage V1 is a voltage referenced to the power supply voltage Vcc (Vcc-5.5V).

[0047] in addition, Figure 2The logic circuit (not shown) included in the detection circuit 78 (described later) operates based on the aforementioned voltage V1. Therefore, for example, even when the power supply voltage Vcc supplied to the detection circuit 78 becomes high, the logic circuit can still operate based on voltage V1 and a voltage of 5.5V.

[0048] Furthermore, in this embodiment, the "line" is, for example, a wiring formed on a semiconductor chip by aluminum or copper and electrically connected between two predetermined nodes. Moreover, since the "line" only needs to be electrically connected between the two predetermined nodes, components such as resistors can be placed along the middle of the "line".

[0049] <<Voltage Generation Circuit 71>>

[0050] The voltage generation circuit 71 generates a voltage V2 based on the power supply voltage Vcc and the signal Sb (described later) as a reference for, for example, the charge pump circuit 73 and the discharge circuit 77, and applies it to the line Lb. Specifically, when the charge pump circuit 73 turns on the switch X, the voltage generation circuit 71 lowers the voltage V2, and when the charge pump circuit 73 turns off the switch X, the voltage generation circuit 71 raises the voltage V2. Thus, the charge pump circuit 73 can turn on the switch X in a shorter time, as described later.

[0051] Figure 4 This is a diagram illustrating an example of a voltage generation circuit 71. The voltage generation circuit 71 includes Zener diodes 110, 111, and 115, diodes 112, 116, and 117, a resistor 113, a switch 114, and a PMOS transistor 118. The voltage generation circuit 71 is equivalent to a "second voltage generation circuit," and voltage V2 is equivalent to a "second voltage."

[0052] Zener diodes 100 and 111, diode 112, and resistor 113 are connected in series. Therefore, when switch 114 (described later) is open, a voltage Vb2 is generated at the node connected to diode 112 and resistor 113. This voltage Vb2 is lower than the power supply voltage Vcc by the breakdown voltage Vx of Zener diodes 110 and 111 and the forward voltage Vf of diode 112. Here, if the breakdown voltage Vz of Zener diodes 110 and 111 is set to, for example, 5.6V and the forward voltage Vf of diode 112 is set to 0.7V, the voltage Vb2 becomes approximately Vcc - 12V (≈11.2V + 0.7V).

[0053] Zener diodes 115, 116, and 117 are identical to Zener diodes 100, 101, and 102 in voltage generation circuit 70, and are positioned between switch 114 and resistor 113. Therefore, the voltage generated by Zener diodes 115, 116, and 117 becomes 7V. Thus, when switch 114 is turned on, voltage Vb2 becomes, for example, Vcc - 7V.

[0054] When the input signal Sb is high (hereinafter referred to as "H"), switch 114 is open; when the signal Sb is low (hereinafter referred to as "L"), switch 114 is open. Therefore, when the signal Sb is "H", the voltage V2 from the PMOS transistor 118, which operates as a source follower, becomes Vcc-10.5V, and when the signal Sb is "L", this voltage V2 becomes Vcc-5.5V. Here, the threshold voltage of the PMOS transistor 118 is set to 1.5V.

[0055] <<Control Circuits 72>>

[0056] The control circuit 72 is a logic circuit that generates a signal Sa and a signal Sb that change in the same way as the signal Sin, which indicates that the switch X is on and off. Here, when the switch X is on, the signals Sa and Sb become "H", and when the switch X is off, the signals Sa and Sb become "L".

[0057] <<Charge Pump Circuit 73>>

[0058] The charge pump circuit 73 generates predetermined voltages Vdr1 and Vdr2 to turn on the NMOS transistors M1 and M2 constituting "switch X" based on the signal Sa of "H". Specifically, when the signal Sa is "H", the charge pump circuit 73 applies voltage Vdr1 to line Lc to turn on NMOS transistor M1, and voltage Vdr2 to line Ld to turn on NMOS transistor M2. On the other hand, when the signal Sa changes to "L", the charge pump circuit 73 stops generating voltages Vdr1 and Vdr2.

[0059] Line Lc is a wiring that connects the gate electrode of NMOS transistor M1 and the output of charge pump circuit 73 via resistor 74. Line Ld is a wiring that connects the gate electrode of NMOS transistor M2 and the output of charge pump circuit 73 via resistor 75. Furthermore, resistors 74 and 75 are so-called gate resistors used to prevent NMOS transistors M1 and M2 from abruptly turning on. Details will be described later. In addition to resistor 75, other resistors are also connected to line Ld in this embodiment. Furthermore, for example, only one resistor 74 is provided on line Lc, but multiple resistors may also be provided.

[0060] In addition, with voltage V2 as a reference, the power supply voltage Vcc is supplied to the charge pump circuit 73. Moreover, as described above, when the "switch X" is turned on, the voltage V2 becomes, for example, Vcc - 10.5V, and when the "switch X" is turned off, the voltage V2 becomes, for example, Vcc - 5.5V. That is, when the "switch X" is turned on, the charge pump circuit 73 can generate voltages Vdr1 and Vdr2 based on 10.5V which is greater than 5.5V. Therefore, the charge pump circuit 73 can raise the voltages Vdr1 and Vdr2 in a shorter time, thereby turning on the "switch X".

[0061] <<NMOS transistor 76>>

[0062] The NMOS transistor 76 is a depletion-type transistor, and its drain electrode is connected to the line Le. Here, the line Le is a wiring connected between the "node FD" and the detection circuit 78, and the "node FD" is connected to the drain electrodes of the NMOS transistors M1 and M2. In addition, the gate electrode and the source electrode of the NMOS transistor 76 are connected to the line La. Therefore, the NMOS transistor 76 is always turned on, and a prescribed current (for example, a small current of several μA) flows through it.

[0063] In addition, since the NMOS transistor 76 is always turned on, for example, when the power supply terminal VCC stops supplying current to the node FD, the NMOS transistor 76 acts as an element connecting the line Le and the line La to prevent the line Le from becoming a floating state. Specifically, the NMOS transistor 76 acts as a pull-up element that pulls up the line Le to the line La to which the voltage V1 is applied. In addition, the NMOS transistor 76 corresponds to the "first element (third MOS transistor)", the line Le corresponds to the "first line", and the line La corresponds to the "second line".

[0064] <<Discharge circuit 77>>

[0065] The discharge circuit 77 is a circuit for turning off the NMOS transistors M1 and M2 that constitute the "switch X". Specifically, the discharge circuit 77 discharges the gate capacitance of the NMOS transistor M1 through the lines Lc, Lf, and the terminal OUT to the coil 12. In addition, the discharge circuit 77 discharges the gate capacitance of the NMOS transistor M2 through two paths, namely, the "path A" via the lines Ld, Lb and the "path B" via the lines Ld, Lf. Here, the "path A" is a path in which current flows through the lines Ld, Lb and the voltage generation circuit 71 to the terminal GND, and the "path B" is a path in which current flows through the lines Ld, Lf and the terminal OUT to the grounded coil 12.

[0066] Figure 5This is a diagram illustrating an example of the structure of a discharge circuit 77. The discharge circuit 77 includes an NMOS transistor 130, a first circuit 131, and a second circuit 132.

[0067] ==NMOS Transistor 130==

[0068] NMOS transistor 130 is a depletion-type transistor that discharges the gate capacitance of NMOS transistor M1 on the power supply side to terminal OUT. The drain electrode of NMOS transistor 130 is connected to line Lc from the gate electrode of NMOS transistor M1. Furthermore, the gate and source electrodes of NMOS transistor 130 are connected to line Lf from terminal OUT. Therefore, NMOS transistor 130 is always on, and the gate capacitance of NMOS transistor M1 discharges to line Lf with a very small specified current (e.g., a few μA). Additionally, line Lf corresponds to the "third line," line Lc corresponds to the "sixth line," and NMOS transistor 130 corresponds to the "discharge element (fifth MOS transistor)."

[0069] As described above, the current flowing through NMOS transistor 130 is very small. Therefore, when charge pump circuit 73 applies voltage Vdr1 to line Lc and turns on NMOS transistor M1, the effect of NMOS transistor 130 can be ignored.

[0070] Furthermore, as detailed later, the discharge circuit 77 of this embodiment is designed to reliably turn off the NMOS transistor M2 on the ground side of "switch X". Therefore, when "switch X" is turned off, even assuming that the NMOS transistor M1 on the power supply side is not turned off, the discharge circuit 77 can still turn off switch X.

[0071] ==Circuit 131==

[0072] When "switch X" is open, if signal Sb changes to "L", the first circuit 131 discharges the gate capacitance of the NMOS transistor M2 on the ground side through terminal OUT. Furthermore, as detailed later, the first circuit 131 connects lines Lf and Ld, so that, for example, when coil 12 connected to terminal OUT is disconnected, line Lf will not be in a floating state. However, since a floating state of terminal OUT and line Lf is an abnormal situation, the normal state of coil 12 connected to terminal OUT will be explained first here.

[0073] In addition, Figure 2In this diagram, components other than resistor 75 on line Ld are omitted, but resistors 80 to 82 and diode 83 are also provided on line Ld. Resistors 80 to 82 are the same gate resistors as resistor 75, and diode 83 is used to discharge the gate capacitance of NMOS transistor M2. Additionally, for convenience, lines such as Le are omitted here.

[0074] The first circuit 131 includes NMOS transistors 200 to 202, M10, PMOS transistor 203, and resistor 204.

[0075] NMOS transistor 200 is a depletion-type transistor used to discharge the gate capacitance of NMOS transistor M2. NMOS transistor 200 is identical to NMOS transistor 130, therefore detailed description is omitted here. Furthermore, NMOS transistor 200 is equivalent to a "fourth MOS transistor".

[0076] NMOS transistors 201 and 202 are both depletion-type transistors with their gate electrodes connected to their source electrodes, so they are always on. NMOS transistors 201 and 202 are connected in series with PMOS transistor 203.

[0077] Therefore, when "switch X" is turned off, if signal Sb changes to "L", a voltage corresponding to the size ratio of NMOS transistors 201 and 202 is generated at node X1, which is connected to NMOS transistors 201 and 202. In this embodiment, the size ratio of NMOS transistors 201 and 202 is determined such that the voltage at node X1 is greater than the threshold voltage of NMOS transistor M10 when PMOS transistor 203 is turned on.

[0078] On the other hand, if signal Sb changes to "H" when "switch X" is turned on, then PMOS transistor 203 is turned off. As a result, node X1 is pulled down to terminal OUT via NMOS transistor 201, so NMOS transistor M10 is turned off.

[0079] Therefore, since NMOS transistors 201 and 202 are the elements that generate the voltage for turning on NMOS transistor M10, resistors can be used to replace each of NMOS transistors 201 and 202.

[0080] NMOS transistor M10 is off when "switch X" is turned on and on when "switch X" is turned off. Furthermore, when NMOS transistor M10 is on, the gate capacitance of NMOS transistor M2 discharges to coil 12 via line Ld, resistor 204, NMOS transistor M10, line Lf, and terminal OUT. Additionally, NMOS transistor M10 acts as the "first switch".

[0081] ==Second Circuit 132==

[0082] When "switch X" is open, if signal S2 changes to "L", the second circuit 132 discharges the gate capacitance of NMOS transistor M2 through line Lb. Furthermore, as detailed later, the second circuit 132 connects line Ld and line Lb, to which voltage V2 is applied, such that, for example, when coil 12 connected to terminal OUT is disconnected, line Lf connected to terminal OUT will not be in a floating state.

[0083] The second circuit 132 includes NMOS transistors 210, 211, M11, PMOS transistor 212, and resistor 213. Here, the NMOS transistors 210, 211, and PMOS transistor 212 of the second circuit 132 correspond to the NMOS transistors 201, 202, and PMOS transistor 203 of the first circuit 131, respectively. Furthermore, the NMOS transistor M11 and resistor 213 of the second circuit 132 correspond to the NMOS transistor M10 and resistor 204 of the first circuit 131, respectively.

[0084] Therefore, except for the NMOS transistor 200, the second circuit 132 operates in the same way as the first circuit 131. Furthermore, line Ld corresponds to the "fourth line," and line Lb corresponds to the "fifth line." Additionally, the NMOS transistor M11 corresponds to the "second switch."

[0085] <<Detection Circuit 78>>

[0086] Figure 2 The detection circuit 78 in the middle is based on the voltage of signal Sb, line Le and line Lf to detect whether there is an abnormality in switch X and other circuits. Figure 6 This is a diagram showing the relationship between the various states of IPS21 and the signal So output from the detection circuit 78. Here, "State 1 (normal)" indicates that IPS21 is in a normal state, and states 2 to 7 indicate that the circuits contained in IPS21 are in an abnormal state.

[0087] Specifically, "State 2 (M1 not turned on)" indicates that the NMOS transistor M1 on the power supply side of "Switch X" is not turned on, while "State 3 (Power supply open)" indicates, for example, from Figure 2 The wiring from terminal VCC to the source electrode of NMOS transistor M1 is broken. "State 4 (M1 short circuit)" indicates that NMOS transistor M1 is short-circuited, that is, a short-circuit fault has occurred.

[0088] In addition, "State 5 (M2 not conducting)" indicates that the NMOS transistor M2 on the ground side of "Switch X" is not conducting, "State 6 (output open circuit)" indicates, for example, that the wiring connecting terminal OUT and coil 12 is broken or disconnected. "State 7 (M2 short circuit)" indicates that the NMOS transistor M2 has a short circuit fault.

[0089] Details are described later. In this embodiment, the voltage levels of lines Le and Lf of IC 51 change according to the logic level of signal Sb and states 1 to 7. Therefore, the state of IPS21 can be determined by referring to the voltage levels of lines Le and Lf and the logic level of signal Sb. States 1 to 7 will be explained under various conditions where "switch X" is open or closed.

[0090] <<<"Switch X" is off>>>

[0091] First, the voltages of lines Le and Lf in states 1 to 7 when “switch X” is open will be explained.

[0092] ==State 1 (Normal)==

[0093] When IPS21 is in its normal state (state 1), when "switch X" is open... Figure 2 When NMOS transistors M1 and M2 are turned off, the power supply voltage Vcc from terminal VCC is applied to node FD through diode 60. Therefore, when the power supply voltage Vcc is set to "H" and the forward voltage Vf of diode 60 is set to "0.7V", the voltage of line Le becomes "H-0.7V".

[0094] On the other hand, since NMOS transistor M2 is turned off and diode 61 is also off, the power supply voltage Vcc is not transmitted to terminal OUT. Furthermore, as... Figure 1 As shown, since the other end of coil 12, which is grounded at one end, is connected to terminal OUT, terminal OUT is also grounded. Therefore, the voltage of line Lf connected to terminal OUT becomes 0V (ground voltage), i.e., it becomes "L".

[0095] ==State 2 (M1 not conducting)==

[0096] In state 2, although the charge pump circuit 73 operates and drives the NMOS transistor M1, the NMOS transistor M1 is in a non-conducting state. State 2 is an anomaly that occurs when "switch X" is turned on, and will therefore be described in detail later. Furthermore, when "switch X" is turned off, state 2 is essentially the same as state 1. Therefore, line Le becomes "H-0.7V" and line Lf becomes "L".

[0097] ==State 3 (Power Open Circuit)==

[0098] Figure 7 This diagram illustrates a state where the wiring from terminal VCC to the source electrode of NMOS transistor M1 is broken. In this state, the supply voltage Vcc is not applied to node FD. Therefore, it is assumed that node FD becomes floating in the absence of NMOS transistor 76.

[0099] However, a always-on NMOS transistor 76 is connected in line Le, which is connected to node FD. Therefore, line Le is connected to line La, where a voltage V1 is applied, via NMOS transistor 76. Thus, as... Figure 6 As shown, the voltage level of line Le becomes "H-5.5V". On the other hand, line Lf, which is connected to terminal OUT, is grounded via coil 12. Therefore, the voltage level of line Lf becomes "L".

[0100] ==State 4 (M1 short circuit)==

[0101] exist Figure 2 For example, when NMOS transistor M1 is in a short-circuit state, the voltage at node FD is the supply voltage Vcc. As a result, the voltage on line Le becomes "H". On the other hand, line Lf, which is connected to terminal OUT, is grounded via coil 12. Therefore, the voltage level on line Lf becomes "L".

[0102] ==State 5 (M2 not conducting)==

[0103] State 5 is a state in which the NMOS transistor M2 is not turned on despite the charge pump circuit 73 operating and driving it. State 5 is an anomaly that occurs when "switch X" is on, and will therefore be described in detail later. Furthermore, when "switch X" is off, state 5 is essentially the same as state 1. Therefore, line Le becomes "H-0.7V" and line Lf becomes "L".

[0104] ==State 6 (Output Open Circuit)==

[0105] When "switch X" is open, even if the wiring between terminal OUT and coil 12 is disconnected or detached, for example, the power supply voltage Vcc will be applied to the source electrode of NMOS transistor M1. Therefore, the voltage at node FD, i.e. the voltage at line Le, becomes "Vcc-0.7V".

[0106] Figure 8This diagram illustrates the state where the wiring between terminal OUT and coil 12 is broken or disconnected. Here, since "switch X" is off, the power supply voltage Vcc is not applied to terminal OUT, so line Lf becomes floating when the first circuit 131 is not present. However, since the power supply voltage Vcc is supplied to the discharge circuit 77, current flows from the power supply voltage Vcc to line Lf, as shown by the dotted line.

[0107] First, when current flows through PMOS transistor 203 and NMOS transistors 201 and 202, the voltage at node X1 rises, and NMOS transistor M10 turns on. As a result, lines Lf and Ld are connected via NMOS transistor M10 and resistor 204. At this time, current from the power supply voltage Vcc flows from line Lf through NMOS transistor M10 and resistor 204 to line Ld.

[0108] Furthermore, similarly to NMOS transistor M10, NMOS transistor M11 in the second circuit 132 is also turned on. Therefore, lines Ld and Lb are electrically connected, and current flows from line Ld through resistor 213 and NMOS transistor M11 to line Lb. The current flowing into line Lb is via... Figure 4 The PMOS transistor 118 shown acts as a source follower and its output is grounded.

[0109] Therefore, in this embodiment, when the terminal OUT is in an open-circuit state with ground, the line Lf of the terminal OUT is connected to the line Ld via the NMOS transistor M10 and the resistor 204. Furthermore, the line Ld is connected to the line Lb via the NMOS transistor M11 and the resistor 213. As a result, the line Lf is pulled up to the line Lb to which a voltage V2 (“H-5.5V”) is applied.

[0110] ==State 7 (M2 short circuit)==

[0111] exist Figure 2 For example, when NMOS transistor M2 is short-circuited, the voltage at terminal OUT becomes the voltage at node FD. When switch X is open, the voltage at node FD becomes "Vcc-0.7V". As a result, the voltage on line Le connected to node FD and the voltage on line Lf connected to terminal OUT both become "Vcc-0.7V".

[0112] <<<“Switch X” is on>>>

[0113] Next, the voltages of lines Le and Lf in states 1 to 7 when "switch X" is turned on will be explained.

[0114] ==State 1 (Normal)==

[0115] In the normal state of IPS21, i.e., "State 1", when "Switch X" is turned on... Figure 2 When NMOS transistors M1 and M2 are turned on, the power supply voltage Vcc from terminal VCC is applied to node FD and terminal OUT. Therefore, the voltages of lines Le and Lf both become "H".

[0116] ==State 2 (M1 not conducting)==

[0117] State 2 is a state in which the charge pump circuit 73 operates and drives the NMOS transistor M1, but the NMOS transistor M1 is not turned on. Even in this case, because the NMOS transistor M2 is turned on, the power supply voltage Vcc from terminal VCC is applied to node FD and terminal OUT via diode 60. Therefore, the voltages of lines Le and Lf both become "H-0.7V".

[0118] ==State 3 (Power Open Circuit)==

[0119] Figure 7 This diagram illustrates a state where the wiring from terminal VCC to the source electrode of NMOS transistor M1 is disconnected. In this state, when "switch X" is turned on, nodes FD and terminal OUT are pulled down to ground through coil 12. Therefore, the voltages on lines Le and Lf both become "L".

[0120] ==State 4 (M1 short circuit)==

[0121] State 4 is the state where the NMOS transistor M1 in "Switch X" is short-circuited. Since this state is essentially the same as "State 1", the voltages of lines Le and Lf both become "H".

[0122] ==State 5 (M2 not conducting)==

[0123] State 5 is a state where, although the charge pump circuit 73 operates and drives the NMOS transistor M2, the NMOS transistor M2 is not turned on. Even in this case, because the NMOS transistor M1 is turned on, the power supply voltage Vcc from terminal VCC is applied to node FD. Therefore, the voltage on line Le becomes "H" and the voltage on line Lf becomes "L".

[0124] ==State 6 (Output Open Circuit)==

[0125] Even if the wiring between terminal OUT and coil 12 is broken or disconnected, when "switch X" is turned on, the power supply voltage Vcc is applied to node FD and terminal OUT. Therefore, the voltages of lines Le and Lf both become "H".

[0126] ==State 7 (M2 short circuit)==

[0127] State 7 is the state where the NMOS transistor M2 in "Switch X" is short-circuited. Since this state is essentially the same as "State 1", the voltages of lines Le and Lf both become "H".

[0128] <<<Output of detection circuit 78>>>

[0129] The detection circuit 78 outputs based on the logic level of signal Sb, the voltage level of line Le, and the voltage level of line Lf. Figure 6 The signal So represents the logic level shown. Here, for example, when "switch X" is open (when signal Sb is "L"), three levels, "H-0.7V", "H-5.5V" and "H", can be obtained as the voltage levels of line Le. Furthermore, in this embodiment, line Lf when signal Sb is "L", line Le when signal Sb is "H", and line Lf when signal Sb is "H" can also obtain three levels respectively.

[0130] Therefore, firstly, for each of the two logic levels of signal Sb, detection circuit 78 converts the three voltage levels input from lines Le and Lf into, for example, 2 bits of data. Then, detection circuit 78 performs logical synthesis on the converted data to output... Figure 6 The signal So represents the logic level shown. Additionally, for example, the detection circuit 78 includes a conversion circuit (not shown) for converting the three input voltage levels into 2-bit data, and a logic circuit (not shown) for logically synthesizing the output of the conversion circuit.

[0131] When the signal So is "L", the detection circuit 78 outputs a signal So of "H" if it is in any of states 1, 2, or 5, and outputs a signal So of "L" if it is in any of states 3, 4, 6, or 7. Similarly, when the signal So is "H", the detection circuit 78 outputs a signal So of "L" if it is in any of states 1, 4, 6, or 7, and outputs a signal So of "H" if it is in any of states 2, 3, or 5. Furthermore, in this embodiment, when the signal Sb is "L", the signal So of "L" indicates an abnormality in "switch X", etc., and when the signal Sb is "H", the signal So of "H" indicates an abnormality in "switch X", etc.

[0132] In addition, such as Figure 1If the microcomputer 20 detects an abnormality in "switch X" or the like based on the logic level of the signal output from IPS 21, it outputs, for example, a signal Sin to disconnect "switch X" and disconnects switch 22. As a result, the motor control device 10 can safely drive the motor coil 12, for example. "Abnormalities in "switch X" or the like" include, for example, abnormalities in the path from the power supply terminal VCC to "switch X", abnormalities in "switch X", and abnormalities in terminal OUT.

[0133] ===Summary===

[0134] The above describes the motor control device 10 of this embodiment. For example, when coil 12 is connected to terminal OUT and "switch X" is turned off, if the voltage of line Le becomes "H", the detection circuit 78 can detect at least a short circuit in NMOS transistor M1. Figure 6 The "disconnected" state 4). Therefore, in this embodiment, since the fault of NMOS transistor M1 can be detected based on the voltage level of line Le, there is no need for complex structures such as changing the voltage applied to node FD.

[0135] For example, when coil 12 is connected to terminal OUT and switch X is turned on, if the voltage of line Le becomes "H-0.7V", then detection circuit 78 can detect that NMOS transistor M1 is not turned on. Figure 6 The "conduction" state in the middle (2).

[0136] Furthermore, for example, when coil 12 is connected to terminal OUT, detection circuit 78 can detect whether power supply voltage Vcc is being supplied to NMOS transistor M1 based on the voltage of line Le. Figure 6 The states 3 are "disconnected" and "connected" (in the context of the three states).

[0137] Furthermore, a resistor can be connected, for example, between lines Le and La, so that line Le does not float. However, in this case, as long as the resistance value does not increase, the current flowing from line Le to line La will increase, and power consumption will increase. In this embodiment, by using an NMOS transistor 76, the area can be reduced and power consumption can be suppressed.

[0138] For example, when the NMOS transistor M2 in "switch X" is short-circuited, "switch X" is open; however, the voltage level of line Lf becomes "H-0.7V". In this case, the detection circuit 78 can detect a fault in the NMOS transistor M2 based on the voltage level of line Lf. Figure 6 The "disconnected" state in 7).

[0139] Furthermore, although "switch X" is on, the level of line Lf changes to "L" when, for example, NMOS transistor M2 is not on. Therefore, detection circuit 78 can detect that NMOS transistor M2 has malfunctioned. Figure 6 The "conduction" state in 5).

[0140] Furthermore, for example, when coil 12 is disconnected from terminal OUT, line Lf connected to terminal OUT is connected to line Lb, to which voltage V2 is applied, via first circuit 131 and second circuit 132. As a result, since voltage V2 is applied to line Lf, detection circuit 78 can detect that coil 12 is not connected to terminal OUT based on the voltage level of line Lf. Figure 6 The "disconnected" state in 6).

[0141] Furthermore, for example, a resistor could be used instead of the NMOS transistor M10 and resistor 204 in the first circuit 131 to prevent line Lf from being in a floating state. However, in this case, when the NMOS transistor M2 is turned on, the resistance value needs to be increased to prevent a large current from flowing through the resistor to the terminal OUT. In this embodiment, since the NMOS transistor M10, which is switched on and off in a complementary manner to the "switch X", is used, the resistance value of the current-limiting resistor 204 can be reduced, for example.

[0142] Furthermore, an NMOS transistor 200 is provided in the first circuit 131, which discharges the gate capacitance of the NMOS transistor M2 through the line Ld. Therefore, the first circuit 131 can turn off the NMOS transistor M2 in a shorter time.

[0143] Furthermore, for example, a resistor could be used instead of the NMOS transistor M11 and resistor 213 in the second circuit 132 to prevent line Ld from being in a floating state. However, in this case, when the NMOS transistor M2 is turned on, the resistance value needs to be increased to prevent a large current from flowing through the resistor to line Lb. In this embodiment, since the NMOS transistor M11, which is switched on and off in a complementary manner to "switch X", is used, the resistance value of the current-limiting resistor 213 can be reduced, for example.

[0144] Furthermore, in this embodiment, since an NMOS transistor 130 is provided to discharge the gate capacitance of the NMOS transistor M1, it is possible to prevent the NMOS transistor M1 from being erroneously turned on when the charge pump circuit 73 stops operating.

[0145] Furthermore, by using an NMOS transistor 130 instead of a resistor as the element for discharging the gate capacitance of the NMOS transistor M1, the discharge current can be reduced with a very small area.

[0146] Furthermore, when the charge pump circuit 73 turns on "switch X", the voltage generation circuit 71 changes the level of the reference voltage V2 of the charge pump circuit 73 from "Vcc-5.5V" to a lower "Vcc-10.5V". Therefore, the charge pump circuit 73 can generate the voltage needed to turn on NMOS transistors M1 and M2 in a short time. Furthermore, "Vcc-5.5V" corresponds to the "first level", and "Vcc-10.5V" corresponds to the "second level".

[0147] The above embodiments are provided to facilitate understanding of the present invention, and are not intended to limit or restrict its interpretation. Furthermore, the present invention can be modified or improved without departing from its spirit, and the present invention naturally includes its equivalents.

[0148] For example, in this embodiment, the output voltage of IPS 21 is applied to the coil 12, which serves as a load, via switch 22 of ECU 13, but is not limited thereto. For example, the output voltage of IPS 21 can be applied directly to the coil 12.

[0149] Label Explanation

[0150] 10. Motor control device

[0151] 11 batteries

[0152] 12 coils

[0153] 13 ECU

[0154] 20 microcomputers

[0155] 21 IPS

[0156] 50, 51 IC

[0157] Diodes 60, 61, 83, 101, 102, 112, 116, and 117

[0158] 70, 71 Voltage generation circuit

[0159] 72 Control Circuit

[0160] 73 Charge Pump Circuit

[0161] Resistors 74, 75, 80–82, 103, 113, 204, 213

[0162] 76, 130, 201, 202, 210, 211, M1, M2, M10, M11 NMOS transistors

[0163] 77 Discharge Circuit

[0164] Zener diodes 100, 110, 111, and 115

[0165] 104, 118, 203, 212 PMOS transistors

[0166] 114 Switch

[0167] 131 First Circuit

[0168] 132 Second Circuit

[0169] La~Lf lines

[0170] IN, ST, VCC, OUT, GND terminals.

Claims

1. An integrated circuit, characterized in that, include: A first line is connected to the drain electrode of a first MOS transistor and the drain electrode of a second MOS transistor. The source electrode of the first MOS transistor is connected to a first terminal to which a power supply voltage is applied, and the source electrode of the second MOS transistor is connected to a second terminal to which a load is connected. A second line, wherein a first voltage lower than the power supply voltage is applied; A third line is connected to the second terminal; A fourth line is connected to the gate electrode of the second MOS transistor; The fifth line is subjected to a second voltage lower than the power supply voltage; A first circuit connects the third line and the fourth line, ensuring that the third line is not in a floating state. A second circuit connects the fourth line and the fifth line, ensuring that the fourth line is not in a floating state. A first element connects the first line and the second line, so that the first line is not in a floating state; as well as The detection circuit, when the first MOS transistor and the second MOS transistor are turned off, detects at least whether the first MOS transistor is abnormal based on the voltage level of the first line, and detects at least whether the second MOS transistor is abnormal based on the voltage level of the third line.

2. The integrated circuit as described in claim 1, characterized in that, When the first MOS transistor and the second MOS transistor are turned on, the detection circuit detects at least whether the first MOS transistor is abnormal based on the voltage level of the first line.

3. The integrated circuit as described in claim 1 or 2, characterized in that, The detection circuit detects whether the power supply voltage is being supplied to the first MOS transistor.

4. The integrated circuit as described in claim 1 or 2, characterized in that, The first element is a depletion-type third MOS transistor that connects the gate electrode and the source electrode.

5. The integrated circuit as described in claim 1, characterized in that, When the first MOS transistor and the second MOS transistor are turned on, the detection circuit detects at least whether the second MOS transistor is abnormal based on the voltage level of the third line.

6. The integrated circuit as claimed in claim 1, characterized in that, The detection circuit detects whether the load is connected to the third line via the second terminal.

7. The integrated circuit as claimed in claim 1, characterized in that, The first circuit includes a first switch that is complementary to the first MOS transistor and the second MOS transistor in being turned on and off.

8. The integrated circuit as described in claim 7, characterized in that, The first circuit also includes a depletion-type fourth MOS transistor that connects the gate electrode and the source electrode.

9. The integrated circuit as described in claim 7 or 8, characterized in that, The second circuit includes a second switch that is complementary to the first MOS transistor and the second MOS transistor in being turned on and off.

10. The integrated circuit as claimed in claim 1, characterized in that, include: A sixth line is connected to the gate electrode of the first MOS transistor; as well as A discharge element that connects the sixth line and the third line.

11. The integrated circuit as claimed in claim 10, characterized in that, The discharge element is a depletion-type fifth MOS transistor that connects the gate electrode and the source electrode.

12. The integrated circuit as claimed in claim 1, characterized in that, include: A charge pump circuit, which is supplied with the power supply voltage and turns on the first MOS transistor and the second MOS transistor with reference to the second voltage; A first voltage generation circuit applies the first voltage to the second line; as well as A second voltage generation circuit applies a first-level second voltage to the fifth line when the charge pump circuit turns off the first MOS transistor and the second MOS transistor, and applies a second-level second voltage to the fifth line when the charge pump circuit turns on the first MOS transistor and the second MOS transistor, wherein the second level is lower than the first level.

13. A semiconductor device, characterized in that, include: The first MOS transistor and the second MOS transistor have their drain electrodes connected between a first terminal to which a power supply voltage is applied and a second terminal to which a load is connected. A first line, which is connected to the drain electrodes of the other two; A second line, wherein a first voltage lower than the power supply voltage is applied; A third line is connected to the second terminal; A fourth line is connected to the gate electrode of the second MOS transistor; The fifth line is subjected to a second voltage lower than the power supply voltage; A first circuit connects the third line and the fourth line, ensuring that the third line is not in a floating state. A second circuit connects the fourth line and the fifth line, ensuring that the fourth line is not in a floating state. A first element connects the first line and the second line, so that the first line is not in a floating state; as well as The detection circuit, when the first MOS transistor and the second MOS transistor are turned off, detects at least whether the first MOS transistor is abnormal based on the voltage level of the first line, and detects at least whether the second MOS transistor is abnormal based on the voltage level of the third line.

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