Based on indicating to avoid defective memory cells

Abstract

This application relates to indicating avoidance of defective memory cells. A non-volatile memory component can store information about one or more memory cells of a volatile memory component that a host device of the volatile memory component is to avoid accessing. The one or more memory cells may, for example, be defective. The device can transmit a request for an indication of the one or more memory cells of the volatile memory component that the host device is to avoid accessing to the non-volatile memory component, and the non-volatile memory can transmit this indication to the host device. The host device can refrain from writing to or reading from the one or more memory cells of the volatile memory component.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 019,843, filed September 14, 2020, entitled “Indication-Based Avoidance of Defective Memory Cells,” which has been assigned to its assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to avoiding defective memory cells based on instructions. Background Technology

[0004] The following text generally refers to one or more systems for memory, and more specifically, to avoiding defective memory cells based on instructions.

[0005] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access stored information, components can read or sense at least one stored state in the memory device. To access information, components can write to or program the states in the memory device.

[0006] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, and others. Memory cells can be volatile or non-volatile. Non-volatile memory (e.g., FeRAM) can retain its stored logical state for a long time, even without external power. Volatile memory devices (e.g., DRAM) lose their stored state when disconnected from external power. Summary of the Invention

[0007] In some instances, a host device can: transmit a request for an indication of one or more addresses of a volatile memory component coupled to the host device from the host device to a non-volatile memory component, the host device avoiding access to the one or more addresses; receive, at the host device, the indication of the one or more addresses of the volatile memory component that the host device avoids accessing from the non-volatile memory component; perform data communication with the volatile memory component via the host device; and, during the data communication with the volatile memory component, prevent writing to or reading from the one or more addresses of the volatile memory component via the host device and at least in part based on the indication received from the non-volatile memory component.

[0008] In some instances, a host device may: receive from a host device a request indicating one or more addresses of a volatile memory component, the host device avoiding access to the one or more addresses; retrieve, at least in part, information from a non-volatile memory component indicating the one or more addresses of the volatile memory component that the host device will avoid accessing, based on the request; and transmit the indication of the one or more addresses of the volatile memory component that the host device will avoid accessing to the host device.

[0009] In some instances, an apparatus may include a volatile memory component and a non-volatile memory component, the non-volatile memory component being configured to: store information indicating one or more defective memory cells within the volatile memory component; receive a request for an indication of the one or more defective memory cells within the volatile memory component; and, in response to the request, output the indication of the one or more defective memory cells within the volatile memory component. Attached Figure Description

[0010] Figure 1 This document describes instances of systems that support instructions to avoid defective memory cells, based on the examples disclosed herein.

[0011] Figure 2 This document describes instances of address indication schemes that support the avoidance of defective memory cells based on the examples disclosed herein.

[0012] Figure 3 This document describes instances of device communication configurations based on instructions to avoid defective memory cells, as disclosed in the examples herein.

[0013] Figure 4 This document describes instances of device communication configurations based on instructions to avoid defective memory cells, as disclosed in the examples herein.

[0014] Figure 5 A block diagram illustrating a host device that supports instruction-based avoidance of defective memory cells, based on examples disclosed herein.

[0015] Figure 6 A block diagram illustrating a memory device that supports instruction-based avoidance of defective memory cells, based on examples disclosed herein.

[0016] Figure 7 and 8 The flowchart illustrates one or more methods for avoiding defective memory cells based on instructions, according to the examples disclosed herein. Detailed Implementation

[0017] A system (e.g., a host device coupled to a memory device or a set of memory devices) may include volatile memory (e.g., dynamic random access memory (DRAM)), which may contain volatile memory cells. In some cases, the host device may want to avoid accessing one or more of the volatile memory cells within the system. For example, a number of volatile memory cells may be defective (e.g., due to manufacturing defects). A memory cell may be considered defective if it is trapped in one state or another, is prone to being read back incorrectly, or is otherwise determined to have failed reliability testing (e.g., post-manufacturing).

[0018] In some cases, to prevent defective memory cells from affecting the performance of the memory device (and therefore the wider system), the memory device may include redundant (e.g., spare) cells configured to replace the defective cells in an unknown or host-detectable manner. For example, when the host device transmits a command to access the defective memory cell (e.g., read from or write to the defective memory cell), the memory device can access the replacement memory cell without warning the host device of the replacement. However, the number of defective cells that can be replaced by redundant cells may be limited. For example, both the redundant cells and associated circuitry (e.g., fuses or antifuses used to activate and configure the use of the redundant cells) occupy space within the memory device. Therefore, the number of redundant cells is limited to avoid excessively increasing the size of the memory device or system, whether at the factory, during system assembly, or during system operation, which limits the extent to which defective memory cells can be repaired through replacement schemes.

[0019] However, as described herein, the host device may receive information from one or more memory devices within the system regarding memory cells (e.g., defective memory cells) that the host device will avoid accessing (e.g., reading data from or writing data to). For example, one or more non-volatile memory devices within the system may store information regarding defective or otherwise avoidable memory cells (e.g., volatile memory cells or other non-volatile memory cells or both). The host device may receive an indication from one or more non-volatile memory devices of memory cells that the host device will avoid accessing, and the host device may therefore avoid accessing the indicated memory cells. Thus, for example, instead of replacing defective memory cells with a finite number of replacement memory cells, the host device may avoid accessing any number of the indicated memory cells. In some cases, for example, the host device may receive (e.g., from a non-volatile memory device) an indication of one or more memory cells (e.g., within a volatile memory device) that the host device will avoid after system startup or restart. When the memory cell to be avoided is a volatile memory cell, the information indicating the memory cell to be avoided (such as the associated address) will be stored in non-volatile memory. This information can be programmed and preserved in the absence of system power, such as before the volatile memory and the associated non-volatile memory are shipped to the customer as part of the same device, die, package or module.

[0020] The teachings in this document are applicable to systems that incorporate various memory types and architectures. As an example, if a system includes a dual in-line memory module (DIMM) comprising volatile memory (e.g., DRAM), the system can store information about defective or otherwise avoidable volatile memory cells in the DIMM's serial presence detection (SPD) memory, where the SPD memory can be non-volatile (e.g., it can be an SPD electrically erasable programmable read-only memory (EEPROM)). As another example, both volatile and non-volatile memory can be contained within a single package, for example, where the volatile memory is contained on one or more chips (e.g., dies) and the non-volatile memory (e.g., NAND flash memory) is contained on one or more other chips (e.g., dies), where information about defective or otherwise avoidable cells in the volatile memory is stored in the non-volatile memory. This architecture can be referred to as a multi-chip package (MCP) architecture. As another example, the system may include both volatile and non-volatile memory on a single chip (e.g., a bare die), which may be called a single-chip package (SCP) architecture, and the system may store information about defective or otherwise avoidable cells in the non-volatile memory on the same chip.

[0021] First, refer to Figure 1The features of this disclosure are described within the context of the example system described. (Refer to...) Figures 2 to 4 The features of this disclosure are further described within the context of the instance address indication scheme and instance architecture described herein. These and other features of this disclosure are illustrated in conjunction with the references to... Figures 5 to 8 The example device diagrams and flowcharts describing the avoidance of defective memory cells are further illustrated and described with reference to the example device diagrams and flowcharts. Although the various examples are described herein in the context of a host device that avoids access to defective memory cells, it should be understood that the teachings herein can be extended to avoid access to one or more memory cells for any reason.

[0022] Figure 1 The description supports an example of a system 100 based on instructions to avoid defective memory cells, according to the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0023] System 100 may include portions of electronic devices, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or the like. Memory device 110 may be a component of the system operable to store data from one or more other components of system 100.

[0024] At least a portion of system 100 may be an instance of host device 105. Host device 105 may be an instance of a processor or other circuitry within a device that uses memory to perform processes, for example, within a computing device, mobile computing device, wireless device, graphics processing device, graphics processing unit (GPU), computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, Internet-connected device, vehicle controller, system-on-a-chip (SoC), or some other fixed or portable electronic device, etc.

[0025] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulating signals, different pin configurations for transmitting signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0026] Memory device 110 is operable to store data of components of host device 105. In some instances, memory device 110 may be used as a slave device of host device 105 (e.g., responding to and executing commands provided by host device 105, for example, via external memory controller 120). Such commands may include one or more of the following: write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0027] Host device 105 may include one or more of the following components: external memory controller 120, processor 125, basic input / output system (BIOS) component 130, boot loader 140, operating system 145, or other components (such as one or more peripheral components or one or more input / output controllers). The components of host device 105 may be coupled to each other using bus 135.

[0028] Processor 125 is operable to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, etc. In some instances, external memory controller 120 may be implemented by or be part of processor 125.

[0029] External memory controller 120 is operable to transfer one or more of the following between a component of system 100 or host device 105 (e.g., processor 125) and memory device 110: information, data, or commands. External memory controller 120 may translate or interpret communications exchanged between components of host device 105 and memory device 110. In some instances, external memory controller 120, or other components of system 100 or host device 105, or the functions described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or combinations thereof, implemented by processor 125, or other components of system 100 or host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120, or the functions described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0030] BIOS component 130 may be a software or firmware component that initializes and runs various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory. In some cases, the code contained in BIOS component 130 may be executed by processor 125.

[0031] In some instances, after host device 105 is booted, host device 105 may operate system 100 according to operating system 145. The operating system may be a software component containing code configured to be executed by processor 125 to operate and manage the various hardware and software components of system 100. Operating system 145 may contain a set of instructions executable by processor 125 and stored in non-volatile memory (e.g., hard disk or NAND memory) within system 100, which may be contained in or separate from memory device 110.

[0032] The boot loader 140 may be a software or firmware component that can be executed (e.g., by processor 125) to initialize the operating system 145 or other software components (e.g., after executing code contained in BIOS component 130). For example, when executed, the boot loader 140 may write some or all of the operating system 145 to volatile memory within the memory device 110 (e.g., after reading operating system 145 code from non-volatile memory). Although in Figure 1Examples are described separately, but in some cases, the boot loader 140 may be included in or combined with the BIOS component 130.

[0033] Memory device 110 may include a memory controller 155 supporting a desired or specified capacity for data storage and one or more memory dies 160 (e.g., memory chips). Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more memory banks, one or more dies, one or more segments), wherein each memory cell is operable to store at least one data bit.

[0034] Device memory controller 155 may include circuitry, logic, or components operable to control the operation of memory device 110. Device memory controller 155 may include hardware, firmware, or instructions enabling memory device 110 to perform various operations, and is operable to receive, transmit, or execute commands, data, or control information associated with components of memory device 110. Device memory controller 155 is operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, device memory controller 155 may control the operation of memory device 110 as described herein in conjunction with local memory controller 165 of memory die 160.

[0035] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data in host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105.

[0036] A local memory controller 165 (e.g., local to memory die 160) may include circuitry, logic, or components operable to control the operation of memory die 160. In some instances, the local memory controller 165 is operable to communicate with a device memory controller 155 (e.g., to receive or transmit data or commands, or both). Memory device 110 may not include a device memory controller 155, and either the local memory controller 165 or the external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 is operable to communicate with the device memory controller 155, with another local memory controller 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers operable to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0037] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 are operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path may be an example of a conductive path operable to carry a signal. For example, channel 115 may include a first terminal comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins are operable to serve as part of a channel.

[0038] Channel 115 (and associated signal paths and terminals) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, signaling may be communicated via channel 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0039] When system 100 starts, bootloader 140 may include routines for initializing one or more memory controllers (e.g., external memory controller 120) coupled to processor 125. For example, initializing external memory controller 120 may include querying memory device 110 to retrieve timing parameters or topology parameters (e.g., rank count) of memory device 110. For example, memory device 110 may include volatile memory (e.g., DRAM) and also include non-volatile memory (e.g., NAND or EEPROM), and the non-volatile memory may be queried to obtain information about the volatile memory.

[0040] After the external memory controller 120 is initialized, the logical address space (which may also be referred to as the virtual or system address space) addressable by the host device 105 can be used to execute addressing commands to the memory device 110, which translates logical addresses into corresponding physical address spaces associated with a set of memory cells (e.g., volatile memory cells) at the memory device 110. For example, after the external memory controller 120 is initialized, the processor 125 or the external memory controller 120 can read or otherwise obtain executable instructions associated with other programs (e.g., application programs) from non-volatile memory (which may be contained in or separate from the memory device 110, depending on the implementation) and can write such executable instructions to the memory device 110. The processor 125 or the external memory controller 120 can then read and execute instructions (based on commands addressing to the associated logical address space) from the memory device 110 and can also write to and read from the memory device 110 (based on commands addressing to the associated logical address space).

[0041] In some cases, if information written to memory device 110 (e.g., executable instructions or data) is not accurately read back from memory device 110, system 100 or associated components or programs (e.g., applications) may suffer from error conditions or even crash. For example, such errors may occur if information is written to one or more defective memory cells within memory device 110. Therefore, as described herein, if host device 105 identifies memory cells (e.g., defective memory cells) within memory device 110 that host device 105 will avoid accessing (e.g., avoiding writing to or reading from them) and host device 105 avoids accessing such memory cells, the likelihood of such errors can be reduced and the reliability of system 100 can be improved, along with other benefits that will be apparent to those skilled in the art. For example, for at least some applications, configuring host device 105 to receive indications of defective or otherwise avoidable memory cells can make memory device 110 available with a larger number of defective memory cells than the number that can be repaired via a limited number of redundant or spare memory cells contained in memory device 110, which can improve production yield or provide other economic benefits.

[0042] As taught herein, information (e.g., addresses) regarding one or more defective volatile memory cells within memory device 110 may be stored in non-volatile memory of system 100, wherein this non-volatile memory may be contained within or separate from memory device 110. Host device 105 may be configured to query indications of one or more defective volatile memory cells in the non-volatile memory and subsequently avoid accessing the indicated volatile memory cells. In some cases, bootloader 140 may be configured to perform this query as part of the boot routine of system 100. For example, if memory device 110 is a DIMM, then host device 105 (e.g., bootloader 140) may be configured to request indications of one or more defective addresses from an SPD EEPROM contained in the DIMM, wherein the SPD EEPROM may also store and provide indications of one or more operational (e.g., timing or topology) parameters of the volatile memory within the DIMM. As another example, memory device 110 may include non-volatile (e.g., NAND) memory on the same or different memory dies 160 as volatile (e.g., DRAM) memory 170, and host device 105 (e.g., bootloader 140) may be configured to request indications of one or more defective addresses from this non-volatile memory. In some cases, external memory controller 120 may not initialize until host device 105 obtains information about memory cells to be avoided within memory device 110.

[0043] Figure 2This document describes examples supporting a memory architecture 200 based on instructions to avoid defective memory cells, as disclosed herein. In some instances, memory architecture 200 may represent a scheme through which the system passes access-avoided addresses to the host device (e.g., referenced in [reference]). Figure 1 The host device 105 described herein can map the received address to a set of system physical addresses through the scheme.

[0044] Memory architecture 200 may include DIMM 205. DIMM 205 may include one or more examples of volatile memories 210-a, 210-b, 210-c, and 210-d (e.g., DRAM devices). In some instances, each example of volatile memory 210 may be referenced. Figure 1 Examples of the described memory device 110 or memory die 160. An example of volatile memory 210 may be configured to store data that is retained when DIMM 205 is in an active state (e.g., powered on). Alternatively, DIMM 205 may contain non-volatile memory (e.g., SPD EEPROM 215). Non-volatile memory may be configured to retain data regardless of whether DIMM 205 is in an active state (e.g., powered on) or an inactive state (e.g., powered off or disconnected from power).

[0045] Memory architecture 200 may also include host device 202, which may be referenced. Figure 1 An example of host device 105 is described. Host device 202 may include bootloader 235, which may be referenced. Figure 1 An example of the bootloader 140 described. The host device 202 can use addresses within the system physical address space 245 (e.g., logical address space), which may represent a set of system physical addresses 250 (e.g., logical addresses) to address commands, data, or other signaling exchanged with the DIMM 205. Additionally, the host device 202 may contain an operating system 255, which may be referenced. Figure 1 An example of operating system 145 is described.

[0046] The SPD EEPROM 215 may be configured to store a table 220 (i.e., a bad memory element table (BMET)) containing information about one or more defective cells or groups of cells (e.g., rows, columns, banks) in an example of volatile memory 210, which may generally be referred to as defective memory locations 225. For example, the SPD EEPROM 215 may store information corresponding to a first defective memory location 225-a of volatile memory example 210-a, a second defective memory location 225-b of volatile memory example 210-b, and a third defective memory location 225-c of volatile memory example 210-d. In some instances, table 220 may contain an entry for each defective memory location 225 and a length corresponding to the number of consecutive defective cells, rows, columns, banks, or bits in said defective memory location 225. For example, defective memory location 225-a may correspond to 8 defective cells, rows, columns or memory banks; defective memory location 225-b may correspond to 2 defective cells, rows, columns or memory banks; and defective memory location 225-c may correspond to 3 defective cells, rows, columns or memory banks.

[0047] In some instances, the SPD EEPROM 215 may be configured to provide indications of one or more defective volatile memory cells to the host device 202. For example, the boot loader 235 of the host device 202 may provide instructions, when executed at the host device 202, causing the host device 202 to transmit a request for indications of one or more defective cells to the SPD EEPROM 215. For example, the request may include a read command or other query for the SPD EEPROM 215. After receiving the request, the SPD EEPROM 215 may retrieve information corresponding to one or more defective cells (e.g., table 220) and may provide indications of one or more defective cells (e.g., indications in table 220) to the host device 202.

[0048] The host device 202 may (e.g., based on executing bootloader 235) map each of the defective memory locations 225 to a corresponding system physical address 250 within the system physical address space 245. For example, each defective memory location 225 may be free of a corresponding address indication in the physical address space associated with DIMM 205 or the volatile memory 210 therein (e.g., via table 220), and bootloader 235 may include code instructing the processor of the host device 202 (e.g., processor 125) to map the corresponding physical address of each defective memory location 225 to the corresponding system physical address 250. For example, the host device 202 may map defective memory location 225-a to system physical address 250-a, defective memory location 225-b to system physical address 250-b, and defective memory location 225-c to system physical address 250-c. Therefore, for example, memory location 225 may be defined relative to the volatile memory example 210 residing therein and may each reside in a first address space (e.g., physical address space) of its respective volatile memory example 210. Meanwhile, system physical address 250 may be defined relative to system physical address space 245 and may therefore reside in a second address space (e.g., logical address space). Thus, mapping memory location 225 to the corresponding system physical address 250 may involve mapping from the first address space to the second address space.

[0049] After mapping memory location 225 to the corresponding system physical address 250, bootloader 235 causes host device 202 to provide operating system 255 with corresponding indications (e.g., a blacklist) of the system physical addresses 250 (e.g., system physical addresses 250-a, 250-b, and 250-c). Upon receiving the blacklist, operating system 255 can isolate the indicated system physical addresses 250 (e.g., prevent host device 202 from reading from, writing to, or otherwise accessing or utilizing the indicated system physical addresses 250), thus preventing operating system 255 from utilizing the corresponding defective memory location 225. For example, operating system 255 may not assign the corresponding system physical address 250 to any application. In some instances, operating system 255 (or a processor, such as a CPU, contained in host device 202) may mark these system physical addresses 250 as reserved, which can prevent exposure to them and associated errors. In some instances, the controller (e.g., the host-side DRAM controller) contained in or coupled to the host device 202 and the DIMM 205 may not be initialized until the avoided system physical address 250 is provided to the operating system 255 or at least obtained by the host device 202 (e.g., by starting the loader 235).

[0050] Figure 3 This document describes an example of a device communication configuration 300 based on instructions to avoid defective memory cells, as disclosed herein. In some instances, the memory architecture 300 may be... Figure 1 Or one or more components of 2 may be implemented. For example, memory device 305 may be a reference. Figure 1 Examples or references to the described memory device 110 Figure 2 An example of volatile memory 210 is described, and host device 320 may be used as a reference. Figure 1 An instance of the described host device 105 or the described host device 202.

[0051] Memory architecture 300 may include memory device 305. Memory device 305 may include DRAM die 310 (which may be an example of volatile memory) and NAND memory 315 (which may be an example of non-volatile memory). DRAM die 310 may be a reference. Figure 1 An example of a memory die 160 is described. The DRAM die 310 and the NAND memory 315 may be contained in the same package. However, in some instances, the DRAM die 310 may be on a first die (which may be referred to as a chip), and the NAND memory 315 may be on a second die. In such cases, the memory device may be considered as an MCP.

[0052] The memory architecture 300 may also include a host device 320. The host device 320 may include a boot loader 325 and an operating system 330. The boot loader 325 may be referenced. Figure 1 The description of the startup loader 140 or reference Figure 2 An example of the bootloader 235 is described. Operating system 330 may be used as a reference. Figure 2 An example of operating system 255 is described.

[0053] In some instances, memory device 305 may be configured to communicate with host device 320. For example, DRAM die 310 may communicate with host device 320 via a first interface (e.g., a first bus or a set of pins), and NAND memory 315 may communicate with host device 320 via a second interface (e.g., a second bus or a set of pins). Communication between memory device 305 and host device 320 may include commands (e.g., commands for accessing DRAM die 310 or NAND memory 315) or data (e.g., data to be written to or read from DRAM die 310 or NAND memory 315).

[0054] In this example, NAND memory 315 may be configured to store a table containing information about one or more defective cells in DRAM die 310 (e.g., reference). Figure 2 The table described is 220 (i.e., BMET). For example, NAND memory 315 may store information corresponding to a first memory location of DRAM die 310, a second memory location of DRAM die 310, and a third memory location of DRAM die 310. For instance, the table may contain entries for each memory location and a length corresponding to the number of consecutive defective cells, rows, or columns in said memory location. In some instances, memory device 305 may include multiple DRAM dies 310. In such instances, the memory locations included in the table may come from one or more of the multiple DRAM dies 310.

[0055] In some instances, NAND memory 315 may be configured to provide indications of one or more defective cells to host device 320. For example, a bootloader 325 of host device 320 may provide instructions to host device 320 to transmit a request for indications of one or more defective cells. For example, the request may include a read command for NAND memory 315. After receiving the request, NAND memory 315 may retrieve information corresponding to one or more defective cells (e.g., a table, e.g., a reference table). Figure 2 The table 220 described herein may be provided to the host device 320 containing the boot loader 325, and indications of one or more defective cells (e.g., indications of Table 220) may be provided. In some instances, the table may have a specific placement (e.g., the first N pages of erase block 0). And in some instances, the driver software of the NAND memory 315 may recognize the table for the DRAM die 310.

[0056] Using the bootloader 325, the host device 320 can map the provided memory location to physical memory, such as reference memory. Figure 2 Description. For example, the bootloader 325 may include code instructing the processor of the host device 320 (e.g., processor 125) to map each memory location indicated by a physical address within the physical address space of the DRAM die 310 to a corresponding system physical address in the address space used by the host device 320. For example, the host device 320 may map a first memory location to a first system physical address, a second memory location to a second system physical address, and a third memory location to a third system physical address. Thus, for example, a memory location indicated by the NAND memory 315 may be defined relative to the DRAM die 310 in which the memory location may reside and may each be in a first address space of the DRAM die 310. Meanwhile, a system physical address may be defined relative to the physical memory and may therefore be in a second address space of the physical memory. Thus, mapping a memory location to a corresponding physical address may involve mapping from the first address space to the second address space.

[0057] After mapping memory locations to corresponding system physical addresses, host device 320 may be instructed by bootloader 325 to relay a blacklist of the corresponding system physical addresses to operating system 330 of host device 320. After receiving the blacklist, operating system 330 may isolate the indicated system physical addresses so that operating system 330 does not use the system physical addresses and does not assign these addresses to applications.

[0058] In some instances, the controller (e.g., the host-side DRAM controller) of the DRAM die 310 contained in or coupled to the host device 320 may not be initialized until the avoided system physical address is provided to the operating system 330 or at least obtained by the host device 320 (e.g., by starting the loader 325).

[0059] although Figure 3 Examples of examples are provided in the descriptions of DRAM and NAND memory types, but it should be understood that the teachings herein are applicable to any memory type, including any combination of volatile and non-volatile memory within an MCP.

[0060] Figure 4 This document describes an example of a device communication configuration 400 based on instructions to avoid defective memory cells, as disclosed herein. In some instances, the memory architecture 400 may be... Figures 1 to 3 One or more components are implemented. For example, DRAM die 405 may be a reference. Figure 1 Examples and references of the memory die 160 described. Figure 2 Examples or references to the described volatile memory 210 Figure 3 The DRAM die 310 is described. Additionally, the host device 435 may be referenced. Figure 1 The described host device 105 or reference Figure 2 An example of the host device 202 described.

[0061] Memory architecture 400 may include DRAM die 405. DRAM die 405 may include DRAM array 410, which may be an example of volatile memory. DRAM array 410 may be a reference. Figure 1 Examples of the described memory array 170. In some examples, the DRAM array 410 may include one or more memory banks 422. For example, in this example, the DRAM array 410 may include memory banks 422-a, 422-b, 422-c, and 422-d.

[0062] In some cases, DRAM die 405 includes a non-volatile memory device 415, which may be an example of non-volatile memory. In some instances, the non-volatile memory device 415 may include, alone or in any combination, a programmable read-only memory (PROM), one or more fuses, one or more antifuses, or any other type of non-volatile memory. DRAM die 405 may be included within a memory device (e.g., memory device 110). DRAM die 405 may further include an address multiplexer (MUX) 430. In instances where a single example of a memory device includes DRAM die 405, the memory device may be considered an SCP.

[0063] The memory architecture 400 may also include a host device 435. The host device 435 may include a boot loader 440 and an operating system 445. The boot loader 440 may be a reference. Figure 1 The description of the startup loader 140, reference Figure 2 The description of the startup loader 235 or reference Figure 3 An example of the boot loader 325 is described. Operating system 445 may be used as a reference. Figure 2 The operating system described is 255 or reference. Figure 3 An example of the operating system 330 described.

[0064] DRAM array 410 and non-volatile memory device 415 may be coupled to address MUX 430. Address MUX 430 may be further coupled to host device 435. For example, address MUX 430 may be coupled to a memory controller of host device 435 configured to execute code corresponding to bootloader 440, operating system 445, or both.

[0065] Address MUX 430 (which may also be referred to as a multiplexing circuitry system) can be configured to selectively route commands or other signals to DRAM array 410 or non-volatile memory device 415. For example, address MUX 430 may route signaling addressing a first portion of the address space of memory die 405 to DRAM array 410, and address MUX 430 may route signaling addressing a second portion of the address space of memory die 405 to non-volatile memory device 415. For instance, when host device 435 provides a command instructing access to a first set of rows of memory in DRAM array 410 (e.g., the first N rows of a given memory), address MUX 430 may route the command to non-volatile memory device 415 instead of DRAM array 410. Although described as included in... Figure 4In the example DRAM die 405, however, those skilled in the art will understand that in some implementations, address MUX 430 may not be included in DRAM die 405. For example, address MUX 430 and related concepts can be used, for example, in references... Figure 3 The MCP instance described.

[0066] In some instances, the non-volatile memory device 415 may include a set of non-volatile mode registers. In some such instances, the bootloader 440 may query the non-volatile memory device 415 by transmitting a read command addressed to the mode register. In some such instances, the address space of the non-volatile memory device 415 may differ from the address space of the DRAM array 410.

[0067] Non-volatile memory device 415 may be configured to store information about one or more defective cells in DRAM array 410, such as (for example) a table (e.g., BMET 420, which may be a reference). Figure 2 (Examples of Table 220 described). For example, non-volatile memory device 415 may store information corresponding to memory location 425-a at memory bank 422-d, memory location 425-b at memory bank 422-b, and memory location 425-c at memory bank 422-a. In some instances, BMET 420 may include an entry for each memory location and a length corresponding to the number of consecutive defective cells, rows, or columns in said memory location 425.

[0068] In some instances, nonvolatile storage device 415 may be configured to provide indications of one or more defective cells to host device 435. For example, a bootloader 440 of host device 435 may provide instructions to host device 435 to transmit a request for indications of one or more defective cells. For example, the request may include a read command for nonvolatile storage device 415. Upon receiving the request, nonvolatile storage device 415 may retrieve information (e.g., a table, such as BMET 220) corresponding to one or more defective cells and may provide indications of one or more defective cells (e.g., indications of BMET 420) to host device 435 containing bootloader 440.

[0069] Using bootloader 440, host device 435 can map memory locations provided from the physical address space associated with DRAM array 410 to the system physical address space (e.g., virtual address space) associated with host device 435, such as by referencing Figure 2Description. For example, the bootloader 440 may include code instructing the processor (e.g., processor 125) of the host device 435 to map each corresponding address of each defective memory location to a corresponding system physical address. For example, the host device 435 may map a first defective memory location to a first system physical address, a second defective memory location to a second system physical address, and a third defective memory location to a third system physical address. Thus, for example, defective memory locations may be defined relative to the DRAM array 410 in which the memory locations may reside and may each reside in a first address space of the DRAM array 410. Meanwhile, system physical addresses may be defined relative to a second address space of commands or other signaling used by the host device 435 to address the DRAM die 405. Therefore, mapping memory locations to corresponding system physical addresses may involve mapping from the first address space to the second address space.

[0070] After mapping memory locations to corresponding system physical addresses, host device 435 may be instructed by bootloader 440 to relay a blacklist of the corresponding system physical addresses to operating system 445 of host device 435. Upon receiving the blacklist, operating system 445 may isolate the indicated system physical addresses, preventing operating system 445 from using them and from assigning these addresses to applications.

[0071] In some instances, the controller (e.g., the host-side DRAM controller) of the DRAM die 405 or DRAM array 410 contained in or coupled to the host device 435 may not be initialized until the avoided system physical address is provided to the operating system 445 or at least obtained by the host device 435 (e.g., by starting the loader 440).

[0072] although Figure 4 Examples of this document refer to the descriptions of DRAM and NAND memory types, but it should be understood that the teachings herein are applicable to any memory type, including any combination of volatile and non-volatile memory within an SCP.

[0073] Figure 5 A block diagram 500 illustrates a host device 505 supporting instruction-based avoidance of defective memory cells, based on examples disclosed herein. The host device 505 may be a reference. Figures 1 to 4 Examples of aspects of the described host device. Host device 505 may include a request transmitter 510, an address indication receiver 515, a data communication component 520, an access component 525, an address mapping component 530, a startup identification component 535, a controller initialization component 540, and an addressing component 545. Each of these modules may communicate with each other directly or indirectly (e.g., via one or more buses).

[0074] The request transmitter 510 can transmit a request from the host device to a non-volatile memory component, indicating one or more addresses of a volatile memory component coupled to the host device, to which the host device will avoid accessing one or more addresses. In some instances, transmitting the request to the non-volatile memory component may include querying the non-volatile memory component for Serial Presence Detection (SPD) information about the volatile memory component.

[0075] In some cases, the host device includes a boot loader, which transmits a request for instructions to one or more addresses.

[0076] Address indication receiver 515 can receive at the host device an indication of one or more addresses of a volatile memory component that the host device will avoid accessing from the non-volatile memory component.

[0077] The data communication component 520 can communicate with the volatile memory component via the host device.

[0078] When communicating with the volatile memory component, the access component 525 can prevent writing to or reading from one or more addresses of the volatile memory component via the host device and based on an instruction received from the non-volatile memory component.

[0079] In some instances, one or more addresses may be located within a first address space associated with the volatile memory component. In some such instances, address mapping component 530 may map one or more addresses to one or more corresponding addresses within a second address space associated with a host device, wherein the restriction by the host device includes isolating one or more corresponding addresses.

[0080] The boot identification component 535 can identify whether a host device is booting or restarting, wherein a request to transmit an instruction to one or more addresses is based on identifying booting or restarting. For example, the boot identification component 535 may be a boot loader described herein, included in, or coupled to the boot loader. In some instances, the boot loader may prevent writing to or reading from one or more addresses of a volatile memory component.

[0081] The controller initialization component 540 can initialize the controller of the volatile memory component at the host device after receiving instructions of one or more addresses (e.g., by the host device).

[0082] Addressing component 545 can address requests to one or more mode registers, wherein transferring the request to the non-volatile memory component is based on addressing. In some instances, addressing component 545 can address requests to addresses within a first portion of the address space of the volatile memory component, wherein one or more addresses are within a second portion of the address space of the volatile memory component, and wherein transferring the request to the non-volatile memory component is based on addressing.

[0083] In some cases, a volatile memory component comprises a set of volatile memory devices, wherein one or more addresses contain addresses of the set of volatile memory devices within the set of volatile memory devices. In some cases, one or more addresses correspond to one or more defective memory cells within the volatile memory component. In some cases, the volatile memory component may comprise dynamic random access memory (DRAM). In some cases, the non-volatile memory component comprises NAND memory.

[0084] Figure 6 A block diagram 600 illustrates a memory device 605 supporting instruction-based avoidance of defective memory cells, based on examples disclosed herein. The memory device 605 may be referenced. Figures 1 to 4 Examples of aspects of the described memory device. Memory device 605 may include a request receiver 610, an address information retrieval unit 615, an address indication transmitter 620, an address identification component 625, a request routing component 630, and a mode register identification component 635. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0085] The request receiver 610 may receive a request from the host device for indication of one or more addresses of the volatile memory component, and the host device will avoid accessing one or more addresses. In some cases, the volatile memory component includes dynamic random access memory (DRAM). In some cases, the volatile memory component includes on-die dynamic random access memory (DRAM) within a package.

[0086] Address information retrieval unit 615 can retrieve, based on a request, information from the non-volatile memory component indicating that the host device will avoid accessing one or more addresses of the volatile memory component. In some cases, the non-volatile memory component stores Serial Presence Detection (SPD) information of DRAM, which includes information indicating one or more addresses. In some cases, the non-volatile memory component includes on-die NAND memory within a package. In some cases, the non-volatile memory component includes one-time programmable memory. In some cases, the volatile memory component and the non-volatile memory component are on the same die.

[0087] Address indication transmitter 620 can transmit an indication of one or more addresses of a volatile memory component that is to be avoided from access to the host device.

[0088] Address identification component 625 can identify the address associated with the request. Request routing component 630 can route the request to a non-volatile memory component based on the address associated with the request, wherein the address associated with the request is within a first portion of the address space of the volatile memory component, and one or more of the addresses are within a second portion of the address space of the volatile memory component.

[0089] In some cases, the mode register identification component 635 can identify one or more mode registers upon request, wherein the non-volatile memory component contains one or more mode registers.

[0090] Figure 7 The illustration describes a flowchart of one or more methods 700 based on instructions to avoid defective memory cells, according to examples disclosed herein. Operation of method 700 may be implemented by a host device or its components described herein. For example, operation of method 700 may be performed by reference to... Figure 5 The described host device performs the function. In some instances, the host device may execute a set of instructions to control the functional elements of the host device to perform the described function. Alternatively, the host device may use dedicated hardware to perform aspects of the described function.

[0091] In 705, the host device may transmit a request for indication of one or more addresses of a volatile memory component coupled to the host device to a non-volatile memory component, and the host device will avoid accessing one or more addresses. Operation 705 may be performed according to the methods described herein. In some instances, aspects of operation 705 may be derived from references Figure 5 The described request is executed by the transporter.

[0092] At 710, the host device may receive from the non-volatile memory component an indication that the host device will avoid accessing one or more addresses of the volatile memory component. Operation 710 may be performed according to the methods described herein. In some instances, aspects of operation 710 may be derived from references Figure 5 The described address instructs the receiver to perform the action.

[0093] At 715, the host device can communicate data with the volatile memory component (e.g., transmit or receive). Operation 715 can be performed according to the methods described herein. In some instances, aspects of operation 715 may be derived from references. Figure 5 The data communication component described is executed.

[0094] At 720, the host device can, during data communication with the volatile memory component, prevent writing to or reading from one or more addresses of the volatile memory component based on an instruction received from the non-volatile memory component. Operation 720 can be performed according to the methods described herein. In some instances, aspects of operation 720 may be referenced from... Figure 5 The described access component is executed.

[0095] In some instances, the device described herein may perform one or more methods, such as method 700. The device may include features, elements, or instructions for transmitting a request from a host device to a non-volatile memory component (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for indication of one or more addresses of a volatile memory component coupled to a host device, which the host device will avoid accessing said one or more addresses. The device may further include operations, features, elements, or instructions for receiving, at the host device, indications from the non-volatile memory component of one or more addresses of the volatile memory component that the host device will avoid accessing. The device may further include operations, features, elements, or instructions for data communication with the volatile memory component via the host device. The device may further include operations, features, elements, or instructions for preventing writing to or reading from one or more addresses of the volatile memory component via the host device and based on indications received from the non-volatile memory component during data communication with the volatile memory component.

[0096] In some instances of the method 700 and apparatus described herein, one or more addresses may be in a first address space associated with a volatile memory component, and the apparatus may further include operations, features, components, or instructions for mapping one or more addresses to one or more corresponding addresses in a second address space associated with a host device, wherein the blocking by the host device may include operations, features, components, or instructions for isolating one or more corresponding addresses.

[0097] Some examples of the method 700 and device described herein may further include operations, features, components, or instructions for identifying the startup or restart of a host device, wherein a request to transmit an indication to one or more addresses may be based on identifying startup or restart.

[0098] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for a controller to initialize a volatile memory component at a host device after receiving an instruction from one or more addresses.

[0099] In some instances of the method 700 and apparatus described herein, the host device may include a bootloader, wherein the bootloader transmits a request for instructions to one or more addresses.

[0100] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for preventing writing to or reading from one or more addresses of a volatile memory component by initiating a loader.

[0101] In some instances of the method 700 and apparatus described herein, the volatile memory component includes a set of volatile memory devices, wherein one or more addresses contain addresses of multiple volatile memory devices (e.g., memory cells in multiple volatile memory devices) within the set of volatile memory devices.

[0102] In some instances of the method 700 and apparatus described herein, one or more addresses may correspond to one or more defective memory cells within a volatile memory component.

[0103] In some instances of the method 700 and apparatus described herein, the operations, features, components, or instructions for transmitting a request to a non-volatile memory component may include operations, features, components, or instructions for querying serial presence detection (SPD) information about the non-volatile memory component.

[0104] In some instances of the method 700 and apparatus described herein, the volatile memory component may include dynamic random access memory (DRAM), and the non-volatile memory component may include NAND memory.

[0105] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for addressing requests to one or more mode registers, wherein transferring the request to a non-volatile memory component may be based on addressing.

[0106] Some examples of the method 700 and apparatus described herein may further include operations, features, components, or instructions for addressing a request for an address within a first portion of the address space of a volatile memory component, wherein one or more addresses may be within a second portion of the address space of the volatile memory component, and wherein transferring the request to a non-volatile memory component may be based on addressing.

[0107] Figure 8 The illustration depicts a flowchart of one or more methods 800 based on instructions to avoid defective memory cells, supported by examples disclosed herein. Operation of method 800 may be implemented by a memory device or its components described herein. For example, operation of method 800 may be provided by reference to... Figure 6 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0108] At 805, the memory device may receive from the host device a request for indication of one or more addresses of a volatile memory component, which the host device will avoid accessing said one or more addresses. Operation 805 may be performed according to the methods described herein. In some instances, aspects of operation 805 may be provided by reference. Figure 6 The described request is executed by the receiver.

[0109] At 810, the memory device may, based on a request, retrieve information from the non-volatile memory component regarding one or more addresses of a volatile memory component that the host device will avoid accessing. Operation 810 may be performed according to the methods described herein. In some instances, aspects of operation 810 may be derived from references... Figure 6 The address information retrieval function described is executed.

[0110] At 815, the memory device may transmit to the host device an indication of one or more addresses of a volatile memory component to be accessed. Operation 815 may be performed according to the methods described herein. In some instances, aspects of operation 815 may be provided by reference. Figure 6 The described address indicates that the transmitter should perform the operation.

[0111] In some instances, the apparatus described herein may perform one or more methods, such as method 800. The apparatus may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a request from a host device for indications to one or more addresses of a volatile memory component, which the host device will avoid accessing. The apparatus may further include features, components, or instructions for retrieving information from a non-volatile memory component, based on the request, indicating that the host device will avoid accessing one or more addresses of the volatile memory component. The apparatus may further include features, components, or instructions for transmitting the indications to the host device that the host device will avoid accessing one or more addresses of the volatile memory component.

[0112] In some instances of the method 800 and apparatus described herein, the volatile memory component may include dynamic random access memory (DRAM), and the non-volatile memory component may store serial presence detection (SPD) information of the DRAM, the SPD information including information indicating one or more addresses.

[0113] In some instances of the method 800 and apparatus described herein, the volatile memory component may include dynamic random access memory (DRAM) on a first die within a package, and the non-volatile memory component may include NAND memory on a second die within a package.

[0114] In some instances of the method 800 and apparatus described herein, the non-volatile memory component may include a one-time programmable memory.

[0115] In some instances of the method 800 and apparatus described herein, volatile memory components and non-volatile memory components may be on the same die.

[0116] Some examples of the method 800 and apparatus described herein may further include operations, features, components, or instructions for identifying an address associated with a request and routing the request to a non-volatile memory component based on the address associated with the request, wherein the address associated with the request may be within a first portion of the address space of the volatile memory component, and one or more of the addresses may be within a second portion of the address space of the volatile memory component.

[0117] Some examples of the method 800 and device described herein may further include operations, features, components, or instructions for identifying one or more mode registers based on a request, wherein the non-volatile memory component includes one or more mode registers.

[0118] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, parts from two or more of the methods may be combined.

[0119] Describe an apparatus. The apparatus may include a volatile memory component and a non-volatile memory component. The non-volatile memory component may be configured to: store information indicating one or more defective memory cells within the volatile memory component; receive a request for an indication of the one or more defective memory cells within the volatile memory component; and, in response to the request, output an indication of the one or more defective memory cells within the volatile memory component.

[0120] In some instances, the device may include a memory module, the volatile memory component may include dynamic random access memory (DRAM) within the memory module, and the non-volatile memory component may include electrically erasable programmable read-only memory (EEPROM) within the memory module and configured to store serial presence detection (SPD) information of the DRAM, the SPD information including information indicating one or more defective memory cells within the volatile memory component.

[0121] In some instances, the device may include a set of dies within a package, the volatile memory component may include dynamic random access memory (DRAM) on a first die in the set of dies, and the non-volatile memory component may include NAND memory on a second die in the set of dies.

[0122] In some instances, the device may include a die containing the volatile memory component and the non-volatile memory component.

[0123] In some instances, the non-volatile memory component may include one or more non-volatile mode registers.

[0124] Some instances of the device may include a multiplexing circuitry system configured to route commands for a first portion of the address space of the die (e.g., addresses addressed therein) to the volatile memory component and commands for a second portion of the address space of the die (e.g., addresses addressed therein) to the non-volatile memory component.

[0125] The information and signals described herein can be represented using any of a variety of different processes and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a signal bus, where the bus can have various bit widths.

[0126] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that supports the flow of signals between them. If there are any conductive paths between components that can support the flow of signals between them at any time, then the components can be considered to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other). At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be open or closed based on the operation of the device containing the connected component. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some instances, one or more intermediate components (such as switches or transistors) may be used to interrupt the flow of signals between connected components for a period of time.

[0127] The term "coupling" refers to a condition that moves from an open-circuit relationship between components (where signals cannot currently be transmitted between components via conductive paths) to a closed-circuit relationship between components (where signals can be transmitted between components via conductive paths). When a component, such as a controller, couples other components together, the component triggers a change that allows signals to flow between the other components via conductive paths that were previously not permitted.

[0128] The term "isolation" refers to a relationship between components in which signals are currently unable to flow between them. If there is an open circuit between components, they are isolated from each other. For example, when a switch positioned between two components is turned on, the components separated by the switch are isolated from each other. When a controller isolates two components, the controller causes a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0129] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of a semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0130] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0131] The descriptions presented herein, together with the accompanying drawings, illustrate exemplary configurations and do not represent all instances that can be implemented or are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," not "preferred" or "superior to other instances." The detailed descriptions include specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concept of the described instances.

[0132] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dashed reference numeral followed by a second reference numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0133] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on a computer-readable medium or transmitted as one or more instructions or code via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located at various locations, including distribution such that portions of the functions are implemented at different physical locations.

[0134] For example, the various specification boxes and modules described in connection with the disclosure herein may be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0135] Furthermore, as used herein (included in the claims), the word "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on..." should not be construed as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on..." should be interpreted in the same manner as the phrase "at least partially based on...".

[0136] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure will be made, and that the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for memory operations, comprising: transmitting, from a host device to a non-volatile memory component, a request for an indication of a set of lengths, each length of the set of lengths corresponding to a respective number of elements of a volatile memory component coupled with the host device, wherein the host device is to refrain from accessing the respective number of elements, and the respective number of elements comprises a contiguous defective bit, cell, row, or column of the volatile memory component; receiving, at the host device from the non-volatile memory component, the indication of the set of lengths; communicating, by the host device with the volatile memory component, data communications; and while communicating the data communications with the volatile memory component, refraining, by the host device and based at least in part on the indication of the set of lengths received from the non-volatile memory component, from writing to or reading from one or more addresses of the volatile memory component associated with the respective number of elements.

2. The method of claim 1, wherein the one or more addresses are within a first address space associated with the volatile memory component, the method further comprising: mapping the one or more addresses to one or more corresponding addresses within a second address space associated with the host device, wherein the refraining by the host device comprises isolating the one or more corresponding addresses.

3. The method of claim 1, further comprising: identifying a boot or a reboot of the host device, wherein transmitting the request for the indication of the set of lengths is based at least in part on identifying the boot or the reboot.

4. The method of claim 3, further comprising: initializing, at the host device, a controller of the volatile memory component after receiving the indication of the set of lengths.

5. The method of claim 3, wherein the host device comprises a boot loader, and wherein the boot loader transmits the request for the indication of the set of lengths.

6. The method of claim 5, further comprising: refraining, by the boot loader, from writing to or reading from the one or more addresses of the volatile memory component.

7. The method of claim 1, wherein the volatile memory component comprises a set of volatile memory devices, and wherein the one or more addresses comprise addresses of a plurality of volatile memory devices within the set of volatile memory devices.

8. The method of claim 1, wherein the one or more addresses correspond to one or more defective memory cells within the volatile memory component.

9. The method of claim 1, wherein transmitting the request to the non-volatile memory component comprises: querying serial presence detect (SPD) information of the non-volatile memory component regarding the volatile memory component.

10. The method of claim 1, wherein: The volatile memory component includes dynamic random access memory (DRAM); and The non-volatile memory component includes negative-and (NAND) memory.

11. The method of claim 1, further comprising: addressing the request to one or more mode registers, wherein transmitting the request to the non-volatile memory component is based at least in part on the addressing.

12. The method of claim 1, further comprising: addressing the request to an address within a first portion of an address space of the volatile memory component, wherein the one or more addresses are within a second portion of the address space of the volatile memory component, and wherein transmitting the request to the non-volatile memory component is based at least in part on the addressing.

13. A method for memory operations, comprising: receiving, from a host device, a request for an indication of a set of lengths, each length of the set of lengths corresponding to a respective quantity of elements of a volatile memory component, wherein the host device is to avoid accessing the respective quantity of elements, and the respective quantity of elements comprises a contiguous defective bit, cell, row, or column of the volatile memory component; retrieving, from a non-volatile memory component, information indicating the set of lengths based at least in part on the request; and transmitting the indication of the set of lengths to the host device to cause the host device to avoid accessing the respective quantity of elements.

14. The method of claim 13, wherein: the volatile memory component includes dynamic random access memory (DRAM); and the non-volatile memory component stores serial presence detect (SPD) information for the DRAM, the SPD information including the information indicating the set of lengths.

15. The method of claim 13, wherein: the volatile memory component includes dynamic random access memory (DRAM) on a first die within a package; and the non-volatile memory component includes negative-and (NAND) memory on a second die within the package.

16. The method of claim 13, wherein the non-volatile memory component includes one-time programmable memory.

17. The method of claim 13, wherein the volatile memory component and the non-volatile memory component are on a same die.

18. The method of claim 17, further comprising: identifying an address associated with the request; and routing the request to the non-volatile memory component based at least in part on the address associated with the request, wherein the address associated with the request is within a first portion of an address space of the volatile memory component, and wherein one or more addresses associated with the respective quantity of elements are within a second portion of the address space of the volatile memory component.

19. The method of claim 17, further comprising: identifying one or more mode registers based at least in part on the request, wherein the non-volatile memory component includes the one or more mode registers.

20. An apparatus for memory operations, comprising: a volatile memory component; and a non-volatile memory component configured to: store information indicative of a set of lengths, each length of the set of lengths corresponding to a respective quantity of elements within the volatile memory component, wherein the respective quantity of elements comprises a contiguous defective bit, cell, row, or column of the volatile memory component; receive a request for an indication of the set of lengths; and output, in response to the request, the indication of the set of lengths to cause a host device to avoid accessing the respective quantity of elements.

21. The apparatus of claim 20, wherein: the apparatus comprises a memory module; the volatile memory component comprises dynamic random access memory (DRAM) within the memory module; and the non-volatile memory component comprises an electrically erasable programmable read-only memory (EEPROM) within the memory module and configured to store serial presence detect (SPD) information for the DRAM, the SPD information comprising the information indicative of the set of lengths.

22. The apparatus of claim 20, wherein: the apparatus comprises a plurality of dies within a package; the volatile memory component comprises dynamic random access memory (DRAM) on a first die of the plurality of dies; and the non-volatile memory component comprises negative-and (NAND) memory on a second die of the plurality of dies.

23. The apparatus of claim 20, wherein the apparatus comprises a die, the die comprising the volatile memory component and the non-volatile memory component.

24. The apparatus of claim 23, wherein the non-volatile memory component comprises one or more non-volatile mode registers.

25. The apparatus of claim 23, further comprising: multiplexing circuitry configured to route commands for a first portion of an address space of the die to the volatile memory component and to route commands for a second portion of the address space of the die to the non-volatile memory component.

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