Trench type semiconductor component manufacturing method

Abstract

A method for manufacturing a trench-type semiconductor device includes the following steps: first, forming an epitaxial layer on a substrate, then forming a trench in the epitaxial layer, and forming a gate structure in the trench. The gate structure includes an upper gate, a lower gate, and an intermediate insulating portion, with the intermediate insulating portion located between and above the upper gate. This effectively improves gate capacitance characteristics and increases gate response speed.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor component, and more particularly to a method for manufacturing a trench-type semiconductor component. Background Art

[0002] Power Metal Oxide Semiconductor Field Effect Transistor (MOSFET), also known as power transistor, is a field-effect transistor currently used extensively in analog and digital circuits. Power MOSFETs have the advantages of very low on-resistance and very fast switching speeds, making them the mainstream power component.

[0003] The structure of power MOSFETs can be categorized based on the current flow path. Horizontal current flows parallel to the device surface, while vertical current flows vertically. Vertical power MOSFETs have the drain terminal located at the bottom of the device, thus reducing resistance per unit chip area.

[0004] Furthermore, trench-gate power MOSFETs (metal oxide semiconductor field-effect transistors) offer reduced on-resistance, making them a mainstream choice for high-frequency, low-voltage power components. For electronics and power, reducing on-resistance and gate capacitance helps improve power component response speed and enhance product quality. Summary of the Invention

[0005] This summary is intended to provide a simplified summary of the present disclosure so that readers can have a basic understanding of the present disclosure. This summary is not a complete overview of the present disclosure and is not intended to identify important / critical components of the present invention or to define the scope of the present invention.

[0006] The purpose of the present invention is to provide a method for manufacturing a trench-type semiconductor component, which can further reduce the input capacitance and reverse transfer capacitance of the semiconductor component, increase the output capacitance, and effectively improve the switching speed of the semiconductor component.

[0007] To achieve the above-mentioned objectives, the technology of the present invention relates to a method for manufacturing a trench-type semiconductor component, which includes the following steps: first, forming an epitaxial layer on a substrate, then forming a trench in the epitaxial layer, and forming a gate structure in the trench, wherein the gate structure includes an upper gate, a lower gate and an intermediate insulating portion, and the intermediate insulating portion is located in the middle and above the upper gate.

[0008] In some embodiments, the method for manufacturing a trench semiconductor device further includes depositing a first oxide layer in the trench, and depositing a first polysilicon layer on the first oxide layer and in the trench.

[0009] In some embodiments, the thickness of the first oxide layer is about 2000 angstroms. The thickness of the first polysilicon layer is between 3000 angstroms and 8000 angstroms, and the trench is filled.

[0010] In some embodiments, the method for fabricating a trench semiconductor device further includes etching back the first polysilicon layer to a position approximately 0.7 micrometers to 1.2 micrometers below the upper surface of the first oxide layer.

[0011] In some embodiments, the trench semiconductor device fabrication method further includes etching back the first oxide layer to a position approximately 1000 angstroms to 1500 angstroms below the upper surface of the first polysilicon layer to form a first dielectric layer.

[0012] In some embodiments, the trench semiconductor device manufacturing method further includes oxidizing the surfaces of the epitaxial layer and the first polysilicon layer to form a gate oxide layer, and using the gate oxide layer and the first dielectric layer to cover the lower gate.

[0013] In some embodiments, the method for fabricating a trench semiconductor device further includes depositing a second polysilicon layer to fill the trench, and etching back the second polysilicon layer to a position approximately 1000 angstroms to 1500 angstroms below the upper surface of the gate oxide layer.

[0014] In some embodiments, the trench semiconductor device manufacturing method further includes depositing a second oxide layer, blanket etching the second oxide layer to form a spacer on the upper surface of the second polysilicon layer in the trench, and using the spacer as a mask to self-align and etch the second polysilicon layer to form an upper gate.

[0015] In some embodiments, the trench semiconductor device manufacturing method further includes depositing a third oxide layer, etching back the third oxide layer and the spacer to form an intermediate insulating portion, wherein the intermediate insulating portion, the gate oxide layer, and the first dielectric layer cover the upper gate.

[0016] In some embodiments, the method for manufacturing a trench semiconductor device further includes performing ion implantation in the epitaxial layer, heating to drive the ions in, and using a source mask to define a source region.

[0017] In some embodiments, the trench semiconductor device manufacturing method further includes forming a second dielectric layer on the gate oxide layer, etching the second dielectric layer and the gate oxide layer using a contact mask to form a plurality of openings, and depositing a metal layer on the second dielectric layer and in the openings.

[0018] Therefore, the trench semiconductor component manufacturing method disclosed in the present invention can manufacture power metal oxide semiconductor transistors, and effectively reduce the size of the upper gate by using the intermediate insulating part, and use a self-aligned etching process to accurately form the upper gate so that it is located between the first dielectric layer, the intermediate insulating part and the gate oxide layer. At the same time, the first dielectric layer and the gate oxide layer are used to cover the lower gate, effectively improving the gate capacitance characteristics and increasing the response speed of the gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] To make the above and other objects, features, advantages and embodiments of the present invention more apparent, the accompanying drawings are described as follows:

[0020] Figures 1 to 10 It is a partial cross-sectional schematic diagram illustrating the manufacturing steps of a trench semiconductor device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0021] The following examples are described in detail with reference to the accompanying drawings. However, the examples provided are not intended to limit the scope of the present invention, and the description of the structural operation is not intended to limit the order of execution. Any device with equivalent functionality resulting from the reconfiguration of the components is within the scope of the present invention. Furthermore, the drawings are for illustrative purposes only and are not drawn to scale. To facilitate understanding, identical or similar components will be designated with the same reference numerals throughout the following description.

[0022] In addition, the terms used throughout the specification and claims generally have their ordinary meanings in the art, in the context of this disclosure, and in the specific context, unless otherwise noted. Certain terms used to describe the present invention are discussed below or elsewhere in this specification to provide additional guidance to those skilled in the art in describing the present invention.

[0023] In the embodiments and claims, unless otherwise specified, "a," "an," and "the" may refer to a single or multiple number. The numbers used in the steps are only used to identify the steps for ease of description and are not intended to limit the order or implementation of the embodiments.

[0024] Secondly, the words "include", "including", "have", "contain", etc. used in this article are all open terms, which mean including but not limited to.

[0025] Figures 1 to 10 A partial cross-sectional diagram illustrating the steps of manufacturing a trench semiconductor device according to an embodiment of the present invention. Figures 1 to 10 , to illustrate the trench semiconductor device manufacturing method. The trench semiconductor device manufacturing method includes the following steps, first, refer to Figure 1 An epitaxial layer 120 is formed on a substrate 110, and a trench 122 is formed in the epitaxial layer 120. In some embodiments, the substrate 110 is an N-type semiconductor substrate or a P-type semiconductor substrate. Taking a silicon substrate as an example, the N-type conductive impurities are pentavalent element ions, such as phosphorus ions or arsenic ions, while the P-type conductive impurities are trivalent element ions, such as boron ions, aluminum ions, or gallium ions.

[0026] Furthermore, the epitaxial layer 120 has the same conductivity type as the substrate 110, but the doping concentration of the epitaxial layer 120 is generally lower than that of the substrate 110. When the substrate 110 has a high concentration of N-type doping, the epitaxial layer 120 may have a low concentration of N-type doping, but the present invention is not limited thereto.

[0027] In some embodiments, the width of the trench 122 is approximately between 0.5 micrometers and 1 micrometer, and the depth of the trench 122 is approximately between 1.5 micrometers and 2.0 micrometers.

[0028] Next, see Figure 2 , depositing a first oxide layer 130 in the trench 122, and then depositing a first polysilicon layer 140 on the first oxide layer 130 and in the trench 122. In some embodiments, the thickness of the first oxide layer 130 is about 2000 angstroms. The thickness of the first polysilicon layer 140 is between 3000 angstroms and 8000 angstroms and is used to fill the trench 122 .

[0029] See Figure 3 The first polysilicon layer 140 is etched back until its upper surface is approximately 0.7 microns to 1.2 microns below the upper surface of the first oxide layer 130. The first oxide layer 130 is then etched back to a position approximately 1000 angstroms to 1500 angstroms below the upper surface of the first polysilicon layer 140 to form a first dielectric layer 132. In some embodiments, the first oxide layer 130 is etched back using a wet etch method, and the first oxide layer 130 on the sides of the trench 122 is removed to a position approximately 1000 angstroms to 1500 angstroms below the upper surface of the first polysilicon layer 140, thereby exposing the surfaces of the first polysilicon layer 140 and the epitaxial layer 120.

[0030] See Figure 4, then the exposed surfaces of the first polysilicon layer 140 and the epitaxial layer 120 are oxidized to form a gate oxide layer 150. Next, a second polysilicon layer 160 is deposited to fill the space in the trench 122. In some embodiments, the gate oxide layer 150 has a thickness of approximately 500 angstroms to 1000 angstroms. The second polysilicon layer 160 has a thickness of approximately 3000 angstroms to 8000 angstroms and fills the space in the trench 122. In some embodiments, the gate oxide layer 150 includes a first portion 152 and a second portion 154. The first portion 152 is formed by oxidizing the exposed surface of the first polysilicon layer 140, and the second portion 154 is formed by oxidizing the exposed surface of the epitaxial layer 120. The first portion 152 of the gate oxide layer 150 and the first dielectric layer 132 cover the lower gate 142, so that the lower gate 142 is sealed within the first dielectric layer 132 and the gate oxide layer 150.

[0031] See Figure 5 As shown in the figure, the second polysilicon layer 160 is etched back to a position approximately 1000 angstroms to 1500 angstroms below the upper surface of the gate oxide layer 150 to form a recessed polysilicon layer 162. Next, a second oxide layer 170 is deposited, such as a silicon oxide layer having a thickness of approximately 2000 angstroms to 3000 angstroms, to fill the recessed portion of the recessed polysilicon layer 162 in the trench 122.

[0032] See Figure 6 As shown in the figure, the second oxide layer 170 is blanket etched to form spacers 172 on the upper surface of the recessed polysilicon layer 162 formed by the second polysilicon layer 160 in the trench 122. In some embodiments, the length of the spacers 172 is between about 1500 angstroms and 2200 angstroms.

[0033] Then, see Figure 7 As shown in the figure, the recessed polysilicon layer 162 formed by the second polysilicon layer 160 is self-alignedly etched using the spacer 172 as a mask to form the desired upper gate 164.

[0034] Then, see Figure 8 A third oxide layer 180 is deposited in the middle opening of the upper gate 164 to fill the trench 122. In some embodiments, the third oxide layer 180 is, for example, a silicon oxide layer with a thickness of about 3000 angstroms to 5000 angstroms to fill the trench 122.

[0035] See Figure 9, the third oxide layer 180 and the spacer 172 are etched back to form an intermediate insulating portion 230, wherein the intermediate insulating portion 230 includes the intermediate oxide layer 182 formed by etching back the third oxide layer 180, and also includes the spacer 172 or the residual spacer 174 after etching back, which is determined by the depth of the etching back, all of which do not depart from the spirit and protection scope of the present invention.

[0036] In some embodiments, the intermediate insulating portion 230 , the gate oxide layer 150 , and the first dielectric layer 132 cover the upper gate 164 .

[0037] Then, ion implantation is performed to implant ions into the epitaxial layer 120 next to the gate structure 220, and further heating is performed to drive the ions in. In some embodiments, a trivalent element such as boron is used to implant P-type ions, and then heating is performed to drive the trivalent elements such as boron in. Next, a source mask is used to define the source region 190. In some embodiments, a source mask is used to implant ions into the source region 190, and further heating is performed to drive the ions in. For example, a pentavalent element such as arsenic, phosphorous, or antimony is shielded by the source mask to implant N-type ions, and then heated to drive the ions in.

[0038] See Figure 10 As shown in the figure, a second dielectric layer 200 is then formed on the gate oxide layer 150 and on the gate structure 220. A contact mask is used to etch the second dielectric layer 200 and the gate oxide layer 150 to form the required opening 156. A metal layer 210 is then deposited on the second dielectric layer 200 and in the opening 156. A mask and etching process are then used to form the required metal lines. In some embodiments, the second dielectric layer 200 includes borophospho-silicate glass (BPSG) as a dielectric layer with a thickness of approximately 6000 angstroms to 10000 angstroms. The metal layer 210 can be an aluminum metal layer with a thickness of approximately 3.0 microns to 5.0 microns, however, the present invention is not limited thereto.

[0039] In some embodiments, the upper gate 164 of the gate structure 220 is formed between the intermediate insulating portion 230 , the gate oxide layer 150 , and the first dielectric layer 132 , and the intermediate insulating portion 230 may be located between and above the upper gate 164 , while the lower gate 142 is enclosed in the first dielectric layer 132 and the gate oxide layer 150 .

[0040] In summary, the trench semiconductor device manufacturing method disclosed in the present invention can produce power metal oxide semiconductor transistors. The size of the upper gate is effectively reduced by the intermediate insulating portion, and the upper gate is accurately formed by the spacer. The upper gate is formed between the first dielectric layer, the intermediate insulating portion and the gate oxide layer. At the same time, the first dielectric layer and the gate oxide layer are used to cover the lower gate. Therefore, the drain-source breakdown voltage (BVDSS) is effectively increased, the input capacitance (Ciss) and the reverse transfer capacitance (Crss) are reduced, the output capacitance (Coss) is increased, the gate capacitance characteristics are improved, and the gate response speed is increased.

[0041] Although the present invention has been disclosed above in terms of embodiments, this is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the claims.

[0042]

Explanation of symbols

[0043] 110: Base material

[0044] 120: epitaxial layer

[0045] 122: Groove

[0046] 130: first oxide layer

[0047] 132: first dielectric layer

[0048] 140: first polysilicon layer

[0049] 142: lower gate

[0050] 150: Gate oxide layer

[0051] 152: Part 1

[0052] 154: Part 2

[0053] 156: Opening

[0054] 160: second polysilicon layer

[0055] 162: Concave polysilicon layer

[0056] 164: Upper gate

[0057] 170: Second oxide layer

[0058] 172: gap wall

[0059] 174: Residual spacer

[0060] 180: Third oxide layer

[0061] 182: Middle oxide layer

[0062] 190: Source region

[0063] 200: second dielectric layer

[0064] 210:Metal layer

[0065] 220: Gate structure

[0066] 230: Intermediate insulating part.

Claims

1. A method for manufacturing a trench semiconductor component, characterized in that: Include: forming an epitaxial layer on a substrate; forming a trench in the epitaxial layer; forming a gate structure in the trench, wherein the gate structure comprises an upper gate, a lower gate, and an intermediate insulating portion, and the intermediate insulating portion is located in the middle and above the upper gate; The gate structure is formed in the trench, comprising: depositing a first oxide layer in the trench; depositing a first polysilicon layer on the first oxide layer and in the trench; Etching back the first oxide layer to below the upper surface of the first polysilicon layer to form a first dielectric layer; Oxidizing the surfaces of the epitaxial layer and the first polysilicon layer to form a gate oxide layer, and using the gate oxide layer and the first dielectric layer to cover the lower gate; depositing a second polysilicon layer to fill the trench; Etching back the second polysilicon layer to below the upper surface of the gate oxide layer on the epitaxial layer; depositing a second oxide layer; blanket etching the second oxide layer to form spacers on an upper surface of the second polysilicon layer in the trench; and The spacer is used as a mask to etch the second polysilicon layer in a self-aligned manner to form the upper gate.

2. The method for manufacturing a trench semiconductor device as claimed in claim 1, wherein the thickness of the first oxide layer is between 2000 angstroms and 3000 angstroms, and the thickness of the first polysilicon layer is between 3000 angstroms and 8000 angstroms, and the trench is filled with the first oxide layer and the first polysilicon layer.

3. The method for manufacturing a trench semiconductor component according to claim 2, wherein: Also includes: The first polysilicon layer is etched back to a position 0.7 micrometers to 1.2 micrometers below the upper surface of the first oxide layer.

4. The method for manufacturing a trench semiconductor component according to claim 3, wherein: Also includes: The first oxide layer is etched back to a position 1000 angstroms to 1500 angstroms below the upper surface of the first polysilicon layer to form the first dielectric layer.

5. The method for manufacturing a trench semiconductor component according to claim 4, wherein: Also includes: The second polysilicon layer is etched back to a position 1000 angstroms to 1500 angstroms below the upper surface of the gate oxide layer on the epitaxial layer.

6. The method for manufacturing a trench semiconductor component according to claim 5, wherein: Also includes: depositing a third oxide layer; The third oxide layer and the spacer are etched back to form an intermediate insulating portion, wherein the intermediate insulating portion, the gate oxide layer and the first dielectric layer cover the upper gate.

7. The method for manufacturing a trench semiconductor device according to claim 6, wherein: Also includes: Ion implantation is performed on the epitaxial layer, and heating is performed to facilitate ion penetration; Use a source mask to define the source region; forming a second dielectric layer on the gate oxide layer; Using a contact region mask, etching the second dielectric layer and the gate oxide layer to form a plurality of openings; as well as A metal layer is deposited on the second dielectric layer and in the openings.

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