Semiconductor processing apparatus

Abstract

The present application provides a semiconductor processing device, which comprises a first chamber part and a second chamber part. The first chamber part has a first channel and the second chamber part has a second channel. When the second chamber part is in a closed position relative to the first chamber part and a semiconductor wafer is contained in the micro chamber, the first channel and the second channel are communicated and jointly form an edge micro processing space at the edge of the wafer. The outer edge of the semiconductor wafer contained in the micro chamber extends into the edge micro processing space. The first chamber part has a sealing joint part outside the first channel and the second chamber part has a joint groove corresponding to the sealing joint part. By means of the edge micro processing space, the present application can realize the processing of the outer edge of the semiconductor wafer.

Description

[Technical Field]

[0001] This invention relates to the field of surface treatment of semiconductor wafers or similar workpieces, and particularly to semiconductor processing apparatus. [Background Technology]

[0002] Precise edge etching of semiconductor wafers is a challenging process. It requires achieving micron-level precision etching at the wafer edge without damaging or contaminating the remaining thin film. In epitaxial wafer fabrication and advanced integrated circuit manufacturing processes, wafer edge etching is a crucial step in ensuring thin film formation quality and improving chip yield.

[0003] Please refer to Figures 1a to 1d ,in: Figure 1a A schematic diagram of the structure of a semiconductor wafer 400 is shown. Figure 1b for Figure 1a EE sectional view; Figure 1c A partial cross-sectional view of the outer edge of a semiconductor wafer before edge processing; Figure 1d This is a cross-sectional view of the outer edge of a semiconductor wafer after edge treatment. (Example:) Figures 1a to 1d As shown, the semiconductor wafer 400 includes a substrate layer 401 and a thin film layer 402 formed on a first edge surface and a second edge surface of the substrate layer 401. After selective etching of the first edge surface 404, the second wafer surface 406, and the outer edge bevel 408 of the outer edge portion of the semiconductor wafer 400, the thin film layer 402 of the outer edge portion of the semiconductor wafer 400 is removed, and the first edge surface and the second edge surface of the substrate layer 401 are exposed.

[0004] Existing wafer edge etching equipment can be broadly categorized into dry and wet methods. Dry methods are mainly divided into plasma etching and polishing. Plasma edge etching equipment is expensive and complex, primarily used in integrated circuit chip manufacturing. Polishing removes the contact film by rotating the wafer and utilizing physical friction and a combination of chemical gases and liquids. Polishing equipment is less expensive, but it is prone to damage and contamination of the retained film, and is mainly used in wafer manufacturing processes smaller than 200mm. Wet methods mainly include film-coating and vacuum adsorption. Film-coating uses a pure, corrosion-resistant plastic film such as PTFE or PE to protect the portion of the film to be retained, then exposes the entire wafer to a chemical etching gas environment or immerses it in a chemical etching solution to etch away the exposed portion. Film-coating involves multiple steps and requires various equipment, including equipment for film coating, wet etching, cleaning, and film removal. Vacuum adsorption uses a vacuum suction head to hold the wafer. The function of the vacuum suction head is to hold the wafer, protecting the portion of the film to be retained inside the suction head, while exposing the portion of the film to be removed outside the suction head. Then, the vacuum suction head and wafer are immersed together in a chemical etching solution to etch away the exposed film portion. The vacuum adsorption method has simple process steps and low equipment cost, but it is prone to damage and contamination of the retained film portion, and is mainly used in wafer manufacturing processes smaller than 200mm.

[0005] Therefore, it is necessary to propose a semiconductor processing apparatus that selectively processes the edges of semiconductor wafers. [Summary of the Invention]

[0006] The purpose of this invention is to provide a semiconductor processing apparatus that enables selective processing of the edges of a semiconductor wafer.

[0007] To achieve the above objectives, according to a first aspect of the present invention, a semiconductor processing apparatus is provided, comprising: a first chamber portion; and a second chamber portion movable relative to the first chamber portion between an open position and a closed position, wherein when the second chamber portion is in the closed position relative to the first chamber portion, a microchamber is formed between the first chamber portion and the second chamber portion, a semiconductor wafer can be accommodated in the microchamber, and when the second chamber portion is in the open position relative to the first chamber portion, the semiconductor wafer can be removed or inserted; the first chamber portion has a first channel formed on its inner wall surface facing the microchamber, and the second chamber portion has a... The second chamber portion faces the inner wall surface of the microcavity and forms a second channel. When the second chamber portion is in the closed position relative to the first chamber portion and a semiconductor wafer is contained in the microcavity, the first channel and the second channel are connected and together form an edge microprocessing space. The edge portion of the semiconductor wafer in the microcavity that needs to be processed extends into the edge microprocessing space. The edge microprocessing space has at least two edge processing through holes that communicate with the outside. Fluid enters or flows out of the edge microprocessing space through the edge processing through holes. The first chamber portion has a sealing joint portion located outside the first channel, and the second chamber portion has a joint groove corresponding to the sealing joint portion.

[0008] Compared to existing technologies, this invention utilizes the obstruction of the semiconductor wafer to be processed at the edge of the microcavity to form a closed edge microprocessing space. Processing fluid flows within this edge microprocessing space while simultaneously processing the outer edge portion of the semiconductor wafer extending into it. Furthermore, the cooperation of the sealing joint and the joint groove not only achieves sealing of the edge microprocessing space but also further reduces its volume.

[0009] In a preferred embodiment, the end portion of the inner edge surface of the sealing joint is perpendicular to the sealing surface of the groove wall of the joint groove in the extension direction of the semiconductor wafer. This arrangement allows the wall surface of the first chamber portion located inside the first channel to abut more closely against the first edge surface of the semiconductor wafer to be processed, and the wall surface of the second chamber portion located inside the second channel to abut more closely against the second edge surface of the semiconductor wafer to be processed, thus preventing the etchant from penetrating inward. [Attached Image Description]

[0010] The invention will be more readily understood in conjunction with the accompanying drawings and the following detailed description, wherein the same reference numerals correspond to the same structural components, wherein:

[0011] Figure 1a This is a schematic diagram of the structure of a semiconductor wafer;

[0012] Figure 1b for Figure 1a EE sectional view;

[0013] Figure 1c A cross-sectional view of the outer edge portion of a semiconductor wafer before edge processing;

[0014] Figure 1d This is a cross-sectional view of the outer edge portion of a semiconductor wafer after edge treatment.

[0015] Figure 2a This is a cross-sectional schematic diagram of the semiconductor processing apparatus in the first embodiment of the present invention;

[0016] Figure 2b for Figure 2a An enlarged diagram of circle A in the diagram;

[0017] Figure 3a for Figure 2a A bottom view of the first chamber portion of the semiconductor processing device;

[0018] Figure 3b for Figure 2a A top view of the second chamber portion of the semiconductor processing device;

[0019] Figure 4 This is a cross-sectional schematic diagram of the semiconductor processing apparatus in the second embodiment of the present invention;

[0020] Figure 5 for Figure 4 An enlarged diagram of circle B in the diagram;

[0021] Figure 6a for Figure 4 A bottom view of the first chamber portion of the semiconductor processing device;

[0022] Figure 6b for Figure 4 A top view of the second chamber of the semiconductor processing device.

Detailed Implementation Methods

[0023] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic associated with that embodiment that is included in at least one implementation of the invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it necessarily a single or alternative embodiment that is mutually exclusive with other embodiments. "A plurality of" or "several" in this invention means two or more. "And / or" in this invention means "and" or "or".

[0025] First embodiment:

[0026] Please refer to Figures 2a to 3b It shows a schematic diagram of the structure of a semiconductor processing apparatus 100 provided in the first embodiment of the present invention, wherein: Figure 2a This is a cross-sectional schematic diagram of the semiconductor processing apparatus in the first embodiment of the present invention; Figure 2b for Figure 2a An enlarged diagram of circle A in the diagram; Figure 3a for Figure 2a A bottom view of the first chamber portion of the semiconductor processing device; Figure 3b for Figure 2a A top view of the second chamber of the semiconductor processing device.

[0027] Please refer to Figures 2a to 3b The semiconductor processing apparatus 100 includes a first chamber portion 110 and a second chamber portion 120. The first chamber portion 110 includes a first chamber plate 119 and a flange 118 extending from the periphery of the first chamber plate 119. The second chamber portion 120 includes a second chamber plate 129 and a flange 128 extending from the periphery of the second chamber plate 129.

[0028] The first chamber portion 110 is movable relative to the second chamber portion 120 between an open position and a closed position. It should be noted that the movement of the first chamber portion 110 and the second chamber portion 120 is relative. The first chamber portion 110 can be fixed while the second chamber portion 120 moves relative to it; the second chamber portion 120 can be fixed while the first chamber portion 110 moves relative to it; or both the first and second chamber portions 110 can move simultaneously, as long as they can move relative to each other. When the first chamber portion 110 is in the closed position relative to the second chamber portion 120, the flange 118 and the flange 128 cooperate to form a micro-cavity 140 between the first chamber plate 118 and the second chamber plate 128. The semiconductor wafer 400 to be processed can be accommodated within the micro-cavity 140, awaiting subsequent processing. When the first chamber portion 110 is in the open position relative to the second chamber portion 120, the flange 118 separates from the flange 128, and the semiconductor wafer 400 to be processed can be removed or placed into the microchamber 140.

[0029] An annular first channel 116 is formed on the side of the first chamber portion 110 facing the microchamber 140, and a second channel 126 is formed on the side of the second chamber portion 120 facing the microchamber 140. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is housed in the microchamber, the first channel 116 and the second channel 126 together form an edge microprocessing space 130, and the outer edge of the semiconductor wafer 400 housed in the microchamber extends into the edge microprocessing space 130.

[0030] like Figures 2a to 3b As shown, in this embodiment, the first channel 116 and the second channel 126 are annular channels. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 is accommodated in the micro-cavity, the wall surface 117 of the first chamber portion 110 located inside the first channel 116 abuts against the first edge surface of the semiconductor wafer 400 to be processed, and the wall surface 127 of the second chamber portion 120 located inside the second channel 126 abuts against the second edge surface of the semiconductor wafer 400 to be processed. The first channel 116 and the second channel 126 together form a closed, annular outer edge microprocessing space 130, and the outer edge portion of the semiconductor wafer 400 to be processed is accommodated within the edge microprocessing space 130.

[0031] Therefore, in this embodiment, the edge microprocessing space 130 can selectively process the entire outer edge of the semiconductor wafer 400 to be processed.

[0032] Of course, the first channel 116 and the second channel 126 can also be configured as arc-shaped channels with an arc degree less than 360 degrees. In this case, a closed, arc-shaped outer edge microprocessing space 130 with an arc degree less than 360 degrees is formed between the first channel 116 and the second channel 126. Correspondingly, a portion of the arc segment of the outer edge of the semiconductor wafer 400 to be processed is accommodated within the edge microprocessing space 130. Therefore, the edge microprocessing space 130 at this time only performs selective processing on a portion of the arc segment of the outer edge of the semiconductor wafer 400 to be processed.

[0033] The first chamber portion 110 has at least two edge processing through holes 112 extending from the outside to communicate with the edge microprocessing space 130, wherein at least one edge processing through hole serves as a fluid inlet and at least one edge processing through hole serves as a fluid outlet. In this embodiment, four edge processing through holes are provided. Of course, the second chamber portion 120 may also be provided with edge processing through holes communicating with the edge microprocessing space 130.

[0034] In application, the processing fluid can enter the edge microprocessing space 130 through an edge processing via 112. The fluid entering the edge microprocessing space 130 can flow within it, allowing it to contact and process the outer edge portion of the semiconductor wafer 400 contained within the edge microprocessing space 130. The processed fluid can then flow out through another edge processing via 112, or through an edge processing via on the second chamber portion 120 that communicates with the edge microprocessing space 130. During processing, the processing fluid can be continuously or periodically introduced into the edge microprocessing space 130 through an edge processing via 112, allowing the fluid within the edge microprocessing space 130 to flow, thus accelerating the processing speed.

[0035] Of course, the process may be an etching process on the outer edge of the semiconductor wafer 400 to remove the thin film layer on the outer edge portion of the semiconductor wafer 400, or it may be selective cleaning of only the outer edge of the semiconductor wafer 400, etc.

[0036] Taking the etching and removal of the thin film layer on the outer edge of the semiconductor wafer 400 to be processed as an example. (Refer to reference...) Figures 1a to 1d and Figures 2a to 3b As shown, when it is necessary to etch away the thin film layer on the first and second sides of the outer edge of the semiconductor wafer 400 to be processed, a corresponding processing fluid with an corrosive effect on the thin film layer is simply introduced into the edge microprocessing space 130 through an edge processing via 112. The processing fluid flows within the edge microprocessing space 130 and directly contacts the outer edge portion of the semiconductor wafer 400 to be processed. The processing fluid flows along the edge of the semiconductor wafer 400 to be processed, and undergoes a chemical or physical reaction with the wafer surface contained within the edge microprocessing space, thereby continuously etching away the thin film layer 402 on the first edge surface, the second edge surface, and the bevel of the outer edge of the semiconductor wafer 400 to be processed. Figure 1d As shown, after processing, the portion of the thin film layer 402 contained within the edge microprocessing space 130 at the outer edge of the semiconductor wafer 400 is etched away, exposing the first edge surface, the second edge surface, and the outer bevel of the substrate layer 401 at the outer edge of the semiconductor wafer 400. The fluid that has been processed from the semiconductor wafer 400 flows out through other edge processing vias.

[0037] As can be seen, based on the edge microprocessing space 130, the semiconductor processing device 100 in this embodiment only requires a small amount of processing fluid to achieve selective etching of the outer edge of a semiconductor wafer 400 to be processed, which greatly reduces processing costs and production waste volume. Furthermore, compared with dry processing devices in the prior art, the semiconductor processing device 100 in this embodiment has significant advantages such as simple structure, ease of use, and low skill requirements for operators.

[0038] As can be seen, the semiconductor processing apparatus 100 provided in this embodiment can selectively process the outer edge of the semiconductor wafer 400 to be processed. Furthermore, by controlling the flow rate of the processing fluid within the semiconductor wafer 400 to be processed, the amount of processing fluid can be saved while ensuring processing effectiveness. Continuing to refer to... Figures 2a to 2b As shown, in this embodiment, the first chamber portion 110 further has a first recess 115 formed on the inner wall surface of the first chamber portion 110 facing the microchamber, the first recess being located inside the first channel 116. The second chamber portion 120 further has a second recess 125 formed on the inner wall surface of the second chamber portion 120 facing the microchamber, the second recess being located inside the second channel 126. The first recess 115 and the second recess 125 are also annular. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110 and the semiconductor wafer 400 to be processed is housed in the micro-cavity, a portion of the second edge surface of the semiconductor wafer 400 to be processed covers the top of the second recess 125 to form a second inner microspace, and a portion of the first edge surface of the semiconductor wafer 400 to be processed covers the top of the first recess 115 to form a first inner microspace. The first inner microspace and the second inner microspace are located inside the edge microprocessing space 130.

[0039] Correspondingly, the first chamber portion 110 has a first inner processing through-hole communicating with the first recess portion 115, and the second chamber portion 120 has a second inner processing through-hole communicating with the second recess portion 125. When etching the edge of the semiconductor wafer 400 using the edge microprocessing space 130, liquid or gas, such as water or nitrogen, can be introduced into the first recess portion 115 and the second recess portion 125, that is, liquid or gas can be introduced into the first inner microspace and the second inner microspace to prevent liquid in the edge microprocessing space 130 from penetrating inward.

[0040] Similarly, the first recess 115 and the second recess 125 can also be arc-shaped.

[0041] Continue to refer to, for example Figures 2a to 2bAs shown, in this embodiment, when the second chamber portion 120 and the first chamber portion 110 are in the closed position, a micro-chamber 140 is also formed in the middle of them. The second chamber portion 120 has a central processing through hole 123 communicating with the micro-chamber 140, and the first chamber portion 110 has a central processing through hole 113 communicating with the micro-chamber 140.

[0042] For reference Figure 2b As shown, the first chamber portion 110 has a sealing engagement portion 210 located outside the first channel 116, and the second chamber portion 120 has an engagement groove 122 corresponding to the sealing engagement portion 210. The sealing engagement portion 210 includes a guide surface 211 at its end and an inner surface 212 at its inner side. When the second chamber portion 120 is in the closed position relative to the first chamber portion 110, the end of the sealing engagement portion 210 extends into the engagement groove 122, and the end portion of its inner surface 212 seals against the groove wall of the engagement groove 122. The upper end portion of its inner surface 212 forms the outer surface of the outer edge microprocessing space 130. Furthermore, the sealing surface of the inner surface 212 of the sealing joint 210 and the groove wall of the joint groove 122 is located below the outer edge microprocessing space 130, and the sealing surface is perpendicular to the extension direction of the semiconductor wafer 400. This arrangement allows the wall surface 117 of the first chamber 110 located inside the first channel 116 to abut more closely with the first edge surface of the semiconductor wafer 400 to be processed, and the wall surface 127 of the second chamber 120 located inside the second channel 126 to abut more closely with the second edge surface of the semiconductor wafer 400 to be processed, thus preventing the etchant from penetrating inward.

[0043] exist Figure 2b In this embodiment, during the closing of the second chamber portion 120 relative to the first chamber portion 110, the inner surface 212 of the sealing joint portion 210 can achieve center positioning of the semiconductor wafer 400. That is, if the center of the semiconductor wafer 400 deviates from the desired center during placement, the inner edge surface 212 of the sealing joint portion 210 can also be pressed against the semiconductor wafer 140 to correct its center to the desired center. In one example, during edge processing, the center deviation of the semiconductor wafer 400 needs to be no more than 0.2 mm. Using the method of the present invention, the center deviation can be adjusted to within 0.1 mm. The guide surface 211 can guide the sealing joint portion 210 into the engagement groove 122 when the first chamber portion 110 and the second chamber portion 120 are closed. The sealing joint portion 210 can be locked within the engagement groove 122.

[0044] For reference Figure 2aAs shown, the first chamber 110 includes a positioning groove 114, and the second chamber 120 includes a positioning post 124, which allows the first chamber 110 and the second chamber 120 to be correctly positioned when closed. During the closing process of the first chamber 110 and the second chamber 120, the positioning post 124 first engages with the positioning groove 114 to achieve initial positioning, and then the end of the sealing joint 210 extends into the engagement groove 122.

[0045] In one embodiment, the semiconductor processing apparatus 100 of the present invention is used to perform a silicon oxide wafer edge etching process. The specific method may include closing the cavity, HF acid etching, DIW (deionized water) rinsing, IPA (isopropanol) rinsing, nitrogen drying, and opening the cavity. The specific processes of HF acid etching, DIW (deionized water) rinsing, and IPA (isopropanol) rinsing can all be performed according to the procedures described above. Specifically, during the HF acid etching process, liquid or gas, such as water or nitrogen, can be introduced into the first recess 115 and the second recess 125 to prevent liquid from seeping into the edge microprocessing space 130.

[0046] Second Embodiment

[0047] Please refer to Figures 4 to 6b It shows a schematic diagram of the structure of a semiconductor processing apparatus 200 provided in the second embodiment of the present invention, wherein: Figure 4 This is a cross-sectional schematic diagram of the semiconductor processing apparatus in the first embodiment of the present invention; Figure 5 for Figure 4 An enlarged diagram of circle B in the diagram; Figure 6a for Figure 4 A bottom view of the first chamber portion of the semiconductor processing device; Figure 6b for Figure 4 A top view of the second chamber of the semiconductor processing device.

[0048] The semiconductor processing device 200 in the second embodiment has a structure that is mostly the same as that of the semiconductor processing device 100 in the first embodiment. Therefore, the same parts are marked with the same symbols. The main difference between the two is that the sealing joint 310 of the semiconductor processing device 200 and the sealing joint 210 of the semiconductor processing device 100 have some differences in structure.

[0049] like Figure 5 As shown, the first chamber portion 110 has the sealing joint portion 310 located outside the first channel 116, and the second chamber portion 120 has a joint groove 122 corresponding to the sealing joint portion 210.

[0050] The sealing joint 310 includes a guide surface 311 at its end, an inner surface 312 at its upper inner end, and a protrusion 313 at its inner end. When the second chamber 120 is in the closed position relative to the first chamber 110, the end of the sealing joint 310 extends into the engagement groove 122, and its protrusion 313 seals against the groove wall of the engagement groove 122. Its inner surface 312 forms the outer surface of the outer edge microprocessing space 130. The inner surface 312 is still spaced from the outer edge of the semiconductor wafer 400.

[0051] The sealing surface formed by the protrusion 313 of the sealing joint 310 and the groove wall of the joint groove 122 is located below the outer edge microprocessing space 130, and the sealing surface is perpendicular to the extension direction of the semiconductor wafer 400. This arrangement allows the wall surface 117 of the first chamber portion 110 located inside the first channel 116 to abut more closely with the first side surface of the semiconductor wafer 400 to be processed, and the wall surface 127 of the second chamber portion 120 located inside the second channel 126 to abut more closely with the second side surface of the semiconductor wafer 400 to be processed, thus preventing the etchant from penetrating inward.

[0052] exist Figure 2b In one embodiment, during the closing process of the second chamber portion 120 relative to the first chamber portion 110, the bumps 313 of the sealing joint portion 310 can achieve center positioning of the semiconductor wafer 140. That is, if the center of the semiconductor wafer 140 deviates from the desired center when it is placed, the bumps 313 of the sealing joint portion 310 can also correct its center to the desired center by squeezing the semiconductor wafer 140.

[0053] Because there is still a distance between the inner surface 312 and the outer edge of the semiconductor wafer 400, the semiconductor wafer 400 is less likely to be clamped by the sealing joint 310 when the second chamber portion 120 disengages from the first chamber portion 110.

[0054] In another embodiment, the semiconductor wafer 400 may not be centered using the bump 313, meaning the bump 313 will not contact the edge of the semiconductor wafer 400. Instead, the centering of the semiconductor wafer 400 can be achieved using the edge of the wall of the first channel 116.

[0055] The foregoing description has fully disclosed the specific embodiments of the present invention. It should be noted that any modifications made to the specific embodiments of the present invention by those skilled in the art do not depart from the scope of the claims. Accordingly, the scope of the claims is not limited to the specific embodiments described.

Claims

1. A semiconductor processing apparatus, characterized in that, It includes: First chamber section; A second chamber portion movable between an open position and a closed position relative to a first chamber portion, wherein when the second chamber portion is in the closed position relative to the first chamber portion, a micro-chamber is formed between the first chamber portion and the second chamber portion, and a semiconductor wafer can be accommodated in the micro-chamber; when the second chamber portion is in the open position relative to the first chamber portion, the semiconductor wafer can be removed or placed in. The first chamber portion has a first channel, and the second chamber portion has a second channel. When the second chamber portion is in the closed position relative to the first chamber portion and a semiconductor wafer is housed within the microcavity, the first channel and the second channel communicate with each other and together with the edge of the semiconductor wafer to form an edge microprocessing space. The outer edge of the semiconductor wafer housed within the microcavity extends into the edge microprocessing space. This edge microprocessing space communicates with the outside through edge processing vias, and fluid enters or exits the edge microprocessing space through these vias. The first chamber portion has a sealing joint portion located outside the first channel, and the second chamber portion has a joint groove corresponding to the sealing joint portion. The sealing joint includes an inner edge surface located on the inner side. When the second chamber is in the closed position relative to the first chamber, the end of the sealing joint extends into the engagement groove, and the end portion of its inner edge surface seals against the groove wall of the engagement groove. The upper portion of its inner edge surface forms the outer surface of the edge microprocessing space. The end portion of the inner edge surface of the sealing joint and the sealing surface of the groove wall of the joint groove are located below the edge microprocessing space, and the sealing surface is perpendicular to the extension direction of the semiconductor wafer.

2. The semiconductor processing apparatus according to claim 1, characterized in that, The first edge surface, the second edge surface, and the outer bevel surface of the semiconductor wafer are exposed to the edge microprocessing space. One or more of the edge processing vias serve as fluid inlets and one or more of the edge processing vias serve as fluid outlets. The edge microprocessing space is annular or arc-shaped, and the outer edge of the semiconductor wafer extends into the edge microprocessing space. The edge microprocessing space is a closed space and communicates with the outside through edge processing vias. The top surface of the inner wall portion of the first channel abuts against the first edge surface of the semiconductor wafer near the first chamber portion, and the top surface of the inner wall portion of the second channel abuts against the second edge surface of the semiconductor wafer near the second chamber portion.

3. The semiconductor processing apparatus according to claim 1, characterized in that, The first chamber portion further has a first recessed portion formed on the inner wall surface of the first chamber portion facing the microcavity, the first recessed portion being located inside the first channel. The second chamber portion further has a second recessed portion formed on the inner wall surface of the second chamber portion facing the microcavity, the second recessed portion being located inside the second channel. When the second chamber portion is in the closed position relative to the first chamber portion and the semiconductor wafer is accommodated in the microcavity, a portion of the second edge surface of the semiconductor wafer covers the top of the second recessed portion to form a second inner microspace. A portion of the first edge surface of the semiconductor wafer covers the top of the first recessed portion to form a first inner microspace. The first inner microspace and the second inner microprocessing space are located inside the edge microprocessing space. The first chamber portion has a first inner surface processing through-hole communicating with the first recessed portion, and the second chamber portion has a second inner surface processing through-hole communicating with the second recessed portion.

4. The semiconductor processing apparatus according to claim 3, characterized in that, The first and second recesses are annular or arc-shaped. When the edge of the semiconductor wafer is etched using the edge microprocessing space, liquid or gas is introduced into the first and second recesses to prevent liquid in the edge microprocessing space from penetrating inward.

5. The semiconductor processing apparatus according to claim 1, characterized in that, During the closing process of the second chamber relative to the first chamber, the inner edge surface of the sealing joint achieves center positioning of the semiconductor wafer. If the center of the semiconductor wafer deviates from the desired center during placement, the inner edge surface of the sealing joint corrects its center to the desired center by pressing against the semiconductor wafer.

6. The semiconductor processing apparatus according to claim 1, characterized in that, The first chamber includes a positioning groove, and the second chamber includes a positioning post. The positioning post and the positioning groove cooperate to ensure that the first chamber and the second chamber can be correctly positioned when closed.

7. The semiconductor processing apparatus according to claim 1, characterized in that, The semiconductor wafer is centered using the edge of the wall of the first channel.

8. The semiconductor processing apparatus according to claim 1, characterized in that, The sealing joint also includes a guide surface located at the end.

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