Supervision and control-based wafer combination equipment punctual system scheduling method and system

Abstract

The invention discloses a supervision and control-based punctual scheduling method and system for wafer combination equipment, and mainly solves the problems of high probability of blockage, path conflict and low scheduling efficiency during multi-resource parallel operation of the existing wafer combination equipment. According to the implementation scheme, the method comprises the following steps: respectively constructing corresponding automaton models for process units in equipment, and carrying out synchronous splicing according to a real process flow to form an overall model capable of reflecting dynamic behaviors of a system; a corresponding constraint model is established by combining factors such as process sequence constraint, equipment capacity limitation, carrying time constraint and residence time limitation; and the supervision controller continuously judges whether the event to be executed can cause blockage or not, gradually eliminates the blockage by disabling the controllable event, triggers the optimal event according to the priority of the event, and guides the scheduling path to propel and output the optimal scheduling scheme along the optimal direction. According to the method, the overall model capable of being dynamically adjusted is constructed, the event priority and multi-class constraint collaborative optimization scheduling is utilized, the wafer residence time can be remarkably shortened, the overall scheduling efficiency is improved, and the method can be used for operation inspection, evaluation and optimization of an equipment system.

Description

Technical Field

[0001] This invention belongs to the field of scheduling technology, specifically relating to a just-in-time scheduling method and system for wafer assembly equipment, which can be used for the operation inspection, evaluation and optimization of equipment systems. Background Technology

[0002] Scheduling wafer assembly equipment involves allocating wafer processing tasks, determining the sequence of processes, coordinating equipment resources, and monitoring overall progress. Scheduling enables the inspection, evaluation, and optimization of the entire equipment system's operation. Because the wafer manufacturing process involves numerous steps, including robotic arm handling, process module processing, calibration and testing, the units are tightly coupled and highly dependent, requiring extremely high continuity and stability. A delay in any process or a malfunction in any equipment component can lead to an imbalance in the entire processing chain, affecting the system's overall capacity and reliability. Therefore, achieving efficient scheduling of wafer assembly equipment is crucial.

[0003] Typically, wafer fabrication equipment scheduling is a dynamic balancing act, requiring the search for an optimal rhythm between process complexity, uncertainty, and operational dynamism. This involves not only technical challenges at the algorithmic and control levels but also a systems engineering problem. To achieve efficient and stable operation of wafer fabrication equipment, researchers are constantly exploring new scheduling methods and modeling approaches.

[0004] Patent application CN202311633566.3 discloses a "method and system for pre-grouping wafer sets in semiconductor furnace tube processes." This method constructs an intelligent algorithm model to comprehensively evaluate factors such as wafer set arrival and failure times, priorities, and combines these with multi-dimensional characteristics including machine configuration, processing time, waiting time, and batch capacity limitations to intelligently bind wafer sets and generate processing groups. Subsequently, processing groups are assigned to furnace tube machines based on their characteristics, achieving a synergistic goal of maximizing processing volume and minimizing fill wafer usage. While this approach can improve the processing efficiency and stability of furnace tube processes, reduce resource consumption, and optimize overall production quality, it lacks a clear priority and conflict resolution mechanism between multiple objectives, as it simultaneously optimizes processing volume, waiting time, failure rate, and fill wafer usage. This may lead to decision-making instability or difficulty in guaranteeing global optimality in actual operation.

[0005] Patent document with application number "CN202411292489.4" discloses a "multi-agent multi-processing module wafer manufacturing scheduling and control method". It first constructs an optimization model with the objectives of minimizing maximum completion time, total workshop energy consumption, and wafer scrap rate. After initializing processing parameters, it sequentially executes collaborative scheduling strategies for the entry / exit area, transport area, and cooling / temporary storage area to ensure smooth switching of wafers between processing, cooling, and transport stages. Then, by uniformly coordinating the multi-stage scheduling process of the processing area and transport area, it improves the overall operational quality and production efficiency of the wafer manufacturing system. However, this method needs to simultaneously handle multi-objective optimization, cross-area collaborative scheduling, and multi-agent control, resulting in a complex overall model structure that can lead to long solution times or difficulty in real-time application within actual production cycles. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of the prior art by proposing a just-in-time scheduling method and system for wafer assembly equipment based on supervisory control, so as to achieve efficient allocation of wafer processing tasks, optimization of process sequence and coordination of equipment resources, improve the reliability and flexibility of overall scheduling, and reduce the reconfiguration cost of the system due to process adjustments or equipment changes.

[0007] The technical approach to achieve the objective of this invention is as follows: Each process unit is independently modeled and constrained using modular modeling based on Discrete Event System (DES) supervisory control theory, forming a dynamically combinable overall system model. During the modeling phase, the priority of scheduling objectives is clearly defined, and key constraints are processed hierarchically. The system is then comprehensively solved using a supervisory controller, achieving efficient allocation of wafer processing tasks, optimization of process sequence, and coordination of equipment resources. This improves the reliability and flexibility of overall scheduling and allows for rapid reconfiguration during process adjustments or equipment changes, reducing reconfiguration costs.

[0008] Based on the above ideas, the technical solution of the present invention includes:

[0009] 1. A just-in-time scheduling method for wafer assembly equipment based on supervisory control, characterized in that it includes:

[0010] (1) Based on the supervisory control theory, each process unit of the wafer assembly equipment is independently modeled and spliced ​​together according to the equipment operation sequence to form a dynamically adjustable overall model.

[0011] (2) Establish a constraint model based on the constraints of process sequence, equipment capacity, handling and dwell time in wafer assembly equipment scheduling;

[0012] (3) Based on the current overall model and constraint model, repeatedly call the supervisory controller to determine whether the event to be executed will cause the scheduling path to be blocked:

[0013] If the scheduling path is blocked, then execute (4);

[0014] If the scheduling path is non-blocking, the controller is guided to select the optimal scheduling path based on the priority of the scheduling target, ensuring that the overall scheduling process is optimal and the system dwell time is minimized.

[0015] (4) Repeat step (3) to repeatedly judge, select, execute and update the status of the remaining events to be executed until all scheduled tasks are completed.

[0016] Furthermore, in (1), based on the supervisory control theory, each process unit of the wafer assembly equipment is subjected to...

[0017] Independent modeling involves abstracting the process units such as loading / unloading stations, calibration stations, vacuum locks, processing stations, and robotic arms in wafer assembly equipment into their respective automata models based on their discrete event characteristics. Each automata model is a quintuple that includes a set of states, a set of events, an initial state, a marked state, and a set of state transitions.

[0018] Furthermore, the step (1) of assembling the independent models according to the equipment operation sequence is achieved through supervision and control.

[0019] The synchronous integration synthesis method based on control theory combines independently modeled automata in a synchronous and parallel manner according to the wafer processing flow to form an uncontrolled overall model, which can be dynamically adjusted.

[0020] Furthermore, in step (3), based on the current overall model and constraint model, the supervisory controller is called cyclically to determine whether the event to be executed will cause the scheduling path to be blocked. Its implementation includes:

[0021] 3a) Based on a predetermined set of controllable events, the supervisory controller performs the solution operation on the overall model and the constraint model by gradually disabling controllable events for the scheduling path after the execution event, thereby obtaining the scheduling path;

[0022] 3b) Determine if the scheduling path is empty by using an empty language function: if the scheduling path is not empty, it is considered to be in a non-blocking state; otherwise, it is considered to be in a blocking state.

[0023] In step (3), for non-blocking scheduling paths, the controller is guided to select the optimal scheduling path based on the priority of the scheduling target. This is implemented by:

[0024] 3c) Based on scheduling parameters such as dwell time limits, resource utilization efficiency, and critical equipment utilization, establish an event priority set for executable events;

[0025] 3d) Traverse and record all triggerable events in the branching state of the scheduling path to form an independent set describing these branching events;

[0026] 3e) Based on the event priority set, determine the priority of each event in the fork event set in each fork state, identify the highest priority event in each fork state, and mark events with lower priority as events to be deleted.

[0027] 3f) Prune the state transitions corresponding to all events marked as pending deletion to form a unique optimal scheduling path.

[0028] 2. A just-in-time system for wafer assembly equipment based on supervisory control, characterized in that it comprises:

[0029] Wafer input module: Used to realize the input and preparation process of wafers from the loading and unloading position to the inside of the equipment, so as to ensure that the wafers can enter the processing module under the condition of meeting the equipment process requirements;

[0030] Wafer processing module: It is used to perform process processing on the input wafers and to complete the handling and transfer of wafers by means of a robotic arm, so as to ensure that the wafers complete the entire processing process under the specified timing and resource constraints.

[0031] Wafer output module: Used to unload wafers from inside the equipment to the loading / unloading position, ensuring that the wafers can be safely, stably, and without contamination output to the loading / unloading position after all processing steps are completed.

[0032] Constraint Module: Used to uniformly constrain and coordinate key resources and timing conditions during the operation of wafer assembly equipment, so as to ensure that the system operates stably under the premise of meeting process requirements, resource capacity and safety specifications.

[0033] Compared with the prior art, the present invention has the following advantages:

[0034] Firstly, by independently modeling each process module, this invention enables the overall structure to have higher reconfigurability, making model maintenance and expansion more convenient, improving the reliability and flexibility of overall scheduling, and reducing the reconfiguration cost of the system due to process adjustments or equipment changes.

[0035] Secondly, this invention achieves efficient allocation of wafer processing tasks and optimization of process sequence by setting the priority of scheduling targets and hierarchically managing key resources and timing constraints;

[0036] Third, by introducing time constraints based on Just-in-Time (JIT), this invention can effectively avoid wafers staying between process nodes for too long, thus preventing process failures caused by excessive dwell time.

[0037] Fourth, by constructing valve mutual exclusion constraints, this invention ensures that only a single valve is allowed to open at any given time in the shared vacuum system, thereby effectively avoiding vacuum fluctuations and process interruptions caused by concurrent valve opening, and ensuring process safety and gas path stability. Attached Figure Description

[0038] Figure 1 This is a flowchart illustrating the implementation of the just-in-time scheduling method for wafer assembly equipment based on supervisory control, as described in this invention.

[0039] Figure 2 This is a structural diagram of the wafer assembly equipment used in the method of this invention;

[0040] Figure 3 This is a basic unit structure diagram of the DES model established in the method of this invention;

[0041] Figure 4 This is a DES model diagram of the processing technology constructed in the method of this invention;

[0042] Figure 5 This is a DES model diagram of the process sequence restriction processing position in this invention;

[0043] Figure 6 This is a model diagram of the DES (Device-Assisted System) for process sequence limitation calibration in this invention;

[0044] Figure 7 This is a diagram of the DES model for handling time constraints in this invention;

[0045] Figure 8 This is a model diagram of the valve mutual exclusion specification (DES) in this invention;

[0046] Figure 9 This is a block diagram of the just-in-time scheduling system for wafer assembly equipment based on supervisory control, as described in this invention. Detailed Implementation

[0047] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, other embodiments obtained by those skilled in the art without creative effort should all fall within the protection scope of the present invention.

[0048] It should be noted that the step numbers in the specification and claims of this invention are only for the purpose of clearly describing the embodiments of this invention and facilitating understanding, and their order is not limited.

[0049] Example 1: Just-in-Time Scheduling Method for Wafer Assembly Equipment Based on Supervisory Control

[0050] Reference Figure 1 The implementation steps of this example include:

[0051] Step 1: Construct an overall model of the dynamically adjustable wafer assembly equipment.

[0052] The wafer assembly equipment is a manufacturing equipment that integrates wafer loading, unloading, calibration, vacuum conversion, process processing, and handling functions. It is used to realize the entire processing flow of wafers from input, processing, to output across multiple process stages. Specifically, it includes five parts: loading / unloading positions LP1, LP2, and LP3; robotic arms TM1 and TM2; calibration position AL; and processing modules PM1, PM2, PM3, PM4, PM5, and PM6. Figure 2 As shown.

[0053] This step includes:

[0054] 1.1) Based on supervised control theory, each process unit of the wafer assembly equipment is independently modeled:

[0055] The aforementioned supervisory control theory is a class of formal control methods used for controllability analysis and behavioral constraints of discrete event systems (DES).

[0056] The discrete event characteristic refers to the fact that during the operation of wafer assembly equipment, its state changes are triggered by events that are instantaneous and discrete, and there is no continuous time evolution process between events. This characteristic is manifested as follows: the system only updates its state when an event occurs, while the system state remains unchanged when no event is triggered.

[0057] Based on the theory of supervised control, each process unit in the wafer assembly equipment is independently modeled. This method transforms the operation process of the process unit into a formalized automaton structure in a systematic way, according to the operation events triggered by the process unit during actual operation, resource occupation patterns and state transition rules.

[0058] Reference Figure 3 In one instance, this step is implemented as follows:

[0059] 1.1.1) The executable actions of the process unit are processed as events. The system time is represented by the event "tick". That is, each trigger of the "tick" event represents the system time advancing by 1 second.

[0060] Within this discrete time framework, the discrete operations in the equipment, such as wafer picking, wafer placement, valve switching, and processing start / end, are categorized into two types of events: "ev" and "ev_fn," and then integrated into a single event set. ,in:

[0061] For the loading and unloading process unit, its process operation is discretized into eight major events: wafer loading start event, wafer loading end event, wafer unloading start event, wafer unloading end event, loading and unloading valve opening start event, loading and unloading valve opening end event, loading and unloading valve closing start event, and loading and unloading valve closing end event.

[0062] For the calibration process unit, the process operation is discretized into calibration start event and calibration end event;

[0063] For the vacuum lock process unit, its process operation is discretized into 12 major events: vacuuming start event, vacuuming end event, inflation start event, inflation end event, vacuum lock atmospheric side valve opening start event, vacuum lock atmospheric side valve opening end event, vacuum lock atmospheric side valve closing start event, vacuum lock atmospheric side valve closing end event, vacuum lock vacuum side valve opening start event, vacuum lock vacuum side valve opening end event, vacuum lock vacuum side valve closing start event, and vacuum lock vacuum side valve closing end event.

[0064] For a machining station process unit, its process operation is discretized into six major events: machining station start event, machining station end event, machining station valve opening start event, machining station valve opening end event, machining station valve closing start event, and machining station valve closing end event.

[0065] For the robotic arm process unit, its process operations are discretized into six major events: robotic arm wafer pick-up start event, robotic arm wafer pick-up end event, robotic arm wafer placement start event, robotic arm wafer placement end event, robotic arm movement start event, and robotic arm movement end event.

[0066] 1.1.2) Based on the occupation and release status of resources such as wafers, robotic arms, chamber states, and vacuum environments at the time of the event, the possible operating conditions of the equipment at any given moment are organized to define a set of states. ,in:

[0067] For the loading and unloading process unit, its process state set is defined as including: wafer loading start state, wafer loading complete state, wafer unloading start state, wafer unloading complete state, loading and unloading valve opening start state, loading and unloading valve fully open state, loading and unloading valve closing start state, and loading and unloading valve fully closed state.

[0068] For a calibration process unit, its process state set is defined to include: calibration start state and calibration completion state;

[0069] For a vacuum lock process unit, its process state set is defined as including: vacuuming start state, vacuuming complete state, inflation start state, inflation complete state, vacuum lock atmospheric side valve opening start state, vacuum lock atmospheric side valve opening complete state, vacuum lock atmospheric side valve closing start state, vacuum lock atmospheric side valve closing complete state, vacuum lock vacuum side valve opening start state, vacuum lock vacuum side valve opening complete state, vacuum lock vacuum side valve closing start state, and vacuum lock vacuum side valve closing complete state.

[0070] For a machining station process unit, its process state set is defined as including: machining start state, machining complete state, machining station valve open start state, machining station valve open complete state, machining station valve close start state, and machining station valve close complete state.

[0071] For a robotic arm process unit, its process state set is defined as including: robotic arm wafer picking start state, robotic arm wafer picking completion state, robotic arm wafer placement start state, robotic arm wafer placement completion state, robotic arm movement start state, and robotic arm movement completion state.

[0072] 1.1.3) Based on the above-defined event set and state set, analyze the executableness of each event in a specific state and the changes in system resource allocation after the event occurs, clarify the transition conditions of the system from one state to another, and construct each state transition function accordingly. That is, the process of transitioning from one state to another through an event;

[0073] For a loading / unloading process cell, its state transition function refers to the process by which the initial state reaches the marked state through wafer loading-related events. In this example, the state transition function for each process cell is... It can be represented as:

[0074] ,

[0075] in, This represents the state set of the i-th process unit. Let i represent the event set of the i-th process unit. [1,5]; For example, for the first loading / unloading process unit, its state transition function is expressed as: ;

[0076] 1.1.4) The initial state is used to characterize the initial operating state of the process unit at the start of modeling; that is, for each process unit, its initial state is represented as... ;

[0077] 1.1.5) The marked state is used to characterize the target state or termination state that a process unit is expected to reach after completing a predetermined operation. That is, for each process unit, its marked state is represented as follows: ;

[0078] Through steps 1.1.1) to 1.1.5) above, the actual operating logic of the process unit can be completely mapped to an automaton model described by a quintuple:

[0079] ,

[0080] in, Represents the automaton model for the i-th process unit;

[0081] 1.2) These independent automata models are spliced ​​together using the synchronization product method of supervised control theory:

[0082] The synchronous product method in the supervisory control theory refers to a model combination method used in the discrete event system modeling framework to achieve synchronous execution of multiple independent automata models according to their shared events and parallel advancement according to their non-shared events.

[0083] The synchronous product method based on supervisory control theory is used to splice together the independent automata. It combines the automata according to the principles of synchronization and parallelism based on the shared and non-shared events involved in the actual wafer processing flow. That is, for shared events in which multiple process units participate, the synchronous product requires that the relevant automata must undergo state transitions synchronously under the trigger of the same event.

[0084] The specific implementation of this step in one instance includes:

[0085] First, perform synchronous integration operations on the automatic machines of the relevant process units according to the actual process flow;

[0086] Then, the event set is analyzed by the supervisory controller, and events that participate in multiple process units are identified as shared events, while the remaining events are identified as non-shared events.

[0087] Finally, the supervisory controller splices the relevant automata based solely on the shared events.

[0088] For example, when the robotic arm performs a wafer retrieval operation at the loading / unloading position, it needs to synchronize the loading / unloading position automaton and the robotic arm automaton. The supervisory controller will regard the "loading / unloading position valve opening / closing event" as a shared event between the two automatons. The loading / unloading position automaton uses this event as its ending event, and the robotic arm automaton uses this event as its starting event. Through synchronization, the two automatons will simultaneously undergo state transitions when the shared event is triggered. After the loading / unloading position completes the "loading / unloading position valve opening / closing event", the robotic arm executes the "robotic arm wafer retrieval start event", realizing the robotic arm's collaborative wafer retrieval operation at the loading / unloading position, that is, completing the splicing of the loading / unloading position and the robotic arm automaton.

[0089] For example, when the robotic arm performs a wafer placement operation at the calibration position, the robotic arm automaton and the calibration position automaton need to undergo synchronization integration. The supervisory controller treats the "robotic arm wafer placement completion event" as a shared event between the two automata. The robotic arm automaton uses this event as its end event, and the calibration position automaton uses it as its start event. Through synchronization integration, both automata undergo state transitions simultaneously when this shared event is triggered. Only after the robotic arm completes the "robotic arm wafer placement completion event" can the calibration position automaton execute the "calibration start event," realizing the robotic arm's coordinated wafer placement operation at the calibration position, thus completing the connection between the robotic arm and the calibration position automaton.

[0090] The assembly of the automata in the remaining process flows also follows the same synchronization mechanism. The assembly of the automata is achieved by triggering cross-unit state collaboration through shared events. The local states of each process unit constitute the global state space of the whole system. At the same time, it accurately expresses the cross-unit collaborative actions between units, thereby forming an uncontrolled overall model that can be used for subsequent scheduling and solving.

[0091] The uncontrolled overall model, such as Figure 4 As shown, its state set Used to characterize the current state of each of the n groups of automata participating in the splicing, “ev_n” and “ev_n_fn” represent the start event and end event of the nth automaton, respectively. The event “tick” self-loop indicates that the number of events “tick” can be increased or decreased according to the actual situation.

[0092] Step 2: Establish a scheduling constraint model for the wafer assembly equipment.

[0093] The constraints in the wafer assembly equipment scheduling refer to a class of restrictions that must be followed to ensure the safety of equipment operation, the correctness of process execution, and the mutual exclusivity of resource use during the process of wafers flowing between process units such as loading and unloading positions, calibration positions, vacuum locks, processing positions, and robotic arms.

[0094] This step includes:

[0095] 2.1) Construct process sequence constraints.

[0096] By pre-setting strict pre- and post-processing state relationships in the automata models of each process unit, the wafer cannot proceed to the next processing stage until the current process step is completed; this includes:

[0097] 2.1.1) Reference Figure 5 Establish a sequential constraint automaton for the calibration position process unit:

[0098] Only when the current wafer completes the corresponding calibration bit start event set End of calibration bit event set Only after that can the next processing stage be entered. ;

[0099] If the calibration bit end event set has not been completed, the system remains in the processing state. This ensures that the wafers are transferred strictly according to the established process sequence;

[0100] 2.1.2) Reference Figure 6 Establish a sequential constraint automaton for the processing unit:

[0101] Only when the current wafer completes the corresponding processing bit start event set Processing station end event set Only after that can the process proceed to the next stage. ;

[0102] If the processing end event has not yet been completed, the system remains in the processing state. This ensures that the wafers are transferred strictly according to the established process sequence;

[0103] 2.2) Constructing equipment capacity constraints:

[0104] By presetting the upper limit of the number of wafers that the loading and unloading position can accommodate in the system's input parameters, and using this capacity parameter as a judgment condition in the automaton model or scheduling logic, all events related to "wafer placement and wafer retrieval" must first check whether the current occupied quantity has reached the upper or lower limit. If the set capacity is exceeded, the system will automatically disable the corresponding event. Through this parameterized capacity upper limit-based checking mechanism, the constraint control of equipment capacity can be achieved.

[0105] 2.3) Reference Figure 7 Establish transportation time constraints:

[0106] When the robotic arm executes the "robotic arm wafer pick-up start event", the time-constrained automaton enters the handling occupancy state. During this period, the supervisory controller will prevent other wafers from occupying the robotic arm, thereby preventing the robotic arm from performing tasks before the handling is completed.

[0107] After the "robotic arm wafer placement completion event" occurs, the time-constrained automated handling machine enters the handling idle state. The robotic arm regained its ability to accept new handling tasks;

[0108] This constraint enables the full locking and releasing of robotic arm resources, thereby avoiding task conflicts, event overlaps, and resource competition.

[0109] 2.4) Constructing residency time constraints:

[0110] This is achieved through time-event accumulation: after a wafer completes processing at a certain process node, the system accumulates the dwell time using time events. During the accumulation process, the system continuously compares the current dwell time with the preset maximum allowable dwell time;

[0111] When the cumulative time has not exceeded the maximum allowable dwell time, the dwell flag is kept at 0, indicating that the wafer is still within the allowable dwell window and can continue to execute the event to enter the next process step;

[0112] Once the accumulated time exceeds the set limit, the system will set the dwell flag to 1, indicating that the wafer has timed out. The supervisory controller will then prohibit the triggering of events related to the next processing stage, thereby preventing the wafer from failing due to excessive dwell time.

[0113] By continuously accumulating time events and switching flags, real-time monitoring and over-limit constraints on dwell time can be achieved.

[0114] 2.5) Reference Figure 8 Construct mutual exclusion constraints for valves:

[0115] Only when the current channel completes the corresponding valve closure event set will the event end. Afterwards, the valve mutual exclusion constraint automatic machine enters... Only when the state is met can other channels within the same vacuum system trigger the valve opening start event set. ;

[0116] If the opening and closing cycle of the previous channel valve has not yet been completed, that is, when the valve mutual exclusion constraint automatic machine is in a state of... When in a certain state, the system automatically prevents other channel valves from performing opening events, thereby ensuring that the vacuum environment remains stable and avoiding vacuum failure and chamber contamination caused by multiple valves opening simultaneously.

[0117] Step 3: Establish a priority-oriented optimal scheduling path decision.

[0118] Terminology Explanation:

[0119] A blocked path is a scheduling path from the initial state to the marked state.

[0120] A controllable event set refers to a set of events that can be intervened upon by a supervisory controller through enabling or disabling.

[0121] The fork event set is a set of events established for fork states that occur in the scheduling path.

[0122] This step includes:

[0123] 3.1) The supervisory controller solves for the scheduling path based on the gradual disabling of controllable events:

[0124] The supervisory controller uses the overall model and constraint model, as well as a pre-divided set of controllable events, to sequentially disable controllable events that block the path, gradually reducing the number of blocked paths, thereby solving for the final executable scheduling path;

[0125] 3.2) Determining blocking paths based on empty language functions:

[0126] The supervisory controller automatically traverses the executable scheduling path automaton structure, checking whether there exists a feasible path starting from the initial state and eventually reaching the marked state:

[0127] If the traversal results indicate that there is at least one path that can reach the marked state, then the path to be scheduled is non-blocking, and steps 3.3) and 3.4) are executed.

[0128] If no path from the initial state to the marked state is found in the traversal results, the path to be scheduled is blocked.

[0129] Perform step 4;

[0130] 3.3) Construct an event priority set based on key scheduling parameters:

[0131] Analyze the key factors affecting overall scheduling efficiency, determine the optimal execution order of each event, and construct an event priority set accordingly;

[0132] By using the event priority set as the basis for scheduling optimization decisions, the supervisory controller can select the better execution event from the candidate events according to the priority, thereby continuously optimizing the scheduling path, reducing path redundancy and waiting time, and improving the overall system's operating efficiency and stability.

[0133] 3.4) Constructing a set of fork events:

[0134] First, identify all branching states in the scheduling path that have multiple triggerable events;

[0135] Then, the events in each branching state are traversed and recorded one by one, and these events are summarized into an independent set;

[0136] 3.5) Filtering the set of fork events based on the priority event set:

[0137] During the scheduling process, each established fork event set is traversed item by item according to the established event priority set. By judging and comparing the priority of each event, the highest priority event in each fork state is determined.

[0138] Mark all events with a lower priority than this highest priority as events to be deleted;

[0139] 3.6) Optimal scheduling path generation:

[0140] All events marked as pending deletion are deleted to eliminate redundancy or suboptimal paths. Ultimately, a unique optimal scheduling path consisting of the highest priority events is retained in the original scheduling graph, thus ensuring that only the highest priority event is executed in each branching state, guaranteeing the efficiency of scheduling execution.

[0141] Step 4: Determine and disable the loop for controllable events blocking the path.

[0142] 4.1) Controllability assessment and handling of blocking events:

[0143] The supervisory controller compares the events to be executed on the blocked path with a predefined set of controllable events: if the event to be executed belongs to the set of controllable events, then 4.2 is executed.

[0144] Otherwise, it is an uncontrollable event, and 4.3 will be executed.

[0145] 4.2) The supervisory controller performs a disable operation on the event in the blocked path to eliminate the blockage;

[0146] 4.3) Loop through pending events:

[0147] The supervisory controller selects the next pending event from the remaining unprocessed pending events; and uses this event as the new judgment object, repeating steps 4.1) and 4.2) until all pending events have been judged and processed, thereby realizing the deletion of events in the blocked path one by one.

[0148] 4.4) Synchronously update the status of the scheduling path to ensure that blocking events in the path are effectively eliminated and that the scheduling status remains consistent and stable.

[0149] Example 2: Just-in-Time Scheduling System for Wafer Assembly Equipment Based on Supervisory Control

[0150] Reference Figure 9The just-in-time (JIT) scheduling system platform shown in this example is based on wafer assembly equipment and is divided into three main parts: input, processing, and output. It includes: wafer input module 1, wafer processing module 2, wafer output module 3, and constraint module 4. Wafer input module 1 includes a loading / unloading position input submodule 11, a calibration position submodule 12, a robotic arm input submodule 13, and a vacuum lock input submodule 14. Wafer output module 3 includes a vacuum lock output submodule 31, a robotic arm output submodule 32, and a loading / unloading position output submodule 33. Constraint module 4 includes a JIT time constraint submodule 41, a robotic arm constraint submodule 42, a processing position constraint submodule 43, a calibration position constraint submodule 44, and a valve mutual exclusion constraint submodule 45. The working principle of the entire system is as follows:

[0151] The wafer input module 1 is used to realize the input and preparation process of the wafer from the loading / unloading position to the inside of the equipment. Wherein:

[0152] The loading / unloading input submodule 11 executes the wafer loading process and outputs the wafer to the robotic arm input submodule 13; the robotic arm input submodule 13 transports the wafer and outputs the wafer to the calibration submodule 12 to perform wafer attitude calibration operation, then returns to the robotic arm input submodule 13 to transport the wafer and outputs the wafer to the vacuum lock input submodule 14; the vacuum lock input submodule 14 converts the atmospheric environment to a vacuum environment and outputs the wafer to the wafer processing module 2.

[0153] The wafer processing module 2 is used to perform process processing on the input wafer and to complete the handling and transfer of the wafer by means of a robotic arm, so as to ensure that the wafer completes the entire processing process under the specified timing and resource constraints and outputs it to the wafer output module 3.

[0154] The wafer output module 3 is used to unload wafers from inside the equipment to the loading / unloading position, ensuring that the wafers can be safely, stably, and without contamination output to the loading / unloading position after completing all processing steps. Wherein:

[0155] The vacuum lock output submodule 31 converts the vacuum environment into an atmospheric environment and outputs the wafer to the robotic arm output submodule 32. The robotic arm output submodule 32 then transports the wafer to the loading and unloading position output submodule 33 to store the processed wafer.

[0156] The constraint module 4 is used to uniformly constrain and coordinate key resources and timing conditions during the operation of the wafer assembly equipment, ensuring stable system operation while meeting process requirements, resource capacity, and safety specifications. Specifically:

[0157] The just-in-time constraint submodule 41 is used to limit the dwell time of the wafer at the processing station in the wafer processing module 2;

[0158] The robotic arm constraint submodule 42 is used to impose time and occupancy restrictions on the handling process of the robotic arm input submodule 13 and the robotic arm output submodule 32;

[0159] The processing position constraint submodule 43 is used to constrain the wafer processing sequence of each processing position in the wafer processing module 2;

[0160] The calibration bit constraint submodule 44 is used to restrict the wafer calibration sequence of the calibration bits in the calibration bit submodule 12;

[0161] The valve mutual exclusion constraint submodule 45 is used to implement mutual exclusion restrictions on the valve opening behavior of the shared vacuum system in the wafer processing module 2.

[0162] It should be noted that the above functional modules can be implemented, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, they can be implemented, in whole or in part, as program instruction products. A program instruction product includes one or a set of program instructions. When the program instructions are loaded and executed on a computer, the described process or function is generated, in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The program instructions can be stored in a computer-readable and writable storage medium, or transferred from one computer's readable and writable storage medium to another.

[0163] The direct coupling or communication connections between the modules shown or discussed in this embodiment can be achieved through indirect coupling or communication connections via interfaces, devices, or modules. The various functional modules and sub-modules in this embodiment can dynamically reside within a single processing unit, or each module can exist physically independently, or two or more modules can dynamically reside within a single processing unit. When these dynamic components are implemented as software functional modules and sold or used as independent products, they can also be stored in a computer-readable and writable storage medium. This storage medium can be a memory, disk, or optical disc, etc.

[0164] The effects of this invention can be further illustrated by the following simulation results:

[0165] I. Simulation Conditions

[0166] For two adjacent wafers of LP1, execute the processing path [LP1-AL-LLA-PM2].

[0167] Each processing station can only process one wafer per processing cycle;

[0168] The processing time for each process operation is fixed;

[0169] The robotic arm takes the same amount of time to load and unload wafers.

[0170] Each vacuum lock has a storage capacity of exactly one wafer;

[0171] II. Simulation Content and Results

[0172] Under the above simulation conditions, the wafer assembly equipment was scheduled on time using the method of the present invention, and the scheduling path results are shown in Table 1 and Table 2.

[0173] Table 1. Partial scheduling path results for wafer 1 according to the present invention.

[0174]

[0175] Table 2. Partial scheduling path results for wafer 2 according to the present invention.

[0176]

[0177] Tables 1 and 2 detail the partial flow sequence of the present invention among various process modules.

[0178] As can be seen from the scheduling paths Tables 1 and 2, the execution time difference between the event “LP1_wf_1_LP_open_door” (start of valve opening for wafer 1 at loading / unloading position) and the event “LP1_wf_2_LP_open_door” (start of valve opening for wafer 2 at loading / unloading position) is only 29 seconds. That is, the processing start time interval between two adjacent wafers is 29 seconds. Compared with the waiting and blocking phenomena that are prone to occur in traditional scheduling methods, the present invention can improve the overall scheduling efficiency while ensuring process continuity.

Claims

1. A Just-In-Time scheduling method for a supervised control based wafer cluster tool, characterized in that, Comprise: (1) Based on the theory of supervisory control, each process unit of the wafer assembly equipment is independently modeled, and the independent models are spliced according to the running order of the equipment to form a dynamically adjustable overall model; (2) Based on the constraints of process sequence, equipment capacity, handling and residence time in the scheduling of wafer assembly equipment, a constraint model is established; (3) According to the current overall model and constraint model, the supervisory controller is called cyclically to determine whether the to-be-executed event will cause the scheduling path to be blocked: If the scheduling path is blocked, execute (4); If the scheduling path is not blocked, combine the priority of the scheduling target to guide the controller to select the optimal scheduling path to ensure that the overall scheduling process is optimal and the system residence time is minimized; (4) Repeat steps (3) for the remaining to-be-executed events to repeat the judgment, selection, execution and state update, Until all scheduling tasks are completed.

2. The method of claim 1, wherein: In the (1), based on the theory of supervisory control, each process unit of the wafer assembly equipment is independently modeled, the loading and unloading sites, calibration sites, vacuum locks, processing sites, and mechanical arms in the wafer assembly equipment are abstracted into their own automaton models according to their discrete event characteristics, and each automaton model is a five-tuple including a state set, an event set, an initial state, a marked state, and a state transition set; In the (1), the independent models are spliced according to the running order of the equipment, which is to combine the independently modeled automata in parallel according to the wafer processing flow by the synchronous composition method of the supervisory control theory to form an uncontrolled overall model, i.e. a dynamically adjustable overall model. The (2) establishes a constraint model based on the constraints of process sequence, equipment capacity, handling and residence time in the scheduling of wafer assembly equipment, and its implementation includes: Process sequence constraint: the precedence and succession relationship of processing sites and calibration sites is established respectively, 3. The method of claim 1, wherein, It is stipulated that only after the current wafer completes the corresponding process step, the next wafer can enter the next processing link; Equipment capacity constraint: set the occupancy and release rules for the capacity of the loading and unloading sites, prohibit events from triggering when the number of accommodated wafers exceeds the maximum capacity, to achieve safety and controllability of resource use; Handling time constraint: define the state of resource occupation of the mechanical arm during the execution of a handling task, and prohibit the triggering of new handling events before the state is released, to avoid handling conflicts; Residence time constraint: set the maximum allowed time for the residence time of wafers after completing processing or operation at any process node, to prevent process failure due to excessive residence of wafers; Valve mutual exclusion constraint: set mutual exclusion opening rules for the channel valves of the shared vacuum system to prevent multiple valves from being opened simultaneously, which may cause chamber contamination, vacuum failure or process interruption. The (3) according to the current overall model and constraint model, Cyclically call the supervisory controller to determine whether the to-be-executed event will cause the scheduling path to be blocked, which includes:

4. The method of claim 1, wherein, 3a) The supervisory controller performs solving operations on the overall model and the constraint model by gradually disabling controllable events for the scheduling path after the execution event, to obtain the scheduling path; ​ ​ 3b) judging whether the dispatch path is empty by empty language function: If the dispatch path is not empty, the dispatch path is identified as non-blocking state; Otherwise, the dispatch path is identified as blocking state.

5. The method of claim 1, wherein, For the non-blocking dispatch path in the (3), the controller selects the optimal dispatch path in combination with the priority of the dispatch target, and the implementation includes: 3c) establishing an event priority set for the executable event according to the scheduling parameters such as residence time limit, resource occupation efficiency and key equipment utilization; 3d) defining a bifurcation event set, i.e. traversing and recording all triggerable events in the dispatch path under the bifurcation state to form an independent set describing the bifurcation events of the state; 3e) determining the highest priority event of each bifurcation state and marking the events below the priority as to-be-deleted events based on the event priority set and the priority determination of the events in the bifurcation event set in each bifurcation state; 3f) pruning the states corresponding to the to-be-deleted events to finally form a unique optimal dispatch path.

6. The method of claim 1, wherein, For the repeated judgment, selection, execution and state update of the remaining to-be-executed events in the (4), the implementation includes: 4a) the supervisory controller judges whether the to-be-executed event appearing on the blocking path belongs to a controllable event: If the to-be-executed event is determined to be a controllable event, the related events in the blocking path are executed by disabling operation; Otherwise, the to-be-executed event cannot be eliminated by disabling operation, and 4b) is executed; 4b) the supervisory controller continues to select the next to-be-executed event from the remaining to-be-executed events for judgment; 4c) repeating 4a) and 4b) until there is no controllable event that can continue to be disabled, and the supervisory controller synchronously updates the state of the dispatch path.

7. A supervisory control-based wafer cluster tool just-in-time system, characterized by, It includes: Wafer input module: used to realize the input and preparation process of wafer from loading and unloading site to internal device to ensure that the wafer can enter the processing module under the condition of meeting the process requirements of the device; Wafer processing module: used to execute process processing on the input wafer, and complete the handling of wafer pick and place and transmission through the mechanical arm to ensure that the wafer completes the whole processing process under the specified time sequence and resource constraints; Wafer output module: used to unload the wafer from the internal device to the loading and unloading site to ensure that the wafer can be safely, stably and non-polluted output to the loading and unloading site after completing the whole processing process; Constraint module: used to uniformly constrain and coordinate the key resources and time sequence conditions in the running process of wafer assembly device to ensure that the system runs stably under the premise of meeting the process demand, resource capacity and safety specification.

8. The system of claim 7, wherein, The wafer input module includes: Loading and unloading site input submodule, used to realize the loading process of wafer; Calibration site submodule, used to realize the calibration operation process of wafer; Mechanical arm input submodule, used to realize the process of moving wafer from loading and unloading site to other devices in atmospheric environment; Vacuum lock input submodule, used to realize the conversion process of vacuum environment.

9. The system of claim 7, wherein, The wafer output module includes: Vacuum lock output submodule, used to realize the conversion process of atmospheric environment; Mechanical arm output submodule, used to realize the process of moving wafer from other devices to loading and unloading site in atmospheric environment; The loading and unloading site output sub-module is configured to implement the wafer unloading process.

10. The system of claim 7, wherein, The constraint module comprises A just-in-time constraint sub-module is configured to limit the maximum residence time of the wafer between process nodes, so as to ensure the process stability. A mechanical arm constraint sub-module is configured to prevent the mechanical arm path conflict and repeated occupation, and ensure the carrying safety. A processing site constraint sub-module is configured to limit the processing site to process only one wafer at any time, so as to prevent the processing conflict. A calibration site constraint sub-module is configured to limit the calibration site resource sharing, so as to avoid the conflict caused by the simultaneous occupation of multiple mechanical arms. A valve mutual exclusion constraint sub-module is configured to prevent the valves of the shared vacuum system from being opened simultaneously, so as to ensure the process safety and the air path stability.

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