Image sensing device

Abstract

The present disclosure relates to an image sensing device including: an upper substrate configured to include a pixel region and a first peripheral region located outside the pixel region, the pixel region including unit pixels configured to generate electrical signals by conversion of incident light; a lower substrate configured to include a logic region and a second peripheral region located outside the logic region, the logic region coupled to receive the electrical signals from the unit pixels and configured to generate an image based on the electrical signals from the unit pixels; a light receiving element disposed on the upper substrate and configured to transmit the incident light to the pixel region; an insulating layer disposed between the upper substrate and the lower substrate; a light receiving alignment mark disposed in the first peripheral region and configured to assist positioning of the light receiving element; and an alignment pattern disposed between the first peripheral region and the second peripheral region and located in the insulating layer. The alignment pattern is configured to absorb light used to measure the light receiving alignment mark.

Description

Technical Field

[0001] The technology and implementation disclosed in this patent document generally relate to an image sensing device. Background Technology

[0002] Image sensing devices are used in electronic devices to convert optical images into electrical signals. With recent advancements in the automotive, medical, computer, and communications industries, the demand for highly integrated, higher-performance image sensors is rapidly increasing in various electronic devices such as digital cameras, camcorders, personal communication systems (PCS), video game consoles, surveillance cameras, medical miniature cameras, and robots. Summary of the Invention

[0003] Various embodiments of the disclosed technology relate to an image sensing device that includes alignment marks configured to aid in the positioning of certain elements. In some implementations, the alignment marks can be positioned freely regardless of the position of a lower pattern included in the image sensing device.

[0004] According to one embodiment of the disclosed technology, an image sensing device may include: an upper substrate configured to include a pixel region and a first peripheral region located outside the pixel region, the pixel region including a unit pixel configured to generate an electrical signal by converting incident light; a lower substrate configured to include a logic region and a second peripheral region located outside the logic region, the logic regions being connected to receive the electrical signal from the unit pixel and configured to generate an image based on the electrical signal from the unit pixel; a light receiving element disposed on the upper substrate and configured to transmit incident light to the pixel region; an insulating layer disposed between the upper and lower substrates; a light receiving alignment mark disposed in the first peripheral region and configured to assist in the positioning of the light receiving element formed on a first surface of the upper substrate in the pixel region; and an alignment pattern disposed between the first and second peripheral regions and located in the insulating layer. The alignment pattern is configured to absorb light used for measuring the light receiving alignment mark.

[0005] According to another embodiment of the disclosed technology, an image sensing device may include: a semiconductor substrate configured to include a pixel region and a peripheral region outside the pixel region, the pixel region including a plurality of photoelectric conversion elements configured to generate electrical signals by converting light; a plurality of light receiving elements formed on a first surface of the semiconductor substrate and configured to transmit incident light to the photoelectric conversion elements; an insulating layer disposed on a second surface opposite to the first surface; a light receiving alignment mark disposed in the peripheral region and configured to assist in the positioning of the light receiving elements; and an alignment pattern formed in the insulating layer to overlap with the light receiving alignment mark. The alignment pattern includes a plurality of dotted patterns disposed in different sublayers of the insulating layer.

[0006] It should be understood that the foregoing general description of the disclosed technology and the following detailed description are illustrative and explanatory, and are intended to provide further explanation of the claimed disclosure. Attached Figure Description

[0007] Figure 1 This is a schematic diagram illustrating an exemplary layout of a stacked image sensing device based on some implementations of the disclosed technology.

[0008] Figure 2 This is a schematic diagram illustrating an exemplary layout of an image sensing device based on some implementations of the disclosed technology.

[0009] Figure 3 This illustrates some implementation methods based on the disclosed technology. Figure 1 The cross-sectional view of an example image sensing device shown by line X-X'.

[0010] Figure 4 This illustrates some implementation methods based on the disclosed technology. Figure 1 The image sensing device shown is a cross-sectional view of an example image sensing device captured by line Y-Y'.

[0011] Figure 5A This is a schematic diagram illustrating an example of the layout structure of an upper dummy pattern in an aligned dummy pattern based on some implementations of the disclosed technology.

[0012] Figure 5B This is a schematic diagram illustrating an example of the layout structure of a lower dummy pattern in an aligned dummy pattern based on some implementations of the disclosed technology.

[0013] Figure 6 This is a schematic diagram illustrating an example of an upper dummy pattern and a lower dummy pattern overlapping each other, based on some implementations of the disclosed technology. Detailed Implementation

[0014] This patent document provides implementations and examples of an image sensing device, and the disclosed features can be implemented to substantially solve one or more problems caused by the limitations and drawbacks of various image sensing devices. Some implementations of the disclosed technology propose a design for an image sensing device that provides greater flexibility in the placement of alignment marks required for subsequent processes. In some implementations, alignment marks can be freely formed without being limited by the position of the underlying pattern.

[0015] Figure 1 This is a schematic diagram illustrating an exemplary layout of a stacked image sensing device based on some implementations of the disclosed technology. Figure 2 This is a schematic diagram illustrating an exemplary layout of an image sensing device based on some implementations of the disclosed technology.

[0016] Reference Figure 1 and Figure 2 The image sensing device may include an upper substrate 100 and a lower substrate 200 stacked in a vertical direction. Each of the upper substrate 100 and the lower substrate 200 may include a semiconductor substrate.

[0017] The upper substrate 100 may include a pixel region 110 and a peripheral region 120.

[0018] Pixel region 110 may include a plurality of unit pixels (PX) arranged in succession. Each unit pixel (PX) can generate an electrical signal (i.e., a pixel signal) corresponding to the incident light by photoelectric conversion of the incident light.

[0019] Each unit pixel (PX) may include: a photoelectric conversion element configured to generate photocharge by converting light; a plurality of light receiving elements configured to transmit incident light to the photoelectric conversion element; and a plurality of pixel transistors configured to output a pixel signal corresponding to the photocharge generated by the photoelectric conversion element. Each photoelectric conversion element may include a photodiode (PD) and may be formed in the upper substrate 100. The light receiving element may be configured to transmit light and guide incident light to the photoelectric conversion element. For example, the light receiving element may include a microlens or a filter. In an implementation where each light receiving element includes a microlens and a color filter, the light receiving element is configured to converge incident light onto the corresponding photoelectric conversion element, and the color filter is configured to filter out light of a specific color from the incident light that has passed through the microlens. The light receiving element may be formed on a first surface of the upper substrate 100 (i.e., Figure 1The pixel transistor may be disposed on the top surface of the upper substrate 100. The pixel transistor may include a transfer transistor, a reset transistor, a source follower transistor, and a select transistor. The pixel transistor may be disposed on a second surface of the upper substrate 100 that faces or is opposite to the first surface (i.e., the top surface of the substrate). Figure 1 On the bottom surface.

[0020] The peripheral region 120 can be defined as the region in the upper substrate 100 located outside the pixel region 110. The peripheral region 120 may include residual areas in the scribe region that were not removed by dicing. In some implementations, the peripheral region 120 may surround the pixel region 110 in the upper substrate 100.

[0021] The peripheral region 120 may include a plurality of pads 122 and a plurality of alignment marks 124. The pads 122 can communicate with and receive signals from external devices, and can receive power supply voltages from external devices. The alignment marks 124 can be used to position the photoreceiving element during the process of forming the photoreceiving element. To distinguish the alignment marks 124 from other alignment marks designed for other purposes, the alignment marks 124 will be referred to hereinafter as photoreceiving alignment marks for ease of description.

[0022] The pad 122 may include metal and may be formed on a first surface of the upper substrate 100. The light-receiving alignment mark 124 may be formed by burying a trench etched from the first surface of the upper substrate 100 to a predetermined depth using an insulating material. The light-receiving alignment mark 124 may be formed in a dicing region or in a chip region located within a dicing region. When the light-receiving alignment mark 124 is formed in a dicing region, Figure 1 The light receiving alignment mark 124 shown may be a residual area that was not removed by cutting.

[0023] The lower substrate 200 can be disposed below the upper substrate 100, such that the lower substrate 200 and the upper substrate 100 are stacked in the vertical direction. In this case, the lower substrate 200 may include a logic region 210 and a peripheral region 220.

[0024] Logic region 210 can receive pixel signals from unit pixels (PX) of pixel region 110, process the received pixel signals using predefined logic, and thereby form an image based on the processed pixel signals. Logic region 210 may include a correlated dual sampler (CDS) 211, an analog-to-digital converter (ADC) 212, a buffer 213, a line driver 214, a timing generator 215, a control register 216, and a ramp signal generator 217.

[0025] As described above, each unit pixel PX can output a pixel signal to the Correlated Double Sampler (CDS) 211. CMOS image sensors can use Correlated Double Sampler (CDS) to eliminate unwanted pixel offset values ​​by sampling the pixel signal twice to eliminate the difference between the two samples. In one example, Correlated Double Sampler (CDS) can eliminate unwanted pixel offset values ​​by comparing the pixel output voltage obtained before and after the light signal is incident on the pixel, thereby enabling the measurement of only the pixel output voltage based on the incident light. In some embodiments of the disclosed technology, the Correlated Double Sampler (CDS) 211 can sequentially sample and hold the voltage levels of the reference signal and the image signal provided from the pixel array 110 to each of the multiple column lines. For example, the Correlated Double Sampler (CDS) 211 can perform sampling of the reference voltage level and the voltage level of the received pixel signal in response to a clock signal received from the timing generator 215, and can send an analog signal corresponding to the difference between the reference voltage level and the voltage level of the received pixel signal to the analog-to-digital converter (ADC) 212.

[0026] Analog-to-digital converter (ADC) 212 can be used to convert analog CDS signals into digital signals. In some implementations, ADC 212 can be implemented as a ramp-comparison type ADC. A ramp-comparison type ADC may include comparator circuitry and a timer. The comparator circuitry compares the analog pixel signal with a reference signal (e.g., a ramp signal that is rising or falling), and the timer counts until the voltage of the ramp signal matches the analog pixel signal. In some embodiments of the disclosed technology, ADC 212 can convert the correlated double-sampled signal generated by CDS 211 for each column into a digital signal and output the digital signal. ADC 212 can perform counting and calculation operations based on the correlated double-sampled signal for each column and the ramp signal received from ramp signal generator 800. Thus, when generating digital image data, ADC 212 can eliminate or reduce noise (e.g., reset noise generated by imaging pixels).

[0027] The ADC 212 may include multiple column counters. Each column of the pixel array 110 is coupled to a column counter and is capable of generating image data by converting the correlated double-sampled signals received from each column into digital signals using the column counters. In another embodiment of the disclosed technology, the ADC 212 may include a global counter to convert the correlated double-sampled signals corresponding to each column into digital signals using global codes provided from the global counters.

[0028] Buffer 213 can temporarily hold or latch each digital signal received from analog-to-digital converter (ADC) 212, can sense or detect and amplify each digital signal, and can output each amplified digital signal. Therefore, buffer 213 may include a memory (not shown) and a sensing amplifier (not shown). The memory can store count values, and the count values ​​can be associated with output signals of multiple unit pixels PX. The sensing amplifier can sense and amplify each count value received from the memory.

[0029] The row driver 214 can be used to drive the pixel array 110 in response to the output signal of the timing generator 215. In some implementations, the row driver 214 can select one or more imaging pixels arranged in one or more rows of the pixel array 110. The row driver 214 can generate a row selection signal to select one or more rows among multiple rows. The row driver 214 can sequentially enable a pixel reset signal for resetting the imaging pixel corresponding to at least one selected row, and a transmission signal corresponding to the pixel of the at least one selected row.

[0030] The timing generator 215 can generate timing signals to control the line driver 214, the correlated dual sampler (CDS) 211, the analog-to-digital converter (ADC) 212, and the ramp signal generator 217.

[0031] The control register 216 can generate control signals to control the ramp signal generator 217, the timing generator 215, and the buffer 213.

[0032] The ramp signal generator 217 can generate a ramp signal in response to the control signal of the control register 216 and the timing signal received from the timing generator 215, and can output the ramp signal to the analog-to-digital converter (ADC) 212.

[0033] The peripheral region 220 can be defined as the region in the lower substrate 100 located outside the logic region 210. The peripheral region 220 may include residual areas in the dicing region that were not removed by cutting. In some implementations, the peripheral region 220 may surround the logic region 210 in the lower substrate 200.

[0034] An insulating layer (not shown) may be disposed between the upper substrate 100 and the lower substrate 200. Within the insulating layer, wires for electrically connecting pixel transistors to logic circuits may be disposed between the pixel region 110 and the logic region 210. Within the insulating layer, various patterns (lower patterns) used for positioning during the process of forming the logic region 210 or during the process of stacking the upper substrate 100 and the lower substrate 200 may be disposed in the region between the peripheral regions 120 and 220.

[0035] Specifically, in some implementations, an alignment dummy pattern can be formed between the light receiving alignment mark 124 and the lower pattern in an insulating layer disposed between the peripheral regions 120 and 220 to prevent alignment failure caused by the lower pattern during the process of measuring the light receiving alignment mark 124. A detailed description of such an alignment dummy pattern will be given below.

[0036] Figure 3 This illustrates some implementation methods based on the disclosed technology. Figure 1 The cross-sectional view of an example image sensing device shown by line X-X'. Figure 4 This illustrates some implementation methods based on the disclosed technology. Figure 1 The image sensing device shown is a cross-sectional view of an example image sensing device captured by line Y-Y'.

[0037] Reference Figure 3 and Figure 4 The image sensing device may include a stacked structure, which includes an upper substrate 100 of pixel region 110 and a lower substrate 200 including logic region 210 stacked in the vertical direction.

[0038] In the pixel region 110 of the upper substrate 100, photoelectric conversion elements 112 can be formed per pixel, and light receiving elements can be formed on the first surface of the upper substrate 100. Each light receiving element includes a color filter 114 and a microlens 116. In the peripheral region 120 located outside the pixel region 110, light receiving alignment marks 124 can be formed in the upper part of the upper substrate 100. The light receiving alignment marks 124 can refer to marks used to position the light receiving elements in the process of forming the light receiving elements on the first surface of the upper substrate 100. Each light receiving alignment mark 124 can be formed by burying a trench etched from the first surface of the upper substrate 100 to a predetermined depth using an insulating material.

[0039] An upper insulating layer 300 may be formed on a second surface of an upper substrate 100, and a lower insulating layer 400 may be formed on a first surface of a lower substrate 200. The upper insulating layer 300 and the lower insulating layer 400 may be stacked to contact each other.

[0040] In the upper insulating layer 300 and the lower insulating layer 400, wires 310 and 410 for electrically connecting the pixel transistor 118 of the pixel region 110 to the logic circuit 212 of the logic region 210 can be formed between the pixel region 110 and the logic region 210. In each of the upper insulating layer 300 and the lower insulating layer 400, there is a specific portion disposed between the peripheral regions 120 and 220. This specific portion will be referred to as the peripheral insulating portion, and the alignment dummy pattern 320 and the lower pattern 420 can be formed in the peripheral insulating portion of the upper insulating layer 300 and the lower insulating layer 400.

[0041] The alignment dummy pattern 320 may include a pattern for preventing alignment failures caused by the lower pattern 420 during the process of measuring the light receiver alignment mark 124. For example, the alignment dummy pattern 320 may include a pattern for preventing the laser beam used to measure the light receiver alignment mark 124 from being reflected by the lower pattern 420 during the alignment process.

[0042] The lower pattern 420 may include various patterns (lower patterns) for performing positioning in the process of forming the logic region 210 or in the process of stacking the upper substrate 100 and the lower substrate 200. In some implementations, the lower pattern 420 may include other patterns designed for other purposes, and is not limited to patterns designed for performing positioning.

[0043] The alignment dummy pattern 320 can be disposed between the light receiving alignment mark 124 and the lower pattern 420 in such a way that the alignment dummy pattern 320 overlaps with the lower pattern 420. For example, the alignment dummy pattern 320 can be formed in the outer insulating portion of the upper insulating layer 300, and the lower pattern 420 can be formed in the outer insulating portion of the lower insulating layer 400.

[0044] In some implementations, if the image sensing device is formed as a stacked structure having an upper substrate 100 and a lower substrate 200, a light-receiving element can be formed on a first surface of the upper substrate 100 after the upper substrate 100 and the lower substrate 200 are stacked such that insulating layers 300 and 400 are in contact with each other. Therefore, a light-receiving alignment mark 124 for positioning the light-receiving element can be formed after the upper substrate 100 and the lower substrate 200 are stacked. The light-receiving alignment mark 124 can be formed in the peripheral region 120 of the upper substrate 100.

[0045] In some cases, various lower patterns 420 used in previous processes may have already been formed in the peripheral insulating portions of insulating layers 300 and 400. In this case, if the light receiving alignment mark 124 is formed above the lower pattern 420 in an overlapping manner, the laser beam used to measure the light receiving alignment mark 124 in the alignment process may be reflected by the lower pattern 420, generating noise. Therefore, accurate measurement of the light receiving alignment mark 124 becomes more difficult. Therefore, if the lower pattern 420 is positioned below the lower receiving alignment mark 124, the likelihood of alignment failure is greater due to reflection from the lower pattern 420.

[0046] Typically, to prevent such alignment failures, the light receiving alignment mark 120 is formed not above the area where the lower pattern 420 is formed when forming the light receiving alignment mark 124. However, this arrangement restriction leads to difficulties in manufacturing operations. In addition, if there is not enough space in width for the image sensing device, and the area that meets the arrangement restrictions is not adequately guaranteed, the possibility of such alignment failures still exists.

[0047] Some implementations of the disclosed technology include an alignment dummy pattern 320 to address or avoid arrangement limitations. In some implementations, since the alignment dummy pattern 320 is formed below the light receiving alignment mark 124, the laser beam used to measure the light receiving alignment mark 124 can be absorbed by the alignment dummy pattern 320 and not introduced into the lower pattern 420. By using this alignment dummy pattern 320, the light receiving alignment mark 124 can be positioned anywhere without avoiding overlap with the lower pattern 420.

[0048] The alignment dummy pattern 320 may include an upper dummy pattern 322 and a lower dummy pattern 324, which are disposed in the peripheral insulating portion of the upper insulating layer 300 and are alternately formed along at least one of the vertical or horizontal directions. If the upper insulating layer 300 comprises multiple layers stacked on top of each other, the upper dummy pattern 322 and the lower dummy pattern 324 may be located in different layers of the upper insulating layer 300.

[0049] Figure 5A This is a schematic diagram illustrating an example of the layout structure of an upper dummy pattern in an aligned dummy pattern based on some implementations of the disclosed technology. Figure 5B This is a schematic diagram illustrating an example of the layout structure of a lower dummy pattern in an aligned dummy pattern based on some implementations of the disclosed technology.

[0050] Reference Figure 5A and Figure 5BThe upper dummy pattern 322 and the lower dummy pattern 324 can be formed in a shape in which dot patterns are arranged alternately in the X-axis and Y-axis directions, wherein each dot pattern is formed into a square shape. For example, the upper dummy pattern 322 and the lower dummy pattern 324 can be formed in a chessboard pattern by arranging multiple dot patterns with the same size (i.e., the same horizontal length and vertical length).

[0051] In this configuration, the upper dummy pattern 322 and the lower dummy pattern 324 can be formed in different layers. For example, the upper dummy pattern 322 can be formed in metal layer M3, and the lower dummy pattern 324 can be formed in metal layer M4. The upper dummy pattern 322 can be formed simultaneously with the formation of the conductor 310 in metal layer M3, and the lower dummy pattern 324 can be formed simultaneously with the formation of the conductor 310 in metal layer M4. The dot pattern of the upper dummy pattern 322 and the dot pattern of the lower dummy pattern 324 can include a metal such as copper (Cu).

[0052] Specifically, the dot patterns of the upper dummy pattern 322 and the lower dummy pattern 324 can be positioned alternately. Therefore, the dot patterns of the upper dummy pattern 322 and the lower dummy pattern 324 can be arranged in staggered positions. For example, the dot patterns of the upper dummy pattern 322 can be arranged to overlap perpendicularly with the insulating layer disposed between the dot patterns of the lower dummy pattern 324. Therefore, the overlapping appearance of the upper dummy pattern 322 and the lower dummy pattern 324 can be as follows... Figure 6 The diagram is represented by a shape such as a wide board.

[0053] As is evident from the above description, image sensing devices based on some implementations of the disclosed technology are free to form alignment marks required for subsequent processes, regardless of the position of the underlying pattern.

[0054] Although several exemplary embodiments have been described, it should be understood that various variations and other embodiments of the disclosed embodiments can be designed based on the description and / or illustration in this patent document.

[0055] Cross-references to related applications

[0056] This patent document claims priority and benefit to Korean Patent Application No. 10-2020-0118257, filed on September 15, 2020, the entire contents of which are incorporated herein by reference as part of the disclosure of this patent document.

Claims

1. An image sensing device, the image sensing device comprising: an upper substrate configured to include a pixel region and a first peripheral region located outside the pixel region, the pixel region including unit pixels configured to generate electrical signals by conversion of incident light; a lower substrate configured to include a logic region and a second peripheral region located outside the logic region, the logic region coupled to receive the electrical signals from the unit pixels and configured to generate an image based on the electrical signals from the unit pixels; light-receiving elements disposed on the upper substrate and configured to transmit the incident light to the pixel region; an insulating layer disposed between the upper substrate and the lower substrate; a light-receiving alignment mark disposed in the first peripheral region and configured to assist positioning of the light-receiving elements on a first surface of the upper substrate in the pixel region; and an alignment pattern disposed between the first peripheral region and the second peripheral region and located in the insulating layer, the alignment pattern configured to absorb light used to measure the light-receiving alignment mark. The light-receiving alignment mark includes:

2. The image sensing device according to claim 1, wherein a trench etched from the first surface to a predetermined depth in the first peripheral region; and an insulating material buried in the trench. The alignment pattern includes:

3. The image sensing device according to claim 1, wherein a plurality of dot patterns alternately disposed in the insulating layer. The plurality of dot patterns includes a first dot pattern disposed in a first layer and a second dot pattern disposed in a second layer disposed below the first layer.

4. The image sensing device according to claim 3, wherein The first dot pattern and the second dot pattern are disposed in a checkered shape.

5. The image sensing device according to claim 4, wherein Each of the dot patterns has an equal size.

6. The image sensing device according to claim 3, wherein Each dot pattern includes copper (Cu).

7. The image sensing device according to claim 3, wherein The insulating layer includes:

8. The image sensing device according to claim 1, wherein an upper insulating layer formed on a second surface positioned opposite the first surface and formed to include the alignment pattern; and a lower insulating layer formed on a first surface of the lower substrate to be in contact with the upper insulating layer. The lower insulating layer includes an additional pattern.

9. The image sensing device according to claim 8, wherein The alignment pattern is disposed to overlap the additional pattern.

10. The image sensing device according to claim 9, wherein Each of the light-receiving elements includes a lens or a filter.

11. The image sensing device according to claim 1, wherein 12.An image sensing device, the image sensing device comprising: a semiconductor substrate configured to include a pixel region and a peripheral region located outside the pixel region, the pixel region including a plurality of photoelectric conversion elements configured to generate electrical signals by conversion of light; a plurality of light-receiving elements formed on a first surface of the semiconductor substrate and configured to transmit incident light to the photoelectric conversion elements; an insulating layer disposed on a second surface positioned opposite the first surface; a light-receiving alignment mark disposed in the peripheral region and configured to assist positioning of the light-receiving elements; and an alignment pattern disposed between the peripheral region and the peripheral region and located in the insulating layer, the alignment pattern configured to absorb light used to measure the light-receiving alignment mark. an alignment pattern formed in the insulating layer to overlap with the light-receiving alignment mark, wherein the alignment pattern includes a plurality of dot patterns disposed in different sub-layers of the insulating layer, wherein the alignment pattern is configured to absorb light used to measure the light-receiving alignment mark.

13. The image sensing device according to claim 12, wherein The alignment pattern includes: a first dot pattern disposed in a first sub-layer of the insulating layer; and a second dot pattern disposed in a second sub-layer disposed below the first sub-layer.

14. The image sensing device according to claim 13, wherein The first dot pattern and the second dot pattern are disposed in a checkered shape.

15. The image sensing device according to claim 13, wherein The first dot pattern and the second dot pattern have the same size.

16. The image sensing device according to claim 12, wherein The dot pattern includes metal.

17. The image sensing device according to claim 12, wherein The insulating layer includes: an upper insulating layer formed on the second surface positioned opposite the first surface and formed to include the alignment pattern; and a lower insulating layer formed in contact with the upper insulating layer.

18. The image sensing device of claim 12, further comprising an additional substrate disposed below the insulating layer and configured to include a logic area configured to generate an image upon receiving the electrical signal from the pixel area.

19. The image sensing device according to claim 17, wherein The lower insulating layer includes an additional pattern, and the alignment pattern is disposed to overlap with the additional pattern.

20. The image sensing device according to claim 12, wherein Each of the light-receiving elements includes a lens or a filter.

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