Semiconductor memory and method of making the same, electronic device

Abstract

The application provides a semiconductor memory and a manufacturing method thereof and an electronic device, comprising: a substrate; a plurality of control gate stack structures and a plurality of array common source isolation layers alternately and separately arranged on one side surface of the substrate; an array common source connection layer on the side of the array common source isolation layer away from the substrate; an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling into a groove between adjacent array common source connection layers, the insulating filling layer comprising a via hole corresponding to the array common source connection layer; and a bridge wire on the side of the insulating filling layer away from the substrate and connecting the adjacent two array common source connection layers through the via hole.

Description

[0001] This application is a divisional application of the patent with the application date of May 7, 2020, the application number of 202010377292.6, and the invention name of "a semiconductor memory and its manufacturing method, electronic equipment". TECHNICAL FIELD

[0002] The present application relates to the technical field of semiconductor memory, more specifically, to a semiconductor memory and its manufacturing method, electronic equipment. BACKGROUND

[0003] NAND flash is a kind of non-volatile storage product with low power consumption, light weight and good performance, which has been widely used in electronic products. At present, the planar structure of NAND flash has reached the limit of practical expansion. In order to further improve the storage capacity and reduce the storage cost per bit, 3D NAND memory with 3D structure is proposed. In the process of manufacturing 3D NAND memory, the damage to the gate stack structure often occurs. SUMMARY

[0004] Therefore, the present application provides a semiconductor memory and its manufacturing method, electronic equipment, which effectively solves the technical problems existing in the prior art and avoids the damage to the control gate stack structure during the manufacturing of the semiconductor memory.

[0005] To achieve the above-mentioned purpose, the technical solutions provided by the present application are as follows:

[0006] A semiconductor memory comprises:

[0007] a substrate;

[0008] a plurality of control gate stack structures and a plurality of array common source isolation layers arranged alternately and isolated on one side surface of the substrate;

[0009] an array common source connection layer located on the side of the array common source isolation layer away from the substrate;

[0010] an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling the recess between adjacent array common source connection layers, the insulating filling layer comprising a via corresponding to the array common source connection layer;

[0011] and a bridge line located on the side of the insulating filling layer away from the substrate and connecting adjacent two array common source connection layers through the via.

[0012] Optionally, the insulating filling layer comprises a groove corresponding to the bridge line, and the bridge line is located in the corresponding groove.

[0013] Optionally, the bridge wire is made of the same material as the array common source connection layer.

[0014] Optionally, the bridge wire is made of tungsten.

[0015] Optionally, the semiconductor memory is a 3D NAND memory.

[0016] Correspondingly, the application further provides a semiconductor memory manufacturing method, comprising:

[0017] A substrate is provided, which comprises a substrate, a plurality of control gate stack structures and a plurality of array common source isolation layers alternately and separately arranged on one side surface of the substrate, an array common source connection layer on the side of the array common source isolation layer away from the substrate, and an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling the recess between adjacent array common source connection layers.

[0018] A via hole corresponding to the array common source connection layer is formed on the insulating filling layer.

[0019] A bridge wire is formed on the side of the insulating filling layer away from the substrate, which connects two adjacent array common source connection layers through the via hole.

[0020] Optionally, after the via hole is formed and before the bridge wire is formed, the method further comprises:

[0021] A groove is formed between the via holes corresponding to the two adjacent array common source connection layers, and the bridge wire is located in the groove.

[0022] Optionally, the bridge wire is made of the same material as the array common source connection layer.

[0023] Optionally, the bridge wire is made of tungsten.

[0024] Correspondingly, the application further provides an electronic device comprising the semiconductor memory.

[0025] Compared with the prior art, the technical solution provided by the application has at least the following advantages:

[0026] The application provides a semiconductor memory and a manufacturing method thereof and an electronic device, comprising: a substrate; a plurality of control gate stack structures and a plurality of array common source isolation layers arranged alternately and isolated on one side surface of the substrate; an array common source connection layer on the side of the array common source isolation layer away from the substrate; an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling into a groove between adjacent array common source connection layers, the insulating filling layer comprising a via hole corresponding to the array common source connection layer; and a bridge wire on the side of the insulating filling layer away from the substrate and connecting two adjacent array common source connection layers through the via hole.

[0027] From the above, the technical scheme provided by the application can form a via hole in the insulating filling layer corresponding to the array common source connection layer when electrically connecting two adjacent array common source connection layers, and then form a bridge wire on the insulating filling layer and achieve electrical connection through the via holes corresponding to the two adjacent array common source connection layers. The application does not need to perform large-area hole digging or other processing on the insulating filling layer corresponding to the control gate stack structure, thereby avoiding damage to the control gate stack structure when manufacturing the semiconductor memory. BRIEF DESCRIPTION OF DRAWINGS

[0028] In order to more clearly illustrate the technical scheme in the embodiments of the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only constitute the embodiments of the application, and those skilled in the art can obtain other drawings according to the provided drawings without creative labor.

[0029] Figure 1 A structure schematic diagram of a semiconductor memory provided by the embodiment of the application;

[0030] Figure 2 A top view of a semiconductor memory provided by the embodiment of the application;

[0031] Figure 3 A structure schematic diagram of another semiconductor memory provided by the embodiment of the application;

[0032] Figure 4 A flowchart of a manufacturing method of a semiconductor memory provided by the embodiment of the application;

[0033] Figure 5 A flowchart of another manufacturing method of a semiconductor memory provided by the embodiment of the application. DETAILED DESCRIPTION

[0034] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all the other embodiments obtained by those skilled in the art without creative efforts belong to the scope of the present application.

[0035] As described in the background, NAND flash is a nonvolatile storage product with low power consumption, light weight and good performance, which is widely used in electronic products. At present, the planar structure of NAND flash has reached the limit of practical expansion. In order to further improve the storage capacity and reduce the storage cost per bit, a 3D NAND memory with 3D structure is proposed. In the existing manufacturing process of 3D NAND memory, the damage to the gate stack structure often occurs during the manufacturing process.

[0036] Based on this, the embodiments of the present application provide a semiconductor memory and a manufacturing method thereof, and an electronic device, which effectively solve the technical problems existing in the prior art and avoid the damage to the control gate stack structure during the manufacturing of the semiconductor memory.

[0037] To achieve the above object, the technical solutions provided by the embodiments of the present application are as follows, which will be described in detail with reference to the accompanying drawings. Figures 1 to 5 The technical solutions provided by the embodiments of the present application will be described in detail.

[0038] As shown in Figure 1 and Figure 2 , a structure diagram of a semiconductor memory provided by the embodiments of the present application is shown in Figure 1 A top view of a semiconductor memory provided by the embodiments of the present application is shown in Figure 2 The semiconductor memory comprises:

[0039] A substrate 100.

[0040] A plurality of control gate stack structures 210 and a plurality of array common source isolation layers 220 (array common source) are arranged alternately and isolated on one side surface of the substrate 100.

[0041] An array common source connection layer 300 is located on the side of the array common source isolation layer 220 away from the substrate 100.

[0042] An insulating filling layer 400 (insulating layer) covers the side of the array common source connection layer 300 away from the substrate 100 and fills the recesses (intervals) between adjacent array common source connection layers 300, and the insulating filling layer 400 comprises a through hole 410 corresponding to the array common source connection layer 300.

[0043] and a bridge line 500 (bridge structure) located on the side of the insulating filling layer 400 away from the substrate 100 and connecting two adjacent array common source connection layers 300 through the via hole 410.

[0044] It should be noted that the semiconductor memory provided by the embodiment of the present application is located on the side of the bridge line away from the substrate, and further includes a structure composed of more semiconductor memories, which is the same as the prior art, and thus is not described in detail.

[0045] It can be understood that the technical scheme provided by the embodiment of the present application can realize the electrical connection of two adjacent array common source connection layers by forming a via hole in the insulating filling layer corresponding to the array common source connection layer, and then forming a bridge line on the insulating filling layer and realizing electrical connection through the via holes corresponding to the two adjacent array common source connection layers. The embodiment of the present application does not need to perform large-area hole digging or other processing on the corresponding control gate stack structure of the insulating filling layer, thereby avoiding damage to the control gate stack structure during the manufacture of the semiconductor memory.

[0046] In an embodiment of the present application, in order to facilitate the preparation of other component structures on the side of the bridge line and the insulating filling layer away from the substrate after the preparation of the bridge line is completed, the present application can also be optimized. Referring to Figure 3 Fig. 2 shows a structure diagram of another semiconductor memory provided by the embodiment of the present application, wherein the semiconductor memory provided by the present application includes:

[0047] a substrate 100.

[0048] a plurality of control gate stack structures 210 and a plurality of array common source isolation layers 220 arranged alternately and isolated on the side surface of the substrate 100.

[0049] an array common source connection layer 300 located on the side of the array common source isolation layer 220 away from the substrate 100.

[0050] an insulating filling layer 400 covering the side of the array common source connection layer 300 away from the substrate 100 and filling the recess between adjacent array common source connection layers 300, the insulating filling layer 400 including a via hole 410 corresponding to the array common source connection layer 300.

[0051] and a bridge line 500 (bridge structure) located on the side of the insulating filling layer 400 away from the substrate 100 and connecting two adjacent array common source connection layers 300 through the via hole 410.

[0052] In the embodiment of the present application, the insulating filling layer 400 corresponding to the bridge line 500 includes a groove connecting the corresponding two via holes 410, and the bridge line 500 is located in the corresponding groove.

[0053] It can be understood that the insulating filling layer provided by the embodiment of the present application forms a groove between two through holes connected by the bridge connection line on the side away from the substrate, and then the bridge connection line is formed in the groove, so as to reduce the height difference between the bridge connection line and the surface of the insulating filling layer away from the substrate, and facilitate the subsequent component preparation. Further, the surface of the bridge connection line away from the substrate is flush with the surface of the insulating filling layer away from the substrate, so that the side surface is a planarization surface, and further facilitates the preparation of subsequent components thereon.

[0054] In an embodiment of the present application, the bridge connection line and the array common source connection layer are made of the same material. Specifically, the bridge connection line and the array common source connection layer can be made of metal material; alternatively, the bridge connection line and the array common source connection layer are made of tungsten.

[0055] In addition, the insulating filling layer can be made of oxide material, and the array common source isolation layer can be made of doped polysilicon, which is not limited by the present application.

[0056] In addition, the shape of the through hole can be a cylindrical through hole, a cuboid through hole, etc., and the present application does not make specific limitation on the shape and size thereof.

[0057] In an embodiment of the present application, the semiconductor memory provided by the embodiment of the present application is a 3D NAND memory.

[0058] Correspondingly, the embodiment of the present application also provides a manufacturing method of a semiconductor memory, as shown in Figure 4 The manufacturing method includes the following steps.

[0059] S1, providing a substrate, the substrate includes a substrate, a plurality of control gate stack structures and a plurality of array common source isolation layers which are alternately isolated and arranged on one side surface of the substrate, an array common source connection layer located on the side away from the substrate of the array common source isolation layer, and an insulating filling layer covering the side away from the substrate of the array common source connection layer and filling the recess between adjacent array common source connection layers.

[0060] S2, forming a through hole corresponding to the array common source connection layer on the insulating filling layer.

[0061] S3, forming a bridge connection line on the side away from the substrate of the insulating filling layer, the bridge connection line connecting two adjacent array common source connection layers through the through hole.

[0062] It should be noted that the manufacturing method provided by the embodiment of the present application still needs to prepare the remaining component structures of the semiconductor memory on the side of the semiconductor memory away from the bridge connection line after the bridge connection line is manufactured, which is the same as the prior art, and thus no redundant description is made.

[0063] It can be understood that, when electrically connecting the adjacent two array common source connection layers, the technical solution provided by the embodiment of the present application only needs to form a via hole at the insulating filling layer corresponding to the array common source connection layer, and then form a bridge connection line on the insulating filling layer and realize electrical connection through the via hole corresponding to the adjacent two array common source connection layers. The embodiment of the present application does not need to perform large-area hole digging and other processing on the insulating filling layer corresponding to the control gate stack structure, thereby avoiding the damage to the control gate stack structure when the semiconductor memory is manufactured.

[0064] In an embodiment of the present application, in order to facilitate the preparation of other component structures on the side of the bridge connection line and the insulating filling layer away from the substrate after the bridge connection line is manufactured, the present application can also be optimized. Specifically, after the via hole is formed and before the bridge connection line is formed, the method further comprises: forming a groove between the via holes corresponding to the adjacent two array common source connection layers, wherein the bridge connection line is located in the groove.

[0065] Reference Figure 5 As shown in FIG. 5, which is a flow chart of another manufacturing method of a semiconductor memory provided by the embodiment of the present application, the manufacturing method comprises:

[0066] S1, providing a substrate, the substrate comprising a substrate, a plurality of control gate stack structures and a plurality of array common source isolation layers arranged alternately and isolated on the surface of one side of the substrate, an array common source connection layer on the side of the array common source isolation layer away from the substrate, and an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling the recess between the adjacent array common source connection layers.

[0067] S2, forming a via hole corresponding to the array common source connection layer on the insulating filling layer.

[0068] S21, forming a groove between the via holes corresponding to the adjacent two array common source connection layers.

[0069] S3, forming a bridge connection line on the side of the insulating filling layer away from the substrate, the bridge connection line connecting the adjacent two array common source connection layers through the via hole, wherein the bridge connection line is located in the groove.

[0070] It can be understood that the insulating filling layer provided by the embodiment of the present application forms a groove between two through holes connected by the bridge connection line on the side away from the substrate, and then the bridge connection line is formed in the groove, so as to reduce the height difference between the bridge connection line and the surface of the insulating filling layer on the side away from the substrate, and facilitate subsequent component preparation. Further, the surface on the side away from the substrate of the bridge connection line is flush with the surface on the side away from the substrate of the insulating filling layer, so that the side surface is a planarization surface, and further facilitates the preparation of subsequent components thereon.

[0071] In an embodiment of the present application, the bridge connection line and the array common source connection layer are made of the same material. Specifically, the bridge connection line and the array common source connection layer can be made of metal material; alternatively, the bridge connection line and the array common source connection layer are made of tungsten.

[0072] In addition, the insulating filling layer can be made of oxide material, and the array common source isolation layer can be made of doped polysilicon, which is not limited by the present application.

[0073] In addition, the shape of the through hole can be a cylindrical through hole, a cuboid through hole, etc., and the present application does not make specific limitation on the shape and size thereof.

[0074] In an embodiment of the present application, the semiconductor memory provided by the embodiment of the present application is a 3D NAND memory.

[0075] Correspondingly, the present application also provides an electronic device, which comprises the semiconductor memory provided by any one of the above embodiments.

[0076] The present application provides a semiconductor memory, a manufacturing method thereof and an electronic device, which comprises: a substrate; a plurality of control gate stack structures and a plurality of array common source isolation layers alternately and separately arranged on one side surface of the substrate; an array common source connection layer on the side away from the substrate of the array common source isolation layer; an insulating filling layer covering the side away from the substrate of the array common source connection layer and filling the recess between adjacent array common source connection layers, the insulating filling layer comprising a through hole corresponding to the array common source connection layer; and a bridge connection line on the side away from the substrate of the insulating filling layer and connecting two adjacent array common source connection layers through the through hole.

[0077] From the above, the technical scheme provided by the embodiment of the present application can realize the electrical connection between the adjacent two array common source connection layers by forming a through hole in the insulating filling layer corresponding to the array common source connection layer, and then forming a bridging line on the insulating filling layer and realizing the electrical connection through the through holes corresponding to the adjacent two array common source connection layers. The embodiment of the present application does not need to perform large-area hole digging or other processing on the insulating filling layer corresponding to the control gate stack structure, thereby avoiding the damage to the control gate stack structure during the manufacturing of the semiconductor memory.

[0078] The above description of disclosed embodiments enables one of ordinary skill in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A semiconductor memory, characterized in that, include: Alternating stacked control gates and multiple array common source electrodes; The array common source connection layer is located on the array common source pole; An insulating layer located on the array common source interconnect layer and at the interval between adjacent array common source interconnect layers; The via is located in the insulating layer and corresponds to the array common source connection layer; And, a bridging structure located on the side of the insulating layer away from the array common source connection layer and connecting two adjacent array common source connection layers through the via; wherein, the control gate stack structure includes a first surface and a second surface opposite to each other, the first surface being closer to the bridging structure than the second surface, and the orthographic projection of the bridging structure on the plane of the first surface at least partially overlapping the control gate stack structure.

2. The semiconductor memory according to claim 1, characterized in that, The array common source connection layer includes a third surface and a fourth surface that are opposite to each other. The third surface is closer to the insulating layer than the fourth surface. The orthographic projection of the via on the plane of the third surface overlaps with the array common source connection layer.

3. The semiconductor memory according to claim 1, characterized in that, The insulating layer is located at least partially between the bridging structure and the control gate stack structure.

4. The semiconductor memory according to claim 1, characterized in that, The insulating layer includes a groove corresponding to the bridging structure, and the bridging structure is located within the corresponding groove.

5. The semiconductor memory according to claim 1, characterized in that, The bridging structure is made of the same material as the array common source connection layer.

6. The semiconductor memory according to claim 1, characterized in that, The material of the bridging structure and the common source connection layer of the array includes metal.

7. The semiconductor memory according to claim 6, characterized in that, The metal includes tungsten.

8. The semiconductor memory according to claim 1, characterized in that, The semiconductor memory is a 3D NAND memory.

9. The semiconductor memory according to claim 1, characterized in that, The array common source electrode and the array common source connection layer are made of different materials.

10. The semiconductor memory according to claim 9, characterized in that, The material of the array common source electrode includes doped polycrystalline silicon, and the material of the array common source connection layer includes tungsten.

11. The semiconductor memory according to claim 1, characterized in that, The semiconductor memory further includes a substrate located on the side of the control gate stack structure and the array common source away from the bridge structure.

12. The semiconductor memory according to any one of claims 1 to 11, characterized in that, The bridging structure extends from one end of one of the two adjacent array common source connection layers to one end of the other array common source connection layer; and in the direction of extension of the bridging structure, a portion of the structure of the array common source connection layer is offset from the bridging structure.

13. A method for manufacturing a semiconductor memory, characterized in that, include: A substrate is provided, the substrate comprising a plurality of alternately arranged control gate stacked structures and a plurality of arrayed common source electrodes; The array common source connection layer is located on the array common source pole; An insulating layer located on the array common source interconnect layer and at the interval between adjacent array common source interconnect layers; A via corresponding to the array common source connection layer is formed in the insulating layer; A bridging structure is formed; wherein the bridging structure is located on the side of the insulating layer away from the array common source connection layer, and connects two adjacent array common source connection layers through the through-hole; The control gate stack structure includes a first surface and a second surface that are opposite each other. The first surface is closer to the bridging structure than the second surface. The orthographic projection of the bridging structure onto the plane containing the first surface at least partially overlaps with the control gate stack structure.

14. The method for manufacturing a semiconductor memory according to claim 13, characterized in that, After the through hole is formed and before the bridging structure is formed, the method further includes: A trench is formed between the corresponding vias of two adjacent array common source connection layers, wherein the bridging structure is located within the trench.

15. The method for manufacturing a semiconductor memory according to claim 13, characterized in that, The bridging structure is made of the same material as the array common source connection layer, while the array common source connection layer is made of a different material than the array common source electrode.

16. The method for manufacturing a semiconductor memory according to claim 15, characterized in that, The material of the bridging structure and the array common-source connection layer includes tungsten; and / or, The common source electrode of the array is made of doped polycrystalline silicon.

17. An electronic device, characterized in that, The electronic device includes the semiconductor memory according to any one of claims 1-12.

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