Semiconductor memory device

Abstract

An embodiment provides a semiconductor memory device capable of shortening a readout time. The semiconductor memory device of the embodiment has a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, and a charge holding section. The first wiring extends in a first direction along the surface of the substrate. The second wiring is juxtaposed with the first wiring in a second direction intersecting the first direction and extends in the first direction. The third wiring is connected to the first wiring and the second wiring and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting the first direction and the second direction, and is juxtaposed with the third wiring at least in the first direction. The charge holding section is located between the third wiring and the fourth wiring.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-154398 (filing date: September 15, 2020). This application incorporates all the contents of the base application by reference thereto. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Art

[0004] There is known a semiconductor memory device having a stack in which insulating films and word lines are alternately stacked in the thickness direction of a substrate, and a channel portion that penetrates the stack in the thickness direction of the substrate. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device capable of shortening the readout time.

[0006] The semiconductor memory device according to the embodiment has a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, and a charge holding portion. The first wiring extends in a first direction along the surface of the substrate. The second wiring is juxtaposed with the first wiring in a second direction intersecting the first direction and extends in the first direction. The third wiring is connected to the first wiring and the second wiring and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting the first direction and the second direction, and is juxtaposed with the third wiring at least in the first direction. The charge holding portion is located between the third wiring and the fourth wiring. Brief Description of the Drawings

[0007] Figure 1 is a cross-sectional view showing a semiconductor memory device according to a first embodiment.

[0008] Figure 2 is along Figure 1 a cross-sectional view taken along line F2-F2 of the semiconductor memory device shown.

[0009] Figure 3 is along Figure 1 a cross-sectional view taken along line F3-F3 of the semiconductor memory device shown.

[0010] Figure 4 is a cross-sectional view showing the operation of a semiconductor memory device according to a first embodiment.

[0011] Figure 5 is a cross-sectional view showing a manufacturing method of a semiconductor memory device according to a first embodiment.

[0012] Figure 6 It is a cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0013] Figure 7 It is a cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0014] Figure 8 It is a cross-sectional view showing a manufacturing method of a semiconductor memory device according to the first embodiment.

[0015] Figure 9 It is a cross-sectional view of a semiconductor memory device according to the second embodiment.

[0016] Figure 10 It is a cross-sectional view showing a manufacturing method of a semiconductor memory device according to the second embodiment.

[0017] Figure 11 It is a cross-sectional view showing a manufacturing method of a semiconductor memory device according to the second embodiment.

[0018] Figure 12 It is a cross-sectional view of a semiconductor memory device according to the third embodiment.

[0019] Figure 13 It is along Figure 12 A cross-sectional view taken along the line F13 - F13 of the semiconductor memory device shown.

[0020] Figure 14 It is a cross-sectional view of a semiconductor memory device according to the fourth embodiment.

[0021] Figure 15 It is a cross-sectional view of a semiconductor memory device according to the fifth embodiment.

[0022] Description of Reference Numerals

[0023] 1A, 1B, 1C, 1D, 1E... semiconductor memory devices, SL... source line (first wiring), DL... drain line (second wiring), 31... gate wiring (fourth wiring), 40... charge holding section, 50... channel section (third wiring), BL... bit line, ST... selection transistor, SGL... selection gate line. Detailed Embodiments

[0024] Hereinafter, a semiconductor memory device according to an embodiment will be described with reference to the accompanying drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. Moreover, redundant descriptions of these components are sometimes omitted. In this specification, "parallel" includes "substantially parallel". In this specification, "orthogonal" includes "substantially orthogonal". In this specification, "connected" includes not only the case where two components are adjacent to each other without any component interposed therebetween, but also the case where other components are interposed between the two components. In this specification, "ring-shaped" is not limited to a circular shape, but also includes a rectangular shape or a triangular shape. In this specification, "XX is provided on YY" includes not only the case where XX is in contact with YY, but also the case where other components are interposed between XX and YY.

[0025] In addition, first, the +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are defined. The +X direction, -X direction, +Y direction, and -Y direction are directions along the surface 10a of a silicon substrate 10 (see Figure 1 ). The +X direction is the direction in which a source line SL and a drain line DL (see Figure 2 ) described later extend. The -X direction is the direction opposite to the +X direction. When the +X direction and the -X direction are not distinguished, it is simply referred to as the "X direction". The +Y direction and the -Y direction are directions that intersect (e.g., are orthogonal to) the X direction. The +Y direction is the direction in which a bit line BL (see Figure 3 ) described later extends. The -Y direction is the direction opposite to the +Y direction. When the +Y direction and the -Y direction are not distinguished, it is simply referred to as the "Y direction". The +Z direction and the -Z direction are directions that intersect (e.g., are orthogonal to) the X direction and the Y direction, and are the thickness direction of the silicon substrate 10 (see Figure 1 ). The +Z direction is the direction from the silicon substrate 10 toward a laminate 20 described later. The -Z direction is the direction opposite to the +Z direction. When the +Z direction and the -Z direction are not distinguished, it is simply referred to as the "Z direction". In this specification, the "+Z direction" is sometimes referred to as "up" and the "-Z direction" is sometimes referred to as "down". However, these expressions are for convenience and do not define the direction of gravity. The +X direction is an example of the "first direction". The +Y direction is an example of the "second direction". The +Z direction is an example of the "third direction".

[0026] (First Embodiment)

[0027] <1. Configuration of Semiconductor Memory Device>

[0028] First, the configuration of the semiconductor memory device 1A of the first embodiment will be described. The semiconductor memory device 1A is, for example, a non-volatile semiconductor memory device. In addition, in the drawings described below, the illustration of the insulating portion that is not relevant to the description may sometimes be omitted.

[0029] Figure 1 is a cross-sectional view showing the semiconductor memory device 1A. Figure 1 is along Figure 2 a cross-sectional view taken along the line F1 - F1 of the semiconductor memory device 1A shown. The semiconductor memory device 1A has, for example, a silicon substrate 10, an insulating layer 11, a semiconductor layer 12, a stack 20, an insulating portion 25, a plurality of pillars (columnar bodies) 30, an insulating portion STH (refer to Figure 2 ), an upper structure 70, a plurality of contacts 80, and a plurality of bit lines BL (only one is shown in Figure 1 ).

[0030] <1.1 Lower Structure of Semiconductor Memory Device>

[0031] The silicon substrate 10 is a substrate that serves as the base of the semiconductor memory device 1A. At least a part of the silicon substrate 10 is plate-shaped along the X direction and the Y direction. The silicon substrate 10 has a surface 10a facing the stack 20. The silicon substrate 10 is formed of a semiconductor material containing silicon (Si). The silicon substrate 10 is an example of a "substrate".

[0032] The insulating layer 11 is provided on the surface 10a of the silicon substrate 10. The insulating layer 11 is layered along the X direction and the Y direction. The insulating layer 11 is formed of an insulating material such as silicon oxide (SiO2). A part of the peripheral circuit that operates the semiconductor memory device 1A may also be provided between the silicon substrate 10 and the insulating layer 11.

[0033] The semiconductor layer 12 is provided on the insulating layer 11. The semiconductor layer 12 is layered along the X direction and the Y direction. The semiconductor layer 12 is a blocking layer that suppresses the deep digging of the memory trench MT (refer to Figure 5 ) in the manufacturing process of the semiconductor memory device 1A described later. The semiconductor layer 12 is formed of a semiconductor material such as polycrystalline silicon (Poly - Si). When the depth of the memory trench MT is controlled by other factors, the semiconductor layer 12 may be omitted.

[0034] <1.2 Stack>

[0035] Next, the stack 20 will be described. The stack 20 is provided on the semiconductor layer 12. The stack 20 includes a plurality of functional layers 21 (for example, functional layers 21A to 21D) and a plurality of insulating layers 22 (for example, insulating layers 22A to 22D). The plurality of functional layers 21 and the plurality of insulating layers 22 are alternately stacked layer by layer in the Z direction. InFigure 1 In this figure, for the sake of convenience in explanation, four layers of the functional layer 21 and the insulating layer 22 are each shown, but in reality, more functional layers 21 and insulating layers 22 are stacked.

[0036] Figure 2 is along Figure 1 a cross-sectional view taken along the F2 - F2 line of the semiconductor memory device 1A shown. Figure 2 is a cross-sectional view showing the first functional layer 21A. The first functional layer 21A includes a plurality of source lines SL (e.g., source lines SL1 to SL3), a plurality of drain lines DL (e.g., drain lines DL1, DL2), and a plurality of insulating portions 23. The source line SL is an example of the "first wiring". The drain line DL is an example of the "second wiring".

[0037] The plurality of source lines SL each extend linearly in the X direction. The plurality of source lines SL are arranged at intervals in the Y direction. The plurality of drain lines DL each extend linearly in the X direction. The plurality of drain lines DL are arranged at intervals in the Y direction. The plurality of source lines SL and the plurality of drain lines DL are alternately arranged one by one in the Y direction. For example, the drain line DL1 is located between the source line SL1 and the source line SL2 in the Y direction. The other drain line DL2 is located between the source line SL2 and the source line SL3 in the Y direction. In other words, the source line SL2 is located on the opposite side of the source line SL1 with respect to the drain line DL1 in the Y direction. The drain line DL2 is located on the opposite side of the drain line DL1 with respect to the source line SL2 in the Y direction. The source line SL1 is an example of the "first source line". The source line SL2 is an example of the "second source line". The drain line DL1 is an example of the "first drain line". The drain line DL2 is an example of the "second drain line".

[0038] The plurality of source lines SL and the plurality of drain lines DL are conductive portions provided in the laminate 20 and are wirings extending in the laminate 20. The plurality of source lines SL and the plurality of drain lines DL are formed of a conductive material such as tungsten (W). In the present embodiment, the "drain line" refers to a wiring through which current flows toward the channel portion 50 described later. The drain line DL is connected to a sense amplifier circuit SA which is a part of the peripheral circuit of the semiconductor memory device 1A. The operation of the sense amplifier circuit SA will be described later. On the other hand, in the present embodiment, the "source line" refers to a wiring through which the current passing through the channel portion 50 described later flows. The source line SL is connected to the ground of the semiconductor memory device 1A. In addition, the definitions of the "drain line" and the "source line" are not limited to the above examples. For example, the definitions of the "drain line" and the "source line" may be opposite to the above examples.

[0039] The insulating portion 23 is provided between the source line SL and the drain line DL adjacent in the Y direction to electrically insulate the adjacent source line SL and drain line DL. From another perspective, the insulating portion 23 is provided between a plurality of pillars 30 (described later) adjacent in the X direction to electrically insulate between the plurality of pillars 30. The insulating portion 23 is formed of an insulating material such as silicon oxide (SiO2).

[0040] The second to fourth functional layers 21B, 21C, and 21D also have the same configuration as the first functional layer 21A. That is, the second to fourth functional layers 21B, 21C, and 21D each include a plurality of source lines SL1 to SL3, a plurality of drain lines DL1 and DL2, and a plurality of insulating portions 23.

[0041] As Figure 1 shown, the source lines SL of the first to fourth functional layers 21A to 21D are arranged at intervals in the Z direction. The drain lines DL of the first to fourth functional layers 21A to 21D are arranged at intervals in the Z direction. In other words, the plurality of source lines SL and the plurality of drain lines DL are arranged at intervals in the Y direction and the Z direction to form a matrix. The source line SL1 included in the second functional layer 21B is an example of a "third source line". The drain line DL1 included in the second functional layer 21B is an example of a "third drain line".

[0042] The insulating layer 22 included in the laminate 20 is provided between two functional layers 21 adjacent in the Z direction. The insulating layer 22 is in a layered form along the X direction and the Y direction. The insulating layer 22 is formed of an insulating material such as silicon oxide (SiO2). The insulating layer 22 electrically insulates the plurality of source lines SL arranged in the Z direction from each other. The insulating layer 22 electrically insulates the plurality of drain lines DL arranged in the Z direction from each other.

[0043] The insulating portion 25 is provided above the uppermost functional layer 21 in the laminate 20. The insulating portion 25 is located at the same height as the upper end portions of the pillars 30 described later. The insulating portion 25 is provided between the plurality of pillars 30 in the X direction and the Y direction.

[0044] <1.3 Pillars>

[0045] Next, the pillar 30 will be described. As Figure 2 shown, the plurality of pillars 30 are arranged in a matrix in the X direction and the Y direction. Each pillar 30 extends through the laminate 20 and the insulating portion 25 in the Z direction (refer to Figure 1 ). The plurality of pillars 30 include, for example, a plurality of first-column pillars 30A, a plurality of second-column second pillars 30B, a plurality of third-column third pillars 30C, and a plurality of fourth-column fourth pillars 30D. In Figure 2 , for ease of explanation, the outer shape of each pillar 30 is shown as a rectangular parallelepiped shape. However, the pillar 30 can also be cylindrical or conical, etc.

[0046] A plurality of pillars 30A in the first column are provided between the source line SL1 and the drain line DL1 in the Y direction. The plurality of pillars 30A in the first column are arranged at intervals in the X direction. A plurality of pillars 30B in the second column are provided between the drain line DL1 and the source line SL2 in the Y direction. The plurality of pillars 30B in the second column are arranged at intervals in the X direction. The plurality of pillars 30B in the second column are arranged at positions shifted in the +X direction with respect to the plurality of pillars 30A in the first column in the X direction. For example, the plurality of pillars 30A in the first column and the plurality of pillars 30B in the second column are arranged such that the pillars 30A included in the first column and the pillars 30B included in the second column are alternately arranged in the X direction.

[0047] A plurality of pillars 30C in the third column are provided between the source line SL2 and the drain line DL2 in the Y direction. The plurality of pillars 30C in the third column are arranged at intervals in the X direction. For example, the plurality of pillars 30A in the first column and the plurality of pillars 30C in the third column are arranged at the same position in the X direction. A plurality of pillars 30D in the fourth column are provided between the drain line DL2 and the source line SL3 in the Y direction. The plurality of pillars 30D in the fourth column are arranged at intervals in the X direction. The plurality of pillars 30D in the fourth column are arranged at positions shifted in the +X direction with respect to the plurality of pillars 30C in the third column in the X direction. For example, the plurality of pillars 30C in the third column and the plurality of pillars 30D in the fourth column are arranged such that the pillars 30C included in the third column and the pillars 30D included in the fourth column are alternately arranged in the X direction. For example, the plurality of pillars 30B in the second column and the plurality of pillars 30D in the fourth column are arranged at the same position in the X direction. In other words, the plurality of pillars 30B in the second column are provided between the plurality of pillars 30A in the first column and the plurality of pillars 30C in the third column in the Y direction, and are arranged at positions different from those of the plurality of pillars 30A in the first column and the plurality of pillars 30C in the third column in the X direction.

[0048] In the present embodiment, each pillar 30 has a gate wiring 31, a blocking insulating film 32, a memory film 33, a tunnel insulating film 34, a semiconductor layer 35, and an upper insulating portion 36 (refer to Figure 1 ).

[0049] The gate wiring 31 extends in the Z direction so as to cover the entire length (entire height) of the column 30 in the Z direction. The gate wiring 31 forms the core of the column 30 (the central portion when observed in the Z direction). The gate wiring 31 is a conductive portion that penetrates the stacked body 20 and the insulating portion 25 in the Z direction. The gate wiring 31 is formed of a conductive material such as polycrystalline silicon (Poly-Si) doped with impurities. In the present embodiment, the "gate wiring" refers to a wiring to which a voltage is applied during a data writing operation or a data reading operation. According to another expression, the gate wiring 31 refers to a wiring to which a voltage is applied in order to change the state of the charge of the charge holding portion 40 described later. The gate wiring 31 is connected to the bit line BL via a contact 80 described later. The gate wiring 31 is an example of the "fourth wiring".

[0050] When observed from the Z direction, the blocking insulating film 32 is formed in a ring shape surrounding the gate wiring 31. The blocking insulating film 32 is provided between the gate wiring 31 and the memory film 33 described later. The blocking insulating film 32 is an insulating film that suppresses reverse tunneling. Reverse tunneling is a phenomenon in which charges return from the gate wiring 31 to the memory film 33 (charge holding portion 40). The blocking insulating film 32 extends in the Z direction so as to cover most of the Z direction of the column 30. The blocking insulating film 32 is, for example, a laminated structure film in which a silicon oxide film, a metal oxide film, and a plurality of insulating films are laminated. An example of the metal oxide is aluminum oxide (Al2O3). The blocking insulating film 32 may also contain a high dielectric constant material (High-k material) such as silicon nitride (SiN) or hafnium oxide (HfO).

[0051] When observed from the Z direction, the memory film 33 is formed in a ring shape surrounding the blocking insulating film 32. In other words, when observed from the Z direction, the memory film 33 is formed in a ring shape surrounding the gate wiring 31. The memory film 33 is provided between the blocking insulating film 32 and the tunnel insulating film 34 described later. In the present embodiment, the memory film 33 extends in the Z direction so as to cover most of the column 30. In the present embodiment, the memory film 33 is a charge trapping film capable of storing charges in crystal defects. The charge trapping film is formed of, for example, silicon nitride (Si3N4).

[0052] In the present embodiment, the memory film 33 includes a plurality of charge holding portions 40 (refer to Figure 1)。Each charge holding part 40 is a region in the memory film 33 at the same height as the source line SL and the drain line DL. In other words, the charge holding part 40 is a region in the memory film 33 arranged in the Y direction with one of the first to fourth functional layers 21A to 21D. The charge holding part 40 is a storage part capable of storing data by maintaining the state of charges (such as the amount of charges or the direction of polarization). When a voltage satisfying a specified condition is applied to the gate wiring 31, the charge holding part 40 changes the state of charges (such as the amount of charges or the direction of polarization). Thereby, the charge holding part 40 stores data non-volatilely. For example, the charge holding part 40 formed of a charge trapping film stores data non-volatilely according to the amount of charges.

[0053] As Figure 2 shown, the charge holding part 40 includes a first part 40a and a second part 40b. The first part 40a of the charge holding part 40 is located on the +X direction side with respect to the gate wiring 31. The first part 40a of the charge holding part 40 is located between the gate wiring 31 and the first part 50a of the channel part 50 described later. On the other hand, the second part 40b of the charge holding part 40 is located on the -X direction side with respect to the gate wiring 31. The second part 40b of the charge holding part 40 is located between the gate wiring 31 and the second part 50b of the channel part 50 described later.

[0054] When viewed from the Z direction, the tunnel insulating film 34 is formed in a ring shape surrounding the memory film 33. In other words, the blocking insulating film 32 is provided between the memory film 33 and the semiconductor layer 35 described later. The tunnel insulating film 34 is a potential barrier between the charge holding part 40 and the semiconductor layer 35. The tunnel insulating film 34 extends in the Z direction so as to cover most of the pillar 30. The tunnel insulating film 34 is formed of an insulating material containing silicon oxide (SiO2), or a mixture of silicon oxide (SiO2) and silicon nitride (SiN).

[0055] When viewed from the Z direction, the semiconductor layer 35 is formed in a ring shape surrounding the tunnel insulating film 34. In other words, the semiconductor layer 35 is provided between the memory film 33 (charge holding part 40) and the insulating part 23, between the memory film 33 (charge holding part 40) and the source line SL, and between the memory film 33 (charge holding part 40) and the drain line DL. In the present embodiment, the semiconductor layer 35 extends in the Z direction so as to cover most of the pillar 30. That is, the semiconductor layer 35 extends in the Z direction along the gate wiring 31. The semiconductor layer 35 is formed of a semiconductor material such as amorphous silicon (a-Si) or polycrystalline silicon (Poly-Si). The semiconductor layer 35 may be doped with impurities. The impurities contained in the semiconductor layer 35 are, for example, any one selected from the group consisting of carbon, phosphorus, boron, and germanium.

[0056] In the present embodiment, the semiconductor layer 35 includes a plurality of channel portions 50 (see Figure 1 ). Each channel portion 50 is a region in the semiconductor layer 35 that is at the same height as the source line SL and the drain line DL. In other words, the channel portion 50 is a region in the semiconductor layer 35 that is arranged in the Y direction with respect to one of the first to fourth functional layers 21A to 21D. The channel portion 50 includes a semiconductor and is in contact with the source line SL and the drain line DL. In the present embodiment, the "channel portion" refers to a region where a channel is formed when a voltage is applied to the gate wiring 31. In the present embodiment, the channel portion 50 is a region through which a current (channel current) flows from the drain line DL toward the source line SL when a prescribed voltage is applied to the gate wiring 31. The channel portion 50 is an example of the "third wiring".

[0057] In the present embodiment, each channel portion 50 includes a first portion 50a and a second portion 50b that are divided on both sides of the gate wiring 31 in the X direction. The first portion 50a is located on the +X direction side with respect to the gate wiring 31. The first portion 50a extends in the Y direction and is in contact with the source line SL and the drain line DL. The first portion 50a is a portion of the channel portion 50 that is arranged in the X direction with the first portion 40a of the charge holding portion 40 and the gate wiring 31. On the other hand, the second portion 50b is located on the side opposite to the first portion 50a with respect to the gate wiring 31 in the X direction. That is, the second portion 50b is located on the -X direction side with respect to the gate wiring 31. The second portion 50b extends in the Y direction and is in contact with the source line SL and the drain line DL. The second portion 50b is a portion of the channel portion 50 that is arranged in the X direction with the second portion 40b of the charge holding portion 40 and the gate wiring 31.

[0058] In the present embodiment, a MANOS (Metal - Al - Nitride - Oxide - Silicon) type memory cell MC is formed by the above-described gate wiring 31, blocking insulating film 32, charge holding portion 40, tunnel insulating film 34, and channel portion 50. As Figure 1 and Figure 2 shown, a plurality of memory cells MC are three-dimensionally arranged at intervals in the X direction, Y direction, and Z direction.

[0059] Next, other structures of the laminate 20 and the pillar 30 will be described. As Figure 1As shown, the gate wiring 31 has a diameter-expanded portion 31a connected to a selection transistor ST (to be described later) at the upper end of the pillar 30. The diameter-expanded portion 31a extends in the X direction and the Y direction, and the dimensions in the X direction and the Y direction are enlarged compared with other portions of the gate wiring 31. The upper end of the semiconductor layer 35 is located on the -Z direction side compared with the diameter-expanded portion 31a of the gate wiring 31. An upper insulating portion 36 is provided above the semiconductor layer 35. The upper insulating portion 36 is provided between the semiconductor layer 35 and the diameter-expanded portion 31a of the gate wiring 31 to electrically insulate the semiconductor layer 35 from the gate wiring 31.

[0060] As Figure 2 shown, the stacked body 20 has an insulating portion STH provided locally in the X direction and the Y direction. The insulating portion STH extends in the Z direction and penetrates the stacked body 20 to reach the semiconductor layer 12. The insulating portion STH is formed by filling a hole provided in the stacked body 20 with an insulating material in a manufacturing process (replacement process) of the semiconductor memory device 1A to be described later. This will be described in detail later.

[0061] <1.4 Upper Structure of Semiconductor Memory Device>

[0062] Next, the upper structure of the semiconductor memory device 1A will be described. As Figure 1 shown, an upper structure body 70 is provided above the insulating portion 25. The upper structure body 70 has, for example, a plurality of selection transistors ST, a plurality of selection gate lines SGL, and an insulating portion 75.

[0063] The selection transistor ST is a vertical transistor located between a contact 80 (to be described later) and the gate wiring 31 of the pillar 30 in the Z direction. The selection transistor ST is a switching element that switches the electrical connection state between the contact 80 and the gate wiring 31 of the pillar 30. The plurality of selection transistors ST are arranged in a matrix in the X direction and the Y direction at positions corresponding to the pillar 30. An insulating portion 75 is provided between the plurality of selection transistors ST (see Figure 1 ). Each selection transistor ST includes, for example, a semiconductor layer 71, an insulating layer 72, a core insulating portion 73, and a gate electrode 74.

[0064] The semiconductor layer 71 extends in the Z direction and is connected to the contact 80 and the gate wiring 31 of the pillar 30. The semiconductor layer 71 is formed of a semiconductor material such as amorphous silicon (a-Si) or polycrystalline silicon (Poly-Si). The semiconductor layer 71 may be doped with impurities. The impurities contained in the semiconductor layer 71 are, for example, any one selected from the group consisting of carbon, phosphorus, boron, and germanium. When a predetermined voltage is applied to the gate electrode 74 (to be described later), the semiconductor layer 71 forms a channel to electrically connect the contact 80 and the gate wiring 31 of the pillar 30. In the present embodiment, the semiconductor layer 71 is annular when viewed from the Z direction.

[0065] The semiconductor layer 71 has a diameter-expanded portion 71a connected to a contact member 80 described later at the upper end of the selection transistor ST. The diameter-expanded portion 71a extends in the X direction and the Y direction, and the dimensions in the X direction and the Y direction are enlarged compared to other portions of the semiconductor layer 71.

[0066] When viewed from the Z direction, the insulating layer 72 is formed in a ring shape surrounding the semiconductor layer 71. At least a part of the insulating layer 72 is located between the semiconductor layer 71 and the gate electrode 74. The insulating layer 72 is formed of an insulating material such as silicon oxide (SiO2). The core insulating portion 73 is provided inside the ring-shaped semiconductor layer 71. The core insulating portion 73 is formed of an insulating material such as silicon oxide (SiO2).

[0067] The gate electrode 74 is arranged in the Y direction with respect to the semiconductor layer 71. In the present embodiment, the selection transistor ST has two gate electrodes 74. The two gate electrodes 74 are arranged at different positions in the Z direction. The gate electrode 74 is integrally provided with a selection gate line SGL described later, for example. In other words, in the selection gate line SGL, the portion arranged in the Y direction with respect to the semiconductor layer 35 functions as the gate electrode 74.

[0068] Figure 3 is along Figure 1 A cross-sectional view taken along the F3 - F3 line of the semiconductor memory device 1A shown. A plurality of selection gate lines SGL (for example, selection gate lines SGL1, SGL2) extend in the X direction, respectively. Each selection gate line SGL is commonly provided for a plurality of selection transistors ST.

[0069] For example, the first selection gate line SGL1 is located between a plurality of selection transistors ST corresponding to a plurality of pillars 30A in the first column and a plurality of selection transistors ST corresponding to a plurality of pillars 30B in the second column in the Y direction. The first selection gate line SGL1 is connected in the Y direction to the gate electrodes 74 of a plurality of selection transistors ST corresponding to a plurality of pillars 30A in the first column and the gate electrodes 74 of a plurality of selection transistors ST corresponding to a plurality of pillars 30B in the second column. When a voltage is applied to the first selection gate line SGL1, a plurality of selection transistors ST corresponding to a plurality of pillars 30A in the first column and a plurality of selection transistors ST corresponding to a plurality of pillars 30B in the second column become conductive states.

[0070] The second selection gate line SGL2 is located in the Y direction between a plurality of selection transistors ST corresponding to the plurality of columns 30C in the third column and a plurality of selection transistors ST corresponding to the plurality of columns 30D in the fourth column. The second selection gate line SGL2 is connected in the Y direction to the gate electrodes 74 of the plurality of selection transistors ST corresponding to the plurality of columns 30C in the third column and the gate electrodes 74 of the plurality of selection transistors ST corresponding to the plurality of columns 30D in the fourth column. When a voltage is applied to the second selection gate line SGL2, the plurality of selection transistors ST corresponding to the plurality of columns 30C in the third column and the plurality of selection transistors ST corresponding to the plurality of columns 30D in the fourth column become conductive states.

[0071] Each contact 80 is provided in the Z direction between the semiconductor layer 71 of the selection transistor ST and a bit line BL described later. The contact 80 connects the semiconductor layer 71 of the selection transistor ST and the bit line BL. The contact 80 is formed of a conductive material such as tungsten (W).

[0072] The plurality of bit lines BL extend in the Y direction. The plurality of bit lines BL include, for example, bit lines BL1 to BL6. Each bit line BL is provided commonly with respect to the plurality of columns 30. For example, the bit line BL1 is provided above one column 30A included in the first column and one column 30C included in the third column, and is connected to the contact 80 corresponding to one column 30A and the contact 80 corresponding to one column 30C. By applying a voltage to the bit line BL1, a voltage is applied to the contact 80 corresponding to one column 30A and the contact 80 corresponding to one column 30C.

[0073] Similarly, the bit lines BL2 to BL6 are each provided commonly with respect to two columns 30. Regarding the description related to the bit lines BL2, BL4, and BL6, it is sufficient to replace "columns 30A, 30C" with "columns 30B, 30D" in the above description related to the bit line BL1. On the other hand, regarding the description related to the bit lines BL3 and BL5, it is sufficient to replace "columns 30A, 30C" with "columns 30A, 30C" as it is in the above description related to the bit line BL1. The bit line BL1 is an example of the "first bit line". The bit line BL3 is an example of the "second bit line". One selection transistor ST corresponding to the bit line BL1 is an example of the "first selection transistor". Another selection transistor ST corresponding to the bit line BL1 is an example of the "third selection transistor". One selection transistor ST corresponding to the bit line BL3 is an example of the "second selection transistor".

[0074] As described above, the configuration of the semiconductor memory device 1A has been explained. The charge holding part 40 and the channel part 50 included in the pillar 30A at the height corresponding to the first functional layer 21A are examples of the "first charge holding part" and the "first channel part". The gate wiring 31 included in the above pillar 30A is an example of the "first gate wiring". The charge holding part 40 and the channel part 50 included in the other pillar 30A at the height corresponding to the first functional layer 21A are examples of the "second charge holding part" and the "second channel part". The gate wiring 31 included in the above other pillar 30A is an example of the "second gate wiring".

[0075] The charge holding part 40 and the channel part 50 included in the pillar 30B at the height corresponding to the first functional layer 21A are examples of the "third charge holding part" and the "third channel part". The gate wiring 31 included in the above pillar 30B is an example of the "third gate wiring". The charge holding part 40 and the channel part 50 included in the other pillar 30B at the height corresponding to the first functional layer 21A are examples of the "fourth charge holding part" and the "fourth channel part". The gate wiring 31 included in the above other pillar 30B is an example of the "fourth gate wiring".

[0076] The charge holding part 40 and the channel part 50 included in the pillar 30A at the height corresponding to the second functional layer 21B are examples of the "fifth charge holding part" and the "fifth channel part".

[0077] <2. Operation of the semiconductor memory device>

[0078] Next, the operation of the semiconductor memory device 1A will be explained. Figure 4 It is a cross-sectional view showing the operation of the semiconductor memory device 1A. In the semiconductor memory device 1A, any memory cell MC can be selected as an object for data writing or data reading by combining the select gate line SGL and the bit line BL.

[0079] In Figure 4In the example shown, a voltage is applied to the select gate line SGL2 and a voltage is applied to the bit line BL5. In this case, a voltage is applied to the gate wiring 31 of one column 30 (hereinafter referred to as "select column S") corresponding to the intersection of the select gate line SGL2 and the bit line BL5. As a result, a channel is formed in the channel portion 50 of the select column S, and the current I flows from the drain line DL2 adjacent to the select column S to the source line SL2. For example, the current I flows separately through the first portion 50a and the second portion 50b of the channel portion 50. On the other hand, a channel is not formed in the channel portion 50 of the columns 30 other than the select column S (hereinafter referred to as "non-select columns NS"). As a result, the electrical insulation state between the drain line DL and the source line SL adjacent to the non-select column NS can be maintained.

[0080] The semiconductor memory device 1A of the present embodiment uses the above operation to perform a data writing operation and a data reading operation on the memory cell MC. For example, in the writing operation, the peripheral circuit of the semiconductor memory device 1A selects only the column 30 corresponding to the memory cell MC to be written as the select column S. Then, the peripheral circuit applies a programming pulse to the gate wiring 31 of the select column S via the bit line BL. The programming pulse is a pulse in which the voltage gradually increases for each cycle. As a result, a current flows through the channel portion 50 corresponding to the memory cell MC to be written, and charges are accumulated in the charge holding portion 40 of the memory cell MC to be written. As a result, the threshold voltage of the charge holding portion 40 rises. The sense amplifier circuit SA determines for each cycle of the programming pulse whether the threshold voltage of the memory cell MC to be written has reached a voltage preset according to the data to be written (hereinafter referred to as "write data"). The peripheral circuit continues to apply the programming pulse based on the determination result of the sense amplifier circuit SA until the threshold voltage of the memory cell MC reaches a voltage corresponding to the write data. In the above writing operation, a predetermined voltage is applied to the drain line DL of the functional layer 21 of the memory cell MC that does not include the memory cell MC to be written. As a result, no current flows through the channel portion 50 corresponding to the memory cell MC other than the memory cell MC to be written.

[0081] On the other hand, in the reading operation, the sense amplifier circuit SA precharges the power supply potential Vcc to the drain line DL adjacent to the memory cell MC to be read. The peripheral circuit selects the column 30 corresponding to the memory cell MC to be read as the select column S. Then, the peripheral circuit sequentially applies a variety of determination potentials (threshold determination voltages) for determining the threshold voltage of the memory cell MC to the gate wiring 31 of the select column S. The sense amplifier circuit SA determines the data stored in the memory cell MC to be read by detecting when the charge precharged flows out to the source line SL when a certain determination voltage is applied.

[0082] <3. Manufacturing Method of Semiconductor Memory Device>

[0083] Next, a manufacturing method of the semiconductor memory device 1A will be described. Figures 5 to 8 It is a cross-sectional view showing the manufacturing method of the semiconductor memory device 1A. In addition, the materials described below are merely examples and do not limit the content of this embodiment.

[0084] As Figure 5 shown in (a) of [], an insulating layer 11 and a semiconductor layer 12 are formed on the silicon substrate 10. Next, on the semiconductor layer 12, an insulating layer 22 formed of silicon oxide (SiO2) and an insulating layer 91 formed of silicon nitride (SiN) are alternately stacked. Thus, an intermediate laminate 20A is formed. The insulating layer 91 is a sacrificial layer that will be replaced with a functional layer 21 in a subsequent process. Next, an insulating portion 25 is provided on the intermediate laminate 20A. Next, a mask M1 is provided on the intermediate laminate 20A and the insulating portion 25. Next, a memory trench MT is provided by etching using the mask M. The memory trench MT is a groove that is dug in the Z direction and extends in the X direction. In this embodiment, by providing the semiconductor layer 12, it is possible to suppress the memory trench MT from being overly deeply dug.

[0085] Next, as Figure 5 shown in (b) of [], the memory trench MT is filled with an insulating material 92 that is silicon oxide (SiO2). This insulating material 92 forms an insulating portion 23 located between the plurality of pillars 30 in a subsequent process (refer to Figure 2 ).

[0086] Next, as Figure 5 shown in (c) of [], a memory hole MH is provided by etching at a position where the pillar 30 will be formed in a subsequent process. The memory hole MH is a hole that extends in the Z direction.

[0087] Next, as Figure 5 shown in (d) of [], materials for the semiconductor layer 35, the tunnel insulating film 34, the memory film 33, and the blocking insulating film 32 are sequentially supplied to the inner surface of the memory hole MH. Thus, the semiconductor layer 35, the tunnel insulating film 34, the memory film 33, and the blocking insulating film 32 are formed. Next, polysilicon (Poly-Si) is supplied to the inside of the blocking insulating film 32 and doped with impurities. Thus, the gate wiring 31 is formed. Next, the upper end portion of the gate wiring 31 is removed by etching.

[0088] Next, as Figure 6 shown in (e) of [], unnecessary portions of the semiconductor layer 35, the tunnel insulating film 34, the memory film 33, and the blocking insulating film 32 are removed by etching. Next, as Figure 6As shown in (f) in [the figure], silicon nitride (SiN) is supplied onto the semiconductor layer 35, the tunnel insulating film 34, the memory film 33, the barrier insulating film 32, and the gate wiring 31 to form the upper insulating portion 93. Next, a mask M2 for removing the central portion of the upper insulating portion 93 is provided. Next, the central portion of the upper insulating portion 93 is removed by etching using the mask M2. Thus, the upper insulating portion 36 is formed.

[0089] Next, as Figure 6 shown in (g) in [the figure], amorphous silicon (a-Si) is supplied to form the enlarged diameter portion 31a of the gate wiring 31. Next, an insulating layer 101 formed of silicon oxide (SiO2) and an insulating layer 102 formed of silicon nitride (SiN) are alternately laminated. Thus, the intermediate laminate 100 is formed. The insulating layer 101 forms the insulating portion 75 in a subsequent process. The insulating layer 102 is a sacrificial layer that is replaced with the gate electrode 74 of the selection transistor ST and the selection gate line SGL in a subsequent process. Next, as Figure 6 shown in (h) in [the figure], unnecessary portions of the intermediate laminate 100 are removed.

[0090] Next, as Figure 7 shown in (i) in [the figure], an insulating material that is silicon oxide (SiO2) is supplied to the region from which the unnecessary portions of the intermediate laminate 100 have been removed to form the insulating portion 105. Next, as Figure 7 shown in (j) in [the figure], holes 106 for providing the semiconductor layer 71, the insulating layer 72, and the core insulating portion 73 of the selection transistor ST are formed in the intermediate laminate 100 and the insulating portion 105.

[0091] Next, as Figure 7 shown in (k) in [the figure], the material of the insulating layer 72 and the material of the semiconductor layer 71 of the selection transistor ST are supplied to the inner peripheral surface of the hole 106. Thus, the insulating layer 72 and the semiconductor cover layer 71b are formed. The semiconductor cover layer 71b is a protective layer for protecting the insulating layer 72. Next, using a mask (not shown), holes are provided at the bottom of the insulating layer 72 and the semiconductor cover layer 71b.

[0092] Next, as Figure 7 shown in (l) in [the figure], the material of the semiconductor layer 71 and the material of the core insulating portion 73 are supplied to the inner surface of the hole 106 to form the semiconductor layer 71 and the core insulating portion 73. Next, as Figure 8 shown in (m) in [the figure], unnecessary portions of the insulating layer 72 and the semiconductor layer 71 are removed. Next, as Figure 8 shown in (n) in [the figure], the upper end portion of the insulating layer 72 is removed to form the enlarged diameter portion 71a of the semiconductor layer 71.

[0093] Next, as Figure 8As shown in (l) in [description], an insulating portion 107 is provided on the selection transistor ST. Next, an unillustrated hole that penetrates the intermediate laminate 20A, the insulating portion 25, and the intermediate laminate 100 in the Z direction is provided, and silicon nitride (SiN) forming the insulating layers 91 and 102 is removed through this hole. Next, a conductive material such as tungsten (W) is supplied to the space from which the insulating layers 91 and 102 have been removed, and the source line SL, the drain line DL, the gate electrode 74, and the selection gate line SGL are formed. Next, as Figure 8 shown in (o) in [description], a contact 80 is provided on the insulating portion 107. Then, the bit line BL is provided. Thus, the semiconductor memory device 1A is completed.

[0094] <4. Advantages>

[0095] As a comparative example, consider a semiconductor memory device having a laminate in which an insulating film and a word line are alternately laminated in the thickness direction of a substrate, and a channel portion that penetrates the laminate in the thickness direction of the substrate. In such a semiconductor memory device, as the number of laminations increases, the length of the channel portion becomes longer. As a result, the read current decreases, and the noise during the read operation increases. Therefore, sometimes the read time required for reading data becomes longer.

[0096] In addition, in the semiconductor memory device of the above comparative example, sequential reading is fast, but reading takes time in random reading. Sequential reading means reading in units of word lines. On the other hand, random reading means an operation of reading data from a plurality of arbitrary memory cells that are not a specific wiring unit.

[0097] On the other hand, the semiconductor memory device of the present embodiment includes: a source line SL and a drain line DL extending in a direction along the surface of the silicon substrate 10; a channel portion 50 provided between the source line SL and the drain line DL; a gate wiring 31 extending in the thickness direction of the silicon substrate 10 and arranged with the channel portion 50; and a charge holding portion 40 provided between the channel portion 50 and the gate wiring 31. According to such a configuration, the channel portion 50 is formed in a direction parallel to the surface of the silicon substrate 10, and the length of the channel portion 50 becomes shorter. As a result, a decrease in the read current and noise during the read operation can be suppressed. Therefore, shortening of the read time can be achieved.

[0098] In the present embodiment, the channel portion 50 includes a first portion 50a and a second portion 50b that are divided on both sides of the gate wiring 31. The charge holding portion 40 includes a first portion 40a located between the first portion 50a of the channel portion 50 and the gate wiring 31 and a second portion 40b located between the second portion 50b of the channel portion 50 and the gate wiring 31. According to such a configuration, two paths through which the channel current flows to one gate wiring 31 can be ensured, and thus data writing and data reading can be performed more stably.

[0099] As Figure 2 shown, the semiconductor memory device 1A has a channel portion 50 and a charge holding portion 40 included in one pillar 30A, and a channel portion 50 and a charge holding portion 40 included in other pillars 30A. These channel portions 50 are connected in parallel to the same source line SL and drain line DL. According to such a configuration, even when performing random readout, it is possible to access the memory cell MC in a shorter readout time. Thus, readout can be performed with low latency.

[0100] (Second Embodiment)

[0101] Next, the second embodiment will be described. The difference between the second embodiment and the first embodiment is that the semiconductor layer 35 is not included in the pillar 30B, and the semiconductor layer 35 is segmented into several in the Z direction. The configuration other than the following description is the same as that of the first embodiment.

[0102] Figure 9 is a cross-sectional view showing the semiconductor memory device 1B of the second embodiment. In the present embodiment, the pillar 30B includes a gate wiring 31, a blocking insulating film 32, a memory film 33, and a tunnel insulating film 34, but does not include the semiconductor layer 35. In the present embodiment, the semiconductor layer 35 is provided in a region arranged in the Y direction with the source line SL and the drain line DL.

[0103] In other words, a part of the insulating layer 22B is provided between the channel portion 50 corresponding to the first functional layer 21A and the channel portion 50 corresponding to the second functional layer 21B. Similarly, a part of the insulating layer 22C is provided between the channel portion 50 corresponding to the second functional layer 21B and the channel portion 50 corresponding to the third functional layer 21C. A part of the insulating layer 22D is provided between the channel portion 50 corresponding to the third functional layer 21C and the channel portion 50 corresponding to the fourth functional layer 21D.

[0104] Figure 10 And Figure 11 is a cross-sectional view showing the manufacturing method of the semiconductor memory device 1B of the second embodiment. As Figure 10As shown in (a) of FIG. 0, an insulating layer 11 and a semiconductor layer 12 are formed on a silicon substrate 10. Next, an insulating layer 22 formed of silicon oxide (SiO2) and an insulating layer 91 formed of silicon nitride (SiN) are alternately stacked on the semiconductor layer 35. Thus, an intermediate laminate 20A is formed. The insulating layer 91 is a sacrificial layer that is replaced with a functional layer 21 in a later process. Next, an insulating portion 25 is provided on the intermediate laminate 20A. Next, a mask MB is provided on the insulating portion 25. Next, a memory hole MH is formed by etching using the mask MB. In the present embodiment, it is different from the first embodiment in that a memory hole MH is formed without forming a memory trench MT.

[0105] Next, as Figure 10 shown in (b) of FIG. 0, the end portions of the insulating layer 91 exposed in the memory hole MH in the intermediate laminate 20A are removed by etching. Thus, a recess 111 is formed between the plurality of insulating layers 22. Next, as Figure 10 shown in (c) of FIG. 0, the material of the semiconductor layer 35 is supplied to the inner surface of the memory hole MH. Next, the unnecessary portions of the supplied material of the semiconductor layer 35 are removed by etching. Thus, an intermediate laminate 20A having a channel portion 50 provided in the recess 111 between the plurality of insulating layers 22 can be obtained. The plurality of channel portions 50 arranged in the Z direction are segmented by the insulating layer 22.

[0106] Next, as Figure 10 shown in (d) of FIG. 0, the material of the tunnel insulating film 34, the material of the memory film 33, and the material of the blocking insulating film 32 are sequentially stacked on the inner surface of the memory hole MH. Thus, the tunnel insulating film 34, the memory film 33, and the blocking insulating film 32 are formed. Next, polysilicon (Poly-Si) is provided inside the blocking insulating film 32 and doped with impurities. Thus, the gate wiring 31 is formed. Next, the upper end portion of the gate wiring 31 is removed by etching.

[0107] Next, as Figure 11 shown in (e) of FIG. 0, the unnecessary portions of the tunnel insulating film 34, the memory film 33, and the blocking insulating film 32 are removed by etching. Next, as Figure 11 shown in (f) of FIG. 0, amorphous silicon (a-Si) is supplied to form a diameter-expanded portion 31a of the gate wiring 31. Next, as Figure 11 shown in (g) of FIG. 0, in the X direction, holes 112 extending in the Z direction are provided in the region between adjacent columns 30B. Next, as Figure 11 shown in (h) of FIG. 0, an insulating material that is silicon oxide (SiO2) is supplied to the holes 112 to form an insulating portion 113. The insulating portion 113 includes the insulating portion 23 described in the first embodiment.

[0108] With such a configuration, a semiconductor memory device 1B capable of shortening the readout time can also be provided in the same manner as in the first embodiment. In the present embodiment, the semiconductor layer 35 is segmented in the Z direction, and a channel portion 50 is provided in a region where the source line SL and the drain line DL are arranged. With such a configuration, the influence of the edge electric field becomes smaller than in the case where the semiconductor layer 35 is connected in the Z direction. As a result, the data writing operation and the data readout operation are more stable.

[0109] (Third Embodiment)

[0110] Next, the third embodiment will be described. The difference between the third embodiment and the first embodiment is that, in addition to the semiconductor layer 35, the memory film 33 and the tunnel insulating film 34 are segmented in the Z direction. The configuration of the third embodiment other than the following description is the same as that of the first embodiment.

[0111] Figure 12 FIG. is a cross-sectional view of the semiconductor memory device 1C according to the third embodiment, showing an enlarged portion related to the memory cell MC. In the present embodiment, the semiconductor memory device 1C has, for example, a plurality of columns 30C (only one is shown in the figure), a plurality of charge holding portions 40, a plurality of tunnel insulating films 34C, and a plurality of channel portions 50.

[0112] Each column 30C has a gate wiring 31 and a barrier insulating film 32. The configurations of the gate wiring 31 and the barrier insulating film 32 are the same as those in the first embodiment. That is, the barrier insulating film 32 extends in the Z direction along the gate wiring 31.

[0113] On the other hand, the charge holding portion 40, the tunnel insulating film 34C, and the channel portion 50 are provided between two insulating layers 22 adjacent in the Z direction. That is, the charge holding portion 40, the tunnel insulating film 34C, and the channel portion 50 are insulated for each functional layer 21. In the present embodiment, the channel portion 50 has a region (i.e., Figure 12 the upper end portion and the lower end portion of the channel portion 50 in, which will be hereinafter referred to as "specific regions") that does not overlap with the charge holding portion 40 in the Y direction and the X direction. In the Y direction and the X direction, a tunnel insulating film 34C is provided between the specific region of the channel portion 50 and the barrier insulating film 32. Thus, the channel portion 50 is provided separately from the barrier insulating film 32 and does not contact the barrier insulating film 32.

[0114] Figure 13 is a cross-sectional view along the Figure 12 F13 - F13 line of the semiconductor memory device 1C shown. As Figure 13 shown, the charge holding portion 40, the tunnel insulating film 34C, and the channel portion 50 are formed in a ring shape surrounding the gate wiring 31.

[0115] According to such a configuration, it is also possible to provide the semiconductor memory device 1C that can achieve a shortening of the readout time, similarly to the first embodiment.

[0116] (Fourth Embodiment)

[0117] Next, the fourth embodiment will be described. The fourth embodiment is different from the first embodiment in that the memory cell MC has the charge holding portion 40D as a floating gate electrode. The configuration of the fourth embodiment other than the following description is the same as the configuration of the first embodiment.

[0118] Figure 14 FIG. is a cross-sectional view of the semiconductor memory device 1D showing the fourth embodiment, and is an enlarged view showing a portion related to the memory cell MC. In the present embodiment, the semiconductor memory device 1D has, for example, a plurality of columns 30D (only one is shown in the figure), a plurality of charge holding portions 40D, a plurality of tunnel insulating films 34D, and a plurality of channel portions 50.

[0119] Each column 30D has a gate wiring 31 and a blocking insulating film 32. The configurations of the gate wiring 31 and the blocking insulating film 32 are the same as those of the first embodiment. That is, the blocking insulating film 32 extends in the Z direction along the gate wiring 31.

[0120] On the other hand, the charge holding portion 40D, the tunnel insulating film 34D, and the channel portion 50 are provided between two insulating layers 22 adjacent in the Z direction. That is, the charge holding portion 40D, the tunnel insulating film 34D, and the channel portion 50 are insulated for each functional layer 21. The charge holding portion 40D is a floating gate electrode and stores data according to the amount of accumulated charge. In the present embodiment, the channel portion 50 has a region (i.e., Figure 14 the upper end portion and the lower end portion of the channel portion 50 in, which are hereinafter referred to as "specific regions") that does not overlap with the charge holding portion 40 in the Y direction and the X direction. In the Y direction and the X direction, a tunnel insulating film 34D is provided between the specific region of the channel portion 50 and the blocking insulating film 32. Thus, the channel portion 50 is provided separately from the blocking insulating film 32 and does not contact the blocking insulating film 32.

[0121] According to such a configuration, it is also possible to provide the semiconductor memory device 1D that can achieve a shortening of the readout time, similarly to the first embodiment.

[0122] (Fifth Embodiment)

[0123] Next, the fifth embodiment will be described. The fifth embodiment is different from the first embodiment in that the memory cell MC has the charge holding portion 40E as a ferroelectric body. The configuration other than the following description is the same as the configuration of the first embodiment.

[0124] Figure 15 This is a cross-sectional view of the semiconductor memory device 1E showing the fifth embodiment, with an enlarged view of the portion related to the memory cell MC. In this embodiment, the semiconductor memory device 1E has, for example, a plurality of pillars 30E and a plurality of channel portions 50. The channel portion 50 is the same as that in the second embodiment and is provided between two insulating layers 22 adjacent in the Z direction.

[0125] Each pillar 30E has a gate wiring 31 and a memory film 33E. The memory film 33E extends in the Z direction along the gate wiring 31. When viewed from the Z direction, the memory film 33E is formed in a ring shape surrounding the gate wiring 31. The memory film 33E is provided between the gate wiring 31 and the channel portion 50. In this embodiment, the memory film 33E extends in the Z direction so as to cover most of the pillar 30E. In this embodiment, the memory film 33E is a ferroelectric film constituting a ferroelectric memory (FeFET: Ferroelectric Field Effect Transistor). The charge holding portion 40E formed of the ferroelectric film stores data according to the direction of polarization (polarization inversion state). The ferroelectric film is formed of a high dielectric constant material such as hafnium oxide (HfO).

[0126] In this embodiment, the memory film 33E includes a plurality of charge holding portions 40E. Each charge holding portion 40E is a region in the memory film 33E that is at the same height as the source line SL and the drain line DL. In other words, the plurality of charge holding portions 40E are regions in the memory film 33E that are arranged in the Y direction with the first to fourth functional layers 21A to 21D. The charge holding portion 40E is a storage portion that can store data by maintaining the state of charge (e.g., the direction of polarization). When a voltage satisfying a specified condition is applied to the gate wiring 31, the charge holding portion 40E changes the state of charge (e.g., the direction of polarization). Thereby, the charge holding portion 40E stores data non-volatilely.

[0127] According to such a configuration, it is also possible to provide the semiconductor memory device 1E that can achieve a shortening of the readout time in the same manner as in the first embodiment. Here, a ferroelectric memory can be expected to operate at high speed under a constant voltage, but the tolerance to interference becomes an issue. However, in this embodiment, since no current flows through the channel portion 50 of the memory cell MC other than the write target or the read target, the problem of interference is less likely to occur. Thereby, the reliability of the semiconductor memory device 1E using a ferroelectric memory can be improved.

[0128] In addition, in the present embodiment, the charge holding unit 40E may also be provided between two adjacent insulating layers 22 in the Z direction in the same manner as in the third embodiment. On the other hand, the channel unit 50 may be formed of a semiconductor layer 35 extending in the Z direction in the same manner as in the first embodiment.

[0129] According to at least one of the above-described embodiments, the semiconductor memory device includes a substrate, a first wiring, a second wiring, a third wiring, a fourth wiring, and a charge holding unit. The first wiring extends in a first direction along the surface of the substrate. The second wiring is arranged with the first wiring in a second direction intersecting the first direction and extends in the first direction. The third wiring is connected to the first wiring and the second wiring and includes a semiconductor. The fourth wiring is located between the first wiring and the second wiring, extends in a third direction intersecting the first direction and the second direction, and is arranged with the third wiring at least in the first direction. The charge holding unit is located between the third wiring and the fourth wiring. With such a configuration, it is possible to shorten the readout time.

[0130] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Claims

1. A semiconductor memory device, wherein, Comprising: A substrate; A first source line extending in a first direction along the surface of the substrate; A first drain line juxtaposed with the first source line in a second direction intersecting the first direction and extending in the first direction; A first channel portion connected to the first source line and the first drain line and containing a semiconductor; A first gate wiring located between the first source line and the first drain line, extending in a third direction intersecting the first direction and the second direction, and juxtaposed with the first channel portion at least in the first direction; A first charge holding portion located between the first channel portion and the first gate wiring; A second channel portion located at a position spaced from the first channel portion in the first direction, connected to the first source line and the first drain line, and containing a semiconductor; A second gate wiring located between the first source line and the first drain line, extending in the third direction, and juxtaposed with the second channel portion at least in the first direction; And A second charge holding portion located between the second channel portion and the second gate wiring.

2. The semiconductor memory device according to claim 1, wherein The first channel portion includes a first part and a second part, the first part being juxtaposed with the first gate wiring in the first direction, and the second part being located on the side opposite to the first part with respect to the first gate wiring in the first direction; The first charge holding portion includes a first part and a second part, the first part being located between the first part of the first channel portion and the first gate wiring, and the second part being located between the second part of the first channel portion and the first gate wiring.

3. The semiconductor memory device according to claim 2, wherein The first charge holding portion is in a ring shape surrounding the first gate wiring.

4. The semiconductor memory device according to claim 1, wherein The semiconductor memory device further comprises: A first bit line located on the side opposite to the substrate with respect to the first gate wiring and extending in the second direction; A second bit line located on the side opposite to the substrate with respect to the second gate wiring and extending in the second direction; A first selection transistor located between the first gate wiring and the first bit line; And A second selection transistor located between the second gate wiring and the second bit line.

5. The semiconductor memory device according to claim 4, wherein The semiconductor memory device further comprises a selection gate line extending in the first direction and connected to the gate electrode of the first selection transistor and the gate electrode of the second selection transistor.

6. The semiconductor memory device according to any one of claims 1 to 3, wherein The semiconductor memory device further comprises: A second source line located on the side opposite to the first source line in the second direction with respect to the first drain line and extending in the first direction; A second drain line, which is located on a side opposite to the first drain line in the second direction with respect to the second source line and extends in the first direction; A third channel portion, which is connected to the second source line and the second drain line and includes a semiconductor; A third gate wiring, which is located between the second source line and the second drain line, extends in the third direction, and is at least juxtaposed with the third channel portion in the first direction; And A third charge holding portion, which is located between the third channel portion and the third gate wiring.

7. The semiconductor memory device according to claim 6, wherein The semiconductor memory device further includes: A fourth channel portion, which is located at a position away from the third channel portion in the first direction, is connected to the second source line and the second drain line, and includes a semiconductor; A fourth gate wiring, which is located between the second source line and the second drain line, extends in the third direction, and is at least juxtaposed with the fourth channel portion in the first direction; And A fourth charge holding portion, which is located between the fourth channel portion and the fourth gate wiring.

8. The semiconductor memory device according to claim 7, wherein The semiconductor memory device further includes: A first bit line, which is located on a side opposite to the substrate with respect to the first gate wiring and the third gate wiring and extends in the second direction; A first selection transistor, which is located between the first gate wiring and the first bit line; And A third selection transistor, which is located between the third gate wiring and the first bit line.

9. The semiconductor memory device according to any one of claims 1 to 3, wherein The semiconductor memory device further includes: A third source line, which is located at a position away from the first source line in the third direction, extends in the first direction, and is juxtaposed with the first gate wiring in the second direction; A third drain line, which is located at a position away from the first drain line in the third direction, extends in the first direction, and is juxtaposed with the first gate wiring in the second direction; A fifth channel portion, which is connected to the third source line and the third drain line, includes a semiconductor, and is at least juxtaposed with the first gate wiring in the first direction; And A fifth charge holding portion, which is located between the fifth channel portion and the first gate wiring.

10. The semiconductor memory device according to claim 9, wherein The semiconductor memory device includes a semiconductor layer, which extends in the third direction along the first gate wiring, The semiconductor layer includes the first channel portion and the fifth channel portion.

11. The semiconductor memory device according to claim 9, wherein The semiconductor memory device further includes an insulating layer, which is provided between the first channel portion and the fifth channel portion in the third direction and disconnects the first channel portion and the fifth channel portion.

12. A semiconductor memory device, wherein, Comprising: A substrate; A first wiring, which extends in a first direction along the surface of the substrate; A second wiring, which is juxtaposed with the first wiring in a second direction intersecting the first direction and extends in the first direction; A third wiring, connected to the first wiring and the second wiring, and including a semiconductor; A fourth wiring, located between the first wiring and the second wiring, extending in a third direction intersecting the first direction and the second direction, and at least being juxtaposed with the third wiring in the first direction; A first charge holding portion, located between the third wiring and the fourth wiring; A plurality of first wirings, extending in the first direction; A plurality of second wirings, extending in the first direction; A plurality of third wirings, respectively connected to one of the plurality of first wirings and one of the plurality of second wirings, and including a semiconductor; A plurality of fourth wirings, respectively located between one of the plurality of first wirings and one of the plurality of second wirings, and extending in the third direction; And A second charge holding portion, The second charge holding portion is located between one of the plurality of third wirings and one of the plurality of fourth wirings, and is juxtaposed with the first charge holding portion in the first direction.

13. The semiconductor memory device according to claim 12, wherein, The semiconductor memory device further includes a third charge holding portion, The plurality of first wirings include two or more first wirings arranged in the second direction, The plurality of second wirings include two or more second wirings arranged in the second direction, The third charge holding portion is located between one of the plurality of third wirings and one of the plurality of fourth wirings, and is juxtaposed with the first charge holding portion in the second direction.

14. The semiconductor memory device according to claim 12 or 13, wherein, The semiconductor memory device further includes a fourth charge holding portion, The plurality of first wirings include two or more first wirings arranged in the third direction, The plurality of second wirings include two or more second wirings arranged in the third direction, The fourth charge holding portion is located between one of the plurality of third wirings and one of the plurality of fourth wirings, and is juxtaposed with the first charge holding portion in the third direction.

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