Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device includes a stacked body comprising: insulating layers and conductive layers containing molybdenum alternately stacked; an aluminum oxide layer disposed between the insulating and conductive layers; and a protective layer, contacting the aluminum oxide layer, containing any one of carbon, nitrogen, and sulfur bonded to aluminum in the aluminum oxide layer and contacting the conductive layer. The stacked body includes an insulator disposed within the insulating and conductive layers, the insulator contacting a portion of the insulating layer, a portion of the aluminum oxide layer, a portion of the protective layer, and a portion of the conductive layer.

Description

[0001] This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2020-154872, filed on September 15, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of the present disclosure relate to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0003] A three-dimensional memory device is proposed, which is constructed by arranging multiple memory cells in a three-dimensional manner. The three-dimensional memory device includes a stack of alternating insulating films and conductive films, and a columnar semiconductor layer arranged in the stacking direction of the stack. The memory cells are arranged between the conductive films of the stack and the columnar semiconductor layer. Summary of the Invention

[0004] The semiconductor device and the method for manufacturing the semiconductor device according to the embodiments of the present disclosure can improve the reliability and productivity of the semiconductor device.

[0005] A semiconductor device according to one embodiment comprises a stack comprising: an insulating layer and a conductive layer containing molybdenum alternately stacked; an aluminum oxide layer disposed between the insulating layer and the conductive layer; and a protective layer in contact with the aluminum oxide layer, comprising any one of carbon, nitrogen, and sulfur bonded to aluminum in the aluminum oxide layer, and in contact with the conductive layer.

[0006] In a method for manufacturing a semiconductor device involved in one embodiment, an insulating layer is formed on a substrate, an aluminum oxide layer is formed on the insulating layer, a first gas containing any one of carbon, nitrogen and sulfur is supplied to the aluminum oxide layer, and after supplying the first gas, a material gas containing molybdenum and a reducing gas for reducing the material gas are further supplied to form a conductive layer containing the molybdenum.

[0007] According to the above-described configuration, the reliability and productivity of the semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a perspective view showing a semiconductor device according to one embodiment.

[0009] Figure 2 is a cross-sectional view showing a semiconductor device according to one embodiment.

[0010] Figure 3 is a cross-sectional view showing a semiconductor device according to one embodiment.

[0011] Figure 4 is a cross-sectional view showing a semiconductor device according to one embodiment.

[0012] Figure 5 is a cross-sectional view showing a semiconductor device according to one embodiment.

[0013] Figure 6 This is a flowchart showing a method for manufacturing a semiconductor device according to one embodiment.

[0014] Figure 7 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0015] Figure 8 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0016] Figure 9 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0017] Figure 10 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0018] Figure 11 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0019] Figure 12 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0020] Figure 13 This is a diagram showing the first principle calculation results of the adsorption energy of gas adsorbed on the surface of each material and the desorption energy of gas desorbed from the surface of each material.

[0021] Figure 14 This is a diagram showing calculation results of the crystal state of the insulating layer when a gas containing hydrogen is supplied.

[0022] Figure 15 This is a diagram showing the first principle calculation results of the desorption energy of gas desorbed from the insulating layer.

[0023] Figure 16 A diagram showing calculation results of the crystal state when a carbon-containing gas is supplied and calculation results of the crystal state when a raw material gas is supplied.

[0024] Figure 17A diagram for explaining the relationship between a film formation cycle and a film thickness in a method for manufacturing a semiconductor device according to an embodiment and a method for manufacturing a semiconductor device without using the method for manufacturing a semiconductor device according to an embodiment.

[0025] Figure 18 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0026] Figure 19 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0027] Figure 20 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0028] Figure 21 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0029] Figure 22 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0030] Figure 23 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0031] Figure 24 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment.

[0032] Figure 25 These are diagrams for explaining a method for manufacturing a semiconductor device according to one embodiment. DETAILED DESCRIPTION

[0033] Hereinafter, the semiconductor device and the method for manufacturing the semiconductor device according to the present embodiment will be described in detail with reference to the accompanying drawings. In the following description, elements having substantially the same function and structure are sometimes given the same reference numeral or a reference numeral with letters appended after the same reference numeral (a, b, A, B, etc. are given after the numbers), and detailed descriptions are appropriately omitted. In addition, the words "first" and "second" appended to each element are used to distinguish each element for the purpose of convenience of description, and have no other meaning unless otherwise specified. The embodiments shown below are examples of embodiments of devices and methods for concretizing the technical ideas of the embodiments, and do not specify the materials, shapes, structures, configurations, etc. of the constituent elements as the following materials, shapes, structures, configurations, etc. The technical ideas of the embodiments include technical solutions obtained by making various changes to the technical solutions described in the claims.

[0034] Furthermore, the semiconductor device and the semiconductor device's vertical direction in this embodiment represent relative directions with the surface of the substrate on which the memory cells are provided being the top. Thus, for ease of explanation, the terms "above" and "below" are used, but, for example, the vertical relationship between the substrate and the memory cells may be reversed from that shown. Furthermore, in the following description, for example, the reference to a memory cell on a substrate merely illustrates the vertical relationship between the substrate and the memory cells, and other components may be disposed between the substrate and the memory cells.

[0035] The following embodiments illustrate examples of semiconductor devices applied to nonvolatile memories including multiple memory cells. The disclosed technology can also be applied to semiconductor devices other than nonvolatile memories (e.g., CPUs, displays, and interposers).

[0036] <Overall Structure of Semiconductor Device 100 >

[0037] use Figures 1 to 5 The overall structure of the semiconductor device 100 according to this embodiment will be described. Figure 1 It is a perspective view showing a semiconductor device 100 according to this embodiment. Figure 2 Yes Figure 1 1 is a cross-sectional view of the semiconductor device 100 taken along the Y direction and the Z direction. Figure 3 It means Figure 2 The illustrated embodiment is a cross-sectional view of an enlarged cross section of a stacked body 2 included in the semiconductor device 100 . Figure 4 Yes Figure 2 1 is a cross-sectional view of a memory hole MH included in the semiconductor device 100 taken along the X direction and the Y direction. Figure 5 It means Figure 3 The cross-sectional view of the cross section obtained by enlarging the region 110 shown in FIG. In this embodiment, the stacking direction of the stacked body 2 is defined as the Z direction, the direction perpendicular to the Z direction is defined as the Y direction, and the directions perpendicular to the Z direction and the Y direction are defined as the X direction. The structure of the semiconductor device 100 according to this embodiment is not limited to Figures 1 to 5 The structure shown.

[0038] like Figure 1 As shown, the semiconductor device 100 has a plurality of memory cells MC arranged in a three-dimensional manner ( Figure 3 ) and a nonvolatile memory of a three-dimensional storage device. For example, the nonvolatile memory is a NAND flash memory.

[0039] The semiconductor device 100 includes a base portion 1 , a stacked body 2 , and a plurality of columnar portions CL.

[0040] The base portion 1 includes a substrate 10, an insulating layer 11, a conductive layer 12, and a semiconductor portion 13. The insulating layer 11, the conductive layer 12, and the semiconductor portion 13 are provided above the substrate 10 in this order.

[0041] The substrate 10 is a semiconductor substrate, such as a silicon substrate. The surface region of the substrate 10 includes, for example, an isolation region 10i and an active area AA. The isolation region 10i is, for example, an insulating region made of silicon oxide. The active area AA includes the source and drain regions of the transistor Tr. The isolation region 10i insulates the multiple active areas AA from each other.

[0042] The insulating layer 11 is in contact with the substrate 10 and is provided on the substrate 10. The insulating layer 11 includes, for example, a gate electrode and a gate insulating layer of the transistor Tr. The insulating layer 11 is an interlayer insulating layer that insulates the plurality of transistors Tr from one another. Within the insulating layer 11, for example, wiring 11aa, wiring 11ab, and insulating layer 11d are stacked in this order from below (the side where the substrate 10 is provided) to above (the side where the conductive layer 12 is provided) relative to the insulating layer 11. That is, the insulating layer 11 includes a multilayer wiring structure in which insulating layers and wiring layers are alternately stacked. Figure 2 In FIG. 1 , a multilayer wiring structure including two wiring layers and three insulating layers is shown, but the multilayer wiring structure is not limited to Figure 2 The example shown is a structure in which a number of layers are stacked without departing from the scope of the present embodiment. The wiring 11aa is a wiring electrically connected to the transistor Tr. The wiring 11ab is a wiring electrically connected to the wiring 11aa.

[0043] The conductive layer 12 is in contact with the insulating layer 11 and is provided on the insulating layer 11. The semiconductor portion 13 is in contact with the conductive layer 12 and is provided on the conductive layer 12. The plurality of transistors Tr constitute a peripheral circuit of the nonvolatile memory.

[0044] The laminate 2 is disposed above the substrate 10 and is positioned in the Z direction relative to the semiconductor portion 13. The laminate 2 is constructed by alternately stacking a plurality of conductive layers 21 and a plurality of insulating layers 22 in the Z direction. The Z direction is the stacking direction of the laminate 2. The insulating layers 22 electrically insulate adjacent conductive layers 21 in the Z direction. The number of conductive layers 21 and insulating layers 22 stacked is arbitrary. The insulating layer 22 may also be a space (gap), for example. An insulating layer 2g, for example, is provided between the laminate 2 and the semiconductor portion 13.

[0045] The conductive layer 21 constitutes at least one source-side select gate SGS, a plurality of word lines WL, and at least one drain-side select gate SGD. The source-side select gate SGS is the gate electrode of the source-side select transistor STS. The word line WL is the gate electrode of the memory cell MC. The drain-side select gate SGD is the gate electrode of the drain-side select transistor STD. The source-side select gate SGS is provided in the lower region of the stack 2 (the region on the side of the stack 2 where the semiconductor portion 13 is provided). The drain-side select gate SGD is provided in the upper region of the stack 2 (the region on the opposite side of the stack 2 where the semiconductor portion 13 is provided). The word line WL is provided between the source-side select gate SGS and the drain-side select gate SGD. In this embodiment, for example, the gate electrode of the memory cell MC and the word line WL function as control gates.

[0046] The stacked body 2 further includes a semiconductor portion 14. The semiconductor portion 14 is located between the stacked body 2 and the semiconductor portion 13. The semiconductor portion 14 is provided between the insulating layer 22 closest to the semiconductor portion 13 and the insulating layer 2g. The semiconductor portion 14 functions as, for example, a source-side select gate SGS.

[0047] The semiconductor device 100 includes a plurality of memory cells MC connected in series between a source-side select transistor STS and a drain-side select transistor STD. The structure in which the source-side select transistor STS, the plurality of memory cells MC, and the drain-side select transistor STD are connected in series is called a memory string or NAND string. The memory string is connected to a bit line BL via, for example, a contact Cb. The bit line BL is provided above the stack 2 (on the side of the stack 2 opposite to the side where the semiconductor portion 13 is provided) and extends in the Y direction.

[0048] use Figures 2 to 5 The cross-sectional structure of the semiconductor device 100 is described. Figures 2 to 4 In the description of the cross-sectional structure of the semiconductor device 100, the following is mainly discussed: Figure 1 The differences are explained, sometimes omitting Figure 1 Description of the same or similar structures.

[0049] like Figure 2 As shown, the semiconductor device 100 includes a semiconductor layer 131, a semiconductor layer 132, and a semiconductor layer 133. The semiconductor portion 13 ( Figure 1 ) includes a semiconductor layer 131, a semiconductor layer 132, and a semiconductor layer 133. The semiconductor layer 131 is in contact with the conductive layer 12 and is disposed on the conductive layer 12. The semiconductor layer 132 is in contact with the semiconductor layer 131 and is disposed on the semiconductor layer 131. The semiconductor layer 133 is in contact with the semiconductor layer 132 and is disposed on the semiconductor layer 132. In addition, Figure 2 in, omit Figure 1The element isolation region 10i, the active region AA, the transistor Tr, the wiring 11aa, the wiring 11ab, and the insulating layer 11d are shown.

[0050] use Figures 2 to 5 , the stacked body 2 , the memory hole MH and the slot ST included in the semiconductor device 100 will be described in more detail.

[0051] like Figures 2 to 5 As shown, each of the plurality of columnar portions CL is disposed inside the storage hole MH. The storage hole MH is disposed in the Z direction so as to penetrate the stacked body 2 from the upper end thereof. A semiconductor body 210, a storage film 220, and a core layer 230 are disposed inside the storage hole MH. The semiconductor body 210, the storage film 220, and the core layer 230 extend in the Z direction along the storage hole MH. The semiconductor body 210, which serves as a semiconductor column (semiconductor layer), is electrically connected to the semiconductor portion 13. The plurality of columnar portions CL arranged in the Y direction are connected to the semiconductor portion 13 via the contact portion Cb ( Figure 1 ) and are commonly connected to a bit line BL ( Figure 1 The shape of the storage hole MH on the X-Y plane ( Figure 4 ) is, for example, circular or elliptical.

[0052] A blocking insulation layer 21a and a protective layer 21b forming part of the storage film 220 are provided between the conductive layer 21 and the insulating layer 22. The blocking insulation layer 21a is provided between the conductive layer 21 and the semiconductor body 210 and between the conductive layer 21 and the insulating layer 22.

[0053] The blocking insulating layer 21 a is disposed around the conductive layer 21 , between the conductive layer 21 and the semiconductor body 210 , and between the conductive layer 21 and the insulating layer 22 .

[0054] The protection layer 21 b is provided around the blocking insulating layer 21 a so as to be in contact with the blocking insulating layer 21 a , and is provided between the conductive layer 21 and the semiconductor body 210 , and between the conductive layer 21 and the insulating layer 22 .

[0055] The semiconductor body 210 has a cylindrical shape, for example, and functions as a channel region of each of the drain-side selection transistor STD, the memory cell MC, and the source-side selection transistor STS.

[0056] The memory film 220 includes a blocking insulating layer 21a, a protective layer 21b, a capping insulating layer 221, a charge trapping layer 222, and a tunnel insulating layer 223. The memory film 220 is provided in a cylindrical shape so as to extend in the Z direction along the inner wall of the memory hole MH. In addition, the memory film 220 is provided between the semiconductor body 210 and the conductive layer 21 or the insulating layer 22. The plurality of memory cells MC have the memory film 220 between the semiconductor body 210 and the conductive layer 21 as a storage area. The plurality of memory cells MC are arranged in the Z direction. The conductive layer 21 can be a word line WL or a wiring electrically connected to the word line WL. The semiconductor body 210, the charge trapping layer 222, and the tunnel insulating layer 223 are each formed along the inner wall of the memory hole MH and extend in the Z direction.

[0057] The cover insulating layer 221 is provided between the insulating layer 22 and the charge trapping layer 222. The cover insulating layer 221 is provided between the sacrificial layer 23 ( Figure 18 ) is replaced by the conductive layer 21 (in the replacement process), the charge capture layer 222 is protected. As a result, the covering insulating layer 221 suppresses the charge capture layer 222 from being etched. The covering insulating layer 221 that is not in contact with the insulating layer 22 can also be removed together with the sacrificial layer 23. In addition, although omitted from the figure, a portion of the covering insulating layer 221 that is not in contact with the insulating layer 22 can also be left without being removed together with the sacrificial layer 23. When a portion of the covering insulating layer 221 that is not in contact with the insulating layer 22 remains, the covering insulating layer 221 is arranged between the conductive layer 21 and the charge capture layer 222.

[0058] The charge trapping layer 222 is provided between the blocking insulating layer 21a or the cap insulating layer 221 and the tunnel insulating layer 223. The portion or region of the charge trapping layer 222 sandwiched between the conductive layer 21 (word line WL) and the semiconductor body 210 serves as the charge trapping portion or storage region of the memory cell MC. The charge trapping portion or storage region, for example, contains trap sites that capture charge. The threshold voltage of the memory cell MC varies depending on the amount of charge trapped in the charge trapping portion. In other words, the charge trapping layer 222 functions as a storage layer that accumulates or stores injected charge. As a result, the memory cell MC can retain data.

[0059] The tunnel insulating layer 223 is provided between the semiconductor body 210 and the charge trapping layer 222. When electrons are injected from the semiconductor body 210 into the charge trapping portion (writing operation) and when holes are injected from the semiconductor body 210 into the charge trapping portion (erasing operation), the electrons and holes respectively pass through (tunnel through) the potential barrier of the tunnel insulating layer 223.

[0060] Tunnel insulating layer 223 is provided between conductive layer 21 and semiconductor body 210, charge trapping layer 222 is provided between tunnel insulating layer 223 and conductive layer 21, and blocking insulating layer 21a and protective layer 21b are provided between charge trapping layer 222 and conductive layer 21. As a result, charge trapping layer 222 can take in charge from semiconductor body 210 via tunnel insulating layer 223, or release charge from semiconductor body 210 via tunnel insulating layer 223. On the other hand, blocking insulating layer 21a and protective layer 21b prevent charge accumulated in charge trapping layer 222 from passing to conductive layer 21, and also prevent charge from conductive layer 21 from passing to charge trapping layer 222. As a result, memory cell MC can store data in charge trapping layer 222, or erase data from charge trapping layer 222.

[0061] The inner space of the cylindrical semiconductor body 210 is filled with a core layer 230. The core layer 230 has a columnar shape, for example.

[0062] The conductive layer 21 that functions as the word line WL and the control gate is provided between a plurality of insulating layers 22 that are adjacent to each other in the Z direction. The conductive layer 21 faces the slit ST in the Y direction and is in contact with the slit ST. The details will be described later, but the slit ST is formed when the conductive layer 21 is formed. Using the slit ST, the sacrificial layer 23 ( Figure 18 ) is replaced (replaced) with the material forming the conductive layer 21. After the material forming the conductive layer 21 is buried in the gap ST and between the insulating layers 22, the material of the conductive layer 21 in the gap ST is removed. Figure 3 and Figure 5 As shown, the material forming the conductive layer 21 buried between the insulating layers 22 is left. The material forming the conductive layer 21 in the gap ST is removed, and the conductive layers 21 remaining between the insulating layers 22 are electrically separated from each other. As a result, each conductive layer 21 can function as a word line WL. Then, the insulating layer 3 is set (filled) inside the gap ST. In addition, Figure 5 It will Figure 3 The enlarged view of the region 110 shows one conductive layer 21 among the plurality of conductive layers 21 (plurality of word lines WL).

[0063] like Figure 3 and Figure 5As shown, the memory cell MC is constructed using a conductive layer 21, a channel region (semiconductor layer), a tunnel insulating layer 223, a charge trapping layer 222, a cap insulating layer 221, an insulating layer 22 (first insulating layer), a blocking insulating layer 21a (second insulating layer), and a protective layer 21b in directions (X and Y directions) intersecting the stacking direction (Z direction) of the stack 2. Furthermore, multiple memory cells MC are arranged in the stacking direction (Z direction) of the multiple conductive layers 21, and are provided relative to each of the multiple conductive layers 21 in the alternating stack of insulating layers 22 and conductive layers 21. That is, each of the multiple conductive layers 21 is connected to a plurality of memory cells MC.

[0064] As described above, in a memory cell MC, the semiconductor body 210 functions as a channel region, and the conductive layer 21 functions as a word line WL and a control gate. The charge trapping layer 222 functions as a storage layer that accumulates charge injected from the channel region. Multiple memory cells MC are arranged in the stacking direction (Z direction) of the multiple conductive layers 21, and the multiple conductive layers 21 are connected to the multiple memory cells MC. The semiconductor device according to this embodiment can control the voltage applied to the conductive layer 21 connected to the memory cell MC, thereby controlling the write or erase operation of the memory cell MC.

[0065] <Method for Manufacturing Conductive Layer 21 of Semiconductor Device 100>

[0066] use Figures 6 to 12 , a method for manufacturing the conductive layer 21 of the semiconductor device 100 according to this embodiment will be described. Figure 6 1 is a flowchart showing a method for manufacturing the conductive layer 21 of the semiconductor device 100 according to the present embodiment. Figures 7 to 12 The diagram is used to explain the method for manufacturing the conductive layer 21 of the semiconductor device 100 according to the present embodiment. The method for manufacturing the semiconductor device 100 according to the present embodiment is not limited to Figures 6 to 12 The composition shown is sometimes omitted. Figures 1 to 5 Description of the same or similar structures.

[0067] As described above, in the method for manufacturing the conductive layer 21 of the semiconductor device 100 according to the present embodiment, the sacrificial layer 23 ( Figure 18 ) is replaced (replaced) with the material forming the conductive layer 21. After removing the sacrificial layer 23 ( Figure 18 ) After that, the formation of the conductive layer 21 is started.

[0068] like Figure 6 and Figure 7As shown, in step 11 (S11), a blocking insulating layer 21a is formed. The blocking insulating layer 21a is formed on the inner wall of the space S2 through the gap ST using a thermal CVD (Chemical Vapor Deposition) method or an ALD (Atomic Layer Deposition) method. More specifically, the blocking insulating layer 21a is formed on the surface 22aa and the surface 22ab of the insulating layer 22, covering a portion of the insulating layer 221 and a portion of the charge trapping layer 222. The blocking insulating layer 21a suppresses the back-tunneling of charges from the conductive layer 21 to the storage film 220 side. In addition, the blocking insulating layer 21a also functions as a seed layer that promotes the stacking of the first metal element (the formation of the conductive layer 21) when forming the conductive layer 21. In this embodiment, the insulating layer 22 is sometimes referred to as a first insulating layer, the surface 22aa and the surface 22ab of the insulating layer 22 are sometimes referred to as a first surface, and the barrier insulating layer 21a is sometimes referred to as an aluminum oxide layer or a second insulating layer.

[0069] As a material forming the blocking insulating layer 21a, for example, an insulating material containing a second metal element can be used. In this embodiment, for example, the second metal element is aluminum (Al), and the insulating material containing the second metal element is aluminum oxide (Al2O3). The thickness of the aluminum oxide is, for example, not less than 1 nm and not more than 5 nm.

[0070] Then, if Figure 6 and Figure 8 As shown, a protective layer 21b is formed in step 13 (S13). The protective layer 21b is formed, for example, on the surface 21aa, the surface 21ab and the surface 21ac of the blocking insulating layer 21a. For the protective layer 21b, a thermal CVD method or the like is used to supply a first gas 21c containing a third element through the gap ST to form the protective layer 21b. The third element is, for example, carbon (C), nitrogen (N) or sulfur (S). The protective layer 21b may contain the third element, the third element and the second metal element, a combination of the third element and the second metal element, or a layer containing a combination of the third element and the second metal element. In this embodiment, for example, the protective layer 21b includes a layer containing a combination of carbon and aluminum. The protective layer 21b may also include oxygen (O). The thickness of the protective layer 21b is at the level of 1 atomic layer, for example, approximately 0.03 nm. In Figure 8 In order to facilitate understanding of the manufacturing method of this embodiment, the first gas 21 c is collectively described as one, but the first gas 21 c is distributed in the space where the slit ST and the blocking insulating layer 21 a are formed.

[0071] The conditions for supplying the first gas 21c and forming the protective layer 21b are, for example: the temperature when supplying the first gas 21c is above 300 degrees Celsius and below 650 degrees Celsius, the pressure when supplying the first gas 21c is above 100 Pascals (Pa) and below 10,000 Pa, and the time for supplying the first gas 21c is less than 3 minutes.

[0072] When the third element is carbon, the first gas 21c is, for example, a gas containing at least one of CO, CO2, CH4, C2H2, C2H4, C3H6, C3H8, C4F6, C4F8 and CH3OH, and the protective layer 21b can contain carbon, carbon and aluminum, a combination of carbon and aluminum, or a layer containing a combination of carbon and aluminum.

[0073] When the third element is nitrogen, the first gas is, for example, a gas containing NH 3 , and the protective layer 21 b may contain nitrogen, nitrogen and aluminum, a combination of nitrogen and aluminum, or a layer containing a combination of nitrogen and aluminum.

[0074] When the third element is sulfur, the first gas is, for example, a gas containing H 2 S, and the protective layer 21 b may contain sulfur, sulfur and aluminum, a combination of sulfur and aluminum, or a layer containing a combination of sulfur and aluminum.

[0075] The protective layer 21b is formed in contact with the blocking insulating layer 21a. As a result, when the conductive layer 21 described later is formed, the protective layer 21b suppresses the corrosion of the blocking insulating layer 21a caused by chlorine and the like contained in the stacking of the first metal element (formation of the conductive layer 21). In addition, when forming the conductive layer 21, the protective layer 21b also functions as a seed layer that promotes the stacking of the first metal element (formation of the conductive layer 21). That is, by using the protective layer 21b, the first metal element is easily stacked on the protective layer 21b. In addition, the thickness of the protective layer 21b is extremely thin, at the level of 1 atomic layer, and therefore, it is possible to suppress the occurrence of a situation in which the resistance of the conductive layer 21 increases as the thickness of the protective layer 21b becomes thicker and the thickness of the conductive layer 21 becomes thinner.

[0076] Then, if Figure 6 、 Figure 9 、 Figure 10 as well as Figure 11 As shown, in step 15 (S15), a conductive layer 21 is formed. The conductive layer 21 is formed, for example, on the surface 21ba, the surface 21bb, and the surface 21bc of the protective layer 21b and the surface (inner wall) of the slit ST. The conductive layer 21 is formed by alternately supplying a raw material gas 21d containing a first metal element and a reducing gas 21f through the slit ST in an atmosphere at a temperature of 500 to 600 degrees Celsius using a thermal CVD method or an ALD method. Figure 9In order to facilitate understanding of the manufacturing method of this embodiment, the raw material gas 21d is summarized as one and described. Figure 10 In order to facilitate understanding of the manufacturing method of this embodiment, reducing gas 21f is described as a single gas. However, raw material gas 21d and reducing gas 21f are distributed in the space where slit ST and blocking insulating layer 21a are formed. In this embodiment, raw material gas is referred to as material gas.

[0077] As a material forming the conductive layer 21, for example, a conductive material containing a first metal element can be used. For example, the first metal element is molybdenum (Mo). In addition, the raw material gas containing the first metal element is a gas containing molybdenum and chlorine (Cl), such as MoCl5, MoOCl4, MoO2Cl2, etc. Chlorine is an impurity contained in the raw material gas. The volume density of chlorine in the conductive layer 21 is 1×10 15 atoms / cm 3 Above and 1×10 20 atoms / cm 3 The reducing gas 21f is, for example, hydrogen (H2) or ammonia (NH3).

[0078] In this embodiment, for example, the second metal element is aluminum, the third element is carbon, the protective layer 21b includes a layer containing a combination of carbon and aluminum, the first metal element is molybdenum, the raw material gas containing the first metal element is a gas containing molybdenum and chlorine, the reducing gas is hydrogen, and the conductive layer 21 contains molybdenum and chlorine. Figure 9 and Figure 10 As shown, during the formation of conductive layer 21, when gases containing molybdenum and chlorine, and hydrogen, are alternately supplied, a chemical reaction occurs between the chlorine contained in the raw material gas or the chlorine and hydrogen contained in conductive layer 21, and the carbon contained in protective layer 21b. Chlorine-containing gas 21e is released from surfaces 21aa, 21ab, and 21ac of blocking insulating layer 21a, and surfaces 21ba, 21bb, and 21bc of protective layer 21b. As a result, molybdenum is adsorbed on the portions of conductive layer 21 from which the chlorine was released, promoting the formation of a molybdenum-containing layer in conductive layer 21. Specifically, molybdenum gradually accumulates inside protective layer 21b in space S2, forming a molybdenum-containing layer.

[0079] Then, if Figure 6 As shown, in step 17 (S17), if the film thickness of the conductive layer 21 is not the desired film thickness (No), as shown in FIG. Figure 9 and Figure 10 As shown in FIG. 1 , the conductive layer 21 does not completely fill the inner side of the protective layer 21b in the space S2. As a result, step 15 (S15) is repeatedly performed until the thickness of the conductive layer 21 reaches the desired thickness. Figure 6 As shown, in step 17 (S17), when the film thickness of the conductive layer 21 is the desired film thickness (yes), as shown in FIG. Figure 11 As shown, the conductive layer 21 completely fills the inner side of the protective layer 21 b in the space S2 , thereby completing the formation of the conductive layer 21 to the inner side of the protective layer 21 b in the space S2 .

[0080] Then, if Figure 12 As shown, the conductive layer 21 provided on the inner side of the protective layer 21b in the space S2 between the insulating layers 22 is retained, and the conductive layer 21 provided on the side wall of the insulating layer 22 in the slit ST is removed. For example, the conductive layer 21 is etched through the slit ST using wet etching. The etching solution used for wet etching is, for example, a mixed solution containing phosphoric acid. As described above, the conductive layer 21 provided on the side wall of the insulating layer 22 in the slit ST is removed (etched back). As a result, for example, Figure 2 As shown, the conductive layers 21 provided inside the protective layer 21b in the plurality of spaces S2 arranged in the Z direction are electrically isolated from each other. Thus, the electrically isolated conductive layers 21 can function as word lines WL and control gates.

[0081] In this embodiment, surfaces 21aa, 21ab, and 21ac of the blocking insulating layer 21a are referred to as second surfaces, and surfaces 21ba, 21bb, and 21bc of the protective layer 21b are referred to as third surfaces. Although not shown in the drawings in this embodiment, the conductive layer 21 may also include grain boundaries.

[0082] In use Figures 6 to 12 In the method for manufacturing the conductive layer 21 of the semiconductor device 100 described above, the conductive layer 21 is formed by using Figures 13 to 17 An example of the mechanism (mechanism) by which the conductive layer 21 is formed will be described. Figure 13 This is a diagram showing the first principle calculation results of the adsorption energy of gas adsorbed on the surface of each material and the desorption energy of gas desorbed from the surface of each material. Figure 14 This is a diagram showing calculation results of the crystal state of the insulating layer when a gas containing hydrogen is supplied. Figure 15 This is a diagram showing a first principle calculation result of the desorption energy of gas desorbed from the blocking insulating layer 21 a of the semiconductor device 100 according to the present embodiment. Figure 16 This is a diagram showing calculation results of the crystal state when a carbon-containing gas is supplied and calculation results of the crystal state when a raw material gas is supplied in the method for manufacturing the semiconductor device 100 according to the present embodiment. Figure 17This figure is used to explain the relationship between the film forming cycle and the film thickness in the manufacturing method of the conductive layer 21 of the semiconductor device 100 according to this embodiment and the manufacturing method when the conductive layer 21 of the semiconductor device 100 according to this embodiment is not used. The mechanism of the manufacturing method of the semiconductor device 100 according to this embodiment is not limited to Figures 13 to 17 The composition shown is sometimes omitted. Figures 1 to 12 Description of the same or similar structures.

[0083] like Figure 13 The following example is shown: the surface (substrate) of the material is a Mo(110) surface, a γ-Al2O3(100) surface, or a titanium nitride (TiN) (110) surface, the adsorbed gas is a gas containing MoO2Cl2 or H2, and the desorbed gas is a gas containing H2O or HCl. Each numerical value represents the adsorption ease of the adsorbed gas or the desorption ease of the desorbed gas. Among the adsorbed gases, when the numerical value is small, it is easy to adsorb but difficult to desorb. Among the desorbed gases, when the numerical value is large, it is difficult to desorb but easy to adsorb. In particular, it can be seen that the desorption energy of Cl is 2.76 eV for the Mo(110) surface, 4.38 eV for the γ-Al2O3(100) surface, and 2.20 eV for the titanium nitride (TiN) (110) surface. Cl is easily adsorbed on the surface of the material and difficult to desorb.

[0084] When a gas containing hydrogen is supplied, for example, chlorine 21g and hydrogen 21h are adsorbed on the surface of Al2O3, and chlorine 21g, hydrogen 21h, aluminum 21i, and oxygen 21j are adsorbed on the surface of Al2O3. Figure 14 As shown in the left figure. Figure 14 As shown in the right figure, in Al2O3, chlorine 21g and hydrogen 21h adsorbed on the surface of Al2O3 combine and detach. Figure 13 As shown in Figure 2, Cl is easily adsorbed on the surface of the material and is difficult to be separated. For example, Al2O3 will be easily corroded if it still contains chlorine. Figure 13 As shown in Figure 1, when forming a conductive layer on Al2O3, Cl contained in the raw material gas used to form the conductive layer is easily adsorbed on the Al2O3 and is difficult to desorb. As a result, Cl remains in the Al2O3, causing Al2O3 corrosion. Furthermore, the Cl remaining in the Al2O3 makes it difficult for the metal elements that form the conductive layer to be adsorbed or deposited on the Al2O3. As a result, it takes time to form the conductive layer on the Al2O3.

[0085] In this embodiment, in order to remove Cl contained in the surface of the material, a Figure 15 The gas described in the gas type shown above modifies the surface of the insulating film (such as Al2O3) containing a metal element. Figure 15The following examples are shown: the gas types are carbon-containing gas (e.g., gas containing CH4), nitrogen-containing gas (e.g., gas containing NH3), sulfur-containing gas (e.g., gas containing H2S), and the desorbed gas (XClH n Desorption (X is one of C, N, S) is a gas containing CClH3 (CClH3 desorption), a gas containing NClH2 (NClH2 desorption), or a gas containing NClH2 (SClH desorption). Figure 15 In, also with Figure 13 Similarly, in the desorbed gas, when the value is large, it is difficult to desorb and easy to be adsorbed. Figure 15 The desorption energy when Cl contained in the surface of the material is reacted with C using a gas containing CH4 to desorb Cl is 0.11 eV. Figure 15 The desorption energy when Cl contained in the surface of the material is reacted with N using a gas containing NH 3 to desorb Cl is 1.60 eV. Figure 15 The desorption energy when the surface of the material is modified by using a gas containing CH4 is shown in FIG. Figure 13 The Cl desorption energy on the surface of the material is significantly improved compared to that shown in FIG. In addition, the desorption energy (3.49 eV) when the surface of the material is modified by using a gas containing H2S is significantly improved compared to that shown in FIG. Figure 13 The shown separation energy from Al2O3 is improved compared to that (4.38 eV).

[0086] In this embodiment, if Figure 16 As shown in the left figure (CH4 flow (C adsorption, C coverage)), for example, when using Figure 6 and Figure 8 In the previously described step 13 (S13), the first gas containing CH4 is supplied onto the Al2O3 serving as the blocking insulating layer 21a to form a layer (protective layer 21b) containing Al and C. For example, a layer containing Al and C serving as the protective layer 21b is formed on the Al2O3 serving as the blocking insulating layer 21a, wherein aluminum 21i, oxygen 21j, and carbon 21k are formed. Figure 16 As shown in the left figure of , the Al2O3 layer is combined. As a result, the layer containing Al and C can protect (cover) the surface of Al2O3. That is, through step 13 (S13), the surface of Al2O3 can be modified.

[0087] In this embodiment, if Figure 16 As shown in the right figure (MoO2Cl2 flow (Mo adsorption)), for example, when using Figure 6 、 Figure 9 as well as Figure 10In the aforementioned step 15 (S15), a gas containing Mo and Cl (raw material gas, for example, MoO2Cl2) and a reducing gas (H2) are alternately supplied onto the protective layer 21b to form the conductive layer 21 containing Mo. For example, a layer containing Al and C is formed as the protective layer 21b on Al2O3 as the barrier insulating layer 21a, and chlorine 21g, aluminum 21i, oxygen 21j, carbon 21k, and molybdenum 21m are formed. Figure 16 Further, from Figure 16 Starting from the crystallized state shown in the right figure, the gas containing Mo and Cl (MoO2Cl2), the reducing gas (H2), and the layer containing Al and C as protective layer 21b react. For example, the gas containing CCl3 is released, and molybdenum 21m is adsorbed or deposited on protective layer 21b. As a result, a layer containing molybdenum 21m (conductive layer 21) is formed on protective layer 21b.

[0088] For example, when the manufacturing method of this embodiment is not used, as described above, Cl is easily adsorbed on Al2O3 and is difficult to be released. Therefore, Cl remains on Al2O3, and thus, the metal element forming the conductive layer is difficult to be adsorbed or deposited on Al2O3. Figure 17 As shown in FIG. 1 , when the conductive layer 21 is formed on the blocking insulating layer 21a at a formation rate of 0.09 nm / cycle (0.09 nm film formation per cycle) without using the manufacturing method of this embodiment, the conductive layer 21 is formed with a delay of approximately 50 cycles in the film formation cycle. In this embodiment, the delay in the start of film formation is referred to as, for example, an incubation cycle, and the absence of a delay in the start of film formation is referred to as a non-incubation cycle.

[0089] On the other hand, when the manufacturing method of the present embodiment is used, as described above, for example, a first gas containing CH4 is supplied onto Al2O3 serving as a blocking insulating layer 21a to form a layer containing Al and C (protective layer 21b). A layer containing Al and C serving as a protective layer 21b is formed on Al2O3 serving as a blocking insulating layer 21a, and further, metal atoms, a raw material gas containing Cl, a reducing gas (H2), and a layer containing Al and C serving as a protective layer 21b react, and for example, a gas containing CClH3 is released to form a conductive layer 21 containing metal atoms. By using the manufacturing method of the present embodiment, it is possible to promote the release of Cl from Al2O3 and the adsorption or accumulation of the metal element forming the conductive layer 21 on Al2O3. For example, Figure 17As shown, when the manufacturing method of this embodiment is used, when the conductive layer 21 is formed on the blocking insulating layer 21a at a formation rate of 0.09 [nm / cycle] (0.09 nm per cycle), the conductive layer 21 is formed without an incubation cycle. In addition, the conductive layer 21 containing metal atoms can be formed without an incubation cycle. Therefore, the conductive layer 21 is uniformly formed on Al2O3. As a result, by using the manufacturing method involved in this embodiment, the coverage of the step difference of the conductive layer 21 can be improved compared to the case where the film thickness of the conductive layer 21 is not uniformly formed. In addition, since the conductive layer 21 can be formed without an incubation cycle, the film thickness (layer thickness) formed relative to the number of film formation cycles can be calculated.

[0090] By using the semiconductor device 100 and the method for manufacturing the semiconductor device 100 of this embodiment, the protective layer 21b can be formed on the blocking insulating layer 21a. As a result, the protective layer 21b, which includes, for example, a layer composed of a combination of aluminum (Al) and carbon (C), can protect the blocking insulating layer 21a, thereby suppressing corrosion of the blocking insulating layer 21a.

[0091] Furthermore, by reacting the raw material gas used to form the conductive layer 21 with carbon (C) and chlorine (Cl) as an impurity, for example, the gas containing chlorine can be desorbed from the protective layer 21b. As a result, the metal atoms contained in the raw material gas that form the conductive layer 21 are deposited on the protective layer 21b, and the formation of the conductive layer 21 can be initiated using the deposited metal atoms as nuclei. This reduces the incubation period without delaying the formation of the conductive layer 21. As a result, by using the semiconductor device 100 and the method for manufacturing the semiconductor device 100 according to this embodiment, the conductive layer 21 can be formed on the step without compromising the coverage of the step.

[0092] As described above, by using the semiconductor device 100 and the method for manufacturing the semiconductor device 100 according to this embodiment, the reliability and productivity of the alternately stacked insulating layers and conductive layers can be improved.

[0093] As described above, the semiconductor device 100 according to this embodiment includes a stacked body 2 having a conductive layer 21, an insulating layer 22 (a first insulating layer), a blocking insulating layer 21a (an aluminum oxide (Al2O3) layer), and a protective layer 21b. The conductive layers 21 and the insulating layers 22 are alternately stacked. The conductive layer 21 contains molybdenum (Mo, a first element). The insulating layer 22 has a surface 22aa and a surface 22ab (a first surface). The blocking insulating layer 21a is in contact with the surfaces 22aa and 22ab and is provided between the surfaces 22aa and 22ab and the conductive layer 21. In other words, the blocking insulating layer 21a is in contact with the insulating layer 22 and the conductive layer 21. Furthermore, the blocking insulating layer 21a contains aluminum (Al, a second element) and has surfaces 21aa, 21ab, and 21ac (a second surface). The protective layer 21b is in contact with the surfaces 21aa, 21ab, and 21ac. Furthermore, protective layer 21b comprises a combination of carbon (C, the third element) and aluminum, and has surfaces 21ba, 21bb, and 21bc (third surface). Surfaces 21ba, 21bb, and 21bc are in contact with conductive layer 21. That is, protective layer 21b is in contact with blocking insulating layer 21a and conductive layer 21. In this embodiment, for ease of explanation, the terms "surface" and "surface" are sometimes used. However, a surface or surface refers to, for example, the portion where the first film or first layer is in contact with the second film or second layer.

[0094] In addition, the stack 2 has a plurality of storage holes MH (second openings), a semiconductor body 210 (semiconductor layer), a covering insulating layer 221, a charge capture layer 222, and a tunnel insulating layer 223. The plurality of storage holes MH extend in the stacking direction (Z direction) of the stack 2 and are arranged in the insulating layer 22 and the conductive layer 21. The plurality of storage holes MH is an opening different from the plurality of slits ST (first openings). The semiconductor body 210 is arranged in a cylindrical shape so as to extend in the stacking direction (Z direction) of the stack 2 along the inner side of the plurality of storage holes MH. The covering insulating layer 221 is arranged between the charge capture layer 222 and the insulating layer 22 or the conductive layer 21. The charge capture layer 222 is arranged between the tunnel insulating layer 223 and the conductive layer 21. The tunnel insulating layer 223 is arranged between the conductive layer 21 and the semiconductor body 210. In this embodiment, for example, a stopper layer 3s (insulator, Figure 22 ) is provided so as to extend in the stacking direction (Z direction) of the stacked body 2 along the inner side of the plurality of slits ST.

[0095] In the method for manufacturing the semiconductor device 100 according to this embodiment, an insulating layer 22 (first insulating layer) having surfaces 22aa and 22ab (first surface) is formed, a blocking insulating layer 21a (aluminum oxide (Al2O3) layer) having surfaces 21aa, 21ab, and 21ac (second surface) is formed on surfaces 22aa and 22ab, a protective layer 21b having surfaces 21ba, 21bb, and 21bc (third surface) is formed on surfaces 21aa, 21ab, and 21ac (second surface), and a conductive layer 21 is formed on surfaces 21ba, 21bb, and 21bc (third surface). Specifically, the insulating layer 22 is formed on a substrate, the blocking insulating layer 21a (aluminum oxide layer) is formed on the insulating layer 22, the protective layer 21b is formed on the blocking insulating layer 21a (aluminum oxide layer), and the conductive layer 21 is formed on the protective layer 21b. The blocking insulating layer 21a comprises aluminum (Al, the second element), the protective layer 21b comprises a combination of carbon (C, the third element) and aluminum (Al, the second element), and the conductive layer 21 comprises molybdenum (Mo, the first element). When forming the protective layer 21b, a gas (the first gas) containing either carbon, nitrogen (N, the third element), or sulfur (S, the third element) is supplied. When forming the conductive layer 21, a source gas containing molybdenum (Mo, the first element) is supplied, along with a gas containing hydrogen (H2, the reducing gas) to reduce the source gas.

[0096] In addition, in the manufacturing method of the semiconductor device 100 involved in this embodiment, a plurality of insulating layers 22 (first insulating layers) and a plurality of sacrificial layers 23 are alternately stacked above the substrate 10 to form a stacked body 2, a plurality of slits ST (first openings) extending in the stacking direction (Z direction) of the stacked body 2 are formed on the plurality of insulating layers 22 and the plurality of sacrificial layers 23, the plurality of sacrificial layers 23 are removed through the plurality of slits ST, and a plurality of spaces S2 obtained by removing the plurality of sacrificial layers 23 are formed between the plurality of insulating layers 22, a first gas, a material gas and a reducing gas are supplied to the plurality of spaces S2 through the slits ST, and a blocking insulating layer 21a (aluminum oxide (Al2O3) layer), a protective layer 21b and a conductive layer 21 are respectively formed in the plurality of spaces S2 through the plurality of slits ST, the blocking insulating layer 21a, the protective layer 21b and the conductive layer 21 set in each of the plurality of spaces S2 are kept in a state of being retained, and the conductive layer 21 set in the plurality of slits ST is removed.

[0097] <Method of Manufacturing Semiconductor Device 100>

[0098] use Figure 1 、 Figure 2 as well as Figures 18 to 25 A method for manufacturing the semiconductor device 100 according to this embodiment will be described. Figures 18 to 25The diagram is used to explain the method for manufacturing the semiconductor device 100 according to the present embodiment. The method for manufacturing the semiconductor device 100 according to the present embodiment is not limited to Figures 18 to 25 The manufacturing method shown is sometimes omitted. Figures 1 to 17 In addition, Figure 2 Likewise, in Figures 18 to 25 in, omit Figure 1 The element isolation region 10i, the active region AA, the transistor Tr, the wiring 11aa, the wiring 11ab, and the insulating layer 11d are shown.

[0099] like Figure 1 As shown, an element isolation region 10i is formed within a substrate 10, and a transistor Tr is formed within an active area AA. Next, an insulating layer 11 is formed on the substrate 10. The insulating layer 11 includes, for example, a gate electrode of the transistor Tr, a gate insulating layer, wiring 11aa, wiring 11ab, and an insulating layer 11d. In other words, the insulating layer 11 includes a multilayer wiring structure formed by alternating insulating layers and wiring layers. Silicon oxide can be used as a material for forming the insulating layer 11, for example. Next, a conductive layer 12 is formed on the insulating layer 11d. For example, a conductive metal such as tungsten can be used as a material for forming the conductive layer 12.

[0100] Then, if Figure 18 As shown, a semiconductor layer 131 is formed on the conductive layer 12. Next, an intermediate layer 13a is formed on the semiconductor layer 131. A silicon oxide film can be used as the material for forming the intermediate layer 13a, for example. Next, a sacrificial layer 13b is formed on the intermediate layer 13a. Silicon doped with impurities or undoped with impurities can be used as the material for forming the sacrificial layer 13b. Next, an intermediate layer 13c is formed on the sacrificial layer 13b. A silicon oxide film can be used as the material for forming the intermediate layer 13c, for example. Next, a semiconductor layer 133 is formed on the intermediate layer 13c. The semiconductor layer 131, intermediate layer 13a, sacrificial layer 13b, intermediate layer 13c, and semiconductor layer 133 form, for example, the semiconductor portion 13. A semiconductor material such as silicon can be used as the material for forming the semiconductor portion 13. Silicon doped with impurities or undoped with impurities can be used as the material for forming the semiconductor layers 131, 132, and 133. As described above, the base portion 1 is formed.

[0101] Then, if Figure 18As shown, an insulating layer 2g is formed on the semiconductor layer 133. Next, a semiconductor layer 134 is formed on the insulating layer 2g. As a material for forming the insulating layer 2g, for example, silicon oxide, a dielectric having a higher dielectric constant than that of silicon oxide, a metal oxide, etc. can be used. The semiconductor portion 14 is formed as described above. Next, an insulating layer 22b is formed on the semiconductor layer 134. Furthermore, sacrificial layers 23 and insulating layers 22 are alternately stacked on the insulating layer 22b. As a material for forming the insulating layer 22, for example, silicon oxide can be used. The insulating layer 22 is, for example, a TEOS layer. The TEOS layer is a silicon oxide layer using TEOS (Tetra Ethyl Ortho Silicate) as a raw material. The TEOS layer is formed using, for example, the CVD (Chemical Vapor Deposition) method. As a material for forming the insulating layer 22b, the same material as the material for forming the insulating layer 22 described above can be used. As a material for forming the sacrificial layer 23, for example, a silicon nitride film can be used. As described above, the stacked body 2 is formed above the semiconductor portion 13.

[0102] Then, if Figure 19 As shown, in a portion of the base portion 1 and a cell region (not shown) included in the stack 2, the stack 2, the semiconductor layer 134, the insulating layer 2g, the semiconductor layer 133, the intermediate layer 13c, the sacrificial layer 13b, the intermediate layer 13a, and the semiconductor layer 131 are anisotropically etched to form a memory hole MH. The memory hole MH is an opening. The memory hole MH is formed to extend in the stacking direction of the stack 2, extending from the upper end of the stack 2 to midway through the semiconductor layer 131.

[0103] Then, if Figure 20 As shown, a memory film 220 is formed in the memory hole MH. Figures 2 to 5The cap insulating layer 221, charge trapping layer 222, and tunnel insulating layer 223 described above are formed in this order within the memory hole MH. Silicon oxide, for example, can be used as the material for forming the cap insulating layer 221. Silicon nitride, for example, can be used as the material for forming the charge trapping layer 222. Insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride can be used as the material for forming the tunnel insulating layer 223. Next, the semiconductor body 210 is formed on the memory film 220. Semiconductor materials such as polycrystalline silicon can be used as the material for forming the semiconductor body 210. Next, the core layer 230 is formed on the semiconductor body 210. Insulating materials such as silicon oxide can be used as the material for forming the core layer 230. As described above, the memory film 220 (cap insulating layer 221, charge trapping layer 222, tunnel insulating layer 223), the semiconductor body 210, and the core layer 230 are formed in this order on the inner wall of the memory hole MH. The memory hole MH is filled with the memory film 220 , the semiconductor body 210 , and the core layer 230 .

[0104] Then, if Figure 21 As shown, the stack 2 is anisotropically etched to form a slit ST. The slit ST extends along the Z direction in the stack 2, passes through the stack 2 from the upper end of the stack 2 and is formed to the middle of the sacrificial layer 13b, and is commonly provided in the insulating layer 22 and the sacrificial layer 13b. The slit ST is an opening portion different from the storage hole MH, and is formed as an opening portion also extending in the X direction. As long as the slit ST passes through the stack 2, it can be formed to any depth. In this embodiment, the storage hole MH is formed before the slit ST (before the slit ST). In this embodiment, for example, the slit ST is referred to as the first opening portion, the storage hole MH is referred to as the second opening portion, and the opening portion is also referred to as a groove.

[0105] Then, if Figure 22 As shown, a stopper layer 3s is formed on the sidewall of the slit ST. As a material forming the stopper layer 3s, silicon nitride can be used, for example. In this embodiment, the stopper layer 3s is also called an insulator.

[0106] Then, if Figure 23 As shown, the intermediate layer 13c, sacrificial layer 13b, and intermediate layer 13a are removed (etched) through the slit ST, thereby embedding the semiconductor layer 132. At this time, the stopper layer 3s covers the inner wall of the slit ST, so the insulating layer 22 is not etched. The material forming the semiconductor layer 132 can be the same as the material forming the semiconductor layer 131 and the semiconductor layer 133 described above. For example, silicon doped with impurities or silicon not doped with impurities can be used as the material forming the semiconductor layer 132.

[0107] Then, if Figure 24As shown in FIG. 1 , the sacrificial layer 23 and the stopper layer 3s are isotropically etched together through the gap ST using a hot phosphoric acid solution. The hot phosphoric acid solution selectively etches the silicon nitride film relative to the silicon oxide film and silicon. Figure 24 As shown, while the insulating layer 22 is retained, the sacrificial layer 23 is selectively removed (etched) to form a space S2 in the Y and X directions. At this time, the etching of the sacrificial layer 23 progresses from the slit ST to the memory hole MH in the Y direction. The covering insulating layer 221 is formed of a silicon oxide film, and therefore, the etching of the sacrificial layer 23 stops at the covering insulating layer 221. Therefore, between the plurality of insulating layers 22 adjacent in the Z direction, a space S2 is provided from the slit ST to the covering insulating layer 221 of the memory hole MH. The covering insulating layer 221 is provided to protect the charge trapping layer 222, and therefore, the covering insulating layer 221 that is not in contact with the insulating layer 22 may be removed together with the etched sacrificial layer 23, or a portion of the covering insulating layer 221 that is not in contact with the insulating layer 22 may not be removed together with the sacrificial layer 23 and may remain.

[0108] Then, if Figure 25 As shown, a conductive layer 21 is formed. For the formation of the conductive layer 21, a Figures 7 to 11 Therefore, we will briefly explain it here. Figures 7 to 11 as well as Figure 12 As described above, aluminum oxide (Al2O3) is thinly formed on the inner wall of space S2 via gap ST using thermal CVD or ALD. Next, a first gas containing carbon (C) (gas containing CH4), for example, is supplied via gap ST using thermal CVD, thereby forming a thin protective layer 21b on barrier insulating layer 21a. This protective layer 21b comprises a layer composed of a combination of aluminum (Al) and carbon (C). Next, a source gas containing molybdenum (Mo) (gas containing MoO2Cl2) and a reducing gas (hydrogen (H2) gas) are alternately supplied via gap ST using thermal CVD, thereby forming conductive layer 21 on barrier insulating layer 21a. At this point, conductive layer 21 is also formed on the sidewalls of insulating layer 22 within gap ST. In addition, the slit ST extends along the Z direction in the laminate 2, penetrates the laminate 2 from the upper end of the laminate 2, and is provided in both the insulating layer 22 and the conductive layer 21. The slit ST included in the laminate 2 is connected to a portion of the insulating layer 22 and the barrier insulating layer 21a ( Figures 9 to 11 ) part, protective layer 21b ( Figures 9 to 11 ) and a portion of the conductive layer 21 are in contact.

[0109] Next, while the molybdenum filled in the spaces S2 between the insulating layers 22 remains, the conductive layer 21 provided on the sidewalls of the insulating layer 22 within the slits ST is removed. For example, a mixed solution containing phosphoric acid is used to wet-etch the conductive layer 21 provided on the sidewalls of the insulating layer 22 through the slits ST. As a result, the conductive layers 21 provided inside the protective layer 21b in the plurality of spaces S2 arranged in the Z direction are electrically separated from each other, forming a plurality of conductive layers 21 (word lines WL).

[0110] Then, if Figure 2 As shown in FIG. 1 , the gap ST is filled with an insulating layer 3. As a material for forming the insulating layer 3, an insulating material such as a silicon oxide film can be used. Figure 1 As shown, a contact portion Cb is formed ( Figure 1 ), bit line BL( Figure 1 ), wiring, etc. As described above, the semiconductor device 100 ( Figure 1 ).

[0111] When this embodiment is applied to a semiconductor device other than a nonvolatile memory, a conductive layer (eg, molybdenum) is formed between a plurality of insulating layers adjacent to each other in any of the X, Y, and Z directions. This conductive layer can be used as wiring, for example.

[0112] The above describes the configurations, manufacturing methods, etc. of several embodiments of the present disclosure, but these configurations, manufacturing methods, etc. are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways and can be implemented in appropriate combinations, or various omissions, substitutions, and changes can be made without departing from the scope of the invention. These embodiments, configurations, manufacturing methods, etc. of the embodiments, or modifications thereof are included within the scope and purpose of the invention and are included within the scope of the invention described in the claims and their equivalents.

Claims

1. A method for manufacturing a semiconductor device, An insulating layer is formed on a substrate, a plurality of the insulating layers and a plurality of sacrificial layers are alternately stacked, a first opening portion extending in a stacking direction is formed in the plurality of the insulating layers and the plurality of the sacrificial layers, the plurality of the sacrificial layers are removed through the first opening portion, a plurality of spaces obtained by removing the plurality of the sacrificial layers are formed between the plurality of the insulating layers, an aluminum oxide layer is formed in the plurality of spaces, a first gas containing any one of carbon, nitrogen and sulfur is supplied to the aluminum oxide layer, and after supplying the first gas, a material gas containing molybdenum and a reducing gas for reducing the material gas are further supplied to form a conductive layer containing the molybdenum.

2. The method for manufacturing a semiconductor device according to claim 1, The first gas, the material gas, and the reducing gas are supplied to the plurality of spaces through the first opening.

3. The method for manufacturing a semiconductor device according to claim 2, Before forming the first opening, a second opening extending in the stacking direction is formed in the plurality of insulating layers and the plurality of sacrificial layers, and a covering insulating layer, a charge trapping layer, a tunnel insulating layer, and a semiconductor layer are sequentially formed along the inner side of the second opening.

4. The method for manufacturing a semiconductor device according to claim 3, In a direction intersecting the stacking direction, a storage unit is formed using the conductive layer, the semiconductor layer, the tunnel insulating layer, the charge capture layer, the covering insulating layer, the insulating layer, and the aluminum oxide layer, and the storage unit is provided for each of the multiple conductive layers among the multiple insulating layers and the multiple conductive layers that are alternately stacked.

5. The method for manufacturing a semiconductor device according to claim 4, Each of the plurality of memory cells includes a control gate, each of the plurality of conductive layers is connected to the control gates, and the control gates control writing or erasing of the memory cells.

6. The method for manufacturing a semiconductor device according to claim 1, The conductive layer contains chlorine as an impurity. 7 . The method for manufacturing a semiconductor device according to claim 1 , wherein the first gas includes at least one of C 2 H 2 , C 2 H 4 , and C 3 H 6 . 8 . The method for manufacturing a semiconductor device according to claim 1 , wherein the conductive layer is formed using a CVD method or an ALD method.

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