Display panel and display device

Abstract

The present disclosure provides a display panel and a display device, which belong to the field of display technology. In the display panel, the pixel located on one side of the substrate includes a first transistor with a dual-gate structure, that is, the first transistor includes a first gate metal layer and a second gate metal layer stacked in sequence and coupled to each other in a direction away from the substrate. Since the orthographic projection of the second gate metal layer on the substrate is located within the orthographic projection of the first gate metal layer on the substrate, the edge of the second gate metal layer will not be located at the edge of the first gate metal layer. Therefore, when the second gate metal layer is formed, the edge of the second gate metal layer will not have a further larger slope angle due to the slope angle of the edge of the first gate metal layer, and then when an interlayer dielectric layer is formed on the side of the second gate metal layer, the interlayer dielectric layer is not prone to breakage. Accordingly, the source and drain metal layer formed on one side of the interlayer dielectric layer and the second gate metal layer will not have the problem of signal crosstalk.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] A low temperature polycrystalline silicon oxide (LTPO) display panel is a display panel including low temperature polycrystalline silicon (LTPS) transistors and indium gallium zinc oxide (IGZO) transistors.

[0003] In related art, IGZO transistors in LTPO display panels typically include an active layer, two gate metal layers, an interlayer dielectric, and a source / drain metal layer stacked sequentially on one side of a substrate. The orthographic projections of the two gate metal layers on the substrate overlap, and the orthographic projections of signal lines on the same layer as the source / drain metal layers overlap with the orthographic projections of the two gate metal layers on the substrate.

[0004] However, because the edges of the two gate metal layers in the related art have a large slope angle, the interlayer dielectric formed on the side of the two gate metal layers away from the substrate is prone to fracture, which in turn causes signal crosstalk between the source and drain metal layers and the gate metal layer located on the upper and lower sides of the interlayer dielectric. Summary of the Invention

[0005] The present disclosure provides a display panel and display device that can solve the problem in related art of transistors with a dual-gate structure where the interlayer dielectric layer is prone to breakage, resulting in signal crosstalk between the source / drain metal layer and the gate metal layer. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, comprising:

[0007] substrate;

[0008] a plurality of pixels located on one side of the substrate, each pixel comprising: a first transistor, the first transistor comprising: a first gate metal layer, a first active layer, a second gate metal layer, and a first source-drain metal layer stacked in sequence in a direction away from the substrate;

[0009] and an interlayer dielectric layer located between the second gate metal layer and the first source / drain metal layer;

[0010] The orthographic projection of the second gate metal layer on the substrate is located within the orthographic projection of the first gate metal layer on the substrate, the second gate metal layer is coupled to the first gate metal layer, and the first source-drain metal layer is coupled to the first active layer.

[0011] Optionally, the first source-drain metal layer includes: a first signal transfer portion and a source-drain metal portion coupled to each other;

[0012] Among them, the orthographic projection of the first signal conversion part on the substrate overlaps with the orthographic projection of the first gate metal layer on the substrate, and does not overlap with the orthographic projection of the second gate metal layer on the substrate; the orthographic projection of the source and drain metal part on the substrate overlaps with the orthographic projection of the first gate metal layer on the substrate and the orthographic projection of the second gate metal layer on the substrate.

[0013] Optionally, an orthographic projection of a coupling portion of the second gate metal layer and the first gate metal layer on the substrate does not overlap with an orthographic projection of the first active layer on the substrate.

[0014] Optionally, the display panel further includes:

[0015] a first overlapping via located on the first gate metal layer, a second overlapping via located on the second gate metal layer, and a second signal transfer portion;

[0016] Two ends of the second signal transfer portion are respectively coupled to the first overlapping via and the second overlapping via, so as to couple the second gate metal layer to the first gate metal layer.

[0017] Optionally, the second signal transfer portion reuses the first source and drain metal layer.

[0018] Optionally, the distance between the first signal transfer portion and the substrate is smaller than the distance between the second signal transfer portion and the substrate.

[0019] Optionally, a distance between a portion of the first source / drain metal layer coupled to the first active layer and the first overlapping via is greater than a distance threshold.

[0020] Optionally, the first overlapping via hole passes through the first gate metal layer, and / or the second overlapping via hole passes through the second gate metal layer.

[0021] Optionally, the display panel further includes:

[0022] at least one first insulating layer located between the first gate metal layer and the first active layer, and at least one second insulating layer located between the first active layer and the second gate metal layer;

[0023] The second gate metal layer and the first gate metal layer are coupled to each other through a via hole penetrating the at least one first insulating layer and the at least one second insulating layer.

[0024] Optionally, the display panel includes:

[0025] Two first insulating layers are located between the first gate metal layer and the first active layer, and one second insulating layer is located between the first active layer and the second gate metal layer.

[0026] Optionally, each of the pixels further includes: a second transistor, the second transistor including: a second active layer, a third gate metal layer, and a second source-drain metal layer stacked in sequence in a direction away from the substrate;

[0027] The third gate metal layer is closer to the substrate than the first gate metal layer, the second source / drain metal layer and the first source / drain metal layer are located in the same layer, and the second source / drain metal layer is coupled to the second active layer.

[0028] Optionally, in the first transistor, the material of the first active layer is indium gallium zinc oxide (IGZO) material; and in the second transistor, the material of the second active layer is low-temperature polycrystalline silicon (LTPS) material.

[0029] Optionally, the display panel further includes:

[0030] at least one third insulating layer located between the third gate metal layer and the first gate metal layer;

[0031] at least one fourth insulating layer located between the second active layer and the third gate metal layer;

[0032] and at least one fifth insulating layer located between the substrate and the second active layer.

[0033] Optionally, the substrate is made of a flexible material.

[0034] On the other hand, a display device is provided, comprising: a power supply component, and the display panel according to the above aspect;

[0035] The power supply component is coupled to the display panel and is used to supply power to the display panel.

[0036] The beneficial effects of the technical solutions provided by the embodiments of the present disclosure include at least:

[0037] A display panel and a display device are provided. In the display panel, a pixel located on one side of a substrate includes a first transistor having a dual-gate structure, and the first transistor includes a first gate metal layer and a second gate metal layer stacked in sequence and coupled to each other in a direction away from the substrate. Because the orthographic projection of the second gate metal layer on the substrate is located within the orthographic projection of the first gate metal layer on the substrate, that is, the edge of the second gate metal layer is not located at the edge of the first gate metal layer, but is located within the orthographic projection of the first gate metal layer on the substrate. Therefore, when the second gate metal layer is formed, the edge of the second gate metal layer will not have a further larger slope angle due to the slope angle of the edge of the first gate metal layer, and further, when an interlayer dielectric layer is formed on the side of the second gate metal layer, the interlayer dielectric layer is less likely to break. Accordingly, the source and drain metal layer formed on the side of the interlayer dielectric layer and the second gate metal layer will not have signal crosstalk problems. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0039] Figure 1 This is a top view of a region corresponding to an oxide transistor in a display panel in the related art;

[0040] Figure 2 yes Figure 1 a cross-sectional view corresponding to the structure shown;

[0041] Figure 3 is a simplified top view of a display panel provided by an embodiment of the present disclosure;

[0042] Figure 4 is a cross-sectional view of a display panel including a first transistor provided by an embodiment of the present disclosure;

[0043] Figure 5 is a top view of a display panel including a first transistor provided by an embodiment of the present disclosure;

[0044] Figure 6 is a cross-sectional view of another display panel including a first transistor provided by an embodiment of the present disclosure;

[0045] Figure 7 is a top view of another display panel including a first transistor provided by an embodiment of the present disclosure;

[0046] Figure 8 is a cross-sectional view of a display panel including a first transistor and a second transistor provided by an embodiment of the present disclosure;

[0047] Figure 9 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure.

[0048] The above drawings illustrate specific embodiments of the present disclosure, which will be described in more detail below. These drawings and textual descriptions are not intended to limit the scope of the present disclosure in any way, but rather to illustrate the concepts of the present disclosure to those skilled in the art by reference to specific embodiments. DETAILED DESCRIPTION

[0049] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0050] The terms used in the embodiments of the present disclosure are only used to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" or "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "a" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Words such as "include" or "comprising" mean that the elements or objects appearing before "include" or "comprising" include the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. "Up", "down", "left" or "right" are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. The term "and / or" used in the embodiments of the present disclosure indicates that three relationships may exist. For example, "A and / or B" may represent the following three situations: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0051] Figure 1 FIG. 1 shows a top view of a related art oxide transistor including a dual-gate structure. Figure 2 yes Figure 1 The cross-sectional view corresponding to the structure shown. Figure 1 and Figure 2 It can be seen that the edge of the gate metal layer GATE1 (hereinafter referred to as the first gate metal layer GATE1) on the side close to the substrate of the oxide transistor has a large slope angle, generally about 45 degrees. As a result, the edge of the gate insulator (GI) formed on the side away from the substrate also has a large slope angle. Figure 2 In the related art, when another gate metal layer GATE2 (referred to as the second gate metal layer GATE2 in the following embodiment) is formed on the side of the first gate metal layer GATE1 away from the substrate, which can also be understood as being on the side of the gate insulating layer away from the substrate, the second gate metal layer GATE2 is often arranged to half-cover the edge of the first gate metal layer GATE1. Therefore, the second gate metal layer GATE2 also has a large slope angle at this half-covering position. Generally, the slope angle of the second gate metal layer GATE2 can reach about 70 degrees or even more than 70 degrees.

[0052] On this basis, it has been tested that when an interlayer dielectric (ILD) layer is formed on the side of the second gate metal layer GATE2 away from the substrate, the ILD layer is very likely to crack at the location where the slope angle exists, that is, the ILD layer is prone to cracks. Figure 1 and Figure 2 This is indicated by the dotted line. This can cause a short circuit between the source / drain metal layer formed on the side of the ILD layer away from the substrate and the second gate metal layer, GATE2. This can generate signal crosstalk between the source / drain metal layer and the second gate metal layer, affecting the normal operation of the dual-gate oxide transistor and causing display anomalies (e.g., bright dots or bright lines across the entire screen) on the display panel, severely impacting product yield. This problem is also known as the ILD crack problem.

[0053] The ILD layer can be formed using chemical vapor deposition (CVD). Because CVD often uses a buffered oxide etch (BOE) and post-etch cleaning (CLN) processes, this can easily lead to cracks in the ILD layer during formation. Furthermore, the edges described in the above embodiments may refer to edges whose lengths are not parallel to the substrate. Figure 1 Also shown is an active layer and a source-drain metal layer included in the dual-gate oxide transistor.

[0054] The embodiments of the present disclosure provide a display panel that does not have an ILD Crack problem and has a good product yield. Figure 3 FIG is a top view of a display panel provided by an embodiment of the present disclosure. Figure 3 As shown, the display panel includes: a substrate 01. A plurality of pixels 02 are located on one side of the substrate 01. The plurality of pixels 02 can be arranged on the substrate 01 as shown in FIG. Figure 3 The array arrangement shown can also be irregular.

[0055] Figure 4 is a cross-sectional view of a display panel provided by an embodiment of the present disclosure. Figure 4 As shown, each pixel 02 described in the embodiment of the present disclosure includes at least a first transistor T1. The first transistor T1 comprises a first gate metal layer GATE1, a first active layer (poly) P1, a second gate metal layer GATE2, and a first source and drain metal layer SD1, stacked sequentially in a direction away from the substrate 01, and an interlayer dielectric layer ILD located between the second gate metal layer GATE2 and the first source and drain metal layer SD1. In other words, the first transistor T1 is a dual-gate transistor, such as an oxide transistor.

[0056] Figure 5 1 is a top view of a display panel including a first transistor provided by an embodiment of the present disclosure. Figure 4 and Figure 5 It can be seen that in the embodiment of the present disclosure, the orthographic projection of the second gate metal layer GATE2 included in the first transistor T1 on the substrate 01 is located within the orthographic projection of the first gate metal layer GATE1 on the substrate 01, the second gate metal layer GATE2 is coupled to the first gate metal layer GATE1 (i.e., electrically connected), and the first source and drain metal layer SD1 is coupled to the first active layer P1.

[0057] The second gate metal layer GATE2 and the first gate metal layer GATE1 coupled to each other can serve as the gate of the first transistor T1, and the first source-drain metal layer SD1 can serve as the source and drain of the first transistor T1. Figure 4 The first source / drain metal layer SD1 may include two parts separated from each other, one of which may serve as the source S1 and the other as the drain D1. The interlayer dielectric layer ILD may be used to insulate the second gate metal layer GATE2 from the first source / drain metal layer SD1 to avoid signal interference. Figure 5 A partial top view of two adjacent first transistors T1 is shown.

[0058] Since the orthographic projection of the second gate metal layer GATE2 on the substrate 01 in the embodiment of the present disclosure is located within the orthographic projection of the first gate metal layer GATE1 on the substrate 01, Figure 4 and Figure 5As shown, the second gate metal layer GATE2 will not be formed at either end of the first gate metal layer GATE1, that is, it will not be formed at the edge of the first gate metal layer GATE1 having a slope angle. Furthermore, when the second gate metal layer GATE2 is formed on one side of the first gate metal layer GATE1, the edge of the second gate metal layer GATE2 will no longer have a large slope angle. In this way, when the interlayer dielectric layer ILD is formed on one side of the second gate metal layer GATE2, the interlayer dielectric layer ILD is less likely to crack. In other words, the ILD cracking problem described in the above embodiment will not occur. Accordingly, a short is less likely to occur between the first source and drain metal layer SD1 formed on one side of the interlayer dielectric layer ILD and the second gate metal layer GATE2, and signal crosstalk will not occur between the second gate metal layer GATE2 and the first source and drain metal layer SD1, ensuring a good product yield of the display panel.

[0059] In summary, an embodiment of the present disclosure provides a display panel. In the display panel, a pixel located on one side of the substrate includes a first transistor with a dual gate, that is, the first transistor includes a first gate metal layer and a second gate metal layer stacked in sequence and coupled to each other in a direction away from the substrate. Since the orthographic projection of the second gate metal layer on the substrate is located within the orthographic projection of the first gate metal layer on the substrate, that is, the edge of the second gate metal layer will not be located at the edge of the first gate metal layer, but will be located within the orthographic projection of the first gate metal layer on the substrate. Therefore, when the second gate metal layer is formed, the edge of the second gate metal layer will not have a further larger slope angle due to the slope angle of the edge of the first gate metal layer, and further, when an interlayer dielectric layer is formed on the side of the second gate metal layer, the interlayer dielectric layer is not prone to breakage. Accordingly, the source and drain metal layer formed on one side of the interlayer dielectric layer and the second gate metal layer will not have the problem of signal crosstalk.

[0060] Figure 6 is a cross-sectional view of another display panel provided by an embodiment of the present disclosure. Figure 7 yes Figure 6 A top view of the structure shown. Figure 6 and Figure 7 It can be seen that the first source-drain metal layer SD1 may include: a first signal transfer portion SD11 and a source-drain metal portion SD12 coupled to each other. Figure 7 Two adjacent first transistors T1 are also schematically shown.

[0061] The orthographic projection of the first signal transfer portion SD11 on substrate 01 overlaps with the orthographic projection of the first gate metal layer GATE1 on substrate 01, and does not overlap with the orthographic projection of the second gate metal layer GATE2 on substrate 01. The orthographic projection of the source / drain metal portion SD12 on substrate 01 overlaps with both the orthographic projection of the first gate metal layer GATE1 and the orthographic projection of the second gate metal layer GATE2 on substrate 01.

[0062] It should be noted that, in addition to the first transistor T1, the pixel P1 also includes multiple other transistors. Currently, the most common pixel has a 7T1C structure (i.e., including 7 transistors and 1 capacitor). Based on the setting position of the first signal transfer portion SD11 and the source-drain metal portion SD12, it can be determined that: wherein, the source-drain metal portion SD12 can be used to form the source S1 and drain D1 described in the above embodiment. The first signal transfer portion SD11 can be used to couple the first transistor T1 with other transistors in the pixel except the first transistor T1 to form a signal loop with other transistors, and ultimately achieve the purpose of lighting up the light-emitting element included in the pixel P1. For example, the other transistor can be a driver transistor in the pixel P1.

[0063] In addition, reference Figure 6 It can also be seen that the first gate metal layer GATE1 may include: a gate metal transfer portion GATE11 and a gate metal portion GATE12 coupled to each other. Like the first signal transfer portion SD11, the gate metal transfer portion GATE11 can also be used to couple the first transistor T1 with other transistors in the pixel other than the first transistor T1 to form a signal loop. The difference is that the first signal transfer portion SD1 can be used to transfer the source S1 or drain D1 of the first transistor T1 with the source S1 or drain D1 of other transistors, while the gate metal portion GATE12 can be used to transfer the gate of the first transistor T1 with the gate of other transistors.

[0064] The orthographic projection of the gate metal transfer portion GATE11 on the substrate 01 may overlap with the orthographic projection of the first signal transfer portion SD11 on the substrate 01 .

[0065] Assuming that the first signal transfer portion SD11 and the gate metal transfer portion GATE11 are both referred to as horizontal wiring located in the display area, based on the above embodiment, it can be seen that in the embodiment of the present disclosure, the horizontal wiring located in the display area only includes the first gate metal layer GATE1, and the first transistor T1 located in the display area includes the first gate metal layer GATE1 and the second gate metal layer GATE2. In other words, the second gate metal layer GATE2 exists only at the location of the first transistor T1. In this way, combined with Figure 7 It can be seen that the first signal transfer portion SD11 can directly cross the line on the side of the first gate metal layer GATE1 away from the substrate 01 (ie, above), which reliably solves the ILD Crack problem.

[0066] Optionally, the orthographic projection of the coupling portion between the second gate metal layer GATE2 and the first gate metal layer GATE1 on the substrate 01 may not overlap with the orthographic projection of the first active layer P1 on the substrate 01 .

[0067] As an optional implementation, continue to refer to Figure 7 It can be seen that the display panel described in the embodiment of the present disclosure may further include: a first overlapping via K1 located on the first gate metal layer GATE1, a second overlapping via K2 located on the second gate metal layer GATE2, and a second signal transfer portion B1.

[0068] Two ends of the second signal transfer portion B1 may be coupled to the first overlapping via K1 and the second overlapping via K2 respectively, so as to couple the second gate metal layer GATE2 to the first gate metal layer GATE1.

[0069] Optionally, the first overlapping via K1 and the second overlapping via K2 can both be formed by a CNT etching process, so the first overlapping via K1 and the second overlapping via K2 can also be referred to as CNT vias. In other words, the second gate metal layer GATE2 and the first gate metal layer GATE1 described in the embodiment of the present disclosure can be overlapped via CNT vias. In addition, the first overlapping via K1 and the second overlapping via K2 can both be filled with carbon nanotube material to enhance the transfer conductivity between the second gate metal layer GATE2 and the first gate metal layer GATE1, ensuring reliable signal transmission.

[0070] Optional, still combined Figure 7 It can be seen that the second signal transfer portion B1 described in the embodiment of the present disclosure can reuse the first source / drain metal layer SD1. That is, in the embodiment of the present disclosure, the first source / drain metal layer SD1 can be formed simultaneously on the side of the interlayer dielectric ILD away from the substrate 01 through a single patterning process, achieving effective overlap between the second gate metal layer GATE2 and the first gate metal layer GATE1, and simultaneously forming the source S1, drain D1, and second signal line L2. This simplifies the manufacturing process, reduces manufacturing costs, and improves manufacturing efficiency.

[0071] Optionally, the first overlapping via K1 may pass through the first gate metal layer GATE1, and / or the second overlapping via K2 may pass through the second gate metal layer GATE2, so as to further ensure reliable coupling between the first gate metal layer GATE1 and the second gate metal layer GATE2.

[0072] Optionally, because the second gate metal layer GATE2 is not present on the side of the first signal transfer portion SD11 closest to the substrate 01, the distance between the first signal transfer portion SD11 in the first source / drain metal layer SD1 described in the embodiment of the present disclosure and the substrate 01 can be smaller than the distance between the second signal transfer portion B1, which couples the second gate metal layer GATE2 with the first gate metal layer GATE1 and reuses the first source / drain metal layer SD1, and the substrate 01. This also confirms that the portion of the first source / drain metal layer SD1 closer to the substrate 01 significantly reduces the risk of fracture in this portion.

[0073] Optionally, in the embodiment of the present disclosure, the distance d0 between the portion where the first source / drain metal layer SD1 is coupled to the first active layer P1 and the first overlapping via K1 may be greater than a distance threshold. That is, the distance d0 between the portion where the first source / drain metal layer SD1 is coupled to the first active layer P1 and the first overlapping via K1 may be larger.

[0074] For example, the first overlapping via K1 can be Figure 7 In the circle shown, the spacing threshold may be the aperture of the first overlapping via K1. That is, the spacing d0 between the portion where the first source / drain metal layer SD1 is coupled to the first active layer P1 and the first overlapping via K1 may be greater than twice the aperture of the first overlapping via K1.

[0075] Optional, reference Figure 7 , the first active layer P1 can be extended to a side away from the second signal transfer portion B1, and the second signal transfer portion B1 is provided on the extended portion and coupled to the first active layer P1 through the transfer via K0. Or, combined with Figure 7 The first active layer P1 may be extended upward, and a first signal transfer portion SD11 may be provided to couple with the first active layer P1 at the upwardly extended portion.

[0076] It should be noted that Figure 7 Only the coupling between the first signal transfer portion SD11 included in the first source / drain metal layer SD1 and the first active layer P1 is schematically illustrated. By providing a larger spacing d0 between the portion where the first source / drain metal layer SD1 is coupled to the first active layer P1 and the first overlapping via K1, sufficient space can be ensured between the portion where the first active layer P1 is coupled to the first signal transfer portion SD11 and the second signal transfer portion B1 that couples the second gate metal layer GATE2 to the first gate metal layer GATE1. This avoids signal interference when the second signal transfer portion B1 reuses the first source / drain metal layer SD1, prevents signal short circuits, and further reduces the probability of signal crosstalk.

[0077] It should also be noted that to prevent signal interference between two adjacent conductive layers, at least one insulating layer is generally disposed between the two adjacent layers. For this reason, in the disclosed embodiment, the insulating layer may be thicker at the portion where the first source / drain metal layer SD1 and the first active layer P1 are coupled. This prevents breakage of other signal lines located on the side of the coupled portion away from the substrate 01.

[0078] As another optional implementation, combining Figure 4It can be seen that the display panel described in the embodiment of the present disclosure may further include: at least one first insulating layer M1 located between the first gate metal layer GATE1 and the first active layer P1, and at least one second insulating layer M2 located between the second gate metal layer GATE2 and the first gate metal layer GATE1. On this basis, the second gate metal layer GATE2 and the first gate metal layer GATE1 may be coupled to each other via a via hole penetrating the at least one first insulating layer M1 and the at least one second insulating layer M2.

[0079] For example, after forming the at least one first insulating layer M1 and the at least one second insulating layer M2, a via hole can be pre-formed (e.g., etched) through the at least one first insulating layer M1 and the at least one second insulating layer M2, so that both the second gate metal layer GATE2 and the first gate metal layer GATE1 are exposed. The second gate metal layer GATE2 can then be extended from the via hole to a side of the first gate metal layer GATE1 to overlap the first gate metal layer GATE1.

[0080] Optionally, the display panel described in the embodiment of the present disclosure may include: two first insulating layers M1 located between the first gate metal layer GATE1 and the first active layer P1, and a second insulating layer M2 located between the second gate metal layer GATE2 and the first gate metal layer GATE1.

[0081] Optionally, the two first insulating layers M1 can be referred to as a first gate insulating layer GI1 and a buffer layer BUFFER, respectively. Furthermore, the materials of the two first insulating layers M1 can be silicon nitride and silicon oxide, respectively, and the material of the second insulating layer M2 can be silicon nitride. Of course, the disclosed embodiments do not limit the materials of the insulating layers.

[0082] Figure 8 FIG is a cross-sectional view of another display panel provided by an embodiment of the present disclosure. Figure 8 As shown, each pixel 02 may further include a second transistor T2, and the second transistor T2 may include a second active layer P2, a third gate metal layer GATE3, and a second source / drain metal layer SD2 stacked sequentially in a direction away from the substrate 01. That is, the second transistor T2 may be a single-gate transistor.

[0083] refer to Figure 8 It can be seen that the third gate metal layer GATE3 is closer to the substrate 01 than the first gate metal layer GATE1. That is, the GATE1, GATE2, and GATE3 described in this embodiment of the disclosure merely identify the film layers and are not intended to limit their positional relationships. The second source / drain metal layer SD2 can be located on the same layer as the first source / drain metal layer SD1, and the second source / drain metal layer SD2 can be coupled to the second active layer P2.

[0084] The third gate metal layer GATE3 can be used as the gate of the second transistor T2, and the second source-drain metal layer SD2 can be used as the source and drain of the second transistor T2. Figure 8 Like the first source-drain metal layer SD1 , the second source-drain metal layer SD2 may also include two parts spaced apart from each other, one part of which may serve as the source S2 , and the other part of which may serve as the drain D2 .

[0085] Optional, continue to refer to Figure 8 It can also be seen that the display panel recorded in the embodiment of the present disclosure may further include: at least one third insulating layer M3 located between the third gate metal layer GATE3 and the first gate metal layer GATE1, at least one fourth insulating layer M4 located between the second active layer P2 and the third gate metal layer GATE3, and at least one fifth insulating layer M5 located between the substrate 01 and the second active layer P2.

[0086] For example, Figure 8 The display panel shown includes: a third insulating layer M3, a fourth insulating layer M4 and two fifth insulating layers M5. The fourth insulating layer M4 may also be referred to as a second gate insulating layer GI2.

[0087] The insulating layers described in the above embodiments can be used to insulate adjacent upper and lower layers to avoid mutual interference of signals, and the insulating layers can be made of inorganic materials.

[0088] Based on the above structure, refer to Figure 8 It can be further seen that the first source / drain metal layer SD1 and the first active layer P1 can be coupled via vias penetrating the film layer between the first source / drain metal layer SD1 and the first active layer P1. The second source / drain metal layer SD2 and the second active layer P2 can also be coupled via vias penetrating the film layer between the second source / drain metal layer SD2 and the second active layer P2.

[0089] Optionally, in the embodiment of the present disclosure, the first transistor T1 may be an oxide transistor, that is, the first active layer P1 in the first transistor T1 may be made of an oxide material. For example, the material of the first active layer P1 may be indium gallium zinc oxide (IGZO) material. Accordingly, the first transistor T1 may also be referred to as an IGZO transistor. The second transistor T2 may be a non-oxide transistor, that is, the material of the second active layer P2 in the second transistor T1 may not be made of an oxide material. For example, the material of the second active layer P2 may be low temperature poly-silicon (LTPS) material. Accordingly, the second transistor T2 may be an LTPS transistor. On this basis, the display panel recorded in the embodiment of the present disclosure may be referred to as an LTPO display panel.

[0090] Optionally, each pixel 02 generally includes a pixel circuit and a light-emitting element coupled to each other, and the above-mentioned first transistor T1 and second transistor T2 both belong to the structure of the pixel circuit. And as described in the above example, the pixel circuit generally includes at least a switching transistor and a driving transistor. Among them, the switching transistor is coupled to the driving transistor, and the driving transistor is coupled to the light-emitting element. The switching transistor is used to transmit a data signal to the driving transistor, so that the driving transistor transmits a driving signal to the coupled light-emitting element based on the data signal to drive the light-emitting element to emit light. The switching transistor in the pixel circuit is generally a first transistor T1 made of IGZO material, and other transistors other than the switching transistor (such as the driving transistor) are generally a second transistor T2 made of LTPS material.

[0091] Testing has shown that transistors made from IGZO material have lower leakage than transistors made from LTPS material, meaning they exhibit low leakage characteristics. This allows the display panel to consume less power at low refresh rates while avoiding the low refresh rate display anomalies caused by leakage from LTPS transistors. Furthermore, transistors made from IGZO material exhibit better operating uniformity, which can improve color shift.

[0092] Optionally, the material of the substrate 01 described in the embodiments of the present disclosure may be a flexible material. For example, the flexible material may be polyimide (PI). Of course, in some embodiments, the substrate 01 may also be made of other materials, such as glass.

[0093] In summary, an embodiment of the present disclosure provides a display panel. In the display panel, the pixel located on one side of the substrate includes a first transistor with a dual-gate structure, that is, the first transistor includes a first gate metal layer and a second gate metal layer stacked in sequence and coupled to each other in a direction away from the substrate. Since the orthographic projection of the second gate metal layer on the substrate is located within the orthographic projection of the first gate metal layer on the substrate, that is, the edge of the second gate metal layer will not be located at the edge of the first gate metal layer, but will be located within the orthographic projection of the first gate metal layer on the substrate. Therefore, when the second gate metal layer is formed, the edge of the second gate metal layer will not have a further larger slope angle due to the slope angle of the edge of the first gate metal layer, and further, when an interlayer dielectric layer is formed on the side of the second gate metal layer, the interlayer dielectric layer is not prone to breakage. Accordingly, the source and drain metal layer formed on one side of the interlayer dielectric layer and the second gate metal layer will not have the problem of signal crosstalk.

[0094] Figure 9 Schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 9 As shown, the display device includes: a power supply component J1, and Figures 3 to 8 Any of the display panels 00 shown.

[0095] The power supply component J1 may be coupled to the display panel 00 and used to supply power to the display panel 00 .

[0096] Optionally, the display device can be any product or component with a display function, such as a flexible OLED display device, an LTPO display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, and a navigator.

[0097] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display panel, characterized in that: The display panel includes: substrate; A plurality of pixels located on one side of the substrate, each pixel comprising: a first transistor, the first transistor comprising: a first gate metal layer, a first active layer, a second gate metal layer, and a first source-drain metal layer stacked in sequence in a direction away from the substrate; the first source-drain metal layer comprising: a first signal transfer portion and a source-drain metal portion coupled to each other; and an interlayer dielectric layer located between the second gate metal layer and the first source / drain metal layer; In which, the orthographic projection of the second gate metal layer on the substrate is located within the orthographic projection of the first gate metal layer on the substrate, the second gate metal layer is coupled to the first gate metal layer, and the first source-drain metal layer is coupled to the first active layer; the orthographic projection of the first signal transfer part on the substrate overlaps with the orthographic projection of the first gate metal layer on the substrate, and does not overlap with the orthographic projection of the second gate metal layer on the substrate; the orthographic projection of the source-drain metal part on the substrate overlaps with the orthographic projection of the first gate metal layer on the substrate and the orthographic projection of the second gate metal layer on the substrate.

2. The display panel according to claim 1, wherein: An orthographic projection of a coupling portion of the second gate metal layer and the first gate metal layer on the substrate does not overlap with an orthographic projection of the first active layer on the substrate.

3. The display panel according to claim 1 or 2, wherein: The display panel further includes: a first overlapping via located on the first gate metal layer, a second overlapping via located on the second gate metal layer, and a second signal transfer portion; Two ends of the second signal transfer portion are respectively coupled to the first overlapping via and the second overlapping via, so as to couple the second gate metal layer to the first gate metal layer.

4. The display panel according to claim 3, wherein: The second signal transfer portion reuses the first source and drain metal layer.

5. The display panel according to claim 4, wherein: The distance between the first signal transfer portion and the substrate is smaller than the distance between the second signal transfer portion and the substrate.

6. The display panel according to claim 3, wherein: A distance between a portion of the first source / drain metal layer coupled to the first active layer and the first overlapping via is greater than a distance threshold.

7. The display panel according to claim 3, wherein: The first overlapping via hole penetrates the first gate metal layer, and / or the second overlapping via hole penetrates the second gate metal layer.

8. The display panel according to claim 1 or 2, wherein: The display panel further includes: at least one first insulating layer located between the first gate metal layer and the first active layer, and at least one second insulating layer located between the first active layer and the second gate metal layer; The second gate metal layer and the first gate metal layer are coupled to each other through a via hole penetrating the at least one first insulating layer and the at least one second insulating layer.

9. The display panel according to claim 8, wherein: The display panel includes: Two first insulating layers are located between the first gate metal layer and the first active layer, and one second insulating layer is located between the first active layer and the second gate metal layer.

10. The display panel according to claim 1 or 2, characterized in that: Each of the pixels further includes: a second transistor, the second transistor including: a second active layer, a third gate metal layer, and a second source / drain metal layer stacked in sequence in a direction away from the substrate; The third gate metal layer is closer to the substrate than the first gate metal layer, the second source / drain metal layer and the first source / drain metal layer are located in the same layer, and the second source / drain metal layer is coupled to the second active layer.

11. The display panel according to claim 10, wherein: In the first transistor, the material of the first active layer is indium gallium zinc oxide IGZO material; Furthermore, in the second transistor, the material of the second active layer is low-temperature polysilicon (LTPS) material.

12. The display panel according to claim 10, wherein: The display panel further includes: at least one third insulating layer located between the third gate metal layer and the first gate metal layer; at least one fourth insulating layer located between the second active layer and the third gate metal layer; and at least one fifth insulating layer located between the substrate and the second active layer.

13. The display panel according to claim 1 or 2, characterized in that: The substrate is made of flexible material.

14. A display device, characterized in that: The display device comprises: a power supply component, and a display panel according to any one of claims 1 to 13; The power supply component is coupled to the display panel and is used to supply power to the display panel.

Images