Source-side process method of LDMOS device

Abstract

The invention discloses a source end process method of an LDMOS device, which comprises coating a photoresist on a substrate or an epitaxial surface, then opening the photoresist at the source end of the LDMOS device to form an injection window of the source end, performing a first ion implantation on the source end to form a source region in the substrate or the epitaxial layer; then partially removing the photoresist in the source region to form a new source end implantation window, redefining the source region and the channel; etching the polysilicon layer in the window under the definition of the newly formed source region window, removing the polysilicon layer in the window, and exposing the silicon oxide layer under the polysilicon layer; and performing a second doping ion implantation in the source region window. After high-energy implantation, the invention redefines the LDMOS channel by dry etching a small amount of de-bonding and polysilicon etching again to reduce the influence of high-energy implantation on the LDMOS channel.

Description

Technical Field

[0001] The invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a source end process method of an LDMOS device integrated in a BCD process. Background Art

[0002] DMOS (Double-diffused MOS) is currently widely used in power management chips due to its high voltage resistance, high current driving capability and extremely low power consumption. In LDMOS (Lateral Double-diffused MOSFET, lateral double diffused field effect transistor) devices, on-resistance is an important indicator. In the BCD (Bipolar-CMOS-DMOS) process, although LDMOS is integrated with CMOS in the same chip, due to the high breakdown voltage BV (Breakdown Voltage) and low characteristic on-resistance R SP There is a contradiction / compromise between (Specific on-Resistance), which often cannot meet the requirements of switch tube applications. High-voltage LDMOS has the characteristics of high voltage and high current of discrete devices, and absorbs the advantages of high-density intelligent logic control of low-voltage integrated circuits. A single chip can achieve the functions that can only be completed by multiple chips, greatly reducing the area, reducing costs, and improving energy efficiency. It is in line with the development direction of miniaturization, intelligence, and low energy consumption of modern power electronic devices. Breakdown voltage and on-resistance are key parameters for measuring high-voltage LDMOS devices. Therefore, in the case of obtaining the same breakdown voltage, R should be reduced as much as possible. SP To improve product competitiveness.

[0003] In an existing LDMOS structure, such as Figure 1 As shown, taking the most common NLDMOS device as an example, in the figure 101 is a P-type substrate or a P-type epitaxial, 103 is a gate dielectric layer, 104 is a polysilicon gate, 105 is a drift region and RESURF layer injection, 107 is a P-type body region injection, 108 is a gate side wall, 109 is a heavily doped N-type region (source region, drain region), and 110 is a heavily doped P-type region.

[0004] When the BCD process enters the 0.18um node, in order to reduce the source-drain on-resistance Rdson*sp of LDMOS, a shorter channel will be formed through the source end engineering of LDMOS to further reduce Rdson*sp. At the same time, considering the requirements of longitudinal withstand voltage and safe working area, multi-step high-energy injection will be used. In order to play a blocking role, a photoresist with a thickness of more than 1um will be used. At this time, the morphology of the photoresist is not good, and its side morphology is relatively inclined rather than vertical, such as Figure 2As shown, the doping source with high energy implantation passes through the inclined photoresist blocking region and enters the channel of the LDMOS, affecting the threshold voltage Vt and Rdson of the LDMOS. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a source end process method of an LDMOS device, which has more excellent threshold voltage performance and characteristic on-resistance performance.

[0006] In order to solve the above problems, the present invention discloses a source end process method of an LDMOS device, which comprises coating a photoresist on a substrate or an epitaxial surface, then opening the photoresist at the source end of the LDMOS device to form an injection window of the source end, performing a first ion injection on the source end, and forming a source region in the substrate or the epitaxial surface;

[0007] Then, the photoresist in the source area is stripped again to form a new source injection window and redefine the source area and the channel;

[0008] Under the definition of the re-formed source region window, the polysilicon layer in the window is etched to remove the polysilicon layer in the window and expose the silicon oxide layer under the polysilicon layer;

[0009] A second low-energy doping ion implantation is performed into the source region window.

[0010] A further improvement is that in the step 1, the thickness of the coated photoresist is not less than 1 um, and after photolithography, the photoresist is opened to form a window, and the side wall of the photoresist in the window is inclined.

[0011] A further improvement is that in the first step, the first ion implantation is a high-energy ion implantation; the implantation is formed by a one-step implantation or a multi-step implantation.

[0012] A further improvement is that in step one, after the first ion implantation, high-energy ions pass through the photoresist sidewalls in the inclined window, and in addition to forming a source region in the substrate or epitaxy, an additional doping source implantation region is formed, which is formed at the edge of the source region and has an implantation depth less than the source region.

[0013] A further improvement is that the photoresist in the source area is partially removed, and the photoresist in the window area is etched by dry etching to further expand the window area.

[0014] A further improvement is that after the window area is enlarged, 50-100% of the area of ​​the doping source implantation region is also within the window opening range.

[0015] A further improvement is that the second low-energy doping ion implantation is completed in one step or in multiple steps.

[0016] A further improvement is that the first high energy implantation has an implantation energy of 50Kev to 2500Kev.

[0017] A further improvement is that the second low-energy implantation has an implantation energy of 1 KeV to 500 KeV.

[0018] After high energy implantation, the present invention redefines the LDMOS channel by dry etching a small amount of degumming and polysilicon etching again to reduce the influence of high energy implantation on the LDMOS channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 This is a cross-sectional view of a traditional LDMOS device.

[0020] Figure 2 It is a schematic diagram of the present invention first performing high-energy ion implantation.

[0021] Figure 3 It is a schematic diagram of the present invention performing modified etching on the source end photoresist.

[0022] Figure 4 It is a schematic diagram of etching the polysilicon layer in the source end photoresist window according to the present invention.

[0023] Figure 5 It is a schematic diagram of the present invention performing low-energy ion implantation on the source end.

[0024] Figure 6 It is a process flow chart of the present invention.

[0025] Description of Reference Numerals

[0026] 101 is a substrate or epitaxy, 103 is an oxide layer, 104 is a polysilicon layer, and 502 is a photoresist. DETAILED DESCRIPTION

[0027] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0029] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0030] The source end process method of a LDMOS device described in the present invention aims at the problem that high-energy ions pass through the inclined photoresist side wall during source end ion implantation to form an additional doping implantation area in the substrate, which has an adverse effect on the device channel. The present invention adopts a new process method. First, photoresist is coated on the substrate or epitaxial surface, and then the photoresist is opened at the source end of the LDMOS device to form an implantation window of the source end, and the source end is implanted for the first time to form a source area in the substrate or epitaxial. Due to the high-energy ion implantation, the implantation energy is 50Kev to 2500Kev, the thickness of the coated photoresist is not less than 1um, and the photoresist is opened after photolithography to form a window, and the photoresist side wall in the window is in an inclined state. Therefore, in the inclined state, the high-energy ions can penetrate the relatively thin photoresist at the lower part, so in addition to forming the source area, an additional doping source implantation area can be formed at a shallower position in the substrate, which is formed at the edge of the source area and has an implantation depth less than the source area.

[0031] Then, a small amount of the source area photoresist is dry-etched to remove the resist, and the source injection window is further enlarged to form a new source injection window, so that most or all of the doping source injection area is also within the range of the window opening, generally 50 to 100% of the doping source injection area is exposed, and the source area and channel are redefined.

[0032] The polysilicon layer in the window is etched under the definition of the re-formed source region window to remove the polysilicon layer in the window and expose the silicon oxide layer under the polysilicon layer.

[0033] A second low-energy doping ion implantation is performed in the source region window, with an implantation energy of 1 KeV to 500 KeV. The low-energy ion implantation can be completed in one implantation or in multiple steps.

[0034] Through the above process method, the present invention performs a small amount of modified etching on the photoresist after high-energy implantation to redefine the implantation range of the source region, thereby avoiding the influence of the doping source injected with high energy into the photoresist blocking area on the LDMOS channel.

[0035] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A source end process method of an LDMOS device, characterized in that: It includes a substrate or epitaxy, a silicon oxide layer located on the upper surface of the substrate or epitaxy, and a polysilicon layer located on the upper surface of the silicon oxide layer; Step 1: coating a photoresist on the upper surface of the polysilicon layer, then opening the photoresist at the source end of the LDMOS device to form an injection window of the source end, performing a first ion implantation on the source end, and forming a source region in the substrate or epitaxy; The photoresist sidewall in the injection window is in an inclined state. After the first ion injection, the ions pass through the photoresist sidewall in the inclined window, and in addition to forming the source region in the substrate or epitaxy, an additional doping source injection region is formed. The doping source injection region is formed at the edge of the source region, and the injection depth is less than the source region. Step 2: etching the source region photoresist to form an enlarged source injection window. After the window area is enlarged, 50-100% of the doping source injection region is also within the range of the enlarged source injection window, redefining the source region and the channel; Step 3: etching the polysilicon layer in the window under the definition of the enlarged source end injection window, removing the polysilicon layer in the window, and exposing the silicon oxide layer under the polysilicon layer; Step 4: Perform a second doping ion implantation into the enlarged source end implantation window of the source region.

2. The source end process method of the LDMOS device according to claim 1, characterized in that: In the step 1, the thickness of the coated photoresist is not less than 1 um, and after photolithography, the photoresist is opened to form a window, and the side wall of the photoresist in the window is in an inclined state.

3. The source end process method of the LDMOS device according to claim 1, characterized in that: In the step 1, the first ion implantation is a high-energy ion implantation with an implantation energy of 50Kev to 2500Kev; The injection is formed by a one-step injection or a multi-step injection.

4. The source end process method of the LDMOS device according to claim 1, characterized in that: In the step 2, the source region photoresist is etched, and the window region photoresist is etched by dry etching to further expand the window region.

5. The source end process method of the LDMOS device according to claim 1, characterized in that: The second low-energy doping ion implantation has an implantation energy of 1Kev to 500Kev and is completed in one implantation or multiple step-by-step implantations.

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