Semiconductor device and method for manufacturing the same

Abstract

Embodiments mainly relate to a semiconductor device and a method for manufacturing the same. According to an embodiment, the semiconductor device includes: a semiconductor structure portion having a plurality of buried electrode portions and a mesa portion provided between the plurality of buried electrode portions and adjacent to the buried electrode portions, the mesa portion having: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; and a fourth semiconductor region of the second conductivity type provided between the buried electrode portion and the second semiconductor region and having a higher second conductivity type impurity concentration than the second semiconductor region; a gate electrode provided in the buried electrode portion and opposed to a side surface of the second semiconductor region that forms a part of a first side wall of the mesa portion; a gate insulating film provided between the gate electrode and the side surface of the second semiconductor region; and an upper electrode having a main portion provided on the semiconductor structure portion and a contact portion extending from the main portion into the buried electrode portion to reach a second side wall opposite to the first side wall of the mesa portion and in contact with the second semiconductor region and the fourth semiconductor region.

Description

[0001] Related Application

[0002] This application claims priority based on Japanese Patent Application No. 2020-153986 (filing date: September 14, 2020). This application incorporates all the contents of the base application by reference thereto. Technical Field

[0003] The embodiments mainly relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] In a semiconductor device with a trench gate structure, it is possible to reduce the on-resistance by the pitch shrinkage caused by the narrowing of the width of the mesa portion between adjacent trenches. When a trench contact is formed at the center of such a narrowed mesa portion, due to the alignment deviation of lithography, there is a concern about problems such as a deviation in the distance between the channel and the bottom of the trench contact, a deviation in the threshold voltage, and a deviation in the on-resistance. + layer, a deviation in the threshold voltage, and a deviation in the on-resistance. Summary of the Invention

[0005] The embodiments provide a semiconductor device and a method for manufacturing the same that can suppress deviations in the threshold voltage and the on-resistance.

[0006] According to an embodiment, a semiconductor device includes: a semiconductor structure portion having a plurality of buried electrode portions and a mesa portion provided between the plurality of buried electrode portions and adjacent to the buried electrode portions, the mesa portion having: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type provided on the first semiconductor region; a third semiconductor region of the first conductivity type provided on the second semiconductor region; and a fourth semiconductor region of the second conductivity type provided between the buried electrode portion and the second semiconductor region, the second conductivity type impurity concentration being higher than the second conductivity type impurity concentration of the second semiconductor region; a gate electrode provided in the buried electrode portion and facing a side surface of the second semiconductor region that forms a part of a first side wall of the mesa portion; a gate insulating film provided between the gate electrode and the side surface of the second semiconductor region; and an upper electrode having a main portion and a contact portion, the main portion being provided on the semiconductor structure portion, the contact portion extending from the main portion into the buried electrode portion to reach a second side wall opposite to the first side wall of the mesa portion and being in contact with the second semiconductor region and the fourth semiconductor region. Brief Description of the Drawings

[0007] Figure 1 is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0008] Figure 2 is Figure 1Cross-sectional view taken along line A - A' in

[0009] Figures 3A to 8B is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a first embodiment.

[0010] Figure 9 is a schematic cross-sectional view of a semiconductor device according to a second embodiment.

[0011] Figure 10 is Figure 9 Cross-sectional view taken along line B - B' in

[0012] Figure 11A and Figure 11B is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a second embodiment.

[0013] Figure 12 is a schematic cross-sectional view of a semiconductor device according to a third embodiment.

[0014] Figure 13 is Figure 12 Cross-sectional view taken along line C - C' in

[0015] Figures 14A to 17B is a schematic cross-sectional view showing a method of manufacturing a semiconductor device according to a third embodiment.

[0016] Figure 18 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment.

[0017] Figure 19 is Figure 18 Cross-sectional view taken along line D - D' in DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] Hereinafter, embodiments will be described with reference to the accompanying drawings. In addition, in each of the drawings, the same reference numerals are assigned to the same components.

[0019] In the following embodiments, the first conductivity type is set to n-type and the second conductivity type is set to p-type for the description, but the first conductivity type may be set to p-type and the second conductivity type may be set to n-type.

[0020] [First Embodiment]

[0021] Figure 1 is a schematic cross-sectional view of a semiconductor device 1 according to a first embodiment.

[0022] Figure 2 is Figure 1 Cross-sectional view taken along line A - A' in

[0023] The semiconductor device 1 includes a semiconductor structure 10, an upper electrode 60, a lower electrode 50, a gate electrode 30, and a field plate electrode 40. The upper electrode 60 is provided on the upper surface of the semiconductor structure 10, and the lower electrode 50 is provided on the lower surface of the semiconductor structure 10. For example, the upper electrode 60 is a source electrode, and the lower electrode 50 is a drain electrode. The semiconductor device 1 is a vertical semiconductor device in which a current flows in a direction (vertical direction) connecting the lower electrode 50 and the upper electrode 60 by control of the gate electrode 30.

[0024] The substrate, semiconductor layer, and semiconductor region included in the semiconductor structure 10 may be made of, for example, silicon. Alternatively, the substrate, semiconductor layer, and semiconductor region included in the semiconductor structure 10 may be made of, for example, silicon carbide, gallium nitride, or the like.

[0025] The semiconductor structure 10 has an n-type semiconductor structure 10 disposed on the lower electrode 50. + The semiconductor structure 10 includes an n-type drain layer (or substrate) 11 and an n-type drift layer 12 provided on the drain layer 11. The n-type impurity concentration of the drift layer 12 is lower than the n-type impurity concentration of the drain layer 11. The drain layer 11 is electrically connected to the lower electrode 50. In addition, the semiconductor structure 10 includes a plurality of buried electrode portions T and a mesa portion 20 provided between adjacent buried electrode portions T and adjacent to the buried electrode portions T.

[0026] exist Figure 2 In the figure, two directions orthogonal to each other in a plane parallel to the upper surface or the lower surface of the semiconductor structure portion 10 are set as the X direction and the Y direction. The plurality of embedded electrode portions T are separated from each other in the X direction and extend in a stripe shape in the Y direction. The plurality of mesa portions 20 are separated from each other in the X direction and extend in a stripe shape in the Y direction.

[0027] exist Figure 1 In FIG. 1 , any four embedded electrode portions T are represented as a first embedded electrode portion T1 , a second embedded electrode portion T2 , a third embedded electrode portion T3 , and a fourth embedded electrode portion T4 . Figure 1 In the following description, the first buried electrode portion T1, the second buried electrode portion T2, the third buried electrode portion T3, and the fourth buried electrode portion T4 are sometimes referred to as the buried electrode portion T without being distinguished from each other, and the first buried electrode portion 20a, the second buried electrode portion 20b, and the third buried electrode portion 20c are sometimes referred to as the buried electrode portion 20 without being distinguished from each other.

[0028] The first mesa portion 20a is disposed between the first buried electrode portion T1 and the second buried electrode portion T2 and is adjacent to the first buried electrode portion T1 and the second buried electrode portion T2. The second mesa portion 20b is disposed between the second buried electrode portion T2 and the third buried electrode portion T3 and is adjacent to the second buried electrode portion T2 and the third buried electrode portion T3. The third mesa portion 20c is disposed between the third buried electrode portion T3 and the fourth buried electrode portion T4 and is adjacent to the third buried electrode portion T3 and the fourth buried electrode portion T4.

[0029] The buried electrode portions T including the gate electrode 30 and the field plate electrode 40 and the buried electrode portions T not including the gate electrode 30 but including the field plate electrode 40 are alternately repeated in the X direction. In Figure 1 the example shown, the first buried electrode portion T1 and the third buried electrode portion T3 include the gate electrode 30 and the field plate electrode 40. The second buried electrode portion T2 and the fourth buried electrode portion T4 do not include the gate electrode 30 but include the field plate electrode 40.

[0030] The buried electrode portion T not including the gate electrode 30 includes the contact portion 62 which is a part of the upper electrode 60. In Figure 1 the example shown, the second buried electrode portion T2 and the fourth buried electrode portion T4 include the contact portion 62 and the field plate electrode 40.

[0031] The mesa portion 20 extending in the Y direction has two side walls. Among the side walls of the mesa portion 20, the side wall facing the gate electrode 30 is defined as the first side wall 21. The mesa portion 20 has a second side wall 22 on the opposite side of the first side wall 21. The contact portion 62 is in contact with the second side wall 22.

[0032] The mesa portion 20 has an n-type drift region (first semiconductor region) 12a which is a part of the drift layer 12, a p-type base region (second semiconductor region) 13 provided on the drift region 12a, an n + -type source region (third semiconductor region) 14 provided on the base region 13, and a p + -type base contact region (fourth semiconductor region) 15 provided between the base region 13 and the buried electrode portion T.

[0033] The n-type impurity concentration of the source region 14 is higher than the n-type impurity concentration of the drift region 12a. The p-type impurity concentration of the base contact region 15 is higher than the p-type impurity concentration of the base region 13.

[0034] The base contact region 15 is formed in a part of the base region 13. The side surface of the base contact region 15 forms a part of the second side wall 22 of the mesa portion 20.

[0035] The drift region 12a is formed over the entire width direction (X direction) of the mesa portion 20, having side surfaces that form part of the first side wall 21 of the mesa portion 20 and side surfaces that form part of the second side wall 22. The base region 13 is formed over the entire width direction (X direction) of the mesa portion 20, having side surfaces that form part of the first side wall 21 of the mesa portion 20 and side surfaces that form part of the second side wall 22. The source region 14 is formed over the entire width direction (X direction) of the mesa portion 20, having side surfaces that form part of the first side wall 21 of the mesa portion 20 and side surfaces that form part of the second side wall 22. In addition, the upper surface of the source region 14 forms the upper surface of the mesa portion 20.

[0036] The bottom of the buried electrode portion T is located within the drift layer 12 and does not reach the drain layer 11.

[0037] The buried electrode portion T (for example Figure 1 the third buried electrode portion T3 in) includes the gate electrode 30 that faces the side surface of the base region 13 forming part of the first side wall 21 of the second mesa portion 20 and the gate electrode 30 that faces the side surface of the base region 13 forming part of the first side wall 21 of the third mesa portion 20. A gate insulating film 72 is provided between the gate electrode 30 and the side surface of the base region 13.

[0038] The field plate electrode 40 is located approximately at the center in the width direction (X direction) of each buried electrode portion T. An insulating film 71 is provided between the field plate electrode 40 and the drift layer 12, and the field plate electrode 40 does not contact the drift layer 12. An insulating film 73 is provided between the field plate electrode 40 and the gate electrode 30.

[0039] The upper electrode 60 has: a main portion 61 that extends in a planar manner over the semiconductor structure portion 10; and a contact portion 62 that extends from the main portion 61 into the buried electrode portion T (the second buried electrode portion T2 and the fourth buried electrode portion T4 in the Figure 1 illustrated example) and reaches the second side wall 22 of each mesa portion 20. The main portion 61 and the contact portion 62 are integrally formed of a metal material, for example.

[0040] The contact portion 62 contacts and is electrically connected to the source region 14 and the base contact region 15 of each mesa portion 20.

[0041] An insulating film 74 is provided between the gate electrode 30 and the upper electrode 60 and between the field plate electrode 40 and the upper electrode 60.

[0042] The gate electrode 30 faces one side wall (the first side wall 21) of each mesa portion 20 with the gate insulating film 72 interposed therebetween. On the other side wall (the second side wall 22) of each mesa portion 20, the contact portion 62 contacts the source region 14 and the base contact region 15.

[0043] By applying a voltage above the threshold value to the gate electrode 30, an n-type channel (inversion layer) can be formed in the portion of the base region 13 that faces the gate electrode 30.

[0044] The field plate electrode 40 extends within the buried electrode portion T to a position below the gate electrode 30 and the contact portion 62. The bottom of the field plate electrode 40 is located at a position closer to the drain layer 11 than the bottom of the gate electrode 30.

[0045] The field plate electrode 40 is electrically connected to the upper electrode 60, for example. Alternatively, the field plate electrode 40 may also be electrically connected to the gate electrode 30. In the off state where a voltage above the threshold value is no longer applied to the gate electrode 30, the field plate electrode 40 flattens the electric field distribution in the drift layer 12.

[0046] Next, with reference to Figures 3A to 8B , the manufacturing method of the semiconductor device 1 of the first embodiment will be described.

[0047] As Figure 3A shown, a plurality of trenches t and a plurality of mesa portions 20 are formed in the drift layer 12. For example, the trenches t are formed by the RIE (Reactive Ion Etching) method. By forming the plurality of trenches t, the mesa portions 20 that are part of the drift layer 12 are formed between adjacent trenches t at the same time.

[0048] After forming the trenches t and the mesa portions 20, as Figure 3B shown, an insulating film 71 is formed to cover the inner walls of the trenches t and the mesa portions 20. The insulating film 71 is, for example, a silicon oxide film formed by the thermal oxidation method. The width of the mesa portion 20 becomes smaller than before the thermal oxidation due to the thermal oxidation reaction. Alternatively, the insulating film 71 may also be formed by the CVD (Chemical Vapor Deposition) method.

[0049] A gap remains inside the insulating film 71 in the trenches t. The field plate electrode 40 shown in Figure 4A is buried in this gap. For example, after the material of the field plate electrode 40 is deposited on the insulating film 71 by the CVD method, its upper surface is recessed to the position shown in Figure 4A .

[0050] The upper surface of the insulating film 71 covering the mesa portion 20 is planarized, and as Figure 4B shown, the upper surface of the mesa portion 20 is exposed from the insulating film 71.

[0051] As Figure 5AAs shown, an insulating film 71 of one of two trenches t in an adjacent configuration relationship is covered by a mask 91, and the insulating film 71 of the other trench t is etched. The upper surface of the etched insulating film 71 recedes to Figure 5A the position shown, and a recess ta for burying a gate electrode is formed above the other trench t.

[0052] One side wall of the upper part of the mesa portion 20 is exposed in the recess ta. In addition, the upper part of the field plate electrode 40 is also exposed in the recess ta.

[0053] The exposed portion of the mesa portion 20 is thermally oxidized, for example, and as Figure 5B shown, a gate insulating film (silicon oxide film) 72 is formed on one side wall of the mesa portion 20 exposed in the recess ta. At this time, a thermal oxidation reaction also occurs from the insulating film (silicon oxide film) 71 in the trench t adjacent to the other side wall of the mesa portion 20. Due to the thermal oxidation reaction from this insulating film 71, the side wall on the opposite side of the side wall of the upper part of the mesa portion 20 where the gate insulating film 72 is formed is slightly inclined so as to bend or curve toward the recess ta side.

[0054] The exposed upper part of the field plate electrode 40 is also thermally oxidized, and an insulating film (silicon oxide film) 73 is formed between the recess ta and the field plate electrode 40.

[0055] As Figure 6A shown, a gate electrode 30 is buried in the recess ta. The gate electrode 30 faces the side wall of the mesa portion 20 with the gate insulating film 72 interposed therebetween.

[0056] After forming the gate electrode 30, p-type impurities and n-type impurities are sequentially implanted into the mesa portion 20 by, for example, the ion implantation method. Further, as Figure 6B shown, through the thermal diffusion treatment after implantation, a p-type base region 13 is formed in the portion of the mesa portion 20 facing the gate electrode 30, and an n-type source region 14 is formed on the base region 13.

[0057] After forming the base region 13 and the source region 14, as Figure 7A shown, an insulating film 74 covering the mesa portion 20 and the gate electrode 30 is formed.

[0058] As Figure 7B shown, a mask 92 is formed on the upper surface of the insulating film 74. On the mask 92, an opening 92a is formed by photolithography. The opening 92a is located between the mesa portion 20 and the field plate electrode 40 above the trench t in which the gate electrode 30 is not buried.

[0059] Then, using this mask 92, the insulating film 74 is etched by, for example, the RIE method. Thus, as Figure 8AAs shown, a contact trench 74a is formed in the insulating film 74. The contact trench 74a reaches the second sidewall opposite to the first sidewall facing the gate electrode 30 at the upper part of the mesa portion 20.

[0060] The side surfaces of the source region 14 and the base region 13 are exposed in the contact trench 74a. For example, p-type impurities are implanted into the exposed side surface of the base region 13 by ion implantation, and after subsequent thermal diffusion treatment, as Figure 8B shown, a p-type base contact region 15 having a p-type impurity concentration higher than the p-type impurity concentration of the base region 13 is formed on the side surface of the base region 13 exposed in the contact trench 74a.

[0061] After forming the base contact region 15, as Figure 1 shown, the contact portion 62 of the upper electrode 60 is buried in the contact trench 74a. The contact portion 62 is in contact with the source region 14 and the base contact region 15 which are a part of the second sidewall 22 opposite to the first sidewall 21 facing the gate electrode 30 in the formation of the mesa portion 20.

[0062] That is, the upper part of the first sidewall 21 of the mesa portion 20 faces the gate electrode 30 disposed in the buried electrode portion T adjacent to the first sidewall 21, and the contact portion 62 is disposed in the buried electrode portion T adjacent to the second sidewall 22 opposite to the first sidewall 21, and the contact portion 62 is in contact with the second sidewall 22.

[0063] According to the embodiment described above, when forming the contact trench 74a for connecting the upper electrode 60 to the source region 14 and the base contact region 15, no recess formed by etching is formed on the mesa portion 20. In this embodiment, as Figure 8A shown, the insulating film 74 covering the mesa portion 20 is etched to form the contact trench 74a reaching the sidewall at the upper part of the mesa portion 20.

[0064] The insulating film 74 and the mesa portion 20 are made of materials of different types. For example, the insulating film 74 is a silicon oxide film, and the mesa portion 20 is a silicon portion. Therefore, when etching the insulating film 74, the mesa portion 20 functions as an etching stopper, and the contact trench 74a is formed self-aligned with respect to the sidewall of the mesa portion 20. Therefore, it is possible to suppress the deviation of the position of the base contact region 15 formed by injecting p-type impurities into the side surface of the base region 13 exposed in the contact trench 74a with respect to the gate electrode 30. Thereby, the distance between the channel formed on the first sidewall 21 of the mesa portion 20 and the base contact region 15 formed on the second sidewall 22 opposite to the first sidewall 21 can be made constant, and the deviation of the threshold voltage and the on-resistance can be suppressed.

[0065] In addition, the side surface of the base region 13 of the mesa portion 20 that the contact groove 74a reaches (where the contact portion 62 makes contact) is inclined with respect to the side surface of the drift region 12a below the base region 13 during the thermal oxidation shown above. Figure 5B Therefore, in the contact groove 74a, the side surface of the base region 13 that is inclined or bent with respect to the direction of ion implantation (the vertical direction along the depth direction of the groove t) can be exposed, making it easier to form the base contact region 15 based on ion implantation through the contact groove 74a.

[0066] Since there is no need to form a recess for forming the contact portion in the mesa portion 20, it is possible to miniaturize the width of the mesa portion 20. The tensile stress caused by the insulating film 71 can be applied to the miniaturized mesa portion 20, and the carrier mobility in the drift region 12a can be increased to reduce the on-resistance.

[0067] In the present embodiment where a channel is formed only on one side wall of the mesa portion 20, compared with the configuration where channels are formed on both side walls of the mesa portion 20, the channel density is reduced. However, by miniaturizing the width of the mesa portion 20 and reducing the pitch, the reduction in channel density can be compensated for. The structure of the present embodiment is particularly effective in elements with high breakdown voltage (above several hundred volts) where the proportion of channel resistance is small.

[0068] [Second Embodiment]

[0069] Figure 9 FIG. is a schematic cross-sectional view of the semiconductor device 2 according to the second embodiment.

[0070] Figure 10 It is Figure 9 The cross-sectional view taken along line B - B' in

[0071] The second embodiment differs from the first embodiment in the following aspects.

[0072] Among the two mesa portions 20 (the first mesa portion 20a and the second mesa portion 20b) adjacent to the buried electrode portion T provided with the contact portion 62 (for example, the second buried electrode portion T2 in Figure 9 ), the contact portion 62 in contact with the second side wall 22 of the first mesa portion 20a and the contact portion 62 in contact with the second side wall 22 of the second mesa portion 20b are connected to each other through the second buried electrode portion T2.

[0073] Moreover, the field plate electrode 40 provided in the second buried electrode portion T2 is in contact with the contact portion 62 connected to each other through the second buried electrode portion T2.

[0074] Next, with reference to Figure 11A and Figure 11B , the manufacturing method of the semiconductor device 2 according to the second embodiment will be described.

[0075] Figures 3A to 7A The process is carried out in the same manner as in the first embodiment. Thereafter, in the second embodiment, as Figure 11A shown, the width of the opening 92a of the mask 92 formed on the insulating film 74 is made wider than that in the first embodiment. The opening 92a is located above the trench t where the gate electrode 30 is not disposed, and the upper surface of the insulating film 74 on the trench t is exposed in the opening 92a.

[0076] In this state, the insulating film 74 is etched to form a contact trench 74a that exposes the upper portions of the side walls of the two step portions 20 and the upper portion of the field plate electrode 40 disposed between the two step portions 20 below the opening 92a.

[0077] Thereafter, in the same manner as in the first embodiment, by ion implantation through the contact trench 74a, as Figure 11B shown, a base contact region 15 is formed on the side surface of the base region 13 exposed in the contact trench 74a. Further, a trench contact portion 62 is formed in the contact trench 74a thereafter.

[0078] According to the second embodiment, compared with the first embodiment, the width of the opening 92a of the mask 92 for forming the contact trench 74a can be enlarged, so that lithography becomes easy.

[0079] [Third Embodiment]

[0080] Figure 12 is a schematic cross-sectional view of the semiconductor device 3 of the third embodiment.

[0081] Figure 13 is Figure 12 the cross-sectional view taken along C - C' in

[0082] In the third embodiment, both the gate electrode 30 and the contact portion 62 are provided in one buried electrode portion T. In the Figure 12 example shown, the contact portion 62 disposed in the second buried electrode portion T2 is in contact with the source region 14 and the base contact region 15 at the upper portion of the second side wall 22 of the first step portion 20a. The gate electrode 30 disposed in the second buried electrode portion T2 is opposed to the base region 13 that forms a part of the first side wall 21 of the second step portion 20b with the gate insulating film 72 interposed therebetween. The contact portion 62 disposed in the third buried electrode portion T3 is in contact with the source region 14 and the base contact region 15 at the upper portion of the second side wall 22 of the second step portion 20b. The gate electrode 30 disposed in the third buried electrode portion T3 is opposed to the base region 13 that forms a part of the first side wall 21 of the third step portion 20c with the gate insulating film 72 interposed therebetween.

[0083] In an embedded electrode portion T, a field plate electrode 40 is located between a gate electrode 30 and a contact portion 62.

[0084] The embedded electrode portion T and the mesa portion 20 in which the gate electrode 30, the contact portion 62, and the field plate electrode 40 are arranged are alternately and repeatedly arranged in the X direction.

[0085] Next, with reference to Figures 14A to 17B , a method of manufacturing the semiconductor device 3 of the third embodiment will be described.

[0086] Figures 3A to 4B The processes of Figure 14A are performed in the same manner as in the first embodiment. Thereafter, in the third embodiment, as Figure 14A shown, the upper surface of one of the insulating films 71 disposed on both sides of the field plate electrode 40 embedded in each trench t is covered with a mask 91, and the other insulating film 71 exposed from the mask 91 is etched. The upper surface of the etched insulating film 71 recedes to the position shown in

[0087] , and a recess ta for embedding the gate electrode is formed in the insulating film 71.

[0088] One side wall of the upper portion of the mesa portion 20 and one side wall of the upper portion of the field plate electrode 40 are exposed in the recess ta. Figure 14B The exposed portion of the mesa portion 20 is thermally oxidized, for example, and as

[0089] shown, a gate insulating film (silicon oxide film) 72 is formed on one side wall of the mesa portion 20 exposed in the recess ta. At this time, a thermal oxidation reaction also occurs in the insulating film (silicon oxide film) 71 in the trench t adjacent to the other side wall provided on the mesa portion 20. Due to the thermal oxidation reaction from this insulating film 71, the side wall on the opposite side of the side wall of the mesa portion 20 where the gate insulating film 72 is formed in the upper portion is slightly inclined so as to bend or curve toward the recess ta side.

[0090] As Figure 15A shown, the gate electrode 30 is embedded in the recess ta. The gate electrode 30 faces the side wall of the mesa portion 20 with the gate insulating film 72 interposed therebetween.

[0091] After forming the gate electrode 30, p-type impurities and n-type impurities are sequentially implanted into the mesa portion 20, for example, by ion implantation. Further, as Figure 15B shown, by the thermal diffusion treatment after implantation, a p-type base region 13 is formed in the portion of the mesa portion 20 facing the gate electrode 30, and an n-type source region 14 is formed on the base region 13.

[0092] After forming the base region 13 and the source region 14, as Figure 16A shown, an insulating film 74 covering the mesa portion 20 and the gate electrode 30 is formed.

[0093] As Figure 16B shown, a mask 92 is formed on the upper surface of the insulating film 74. On the mask 92, an opening 92a is formed by photolithography. The opening 92a is located between the mesa portion 20 and the field plate electrode 40 above the portion where the gate electrode 30 is not buried.

[0094] Then, using this mask 92, the insulating film 74 is etched, for example, by the RIE method. Thus, as Figure 17A shown, a contact trench 74a is formed in the insulating film 74. The contact trench 74a reaches the second side wall opposite to the first side wall opposed to the gate electrode 30 at the upper part of the mesa portion 20.

[0095] In the contact trench 74a, the side surfaces of the source region 14 and the base region 13 are exposed. On the exposed side surface of the base region 13, a p-type impurity is implanted, for example, by ion implantation, and through a subsequent thermal diffusion treatment, as Figure 17B shown, a p-type base contact region 15 having a p-type impurity concentration higher than the p-type impurity concentration of the base region 13 is formed on the side surface of the base region 13 exposed in the contact trench 74a.

[0096] After forming the base contact region 15, as Figure 12 shown, the contact portion 62 of the upper electrode 60 is buried in the contact trench 74a. The contact portion 62 is in contact with a part of the source region 14 and the base contact region 15 on the second side wall opposite to the first side wall 21 opposed to the gate electrode 30 in the formation of the mesa portion 20.

[0097] In the third embodiment, the insulating film 74 covering the mesa portion 20 is also etched to form a contact trench 74a reaching the side wall at the upper part of the mesa portion 20. When etching the insulating film 74, the mesa portion 20 functions as an etching stopper, and the contact trench 74a is formed self-aligned with respect to the side wall of the mesa portion 20. Therefore, it is possible to suppress the deviation of the position of the base contact region 15 formed by implanting a p-type impurity into the side surface of the base region 13 exposed in the contact trench 74a with respect to the gate electrode 30. As a result, it is possible to make the distance between the channel formed on the first side wall 21 of the mesa portion 20 and the base contact region 15 formed on the second side wall opposite to the first side wall 21 constant, and to suppress the deviation of the threshold voltage and the on-resistance.

[0098] In the third embodiment, the buried electrode portions T and the table portions 20 having the same structure are alternately arranged in the X direction that intersects (for example, is orthogonal to) the Y direction in which the buried electrode portions T and the table portions 20 extend, so that the layout is easy.

[0099] [Fourth Embodiment]

[0100] Figure 18 FIG. is a schematic cross-sectional view of the semiconductor device 4 according to the fourth embodiment.

[0101] Figure 19 is Figure 18 the cross-sectional view taken along D-D' in

[0102] In the fourth embodiment, the plurality of buried electrode portions T are formed in a columnar shape rather than a stripe shape in the drift layer 12. In Figure 19 , for example, a hexagonal prism-shaped buried electrode portion T is shown, but the buried electrode portion T may also be a prism other than a cylinder or a hexagonal prism.

[0103] The plurality of buried electrode portions T include a buried electrode portion T5 that includes the field plate electrode 40 and the gate electrode 30 and does not include the contact portion 62, and a buried electrode portion T6 that includes the field plate electrode 40 and the contact portion 62 and does not include the gate electrode 30.

[0104] The field plate electrode 40 is located on the central axis of each of the buried electrode portions T5 and T6. The gate electrode 30 surrounds the periphery of the upper portion of the field plate electrode 40 of the buried electrode portion T5 with an insulating film 73 interposed therebetween. The contact portion 62 surrounds the periphery of the upper portion of the field plate electrode 40 of the buried electrode portion T6. The upper portion of the field plate electrode 40 of the buried electrode portion T6 is in contact with the contact portion 62. The field plate electrode 40 of the buried electrode portion T5 penetrates the insulating film 74 between the buried electrode portion T5 and the upper electrode 60 and is connected to the main portion 61 of the upper electrode 60.

[0105] In the fourth embodiment, similar to the above-described embodiments, the insulating film 74 covering the table portion 20 can be etched to form a contact trench that reaches the upper sidewall of the table portion 20. Therefore, it is possible to suppress the deviation in the position of the base contact region 15 formed by injecting p-type impurities into the side surface of the base region 13 exposed in the contact trench with respect to the gate electrode 30. As a result, the distance between the channel formed in the first sidewall 21 of the table portion 20 and the base contact region 15 formed in the second sidewall 22 on the opposite side of the first sidewall 21 can be made constant, and the deviation of the threshold voltage and the on-resistance can be suppressed.

[0106] Several embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention and are included in the invention described in the claims and its equivalents.

Claims

1. A semiconductor device, wherein, Comprising: A semiconductor structure portion having a plurality of buried electrode portions and a mesa portion disposed between the plurality of buried electrode portions and adjacent to the buried electrode portions, the mesa portion having: a first semiconductor region of a first conductivity type; A second semiconductor region of a second conductivity type disposed on the first semiconductor region; a third semiconductor region of a first conductivity type disposed on the second semiconductor region; And a fourth semiconductor region of a second conductivity type disposed between the buried electrode portion and the second semiconductor region, the second conductivity type impurity concentration being higher than the second conductivity type impurity concentration of the second semiconductor region; A gate electrode disposed within the buried electrode portion and opposed to a side surface of the second semiconductor region that forms a part of a first side wall of the mesa portion; A gate insulating film disposed between the gate electrode and the side surface of the second semiconductor region; And An upper electrode having a main portion and a contact portion, the main portion being disposed on the semiconductor structure portion, the contact portion extending from the main portion into the buried electrode portion to reach a second side wall opposite to the first side wall of the mesa portion and being in contact with the third semiconductor region and the fourth semiconductor region; The upper portion of the second side wall is inclined or bent toward the first side wall, The side surface of the fourth semiconductor region contacted by the contact portion is continuously inclined or bent along the contact portion.

2. The semiconductor device according to claim 1, wherein The semiconductor device is provided with 4 or more of the buried electrode portions and 3 or more of the mesa portions, the 4 or more of the buried electrode portions including a first buried electrode portion, a second buried electrode portion, a third buried electrode portion, and a fourth buried electrode portion, the 3 or more of the mesa portions including a first mesa portion, a second mesa portion, and a third mesa portion, The first mesa portion is disposed between the first buried electrode portion and the second buried electrode portion and is adjacent to the first buried electrode portion and the second buried electrode portion, The second mesa portion is disposed between the second buried electrode portion and the third buried electrode portion and is adjacent to the second buried electrode portion and the third buried electrode portion, The third mesa portion is disposed between the third buried electrode portion and the fourth buried electrode portion and is adjacent to the third buried electrode portion and the fourth buried electrode portion, A gate electrode opposed to the first side wall of the first mesa portion is provided in the first buried electrode portion, A contact portion in contact with the second side wall of the first mesa portion and a contact portion in contact with the second side wall of the second mesa portion are provided in the second buried electrode portion, A gate electrode opposed to the first side wall of the second mesa portion and a gate electrode opposed to the first side wall of the third mesa portion are provided in the third buried electrode portion, A contact portion in contact with the second side wall of the third mesa portion is provided in the fourth buried electrode portion.

3. The semiconductor device according to claim 2, wherein The second buried electrode portion and the fourth buried electrode portion do not include the gate electrode.

4. The semiconductor device according to claim 2, wherein The contact portion in contact with the second side wall of the first mesa portion and the contact portion in contact with the second side wall of the second mesa portion are connected to each other through the second buried electrode portion.

5. The semiconductor device according to claim 4, wherein the semiconductor device further includes a field plate electrode provided in the second buried electrode portion and in contact with the contact portion.

6. The semiconductor device according to claim 5, wherein the second buried electrode portion does not include the gate electrode.

7. The semiconductor device according to claim 1, wherein both the gate electrode and the contact portion are provided in one of the buried electrode portions.

8. The semiconductor device according to claim 7, wherein the buried electrode portion further has a field plate electrode located between the gate electrode and the contact portion.

9. The semiconductor device according to claim 1, wherein the buried electrode portion and the mesa portion extend in a striped shape.

10. The semiconductor device according to claim 1, wherein the plurality of buried electrode portions are formed in a columnar shape.

11. The semiconductor device according to claim 10, wherein the plurality of buried electrode portions include: a fifth buried electrode portion including the gate electrode and not including the contact portion; and a sixth buried electrode portion including the contact portion and not including the gate electrode.

12. The semiconductor device according to claim 11, wherein the fifth buried electrode portion further includes a field plate electrode, and the gate electrode surrounds a part of the field plate electrode.

13. The semiconductor device according to claim 11, wherein the sixth buried electrode portion further includes a field plate electrode, the contact portion surrounds a part of the field plate electrode, and the field plate electrode is in contact with the contact portion.

14. A method of manufacturing a semiconductor device, wherein, Comprising: a step of forming a plurality of trenches in a semiconductor layer and forming a mesa portion of the semiconductor layer between the plurality of trenches; a step of forming a first insulating film so as to cover inner walls of the plurality of trenches and the mesa portion; a step of burying a field plate electrode in a gap remaining between the first insulating films in the trenches; a step of etching an upper portion of the first insulating film in one of two adjacent trenches so as to form a recess in such a manner that an upper portion of a first side wall of the mesa portion and an upper portion of the field plate electrode are exposed; a step of thermally oxidizing the first side wall of the mesa portion exposed in the recess to form a gate insulating film on the first side wall and inclining or bending a second side wall opposite to the first side wall of the mesa portion where the gate insulating film is formed toward the recess side; a step of forming a gate electrode in the recess so as to face the first side wall of the mesa portion where the gate insulating film is formed; a step of further forming a second insulating film covering the mesa portion and the gate electrode; a step of etching the first insulating film and the second insulating film to form a contact trench reaching the inclined or bent second side wall of the mesa portion; A step of forming a contact region on a side surface of the inclined or curved second sidewall of the mesa portion exposed in the contact trench; and A step of forming an electrode in the contact trench that is in contact with the contact region.

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