Virtual memory management method and device supporting physical address greater than virtual address

Abstract

The present invention discloses a virtual memory management method and device that supports physical addresses larger than virtual addresses. The method includes: determining the target virtual address corresponding to the instruction fetch address or memory access address in any of the user mode, supervisor mode or machine mode; determining the target physical address corresponding to the target virtual address by accessing the virtual memory management unit, the virtual memory management unit having a built-in page table entry for mapping the virtual address to the physical address, and the target virtual address bit width may be less than or equal to the target physical address bit width, especially in the field of multi-core applications; finally returning the target physical address to the corresponding instruction fetch unit or memory access unit, and ensuring correctness and validity. By adopting the embodiment of the present invention, the address translation from virtual address to physical address can be completed when the virtual address bit width is less than the physical address bit width, and the multi-core architecture can be ensured to work effectively in multiple modes such as user mode, supervisor mode and machine mode. The applicability of the present invention is high.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a virtual memory management method and device that supports physical addresses being larger than virtual addresses. Background Art

[0002] Any computer system with a certain degree of complexity relies on the collaborative work of multiple processes running on the processor. Since each instruction has its own virtual address, it is necessary to complete the conversion from virtual address to physical address.

[0003] Although in most processor architectures, the virtual address bit width is generally not smaller than the physical address bit width, in some cases there may be a problem that the virtual address bit width is smaller than the physical address bit width. For example, in the Sv39 mode (a 39-bit paged memory management architecture provided for RISC-V 64-bit systems) and Sv48 mode (a 48-bit paged memory management architecture provided for RISC-V 64-bit systems) in the RISC-V architecture, the virtual address bit width is smaller than the physical address bit width, which can easily lead to system errors or even crashes during the address translation process.

[0004] Therefore, how to complete address translation when the virtual address bit width is smaller than the physical address bit width becomes an urgent problem to be solved. Summary of the Invention

[0005] The present invention provides a virtual memory management method and device that supports RISC-V and many-core architectures. The method and device can complete address translation from virtual addresses to physical addresses when the virtual address bit width is smaller than the physical address bit width, and can ensure that the many-core architecture works effectively in multiple modes such as user mode, supervisor mode, and machine mode. The present invention has high applicability.

[0006] In a first aspect, an embodiment of the present invention provides a virtual memory management method, the method comprising:

[0007] Determine a target virtual address corresponding to an instruction fetch address or a memory access address in any mode of user mode, supervisor mode, or machine mode;

[0008] Determining a target physical address corresponding to the target virtual address by accessing a virtual memory management unit, wherein the virtual memory management unit stores a page table entry that maps the virtual address to the physical address, and the bit width of the target virtual address is less than or equal to the bit width of the target physical address;

[0009] Returns the physical address of the target.

[0010] In a second aspect, an embodiment of the present invention provides a virtual memory management device, the device comprising:

[0011] An instruction fetch or memory access module, configured to determine a target virtual address corresponding to an instruction fetch address or memory access address in any of user mode, supervisor mode, or machine mode;

[0012] a virtual address determination module, configured to determine a target physical address corresponding to the target virtual address by accessing a virtual memory management unit, the virtual memory management unit storing a page table entry that maps the virtual address to the physical address, the target virtual address bit width being less than or equal to the target physical address bit width;

[0013] The address returning module is used to return the above-mentioned target physical address.

[0014] In a third aspect, an embodiment of the present invention provides an electronic device, including a processor and a memory, wherein the processor and the memory are connected to each other;

[0015] The memory is used to store computer programs;

[0016] The processor is configured to execute the virtual memory management method provided by the embodiment of the present invention when calling the computer program.

[0017] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the virtual memory management method provided by an embodiment of the present invention.

[0018] Based on the virtual memory management method provided in the embodiment of the present invention, the address translation from virtual address to physical address can be completed when the virtual address bit width is smaller than the physical address bit width, and the many-core architecture can be ensured to work effectively in multiple modes such as user mode, supervisor mode and machine mode, thereby reducing the risk of system errors and improving system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 1 is a flow chart of a virtual memory management method supporting RISC-V and many-core architectures provided by an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of a scenario for determining a target physical address provided by an embodiment of the present invention;

[0022] Figure 3Schematic diagram of a scenario of backfilling a page table directory provided by an embodiment of the present invention;

[0023] Figure 4 is a schematic diagram of another scenario of determining a target physical address provided by an embodiment of the present invention;

[0024] Figure 5 Schematic diagram of a virtual memory management method and apparatus supporting RISC-V and many-core architectures provided by an embodiment of the present invention;

[0025] Figure 6 It is a structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0027] The virtual memory management method supporting RISC-V and many-core architecture provided in the embodiment of the present invention can be applied to a variety of central processing units (CPUs), such as A510 CPU and S710 CPU, and can determine the physical address corresponding to the virtual address in RISC-V Sv39 mode or Sv48 mode.

[0028] See also Figure 1 , Figure 1 This is a flowchart of a virtual memory management method supporting RISC-V and many-core architecture provided by an embodiment of the present invention.

[0029] like Figure 1 As shown, the virtual memory management method supporting RISC-V and many-core architecture provided by the embodiment of the present invention may include the following steps:

[0030] Step S11: Determine a target virtual address corresponding to an instruction fetch address or a memory access address in any one of user mode, supervisor mode or machine mode.

[0031] Specifically, the instruction fetch address is the instruction fetch address corresponding to the fetch instruction sent by the instruction fetch unit (IFU), and the access address is the address corresponding to the memory access instruction sent by the load storage unit (LSU). Determine the target virtual address corresponding to the instruction.

[0032] The instruction fetch instruction may be an instruction fetched on demand by the instruction fetch unit from an internal random access memory (IRAM).

[0033] The memory access instruction may be an instruction sent by the memory access unit to load or store data in the data storage system, such as a memory access instruction to load or store data in the DCache storage system.

[0034] Furthermore, an instruction fetch address or memory access address in any one of user mode, supervisor mode or machine mode may be obtained, and a target virtual address corresponding to the obtained instruction fetch address or memory access address may be determined.

[0035] Step S12: Determine the target physical address corresponding to the target virtual address by accessing the virtual memory management unit.

[0036] In some feasible implementations, the virtual memory management unit stores a page table directory that maps virtual addresses to physical addresses. Therefore, after determining the target virtual address, the target physical address corresponding to the target virtual address can be determined based on the page table directory that maps virtual addresses to physical addresses stored in the virtual memory management unit.

[0037] Wherein, any page table directory is used to indicate a mapping relationship between an address identifier of a virtual address and a virtual page number (VPN) of a corresponding physical address.

[0038] Based on this, when determining the target physical address corresponding to the target virtual address, the virtual page number that matches the address identifier corresponding to the target virtual address in each page table directory can be determined, and then the target physical address corresponding to the target virtual address can be determined based on the virtual page number. That is, the virtual pages in each page table target of the virtual address are compared, and if the corresponding virtual page number is matched, the target physical address corresponding to the target virtual address is determined based on the matched virtual page number.

[0039] In some feasible implementations, the virtual memory management unit includes at least one first translation lookaside buffer (TLB) and at least one second translation lookaside buffer. The first translation lookaside buffer may be a micro-TLB, and the second translation lookaside buffer may be a joint-TLB.

[0040] The first translation lookaside buffer stores page table entries that map virtual addresses to physical addresses within a preset time interval from the current time. That is, the first translation lookaside buffer stores page table entries used to determine the physical addresses corresponding to virtual addresses within a certain period of time. The second translation lookaside buffer stores all page table entries that map virtual addresses to physical addresses, and the first and second translation lookaside buffers store page table entries by physical page.

[0041] Specifically, in user mode or supervisor mode, that is, when the target virtual address is a virtual address determined in user mode or supervisor mode, when determining the target physical address corresponding to the target virtual address by accessing the virtual memory management unit, the fully connected first translation lookaside buffer can be accessed in sequence based on the multi-level index to determine the target physical address corresponding to the target virtual address based on the page table entry of the first translation lookaside buffer.

[0042] If the target physical address corresponding to the target virtual address is not determined based on the page table entries of the first translation lookaside buffer, the multi-way group-connected second translation lookaside buffers are accessed sequentially based on the multi-level index to determine the target physical address corresponding to the target virtual address based on the page table entries of the second translation lookaside buffer.

[0043] If the target physical address corresponding to the target virtual address is not determined based on the page table entry of the second translation lookaside buffer, the target physical address corresponding to the target virtual address is determined based on a page-table walk mechanism.

[0044] Among them, if the target physical address corresponding to the target virtual address is determined based on the page table entry of the second translation lookaside buffer, or the target physical address corresponding to the target virtual address is determined based on the page table traversal mechanism, the target page table entry corresponding to the target physical address is backfilled into the first translation lookaside buffer.

[0045] See also Figure 2 , Figure 2 This is a schematic diagram of a scenario for determining a target physical address provided by an embodiment of the present invention. Figure 2 A virtual memory management unit is provided, comprising a plurality of first translation lookaside buffers (Micro TLBs) and a second translation lookaside buffer (Joint-TLB).

[0046] After obtaining the instruction fetch address corresponding to the instruction sent by the instruction fetch unit and determining the virtual address of the fetch address (hereinafter referred to as the first virtual address for the convenience of description), the first translation lookaside buffer of the virtual memory management unit can be accessed to determine the physical address corresponding to the first virtual address based on the page table entry of the first translation lookaside buffer. If the physical address corresponding to the first virtual address is hit, the determined physical address is returned to the instruction fetch unit.

[0047] If the physical address corresponding to the first virtual address is not hit based on the page table entry in the first translation lookaside buffer, the second translation lookaside buffer is accessed to determine the physical address corresponding to the first virtual address based on the page table entry in the second translation lookaside buffer. If the physical address corresponding to the first virtual address is hit, the page table entry corresponding to the determined physical address is backfilled into the first translation lookaside buffer, and the physical address is returned to the instruction fetch unit via the first translation lookaside buffer.

[0048] If the physical address corresponding to the first virtual address is not determined based on the virtual memory management unit, a page table traversal mechanism is executed based on the execution unit to determine the physical address corresponding to the first virtual address.

[0049] Similarly, after obtaining the memory access address corresponding to the instruction sent by the memory access unit and determining the virtual address corresponding to the memory access address (hereinafter referred to as the second virtual address for the convenience of description), the second translation lookaside buffer of the virtual memory management unit can be accessed to determine the physical address corresponding to the second virtual address based on the page table entry of the second translation lookaside buffer. If the physical address corresponding to the second virtual address is hit, the determined physical address is returned to the instruction fetch unit.

[0050] If the physical address corresponding to the second virtual address is not hit based on the page table entry in the second translation lookaside buffer, the second translation lookaside buffer is accessed to determine the physical address corresponding to the second virtual address based on the page table entry in the second translation lookaside buffer. If the physical address corresponding to the second virtual address is hit, the page table entry corresponding to the determined physical address is backfilled into the second translation lookaside buffer, and the physical address is returned to the instruction fetch unit via the second translation lookaside buffer.

[0051] If the physical address corresponding to the second virtual address is not determined based on the virtual memory management unit, a page table traversal mechanism is executed based on the execution unit to determine the physical address corresponding to the second virtual address.

[0052] in, Figure 2 The virtual memory management unit provided also includes a physical memory protection unit (PMP) that specifies read, write, and code execution permissions for physical memory space, which is used to implement memory access control with low overhead.

[0053] in, Figure 2 The provided virtual memory management unit also includes a virtual memory management unit register connected to an external system assist processor for participating in the address translation process.

[0054] In some feasible implementations, the multi-level index may include a 4KiB index, a 2MiB index, and a 1GiB index, wherein the 4KiB index includes the address identifiers corresponding to bits 20 to 12 of the target virtual address, the 2MiB index includes the address identifiers corresponding to bits 29 to 21 of the target virtual address, and the 1GiB index includes the address identifiers corresponding to bits 38 to 30 of the target virtual address.

[0055] Among them, any page table entry of the first translation lookaside buffer and the second translation lookaside buffer is used to represent the mapping relationship between the address identifier of a virtual address and the virtual page number of the corresponding physical address, that is, each page table entry includes a combination of the address identifier of a virtual address and the virtual page number of the physical address, thereby establishing a mapping relationship between the virtual address and the physical address.

[0056] Specifically, the first translation lookaside buffer can be accessed based on the 4KiB index, and the address identifier corresponding to the 4KiB index is matched with each page table entry of the first translation lookaside buffer. If a page table entry including the address identifier corresponding to the 4KiB index exists among the page table entries of the first translation lookaside buffer, it can be determined that each page table entry of the first translation lookaside buffer includes a first virtual page number that matches the address identifier corresponding to the 4KiB index, and then the target physical address corresponding to the target virtual address is determined based on the first virtual page number. Otherwise, it can be determined that the target physical address corresponding to the target virtual address cannot be determined based on the 4KiB index.

[0057] In the case where the target physical address corresponding to the target virtual address cannot be determined based on the 4KiB index, that is, the page table entry of the first translation lookaside buffer does not include the above-mentioned first virtual page number, then the first translation lookaside buffer can be accessed based on the 2MiB index, and the address identifier corresponding to the 2MiB index is matched with each page table entry of the first translation lookaside buffer. If there is a page table entry including the address identifier corresponding to the 2MiB index among the page table entries of the first translation lookaside buffer, it can be determined that each page table entry of the first translation lookaside buffer includes a second virtual page number that matches the address identifier corresponding to the 2MiB index, and then the target physical address corresponding to the target virtual address is determined based on the second virtual page number. Otherwise, it can be determined that the target physical address corresponding to the target virtual address cannot be determined based on the 2MiB index.

[0058] In the case where the target physical address corresponding to the target virtual address cannot be determined based on the 2MiB index, that is, the page table entry of the first translation lookaside buffer does not include the above-mentioned second virtual page number, the first translation lookaside buffer can be accessed based on the 1GiB index, and the address identifier corresponding to the 1GiB index can be matched with each page table entry of the first translation lookaside buffer. If a page table entry including the address identifier corresponding to the 1GiB index exists among the page table entries of the first translation lookaside buffer, it can be determined that each page table entry of the first translation lookaside buffer includes a third virtual page number that matches the address identifier corresponding to the 1GiB index, and the target physical address corresponding to the target virtual address can be determined based on the third virtual page number. Otherwise, it can be determined that the target physical address corresponding to the target virtual address cannot be determined based on the 1GiB index.

[0059] In the case that the target physical address cannot be determined by accessing the first translation lookaside buffer based on the multi-level index, the second translation lookaside buffer may be further accessed based on the multi-level index.

[0060] That is, the second translation lookaside buffer is accessed based on the 4KiB index, and the address identifier corresponding to the 4KiB index is matched with each page table entry of the second translation lookaside buffer. If a page table entry including the address identifier corresponding to the 4KiB index exists among the page table entries of the second translation lookaside buffer, it can be determined that each page table entry of the second translation lookaside buffer includes a fourth virtual page number that matches the address identifier corresponding to the 4KiB index, and then the target physical address corresponding to the target virtual address is determined based on the fourth virtual page number. Otherwise, it can be determined that the target physical address corresponding to the target virtual address cannot be determined based on the 4KiB index.

[0061] In the case where the target physical address corresponding to the target virtual address cannot be determined based on the 4KiB index, that is, the page table entry of the second translation lookaside buffer does not include the above-mentioned fourth virtual page number, then the second translation lookaside buffer can be accessed based on the 2MiB index, and the address identifier corresponding to the 2MiB index is matched with each page table entry of the second translation lookaside buffer. If there is a page table entry including the address identifier corresponding to the 2MiB index among the page table entries of the second translation lookaside buffer, it can be determined that each page table entry of the second translation lookaside buffer includes a fifth virtual page number that matches the address identifier corresponding to the 2MiB index, and then the target physical address corresponding to the target virtual address is determined based on the fifth virtual page number. Otherwise, it can be determined that the target physical address corresponding to the target virtual address cannot be determined based on the 2MiB index.

[0062] If the target physical address corresponding to the target virtual address cannot be determined based on the 2MiB index, that is, if the page table entry of the second translation lookaside buffer does not include the fifth virtual page number, the second translation lookaside buffer can be accessed based on the 1GiB index, and the address identifier corresponding to the 1GiB index can be matched with each page table entry of the second translation lookaside buffer. If a page table entry including the address identifier corresponding to the 1GiB index exists among the page table entries of the second translation lookaside buffer, it can be determined that each page table entry of the second translation lookaside buffer includes a sixth virtual page number that matches the address identifier corresponding to the 1GiB index, and the target physical address corresponding to the target virtual address can be determined based on the sixth virtual page number. Otherwise, it can be determined that the target physical address corresponding to the target virtual address cannot be determined based on the 1GiB index.

[0063] If the target physical address corresponding to the target virtual address still cannot be determined by accessing the second translation lookaside buffer based on the multi-level index, the target physical address may be determined based on a page table traversal mechanism.

[0064] Based on the above method, a software-hardware cooperation mechanism can be implemented to fill the translation lookaside buffer, thereby improving the flexibility of the page table structure and reducing the hardware cost.

[0065] join Figure 3 , Figure 3 Schematic diagram of a backfill page table directory provided by an embodiment of the present invention. Figure 3 As shown, the multi-level index includes a 4KiB index (Index_4KiB), a 2MiB index (Index_2MiB) and a 1GiB index (Index_1GiB) in sequence. The 4KiB index, the 2MiB index and the 1GiB index respectively include 8-bit address identifiers, specifically the address identifiers corresponding to bits 20 to 12 of the target virtual address, the address identifiers corresponding to bits 29 to 21 and the address identifiers corresponding to bits 38 to 30.

[0066] If the target physical address corresponding to the target virtual address is not determined based on the first translation lookaside buffer (Micro TLB), the page table directory of the second translation lookaside buffer (Joint TLB) can be accessed sequentially based on a multi-level index. Specifically, the valid page table directory corresponding to the 4KiB index in the second translation lookaside buffer is accessed based on a 4KiB index. Assuming that the 4KiB index hits the page table directory with virtual page number (VPN) A, the target physical address corresponding to the target virtual address is determined based on VPN A, and the target page table entry including VPN A is backfilled into the first translation lookaside buffer. When accessing the second translation lookaside buffer based on a 1GiB index, the valid page table directory corresponding to the 1GiB index is accessed. Assuming that the 1GiB index hits the page table directory with virtual page number (VPN) X, the target physical address corresponding to the target virtual address is determined based on VPN X, and the target page table entry including VPN X is backfilled into the first translation lookaside buffer.

[0067] In some feasible embodiments, if the target physical address corresponding to the target virtual address cannot be determined by accessing the first translation lookaside buffer based on the multi-level index, the least recently used physical page for storing the page table entry in the first translation lookaside buffer is replaced. Specifically, the least recently used physical page in the first translation lookaside buffer can be determined based on a least recently used algorithm.

[0068] In some feasible implementations, when accessing a virtual memory management unit to determine a target physical address corresponding to a target virtual address, a parity check may be performed on any page table entry in the virtual memory management unit when the page table entry is read. Each page table entry in the virtual memory management unit requires parity encoding when it is written.

[0069] That is, when reading any hit page table entry, a parity check is performed on the page table entry. If the check result includes error information, the error information is reported and the page table entry is marked as invalid information.

[0070] In this case, it can be considered that a hit page table entry is not determined, and the target physical address corresponding to the target virtual address can be determined based on the page table traversal mechanism.

[0071] At the same time, it is also possible to obtain error information and location information that occurs during the process of determining the target physical address, such as error information generated during the parity check process and the relevant location where the error information is generated, and then perform error repair based on this.

[0072] In some feasible implementations, in machine mode, that is, when the target virtual address is a virtual address determined in machine mode, an additional physical address width of 47 to 39 bits provided by a configuration register may be obtained, and the additional physical address width may be sent to a virtual memory management unit to establish a mapping relationship between the virtual address of bits 0 to 47 and the physical address of bits 0 to 47 based on the additional physical address width. The target physical address corresponding to the target virtual address may then be determined by accessing the virtual memory management unit based on the mapping relationship between the virtual address and the physical address stored in the virtual memory management unit.

[0073] See also Figure 4 , Figure 4 This is another schematic diagram of a scenario for determining a target physical address provided by an embodiment of the present invention. Figure 4 A virtual memory management unit is also provided, including a related module for receiving a virtual address based on a user mode or a supervisor mode, and a related module for determining a physical address based on a machine mode.

[0074] An additional physical address width, exPA[47:39], is provided based on the configuration registers in the System-on-Chip (SoC) management unit. The virtual address corresponding to the instruction sent by the instruction fetch unit has a width of 39 bits (IFU_VA[38:0]). By concatenating this with the additional physical address width, we can obtain a mapping relationship between the instruction fetch unit's instruction virtual address (bits 0 to 47) and the instruction physical address (bits 0 to 47): IFU_PA[47:0] = {exPA[47:39], IFU_VA[38:0]}. For the virtual address corresponding to the instruction sent by the memory access unit regarding DCache data, the additional physical address width also provides a mapping relationship between the instruction virtual address (bits 0 to 47) and the DCache data's physical address (bits 0 to 47): DCache_PA[47:0] = LSU_AG_VA[47:0].

[0075] in, Figure 4 The provided virtual memory management unit also includes a virtual memory management unit register connected to an external system assist processor to participate in the address translation process.

[0076] Step S13: Return the target physical address.

[0077] In some feasible implementations, after determining the target physical address corresponding to the target virtual address, if the target virtual address is the virtual address corresponding to the value address, the target physical address is returned to the instruction fetch unit. If the target virtual address is the virtual address corresponding to the memory access address, the target physical address is returned to the memory access unit.

[0078] In some feasible implementations, in order to meet the memory management requirements of the operating system and improve the consistency of the virtual memory management unit and the cache, translation lookaside buffer maintenance information can also be broadcast via the interconnect bus, so that the CPU cores and other components on the interconnect bus maintain their respective translation lookaside buffers based on the translation lookaside buffer maintenance information.

[0079] The translation lookaside buffer maintenance information may include at least one of a specified address space identifier (ASID), a specified base address of a physical page for storing a page table entry, and a specified virtual address.

[0080] In the present invention, translation lookaside buffer maintenance information can be sent to a virtual memory management unit, so that the virtual memory management unit maintains the translation lookaside buffer based on the translation lookaside buffer maintenance information. Based on the above implementation, hardware can perform this maintenance without software intervention, thereby maintaining page table entries in the translation lookaside buffer and rapidly translating virtual addresses into physical addresses.

[0081] Among them, any translation lookaside buffer in the virtual memory management unit in the embodiment of the present invention can support a 16-bit address space identifier, thereby extending the overflow duration of the address space identifier of the translation lookaside buffer and reducing the number of refreshes of the translation lookaside buffer.

[0082] In some feasible implementations, each page table entry in the virtual memory management unit is stored in a physical page, and corresponding permission verification may be performed when reading data (such as a page table entry) in a physical page or writing data to a physical page.

[0083] Specifically, if the accessed physical page is a shared page, access to the physical page is allowed. If the accessed physical page is a non-shared page, access to the physical page is not allowed, and an abnormal prompt is triggered when accessing the physical page.

[0084] A field (or flag bit) for representing the sharing attribute of the physical page may be obtained, and whether the physical page is a shared page may be determined based on the field (or flag bit).

[0085] Optionally, if the accessed physical page is in a secure state, that is, the physical page belongs to a trusted world, access to the physical page is allowed. If the accessed physical page is in an unsecure state, that is, the physical page belongs to an untrusted world, access to the physical page is not allowed, and an exception prompt is triggered when accessing the physical page.

[0086] A field (or flag bit) representing whether the physical page belongs to a trusted world or a non-trusted world may be obtained, and whether the physical page is in a secure state or a non-secure state may be determined based on the field (or flag bit).

[0087] Optionally, if the accessed physical page is allowed to be rewritten, data is allowed to be written to the physical page. If the accessed physical page is not allowed to be rewritten, an abnormal prompt is triggered when data is written to the physical page, such as triggering a PageFault abnormal prompt.

[0088] A field (or flag bit) for indicating whether the physical page is allowed to be rewritten may be obtained, and whether the physical page is allowed to be rewritten may be determined based on the field (or flag bit).

[0089] Optionally, if the accessed physical page is allowed to be accessed, access to the physical page is allowed. If the accessed physical page is not allowed to be accessed, access to the physical page is not allowed, and an abnormal prompt is triggered when accessing the physical page, such as triggering a Page Fault abnormal prompt.

[0090] A flag bit (or field) indicating whether the physical page is accessible may be obtained, and whether the physical page is allowed to be accessed may be determined based on the flag bit (or field).

[0091] As an example, when the flag bit is 0, it indicates that the physical page is not allowed to be accessed. In this case, the physical page cannot be accessed.

[0092] Optionally, the shared process corresponding to the accessed physical page can be determined, and whether the process accessing the physical page belongs to the shared process corresponding to the physical page can be determined. If it does, access to the physical page is allowed; if it does not, access to the physical page is not allowed, and an exception prompt is triggered when accessing the physical page.

[0093] The global page identification field corresponding to the physical page may be obtained, and based on the field, it is determined that the physical page corresponds to multiple shared processes.

[0094] When determining whether the access process accessing the physical page belongs to the shared process corresponding to the physical page, the determination can be made through the respective process IDs ASID.

[0095] Optionally, the first mode and the second mode corresponding to the accessed physical page can be determined, the first mode being the operating mode corresponding to when the physical page is not allowed to be accessed, and the second mode being the operating mode corresponding to when the physical page is allowed to be accessed, and the second mode being a mode other than the first mode in user mode, supervisor mode or machine mode, or a mode specified in user mode, supervisor mode or machine mode, which is not limited here.

[0096] If the physical page is accessed in the first mode, an abnormal prompt is triggered. If the physical page is accessed in the second mode, access to the physical page is allowed.

[0097] As an example, the first mode is the user mode, and the second mode is other modes. If the physical page is accessed in the user mode, an abnormal prompt is triggered.

[0098] Among them, the access identification bits (or fields) corresponding to each operating mode of the above-mentioned physical page can be obtained, and based on the access identification bits (or fields) corresponding to each operating mode, it is determined whether the above-mentioned physical page is allowed to be accessed in the corresponding operating mode, thereby obtaining the first mode and the second mode corresponding to the above-mentioned physical page.

[0099] Optionally, if a preset flag exists in the memory for the accessed physical page, an exception prompt is triggered when accessing the physical page. If the preset flag does not exist, access to the physical page is allowed.

[0100] The preset identification bit is an identification bit pre-allocated to the physical page in the memory.

[0101] The virtual memory management method supporting RISC-V and many-core architectures provided by the embodiments of the present invention can complete address translation from virtual addresses to physical addresses when the virtual address bit width is smaller than the physical address bit width, and can ensure that the many-core architecture works effectively in multiple modes such as user mode, supervisor mode, and machine mode, thereby reducing the risk of system errors and improving system stability. At the same time, corresponding permission verification can be performed when accessing data in physical pages in the virtual memory management unit (such as page table entries) or writing data to physical pages, further improving system security.

[0102] See also Figure 5 , Figure 5 Schematic diagram of a virtual memory management device supporting RISC-V and many-core architecture provided by an embodiment of the present invention. The device provided by an embodiment of the present invention includes:

[0103] An instruction fetch or memory access module 51 is configured to determine a target virtual address corresponding to an instruction fetch address or a memory access address in any of user mode, supervisor mode, or machine mode;

[0104] a virtual address determination module 52 configured to determine a target physical address corresponding to the target virtual address by accessing a virtual memory management unit, the virtual memory management unit storing a page table entry that maps virtual addresses to physical addresses, wherein a bit width of the target virtual address is less than or equal to a bit width of the target physical address;

[0105] The address returning module 53 is used to return the above-mentioned target physical address.

[0106] In some feasible implementations, the virtual memory management unit includes a first translation lookaside buffer and a second translation lookaside buffer, the first translation lookaside buffer storing page table entries that map virtual addresses within a preset time interval from a current time to physical addresses, and the second translation lookaside buffer storing page table entries that map all virtual addresses to physical addresses;

[0107] In the user mode or the supervisor mode, the virtual address determination module 52 is configured to:

[0108] sequentially accessing the first translation lookaside buffer based on a multi-level index to determine a target physical address corresponding to the target virtual address based on a page table entry of the first translation lookaside buffer;

[0109] If the target physical address is not determined, sequentially accessing the second translation lookaside buffer based on the multi-level index to determine the target physical address based on a page table entry of the second translation lookaside buffer;

[0110] If the target physical address is not determined, the target physical address is determined based on a page table traversal mechanism.

[0111] In some feasible implementations, any of the above-mentioned page table entries is used to represent a mapping relationship between an address identifier of a virtual address and a virtual page number of a corresponding physical address, and the above-mentioned multi-level index includes a 4KiB index, a 2MiB index, and a 1GiB index in sequence, the above-mentioned 4KiB index includes the address identifier corresponding to bits 20 to 12 of the above-mentioned target virtual address, the above-mentioned 2MiB index includes the address identifier corresponding to bits 29 to 21 of the above-mentioned target virtual address, and the above-mentioned 1GiB index includes the address identifier corresponding to bits 38 to 30 of the above-mentioned target virtual address;

[0112] The virtual address determination module 52 is configured to:

[0113] accessing the translation lookaside buffer based on the 4KiB index, and if a page table entry of the translation lookaside buffer includes a first virtual page number that matches the address identifier corresponding to the 4KiB index, determining the target physical address based on the first virtual page number;

[0114] If the page table entry of the translation lookaside buffer does not include the first virtual page number, accessing the translation lookaside buffer based on the 2 MiB index, and if the page table entry of the translation lookaside buffer includes a second virtual page number that matches the address identifier corresponding to the 2 MiB index, determining the target physical address based on the second virtual page number;

[0115] If the page table entry of the translation lookaside buffer does not include the second virtual page number, the translation lookaside buffer is accessed based on the 1GiB index. If the page table entry of the translation lookaside buffer includes a third virtual page number that matches the address identifier corresponding to the 1GiB index, the target physical address is determined based on the third virtual page number.

[0116] In some feasible implementations, the virtual address determination module 52 is further configured to:

[0117] If the target physical address is determined based on the page table entry of the second translation lookaside buffer or based on a page table traversal mechanism, the target page table entry corresponding to the target physical address is backfilled into the first translation lookaside buffer.

[0118] In some feasible implementations, the virtual address determination module 52 is further configured to:

[0119] If the target physical address is not determined based on the page table entry in the first translation lookaside buffer, a physical page for storing the page table entry that has been least recently used in the first translation lookaside buffer is replaced.

[0120] In some feasible implementations, in the above machine mode, the above virtual address determination module 52 is further configured to:

[0121] Get the additional physical address width from 47 bits to 39 bits provided by the configuration register;

[0122] Sending the extra physical address bit width to a virtual memory management unit to construct a mapping relationship between the virtual address of bits 0 to 47 and the physical address of bits 0 to 47 based on the extra physical address bit width;

[0123] The target physical address corresponding to the target virtual address is determined by accessing the virtual memory management unit and based on the mapping relationship between the virtual address and the physical address stored in the virtual memory management unit.

[0124] In some feasible implementations, the virtual address determination module 52 is further configured to:

[0125] Sending translation lookaside buffer maintenance information to the virtual memory management unit, so that the virtual memory management unit maintains the transfer lookaside buffer based on the translation lookaside buffer maintenance information;

[0126] The translation lookaside buffer maintenance information includes at least one of a specified address space identifier, a specified base address of a physical page for storing a page table entry, and a specified virtual address.

[0127] In some feasible implementations, the first translation lookaside buffer and the second translation lookaside buffer support a 16-bit address space identifier.

[0128] In some feasible implementations, the page table entries are stored in physical pages in the virtual memory management unit, and the virtual address determination module 52 is further configured to:

[0129] If the physical page is a shared page, access to the physical page is allowed; if the physical page is a non-shared page, an exception prompt is triggered when accessing the physical page;

[0130] If the physical page is in a secure state, access to the physical page is allowed; if the physical page is in an unsecure state, an exception prompt is triggered when accessing the physical page;

[0131] If the physical page is allowed to be rewritten, data is allowed to be written to the physical page. If the physical page is not allowed to be written to, an exception prompt is triggered when writing data to the physical page.

[0132] If the physical page is allowed to be accessed, access to the physical page is allowed; if the physical page is not allowed to be accessed, an abnormal prompt is triggered when accessing the physical page;

[0133] If the access process accessing the physical page belongs to the shared process corresponding to the physical page, access to the physical page is allowed; if it does not belong to the shared process, access to the physical page is not allowed;

[0134] If the physical page is accessed in the first mode, an exception prompt is triggered. If the physical page is accessed in the second mode, access to the physical page is allowed. The first mode is the operating mode corresponding to when the physical page is not allowed to be accessed, and the second mode is the operating mode corresponding to when the physical page is allowed to be accessed.

[0135] If the above physical page has a preset identification bit in the memory, an exception prompt will be triggered when the above physical page is accessed.

[0136] In some feasible implementations, the virtual address determination module 52 is further configured to:

[0137] When reading any of the above page table entries, performing a parity check on the page table entry;

[0138] If the check result includes error information, the error information is reported and the page table entry is marked as invalid information;

[0139] The target physical address is determined based on a page table traversal mechanism.

[0140] In a specific implementation, the above device can execute the above-mentioned functions through its built-in functional modules. Figure 1 For the implementation methods provided in each step, please refer to the implementation methods provided in the above steps for details, which will not be repeated here.

[0141] See also Figure 6 , Figure 6 Schematic diagram of the structure of the electronic device provided by the embodiment of the present invention. Figure 6 As shown, the electronic device 1000 in this embodiment may include: a processor 1001, a network interface 1004 and a memory 1005. In addition, the above-mentioned electronic device 1000 may also include: a user interface 1003, and at least one communication bus 1002. The communication bus 1002 is used to realize the connection and communication between these components. The user interface 1003 may include a display screen (Display), a keyboard (Keyboard), and the user interface 1003 may optionally include a standard wired interface and a wireless interface. The network interface 1004 may optionally include a standard wired interface and a wireless interface (such as a WI-FI interface). The memory 1004 may be a high-speed RAM memory, or a non-volatile memory (non-volatile memory), such as at least one disk memory. The memory 1005 may optionally be at least one storage device located away from the aforementioned processor 1001. As Figure 6 As shown, the memory 1005 as a computer-readable storage medium may include an operating system, a network communication module, a user interface module, and a device control application.

[0142] exist Figure 6 In the electronic device 1000 shown, the network interface 1004 can provide network communication functions; the user interface 1003 is mainly used to provide an interface for user input; and the processor 1001 can be used to call the device control application stored in the memory 1005 to achieve:

[0143] Determine a target virtual address corresponding to an instruction fetch address or a memory access address in any mode of user mode, supervisor mode, or machine mode;

[0144] Determining a target physical address corresponding to the target virtual address by accessing a virtual memory management unit, wherein the virtual memory management unit stores a page table entry that maps the virtual address to the physical address, and the bit width of the target virtual address is less than or equal to the bit width of the target physical address;

[0145] Returns the physical address of the target.

[0146] In some feasible implementations, the virtual memory management unit includes a first translation lookaside buffer and a second translation lookaside buffer, the first translation lookaside buffer storing page table entries that map virtual addresses within a preset time interval from a current time to physical addresses, and the second translation lookaside buffer storing page table entries that map all virtual addresses to physical addresses;

[0147] In the user mode or the supervisor mode, the processor 1001 is configured to:

[0148] sequentially accessing the first translation lookaside buffer based on a multi-level index to determine a target physical address corresponding to the target virtual address based on a page table entry of the first translation lookaside buffer;

[0149] If the target physical address is not determined, sequentially accessing the second translation lookaside buffer based on the multi-level index to determine the target physical address based on a page table entry of the second translation lookaside buffer;

[0150] If the target physical address is not determined, the target physical address is determined based on a page table traversal mechanism.

[0151] In some feasible implementations, any of the above-mentioned page table entries is used to represent a mapping relationship between an address identifier of a virtual address and a virtual page number of a corresponding physical address, and the above-mentioned multi-level index includes a 4KiB index, a 2MiB index, and a 1GiB index in sequence, the above-mentioned 4KiB index includes the address identifier corresponding to bits 20 to 12 of the above-mentioned target virtual address, the above-mentioned 2MiB index includes the address identifier corresponding to bits 29 to 21 of the above-mentioned target virtual address, and the above-mentioned 1GiB index includes the address identifier corresponding to bits 38 to 30 of the above-mentioned target virtual address;

[0152] The processor 1001 is configured to:

[0153] accessing the translation lookaside buffer based on the 4KiB index, and if a page table entry of the translation lookaside buffer includes a first virtual page number that matches the address identifier corresponding to the 4KiB index, determining the target physical address based on the first virtual page number;

[0154] If the page table entry of the translation lookaside buffer does not include the first virtual page number, accessing the translation lookaside buffer based on the 2 MiB index, and if the page table entry of the translation lookaside buffer includes a second virtual page number that matches the address identifier corresponding to the 2 MiB index, determining the target physical address based on the second virtual page number;

[0155] If the page table entry of the translation lookaside buffer does not include the second virtual page number, the translation lookaside buffer is accessed based on the 1GiB index. If the page table entry of the translation lookaside buffer includes a third virtual page number that matches the address identifier corresponding to the 1GiB index, the target physical address is determined based on the third virtual page number.

[0156] In some feasible implementations, the processor 1001 is further configured to:

[0157] If the target physical address is determined based on the page table entry of the second translation lookaside buffer or based on a page table traversal mechanism, the target page table entry corresponding to the target physical address is backfilled into the first translation lookaside buffer.

[0158] In some feasible implementations, the processor 1001 is further configured to:

[0159] If the target physical address is not determined based on the page table entry in the first translation lookaside buffer, a physical page for storing the page table entry that has been least recently used in the first translation lookaside buffer is replaced.

[0160] In some feasible implementations, in the above machine mode, the processor 1001 is configured to:

[0161] Get the additional physical address width from 47 bits to 39 bits provided by the configuration register;

[0162] Sending the extra physical address bit width to a virtual memory management unit to construct a mapping relationship between the virtual address of bits 0 to 47 and the physical address of bits 0 to 47 based on the extra physical address bit width;

[0163] The target physical address corresponding to the target virtual address is determined by accessing the virtual memory management unit and based on the mapping relationship between the virtual address and the physical address stored in the virtual memory management unit.

[0164] In some feasible implementations, the processor 1001 is further configured to:

[0165] Sending translation lookaside buffer maintenance information to the virtual memory management unit, so that the virtual memory management unit maintains the transfer lookaside buffer based on the translation lookaside buffer maintenance information;

[0166] The translation lookaside buffer maintenance information includes at least one of a specified address space identifier, a specified base address of a physical page for storing a page table entry, and a specified virtual address.

[0167] In some feasible implementations, the first translation lookaside buffer and the second translation lookaside buffer support a 16-bit address space identifier.

[0168] In some feasible implementations, the page table entry is stored in a physical page in the virtual memory management unit, and the processor 1001 is further configured to:

[0169] If the physical page is a shared page, access to the physical page is allowed; if the physical page is a non-shared page, an exception prompt is triggered when accessing the physical page;

[0170] If the physical page is in a secure state, access to the physical page is allowed; if the physical page is in an unsecure state, an exception prompt is triggered when accessing the physical page;

[0171] If the physical page is allowed to be rewritten, data is allowed to be written to the physical page. If the physical page is not allowed to be written to, an exception prompt is triggered when writing data to the physical page.

[0172] If the physical page is allowed to be accessed, access to the physical page is allowed; if the physical page is not allowed to be accessed, an abnormal prompt is triggered when accessing the physical page;

[0173] If the access process accessing the physical page belongs to the shared process corresponding to the physical page, access to the physical page is allowed; if it does not belong to the shared process, access to the physical page is not allowed;

[0174] If the physical page is accessed in the first mode, an exception prompt is triggered. If the physical page is accessed in the second mode, access to the physical page is allowed. The first mode is the operating mode corresponding to when the physical page is not allowed to be accessed, and the second mode is the operating mode corresponding to when the physical page is allowed to be accessed.

[0175] If the above physical page has a preset identification bit in the memory, an exception prompt will be triggered when the above physical page is accessed.

[0176] In some feasible implementations, the processor 1001 is further configured to:

[0177] When reading any of the above page table entries, performing a parity check on the page table entry;

[0178] If the check result includes error information, the error information is reported and the page table entry is marked as invalid information;

[0179] The target physical address is determined based on a page table traversal mechanism.

[0180] It should be understood that in some feasible embodiments, the processor 1001 may be a central processing unit (CPU), or may be another general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor, or the processor may be any conventional processor, etc. The memory may include a read-only memory and a random access memory, and provide instructions and data to the processor. A portion of the memory may also include a non-volatile random access memory. For example, the memory may also store device type information.

[0181] In a specific implementation, the electronic device 1000 can execute the above-mentioned functions through its built-in functional modules. Figure 1 For the implementation methods provided in each step, please refer to the implementation methods provided in the above steps for details, which will not be repeated here.

[0182] The embodiment of the present invention further provides a computer-readable storage medium storing a computer program that is executed by a processor to implement Figure 1 For the methods provided in each step, please refer to the implementation methods provided in the above steps for details, which will not be repeated here.

[0183] The above-mentioned computer-readable storage medium can be an internal storage unit of any of the aforementioned devices or electronic devices, such as a hard disk or memory of an electronic device. The computer-readable storage medium can also be an external storage device of the electronic device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc. equipped on the electronic device. The above-mentioned computer-readable storage medium can also include a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc. Further, the computer-readable storage medium can also include both an internal storage unit of the electronic device and an external storage device. The computer-readable storage medium is used to store the computer program and other programs and data required by the electronic device. The computer-readable storage medium can also be used to temporarily store data that has been output or is to be output.

[0184] An embodiment of the present invention provides a computer program product or a computer program, wherein the computer program product or the computer program includes computer instructions, and the computer instructions are stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions, so that the computer device performs Figure 1 The methods provided in each step.

[0185] The terms "first," "second," and the like in the claims, specification, and drawings of the present invention are used to distinguish between different objects, not to describe a specific order. Furthermore, the terms "including," "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or electronic device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to the process, method, product, or electronic device. Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment of the present invention. The presence of such a phrase in various locations in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments. The term "and / or," as used in the specification and appended claims of the present invention, refers to any and all possible combinations of one or more of the associated listed items, including and including such combinations.

[0186] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the above description generally describes the components and steps of each example according to their functions. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the present invention.

[0187] The above disclosure is only a preferred embodiment of the present invention and cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A virtual memory management method, characterized in that: The method comprises: Determine a target virtual address corresponding to an instruction fetch address or a memory access address in any mode of user mode, supervisor mode, or machine mode; determining, by accessing a virtual memory management unit, a target physical address corresponding to the target virtual address, the virtual memory management unit comprising a first translation lookaside buffer and a second translation lookaside buffer, the first translation lookaside buffer storing page table entries that map virtual addresses within a preset time interval from a current time to physical addresses, the second translation lookaside buffer storing page table entries that map all virtual addresses to physical addresses, the target virtual address bit width being less than or equal to the target physical address bit width; Return the target physical address; In the machine mode, determining the target physical address corresponding to the target virtual address by accessing a virtual memory management unit includes: Get the additional physical address width from 47 bits to 39 bits provided by the configuration register; Sending the additional physical address bit width to a virtual memory management unit to construct a mapping relationship between the virtual address of bits 0 to 47 and the physical address of bits 0 to 47 based on the additional physical address bit width; The target physical address corresponding to the target virtual address is determined by accessing the virtual memory management unit and based on the mapping relationship between the virtual address and the physical address stored in the virtual memory management unit.

2. The method according to claim 1, characterized in that In the user mode or the supervisor mode, determining the target physical address corresponding to the target virtual address by accessing a virtual memory management unit includes: sequentially accessing the first translation lookaside buffer based on a multi-level index to determine a target physical address corresponding to the target virtual address based on a page table entry of the first translation lookaside buffer; If the target physical address is not determined, sequentially accessing the second translation lookaside buffer based on the multi-level index to determine the target physical address based on a page table entry of the second translation lookaside buffer; If the target physical address is not determined, the target physical address is determined based on a page table traversal mechanism.

3. The method according to claim 2, characterized in that Any of the page table entries is used to represent a mapping relationship between an address identifier of a virtual address and a virtual page number of a corresponding physical address, the multi-level index sequentially including a 4KiB index, a 2MiB index, and a 1GiB index, the 4KiB index including the address identifier corresponding to bits 20 to 12 of the target virtual address, the 2MiB index including the address identifier corresponding to bits 29 to 21 of the target virtual address, and the 1GiB index including the address identifier corresponding to bits 38 to 30 of the target virtual address; Accessing any one of the first translation lookaside buffer or the second translation lookaside buffer in sequence based on a multi-level index to determine a target physical address corresponding to the target virtual address based on a page table entry of the translation lookaside buffer, comprising: accessing the translation lookaside buffer based on the 4KiB index, and if a page table entry of the translation lookaside buffer includes a first virtual page number that matches the address identifier corresponding to the 4KiB index, determining the target physical address based on the first virtual page number; If the page table entry of the translation lookaside buffer does not include the first virtual page number, accessing the translation lookaside buffer based on the 2 MiB index, and if the page table entry of the translation lookaside buffer includes a second virtual page number that matches the address identifier corresponding to the 2 MiB index, determining the target physical address based on the second virtual page number; If the page table entry of the translation lookaside buffer does not include the second virtual page number, the translation lookaside buffer is accessed based on the 1GiB index; if the page table entry of the translation lookaside buffer includes a third virtual page number that matches the address identifier corresponding to the 1GiB index, the target physical address is determined based on the third virtual page number.

4. The method according to claim 2, characterized in that The method further comprises: If the target physical address is determined based on the page table entry of the second translation lookaside buffer or based on a page table traversal mechanism, the target page table entry corresponding to the target physical address is backfilled into the first translation lookaside buffer.

5. The method according to claim 2, characterized in that The method further comprises: If the target physical address is not determined based on the page table entry in the first translation lookaside buffer, a physical page for storing the page table entry that is least recently used in the first translation lookaside buffer is replaced.

6. The method according to claim 2, characterized in that The method further comprises: Sending translation lookaside buffer maintenance information to the virtual memory management unit, so that the virtual memory management unit maintains the translation lookaside buffer based on the translation lookaside buffer maintenance information; The translation lookaside buffer maintenance information includes at least one of a specified address space identifier, a specified base address of a physical page for storing a page table entry, and a specified virtual address.

7. The method according to claim 2, characterized in that The first translation lookaside buffer and the second translation lookaside buffer support a 16-bit address space identifier.

8. The method according to claim 1, characterized in that The page table entries are stored in physical pages in the virtual memory management unit, and the method further includes at least one of the following: If the physical page is a shared page, access to the physical page is allowed; if the physical page is a non-shared page, an exception prompt is triggered when accessing the physical page; If the physical page is in a secure state, access to the physical page is allowed; if the physical page is in an unsecure state, an abnormal prompt is triggered when accessing the physical page; If the physical page is allowed to be rewritten, data is allowed to be written to the physical page; if the physical page is not allowed to be written to, an abnormal prompt is triggered when data is written to the physical page; If the physical page is allowed to be accessed, access to the physical page is allowed; if the physical page is not allowed to be accessed, an abnormal prompt is triggered when accessing the physical page; If the access process accessing the physical page belongs to the shared process corresponding to the physical page, access to the physical page is allowed; if it does not belong to the shared process, access to the physical page is not allowed; If the physical page is accessed in the first mode, an exception prompt is triggered; if the physical page is accessed in the second mode, access to the physical page is allowed, the first mode is the operating mode corresponding to when the physical page is not allowed to be accessed, and the second mode is the operating mode corresponding to when the physical page is allowed to be accessed; If the physical page has a preset identification bit in the memory, an abnormal prompt is triggered when the physical page is accessed.

9. The method according to claim 2, characterized in that The method further comprises: When reading any of the page table entries, performing a parity check on the page table entry; If the check result includes error information, the error information is reported and the page table entry is marked as invalid information; The target physical address is determined based on a page table traversal mechanism.

10. A virtual memory management device, characterized in that: The device comprises: An instruction fetch or memory access module determines a target virtual address corresponding to an instruction fetch address or memory access address in any mode of user mode, supervisor mode, or machine mode; a virtual address determination module, configured to determine a target physical address corresponding to the target virtual address by accessing a virtual memory management unit, wherein the virtual memory management unit stores a first translation lookaside buffer and a second translation lookaside buffer, wherein the first translation lookaside buffer stores page table entries that map virtual addresses within a preset time interval from a current time to physical addresses, and the second translation lookaside buffer stores page table entries that map all virtual addresses to physical addresses, wherein a bit width of the target virtual address is less than or equal to a bit width of the target physical address; An address returning module, configured to return the target physical address; In the machine mode, when the virtual address determination module determines the target physical address corresponding to the target virtual address by accessing the virtual memory management unit, it is used to: Get the additional physical address width from 47 bits to 39 bits provided by the configuration register; Sending the additional physical address bit width to the virtual memory management unit to construct a mapping relationship between the virtual address of bits 0 to 47 and the physical address of bits 0 to 47 based on the additional physical address bit width; The target physical address corresponding to the target virtual address is determined by accessing the virtual memory management unit and based on the mapping relationship between the virtual address and the physical address stored in the virtual memory management unit.

11. An electronic device, characterized in that: comprising a processor and a memory, wherein the processor and the memory are connected to each other; The memory is used to store computer programs; The processor is configured to execute the method according to any one of claims 1 to 9 when calling the computer program.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and the computer program is executed by a processor to implement the method according to any one of claims 1 to 9.

Images