Display device

Abstract

Disclosed is a display device that can include a substrate including a circular display area and a non-display area; a plurality of pixels including first pixels and second pixels disposed in the display area of the substrate; a first sub-demultiplexer circuit connected to the first pixels and disposed in the non-display area; a second sub-demultiplexer circuit connected to the second pixels and disposed in the non-display area; a first connection line connected to the first sub-demultiplexer circuit and the second sub-demultiplexer circuit and disposed in the non-display area to transmit a first data input signal and a second data input signal to the first sub-demultiplexer circuit and the second sub-demultiplexer circuit, respectively; and a plurality of gate stages connected to the pixels and disposed in the non-display area to transmit a gate signal to the pixels. Some of the gate stages are disposed between the first sub-demultiplexer circuit and the second sub-demultiplexer circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to a display device. More particularly, the present application relates to a display device including a plurality of circuits. BACKGROUND

[0002] Display devices are manufactured as various types of display devices such as organic light emitting diode displays, liquid crystal displays, and quantum dot nano light emitting diode displays.

[0003] Research is being conducted to diversify the shape of display devices. For example, research is being conducted on display devices having a circular display area. The display device having a circular display area can be a circular display device or a polygonal (e.g., rectangular) display device.

[0004] A plurality of circuits (such as, for example, light emitting circuits and gate circuits) can be disposed adjacent to the outer periphery (or circumference, perimeter) of the circular display area. Accordingly, lines for connecting the circuits and the circular display area can be stacked on each other. As a result, coupling can occur between the stacked lines. In addition, since space is required to place the lines, dead space (or ineffective space) of the display device can increase. SUMMARY

[0005] According to an embodiment, a display device including a plurality of circuits is provided.

[0006] In the display device according to an embodiment, the display device can include a substrate, a plurality of pixels, a first sub-demultiplexer circuit, a second sub-demultiplexer circuit, a first connection line, and a plurality of gate stages. The substrate includes a circular display area and a non-display area surrounding the display area. The pixels include first pixels and second pixels disposed in the display area of the substrate. The first sub-demultiplexer circuit is connected to the first pixels and is disposed in the non-display area to transmit first data output signals to the first pixels. The second sub-demultiplexer circuit is connected to the second pixels and is disposed in the non-display area to transmit second data output signals to the second pixels. The first connection line is connected to the first sub-demultiplexer circuit and the second sub-demultiplexer circuit and is disposed in the non-display area to transmit a first data input signal to the first sub-demultiplexer circuit and a second data input signal to the second sub-demultiplexer circuit. The gate stages are connected to the pixels and are disposed in the non-display area to transmit gate signals to the pixels. Some of the gate stages are disposed between the first sub-demultiplexer circuit and the second sub-demultiplexer circuit.

[0007] In one embodiment, the first pixels can be disposed in a first pixel column, and the second pixels are disposed in a second pixel column.

[0008] In one embodiment, the display apparatus can further include a plurality of light emitting stages connected to the pixels and disposed in the non-display area to transmit the light emitting signal to the pixels, wherein some of the light emitting stages can be disposed between the first sub-demultiplexer circuit and the second sub-demultiplexer circuit.

[0009] In one embodiment, the first pixel can include a first sub-pixel, a second sub-pixel, and a third sub-pixel, the second pixel can include a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel, and the first connection line can include a first sub-connection line, a second sub-connection line, and a third sub-connection line.

[0010] In one embodiment, the first sub-connection line can be connected to the first sub-pixel and the fourth sub-pixel and can transmit the data output signal to the first sub-pixel and the fourth sub-pixel. The second sub-connection line can be connected to the second sub-pixel and the fifth sub-pixel and can transmit the data output signal to the second sub-pixel and the fifth sub-pixel. The third sub-connection line can be connected to the third sub-pixel and the sixth sub-pixel and can transmit the data output signal to the third sub-pixel and the sixth sub-pixel.

[0011] In one embodiment, the first sub-connection line can be connected to a first switching transistor connected to the first sub-pixel and a second switching transistor connected to the fourth sub-pixel. The second sub-connection line can be connected to a third switching transistor connected to the second sub-pixel and a fourth switching transistor connected to the fifth sub-pixel. The third sub-connection line can be connected to a fifth switching transistor connected to the third sub-pixel and a sixth switching transistor connected to the sixth sub-pixel.

[0012] In one embodiment, the display apparatus can further include a first transmission line for transmitting the first gate-on signal to the first switching transistor, the third switching transistor, and the fifth switching transistor.

[0013] In one embodiment, the display apparatus can further include a second transmission line for transmitting the second gate-on signal to the second switching transistor, the fourth switching transistor, and the sixth switching transistor.

[0014] In one embodiment, the first gate-on signal and the second gate-on signal can be selectively transmitted.

[0015] In one embodiment, the pixel may further include a third pixel and a fourth pixel disposed in the display area of ​​the substrate. The display device may further include a third sub-demultiplexer circuit, a fourth sub-demultiplexer circuit, and a second connecting line. The third sub-demultiplexer circuit is connected to the third pixel and disposed in the non-display area to transmit a third data output signal to the third pixel. The fourth sub-demultiplexer circuit is connected to the fourth pixel and disposed in the non-display area to transmit a fourth data output signal to the fourth pixel. The second connecting line is connected to the third and fourth sub-demultiplexer circuits and disposed in the non-display area to transmit a third data input signal to the third sub-demultiplexer circuit and a fourth data input signal to the fourth sub-demultiplexer circuit. Another portion of the gate stage may be disposed between the second and third sub-demultiplexer circuits, and yet another portion of the gate stage may be disposed between the third and fourth sub-demultiplexer circuits.

[0016] In one embodiment, the first pixel can be set in the first pixel column, the second pixel can be set in the second pixel column, the third pixel can be set in the third pixel column, and the fourth pixel can be set in the fourth pixel column.

[0017] In one embodiment, the distance between the first sub-demultiplexer circuit and the second sub-demultiplexer circuit connected to the first connection line may be different from the distance between the third sub-demultiplexer circuit and the fourth sub-demultiplexer circuit connected to the second connection line.

[0018] In one embodiment, the display device may further include a plurality of light-emitting levels connected to the pixels to transmit light-emitting signals to the pixels. Some light-emitting levels may be disposed between a first sub-demultiplexer circuit and a second sub-demultiplexer circuit, another portion of the light-emitting levels may be disposed between the second sub-demultiplexer circuit and a third sub-demultiplexer circuit, and yet another portion of the light-emitting levels may be disposed between the third sub-demultiplexer circuit and a fourth sub-demultiplexer circuit.

[0019] In one embodiment, the third pixel may include a first sub-pixel, a second sub-pixel, and a third sub-pixel; the fourth pixel may include a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel; and the second connecting line may include a first sub-connecting line, a second sub-connecting line, and a third sub-connecting line.

[0020] In one embodiment, a first sub-connection line can be connected to a first sub-pixel and a fourth sub-pixel, and can transmit a data output signal to the first sub-pixel and the fourth sub-pixel. A second sub-connection line can be connected to a second sub-pixel and a fifth sub-pixel, and can transmit a data output signal to the second sub-pixel and the fifth sub-pixel. A third sub-connection line can be connected to a third sub-pixel and a sixth sub-pixel, and can transmit a data output signal to the third sub-pixel and the sixth sub-pixel.

[0021] In one embodiment, a first sub-connection line may be connected to a first switching transistor connected to a first sub-pixel and a second switching transistor connected to a fourth sub-pixel. A second sub-connection line may be connected to a third switching transistor connected to a second sub-pixel and a fourth switching transistor connected to a fifth sub-pixel. A third sub-connection line may be connected to a fifth switching transistor connected to a third sub-pixel and a sixth switching transistor connected to a sixth sub-pixel.

[0022] In one embodiment, the display device may further include a first transmission line for transmitting a first gate-on signal to a first switching transistor, a third switching transistor, and a fifth switching transistor.

[0023] In one embodiment, the display device may further include a second transmission line for transmitting a second gate-on signal to a second switching transistor, a fourth switching transistor, and a sixth switching transistor.

[0024] In one embodiment, a first gate-on signal and a second gate-on signal can be selectively transmitted.

[0025] In a display device according to an embodiment, the display device may include a substrate, first pixels to nth pixels, first sub-demultiplexer circuits to nth sub-demultiplexer circuits, connecting lines, and a plurality of gate levels. The substrate includes a circular display area and a non-display area surrounding the display area. The first pixels to nth pixels are disposed in the display area of ​​the substrate, where n is a natural number 3 or greater. The first sub-demultiplexer circuits to nth sub-demultiplexer circuits are respectively connected to the first pixels to nth pixels and disposed in the non-display area to transmit first data output signals to nth data output signals to the first pixels to nth pixels, respectively. The connecting lines are connected to the first sub-demultiplexer circuits to nth sub-demultiplexer circuits and disposed in the non-display area to transmit first data input signals to nth data input signals to the first sub-demultiplexer circuits to nth sub-demultiplexer circuits, respectively. The gate levels are respectively connected to the first pixels to nth pixels and disposed between the first sub-demultiplexer circuits and the nth sub-demultiplexer circuit to transmit gate signals to the first pixels to nth pixels, respectively.

[0026] In one embodiment, the first pixel to the nth pixel can be respectively set in the first pixel column to the nth pixel column.

[0027] In one embodiment, the display device may further include a plurality of light-emitting stages disposed between the first sub-demultiplexer circuit and the nth sub-demultiplexer circuit.

[0028] In one embodiment, each of the first to nth pixels may include a plurality of sub-pixels, and the connecting lines include a plurality of sub-connecting lines having a number corresponding to the number of said sub-pixels for each pixel.

[0029] The display device according to an embodiment may include a plurality of sub-demultiplexer circuits. At least two of the sub-demultiplexer circuits may be connected to operate as a single demultiplexer circuit. For example, two sub-demultiplexer circuits may operate as a single demultiplexer circuit. At least one light-emitting stage and at least one gate stage may be disposed between two sub-demultiplexer circuits.

[0030] When the sub-demultiplexer circuits are set to be separated from each other, the area where the sub-demultiplexer circuits are connected to the data lines of multiple pixels and the area where they are connected to the light-emitting lines of the light-emitting level and the area where they are connected to the gate lines of the gate level can be reduced.

[0031] Additionally, a circuit (or level) can be configured to be adjacent to multiple pixels connected to the circuit (or level), thereby minimizing the space where lines connecting the circuit to the pixels are arranged. Attached Figure Description

[0032] The illustrative, non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0033] Figure 1 and Figure 2 This is a plan view showing a display device according to an embodiment.

[0034] Figure 3A It is shown schematically. Figure 1 An enlarged view of an embodiment of the display device, showing area A.

[0035] Figure 3B It is used for explanation Figure 1 The circuit diagram of the pixels.

[0036] Figure 4 The embodiment schematically illustrates the setting. Figure 1 A block diagram showing the connection relationship of the first demultiplexer circuit in the display device.

[0037] Figure 5 The embodiment schematically illustrates the setting. Figure 1 A block diagram showing the connection relationship between the first demultiplexer circuit and the second demultiplexer circuit in the display device.

[0038] Figure 6 It is shown that it is set in Figure 1 An enlarged view of an embodiment of the first demultiplexer circuit in a display device.

[0039] Figure 7 It shows that it includes Figure 1 A view of an embodiment of the first sub-connecting line to the third sub-connecting line in a display device.

[0040] Figure 8 It shows along Figure 7 A sectional view of the section cut by line I-I'.

[0041] Figure 9 The embodiment schematically illustrates the setting. Figure 1 A block diagram showing the connection relationship of the demultiplexer circuit in the display device.

[0042] Figure 10 It is shown that it is set in Figure 1 An enlarged view of an embodiment of the demultiplexer circuit in a display device.

[0043] Figure 11 This is a view showing the distance between the demultiplexer circuit and the sub-demultiplexer circuit.

[0044] Figure 12 This is a view showing the distance between the demultiplexer circuit and the sub-demultiplexer circuit. Detailed Implementation

[0045] In the following description, embodiments will be presented in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and redundant descriptions of the same components will be omitted.

[0046] Figure 1 and Figure 2 This is a plan view showing a display device according to an embodiment.

[0047] Reference Figure 1 and Figure 2 The display device may include a display area DA and a non-display area NDA. The display area DA may have a circular shape. Although Figure 1 and Figure 2The illustration shows a display area DA with a circular shape having a predetermined curvature, but shapes other than a circular shape with a predetermined curvature are possible. For example, the display area DA may have an elliptical shape. Optionally, in an embodiment, the display area DA may have a predetermined curvature at the region where a first straight line portion extending along a first direction intersects with a second straight line portion extending along a second direction perpendicular to the first direction. For example, the display area DA may have a square shape overall, and each vertex may have a predetermined curvature. A plurality of pixels P may be disposed in the display area DA. For example, the pixels P may be disposed in a matrix shape. The pixels P may be disposed in a stepped manner at the edges of the display area DA. For example, the pixels P may be arranged in a stepped manner at the edges of the display area DA to present curvature (or bending).

[0048] The non-display area NDA can surround the display area DA. For example... Figure 1 As shown, the non-display area NDA can have a circular shape similar to the display area DA. In other words, the display device can have a circular shape.

[0049] In addition, such as Figure 2 As shown, unlike the display area DA, the non-display area NDA can have a rectangular shape. In other words, the display device can have a rectangular shape and a circular display area DA. Alternatively, the display device can have a polygonal shape with a circular display area DA.

[0050] Multiple circuits for driving the display area DA can be located in the non-display area NDA. In other words, the circuits can be electrically connected to the pixels P located in the display area DA. The circuits can be configured to be adjacent to the display area DA. For example, the circuits can be configured in a circular shape along the outer perimeter (or circumference) of the circular display area DA.

[0051] In this embodiment, the circuit may transmit multiple signals for driving pixel P. For example, the circuit may include a data circuit for transmitting data signals to pixel P. Additionally, the circuit may include a light-emitting circuit for transmitting light-emitting signals to pixel P. Furthermore, the circuit may include a gate circuit for transmitting gate signals to pixel P.

[0052] Figure 3A It is shown schematically. Figure 1 An enlarged view of an embodiment of the display device, showing area A. Figure 3B It is used for explanation Figure 1 The circuit diagram of pixel P.

[0053] Reference Figure 1 , Figure 3A and Figure 3BThe display device may include a pixel P. Pixel P may include at least one transistor, at least one capacitor, and a light-emitting diode (OLED). For example, pixel P may include first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6, and TR7, a storage capacitor CST, and an organic light-emitting diode (OLED). Pixel P may be driven by gate control signals GW, GI, GB, light emission control signal EM, data signal DATA, initialization voltage VINT, and power supply voltages ELVDD and ELVSS. The OLED can emit light by receiving a drive current ID according to the signal received.

[0054] Pixel P may include a first pixel P1, a second pixel P2, a third pixel P3, and a fourth pixel P4. The display device may include a first demultiplexer circuit DC1 and a second demultiplexer circuit DC2 (e.g., ...) disposed in the non-display area NDA. Figure 4 and Figure 5 (As shown in the diagram). The first demultiplexer circuit DC1 may include a first sub-demultiplexer circuit SDC1 and a second sub-demultiplexer circuit SDC2. The second demultiplexer circuit DC2 may include a third sub-demultiplexer circuit SDC3 and a fourth sub-demultiplexer circuit SDC4. In an embodiment, demultiplexer circuits DC1 and DC2 can transmit the data signal DATA to pixel P.

[0055] A first pixel P1 can be located in the first pixel column. The first pixel P1 located in the first pixel column can be connected to the first sub-demultiplexer circuit SDC1. A second pixel P2 can be located in the second pixel column. The second pixel P2 located in the second pixel column can be connected to the second sub-demultiplexer circuit SDC2. A third pixel P3 can be located in the third pixel column. The third pixel P3 located in the third pixel column can be connected to the third sub-demultiplexer circuit SDC3. A fourth pixel P4 can be located in the fourth pixel column. The fourth pixel P4 located in the fourth pixel column can be connected to the fourth sub-demultiplexer circuit SDC4.

[0056] In an embodiment, the first sub-demultiplexer circuit SDC1 can output a first data signal (e.g., Figure 4 The first data output signal DO1 is provided to pixel P located in the first pixel column. The second sub-demultiplexer circuit SDC2 can convert the second data output signal (e.g., ...) to the second data output signal (e.g., ...) Figure 4 The second data output signal DO2 is provided to pixel P, which is set in the second pixel column.

[0057] The display device may include a gate circuit and a light-emitting circuit. In an embodiment, the gate circuit may include multiple gate levels (GS). The light-emitting circuit may include multiple light-emitting levels (ES). The gate levels (GS) and light-emitting levels (ES) may be arranged along the periphery of the display area (DA).

[0058] Multiple circuits can be arranged between the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2. In an embodiment, at least one gate level GS can be arranged between the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2. The gate level GS can provide a gate signal to pixel P. The gate level GS can be connected to pixel P via a gate line GL. The gate level GS can transmit multiple gate signals GW, GI, and GB to pixel P.

[0059] Additionally, in this embodiment, at least one light-emitting stage ES can be disposed between the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2. The light-emitting stage ES can provide a light-emitting signal to pixel P. The light-emitting stage ES can be connected to pixel P via a light-emitting line EL. The light-emitting stage ES can transmit the light-emitting signal EM to pixel P.

[0060] Therefore, pixel P can display an image in display area DA in response to data output signals, light emission signals, and gate signals.

[0061] The first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2 can be configured to be separated from each other. Additionally, the third sub-demultiplexer circuit SDC3 and the fourth sub-demultiplexer circuit SDC4 can also be configured to be separated from each other. The first distance D1 separating the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2 can be different from the second distance D2 separating the third sub-demultiplexer circuit SDC3 and the fourth sub-demultiplexer circuit SDC4. The first distance D1 and the second distance D2 can represent the minimum distance between adjacent sub-demultiplexer circuits. For example, as... Figure 3A As shown, the first distance D1 can be determined by a stage (such as the gate level GS and the light-emitting level ES) disposed between the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2. Furthermore, the second distance D2 can be determined by a stage (such as the gate level GS and the light-emitting level ES) disposed between the third sub-demultiplexer circuit SDC3 and the fourth sub-demultiplexer circuit SDC4.

[0062] although Figure 3A The curvature of the display area DA is shown to be constant, but the curvature of the display area DA may not be constant. For example, the display area DA may have an elliptical shape. Optionally, as shown above... Figure 1As described above, the display area DA can have a predetermined curvature in the region where the first and second straight-line portions intersect. The gate level GS and light-emitting level ES can be set in different numbers depending on the curvature of the display area DA. Compared to pixel columns located in portions with small curvature, more pixels P can be set in pixel columns located in the portion with large curvature within the outer periphery of the elliptical display area DA. Therefore, a relatively large number of gate level GS and light-emitting level ES can be set in the region adjacent to the pixel columns located in the portion with large curvature. A relatively small number of gate level GS and light-emitting level ES can be set in the region adjacent to the pixel columns located in the portion with small curvature.

[0063] In other words, the number of stages (such as gate stage GS and light-emitting stage ES) disposed between the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2 can vary according to the curvature of the outer periphery of the display area DA. Therefore, the first distance D1 can also vary. Similarly, the number of circuits disposed between the third sub-demultiplexer circuit SDC3 and the fourth sub-demultiplexer circuit SDC4 can vary according to the curvature of the outer periphery of the display area DA. Therefore, the second distance D2 can also vary.

[0064] The first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2 can be connected via the first connection line 100. Each of the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2 can receive the data signal DATA via the first connection line 100.

[0065] The third sub-demultiplexer circuit SDC3 and the fourth sub-demultiplexer circuit SDC4 can be connected via the second connection line 200. Each of the third sub-demultiplexer circuit SDC3 and the fourth sub-demultiplexer circuit SDC4 can receive data signals via the second connection line 200.

[0066] Figure 4 The embodiment schematically illustrates the setting. Figure 1 A block diagram showing the connection relationship of the first demultiplexer circuit DC1 in the display device.

[0067] Reference Figure 3A and Figure 4 The first pixel P1 can be connected to the first sub-demultiplexer circuit SDC1. The second pixel P2 can be connected to the second sub-demultiplexer circuit SDC2. The first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2 can be connected via the first connecting line 100.

[0068] The first connection line 100 can be connected to a data driver (not shown). The first connection line 100 can receive a first data signal DS1 from the data driver. In an embodiment, the first connection line 100 can transmit a first data input signal DI1, which is the first data signal DS1, to a first sub-demultiplexer circuit SDC1. Additionally, the first connection line 100 can transmit a second data input signal DI2, which is the first data signal DS1, to a second sub-demultiplexer circuit SDC2.

[0069] In this embodiment, each of the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2 can selectively transmit a data output signal to the first pixel P1 and the second pixel P2 based on a gate turn-on signal. For example, when the first gate turn-on signal GO1 for turning on the first sub-demultiplexer circuit SDC1 is transmitted to the first sub-demultiplexer circuit SDC1, the first sub-demultiplexer circuit SDC1 can transmit the first data output signal DO1, which is the first data signal DS1, to the first pixel P1. At this time, the second gate turn-on signal GO2 for turning on the second sub-demultiplexer circuit SDC2 may not be transmitted to the second sub-demultiplexer circuit SDC2.

[0070] Alternatively, for example, when the second gate turn-on signal GO2 is transmitted to the second sub-demultiplexer circuit SDC2, the second sub-demultiplexer circuit SDC2 can transmit the second data output signal DO2, which is the first data signal DS1, to the second pixel P2. In this case, the first gate turn-on signal GO1 may not be transmitted to the first sub-demultiplexer circuit SDC1.

[0071] Multiple circuits can be arranged between the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2. For example, light-emitting stage (ES), gate stage (GS), etc., can be arranged between the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2. At least one light-emitting stage (ES) and at least one gate stage (GS) can be arranged between the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2. The first distance D1 can be determined according to the number of light-emitting stage (ES) and gate stage (GS).

[0072] Figure 5 The embodiment schematically illustrates the setting. Figure 1 A block diagram showing the connection relationship between the first demultiplexer circuit DC1 and the second demultiplexer circuit DC2 in the display device.

[0073] In addition to adding a second demultiplexer circuit DC2, Figure 5 Can be with Figure 4 They are basically the same.

[0074] Reference Figure 3A andFigure 5 The third pixel P3 can be connected to the third sub-demultiplexer circuit SDC3. The fourth pixel P4 can be connected to the fourth sub-demultiplexer circuit SDC4. The third sub-demultiplexer circuit SDC3 and the fourth sub-demultiplexer circuit SDC4 can be connected via the second connecting line 200.

[0075] The second connection line 200 can be connected to a data driver. The second connection line 200 can receive a second data signal DS2 from the data driver. In an embodiment, the second connection line 200 can transmit a third data input signal DI3, which is the second data signal DS2, to a third sub-demultiplexer circuit SDC3. Additionally, the second connection line 200 can transmit a fourth data input signal DI4, which is the second data signal DS2, to a fourth sub-demultiplexer circuit SDC4.

[0076] When the first gate turn-on signal GO1, used to turn on the third sub-demultiplexer circuit SDC3, is transmitted to the third sub-demultiplexer circuit SDC3, the third sub-demultiplexer circuit SDC3 can transmit the third data output signal DO3, which is the second data signal DS2, to the third pixel P3. At this time, the second gate turn-on signal GO2, used to turn on the fourth sub-demultiplexer circuit SDC4, does not need to be transmitted to the fourth sub-demultiplexer circuit SDC4.

[0077] Additionally, for example, when the second gate-on signal GO2 is transmitted to the fourth sub-demultiplexer circuit SDC4, the fourth sub-demultiplexer circuit SDC4 can transmit the fourth data output signal DO4, which is the second data signal DS2, to the fourth pixel P4. In this case, the first gate-on signal GO1 does not need to be transmitted to the third sub-demultiplexer circuit SDC3.

[0078] In an embodiment, multiple stages can be arranged between the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2, between the second sub-demultiplexer circuit SDC2 and the third sub-demultiplexer circuit SDC3, and between the third sub-demultiplexer circuit SDC3 and the fourth sub-demultiplexer circuit SDC4. For example, at least one light-emitting stage ES and at least one gate stage GS can be arranged between the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2, between the second sub-demultiplexer circuit SDC2 and the third sub-demultiplexer circuit SDC3, and between the third sub-demultiplexer circuit SDC3 and the fourth sub-demultiplexer circuit SDC4. Each of the first distance D1 and the second distance D2 can be determined according to the number of light-emitting stages ES and gate stages GS. In other words, the first distance D1 and the second distance D2 can be different from each other.

[0079] Furthermore, the number of light-emitting levels (ES) and gate levels (GS) can vary depending on the structure of the pixels P adjacent to the outer periphery of the display area DA. Therefore, a first distance D1 and a second distance D2 can be determined.

[0080] Therefore, when the sub-demultiplexer circuits SDC1, SDC2, SDC3, and SDC4 are configured to be separated from each other, the lines DL, EL, and GL connected to pixel P can be connected to pixel P with a minimized length. This reduces the dead space (or invalid space) of the display device.

[0081] Furthermore, when the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2 are not separated and are arranged adjacent to each other, the data line DL connected to each pixel column will have an area overlapping with the gate line GL and the light-emitting line EL. Therefore, coupling occurs in the display device. According to the inventive concept, when the sub-demultiplexer circuits SDC1, SDC2, SDC3, and SDC4 are arranged separated from each other, the area where the data line DL overlaps with the gate line GL and the light-emitting line EL can be reduced.

[0082] Figure 6 It is shown that it is set in Figure 1 A magnified view of an embodiment of the first demultiplexer circuit DC1 in the display device.

[0083] Reference Figure 3A and Figure 6 Each pixel P may include multiple sub-pixels. In an embodiment, the first pixel P1 may include first sub-pixels to third sub-pixels SP1, SP2, and SP3. For example, the first sub-pixel SP1 may be red, the second sub-pixel SP2 may be green, and the third sub-pixel SP3 may be blue. However, other colors may be emitted. For example, the first sub-pixels to third sub-pixels SP1, SP2, and SP3 may be magenta, cyan, and yellow, respectively. The first sub-pixels to third sub-pixels SP1, SP2, and SP3 may also emit light of the same color, such as blue light. Light of the same color can be converted into different colors by using color filters, color conversion patterns, etc., disposed on the first sub-pixels to third sub-pixels SP1, SP2, and SP3. Additionally, in an embodiment, the first pixel P1 may include four sub-pixels.

[0084] Additionally, in this embodiment, the first pixel P1 and the second pixel P2 may each include two sub-pixels. The two sub-pixels of the first pixel P1 may emit light having a first color and a second color, respectively. The two sub-pixels of the second pixel P2 may emit light having a first color and a third color, respectively.

[0085] Additionally, in this embodiment, the first pixel P1 and the second pixel P2 may each include two sub-pixels. The two sub-pixels of the first pixel P1 may emit light having a first color and a third color, respectively, and the two sub-pixels of the second pixel P2 may also emit light having a first color and a third color, respectively.

[0086] The second pixel P2 may include the fourth to sixth sub-pixels SP4, SP5, and SP6. In an embodiment, the first pixel P1 may include the first to third sub-pixels SP1, SP2, and SP3. The structure of the second pixel P2 may be substantially the same as the structure of the first pixel P1.

[0087] The first connection line 100 may include a first sub-connection line to a third sub-connection line 110, 120, and 130. The first sub-connection line to the third sub-connection line 110, 120, and 130 may be connected to a first sub-demultiplexer circuit SDC1 and a second sub-demultiplexer circuit SDC2.

[0088] The first sub-connection line 110 can be connected to the first sub-pixel SP1. Additionally, the first sub-connection line 110 can be connected to the fourth sub-pixel SP4. Therefore, data output signals can be selectively transmitted to the first sub-pixel SP1 and the fourth sub-pixel SP4. Red data signals can be selectively transmitted to the first sub-pixel SP1 and the fourth sub-pixel SP4. For example, when the first switching transistor ST1 is turned on, the first red data signal can be transmitted to the first sub-pixel SP1. Optionally, when the second switching transistor ST2 is turned on, the second red data signal can be transmitted to the fourth sub-pixel SP4. In this embodiment, the first sub-pixel SP1 and the fourth sub-pixel SP4 can be selectively activated.

[0089] The second sub-connection line 120 can be connected to the second sub-pixel SP2. Additionally, the second sub-connection line 120 can be connected to the fifth sub-pixel SP5. Therefore, data output signals can be selectively transmitted to the second sub-pixel SP2 and the fifth sub-pixel SP5. Green data signals can be selectively transmitted to the second sub-pixel SP2 and the fifth sub-pixel SP5. For example, when the third switching transistor ST3 is turned on, the first green data signal can be transmitted to the second sub-pixel SP2. Optionally, when the fourth switching transistor ST4 is turned on, the second green data signal can be transmitted to the fifth sub-pixel SP5. In this embodiment, the second sub-pixel SP2 and the fifth sub-pixel SP5 can be selectively activated.

[0090] The third sub-connection line 130 can be connected to the third sub-pixel SP3. Additionally, the third sub-connection line 130 can be connected to the sixth sub-pixel SP6. Therefore, data output signals can be selectively transmitted to the third sub-pixel SP3 and the sixth sub-pixel SP6. Blue data signals can be transmitted to the third sub-pixel SP3 and the sixth sub-pixel SP6. For example, when the fifth switching transistor ST5 is turned on, a first blue data signal can be transmitted to the third sub-pixel SP3. Optionally, when the sixth switching transistor ST6 is turned on, a second blue data signal can be transmitted to the sixth sub-pixel SP6. In this embodiment, the third sub-pixel SP3 and the sixth sub-pixel SP6 can be selectively activated.

[0091] Although the connector is shown as including three sub-connectors, in embodiments, the connector may include more or fewer than three sub-connectors. The number of sub-connectors can also be changed by varying the number of sub-pixels. For example, when each pixel includes four sub-pixels, the connector may also include four sub-connectors.

[0092] The first sub-demultiplexer circuit SDC1 may include a first switching transistor ST1, a third switching transistor ST3, and a fifth switching transistor ST5. The second sub-demultiplexer circuit SDC2 may include a second switching transistor ST2, a fourth switching transistor ST4, and a sixth switching transistor ST6.

[0093] The first sub-connection line 110 can be connected to the first switching transistor ST1 and the second switching transistor ST2. The second sub-connection line 120 can be connected to the third switching transistor ST3 and the fourth switching transistor ST4. The third sub-connection line 130 can be connected to the fifth switching transistor ST5 and the sixth switching transistor ST6.

[0094] The first switching transistor ST1, the third switching transistor ST3, and the fifth switching transistor ST5 can be electrically connected to the first transmission line CLa. The first transmission line CLa can transmit the first gate-on signal GO1 to the first sub-demultiplexer circuit SDC1. For example, the first transmission line CLa can transmit the first gate-on signal GO1 to the first switching transistor ST1, the third switching transistor ST3, and the fifth switching transistor ST5. A data output signal can be transmitted to the first pixel P1 via the first switching transistor ST1, the third switching transistor ST3, and the fifth switching transistor ST5.

[0095] The second switching transistor ST2, the fourth switching transistor ST4, and the sixth switching transistor ST6 can be connected to the second transmission line CLb. The second transmission line CLb can transmit the second gate-on signal GO2 to the second sub-demultiplexer circuit SDC2. For example, the second transmission line CLb can transmit the second gate-on signal GO2 to the second switching transistor ST2, the fourth switching transistor ST4, and the sixth switching transistor ST6. Data output signals can be transmitted to the second pixel P2 via the second switching transistor ST2, the fourth switching transistor ST4, and the sixth switching transistor ST6.

[0096] Multiple stages (such as gate stage GS and light-emitting stage ES) can be set between the first sub-demultiplexer circuit SDC1 and the second sub-demultiplexer circuit SDC2.

[0097] Figure 7 It shows that it includes Figure 1 A view of an embodiment of the first sub-connecting lines to the third sub-connecting lines 110, 120, 130 in a display device.

[0098] Reference Figure 7 The first connecting line 100 may include a first sub-connecting line 110, a second sub-connecting line 120, and a third sub-connecting line 130.

[0099] The first sub-connection line 110 may include a first data input line 110a, a first data distribution line 110b, a first data transmission line 110c, and a second data transmission line 110d. The second sub-connection line 120 may include a second data input line 120a, a second data distribution line 120b, a third data transmission line 120c, and a fourth data transmission line 120d. The third sub-connection line 130 may include a third data input line 130a, a third data distribution line 130b, a fifth data transmission line 130c, and a sixth data transmission line 130d.

[0100] The first data distribution line 110b can be disposed below the first data input line 110a. The first data input line 110a and the first data distribution line 110b can be connected to each other through a contact hole. The first data distribution line 110b can be disposed below the first data transmission line 110c and the second data transmission line 110d. The first data distribution line 110b can be connected to the first data transmission line 110c and the second data transmission line 110d through a contact hole. The signal flowing through the first data transmission line 110c can be transmitted to the first sub-pixel SP1 through the first active layer ACT1 and the first data output line 210c. The signal flowing through the second data transmission line 110d can be transmitted to the fourth sub-pixel SP4 through the fourth active layer ACT4 and the second data output line 210d. Therefore, a data output signal can be transmitted to the first sub-pixel SP1 and the fourth sub-pixel SP4. A red data signal can be selectively transmitted to the first sub-pixel SP1 and the fourth sub-pixel SP4.

[0101] The second data distribution line 120b can be disposed below the second data input line 120a. The second data input line 120a and the second data distribution line 120b can be connected to each other through contact holes. The second data distribution line 120b can be disposed below the third data transmission line 120c and the fourth data transmission line 120d. The second data distribution line 120b can be connected to the third data transmission line 120c and the fourth data transmission line 120d through contact holes. The signal flowing through the third data transmission line 120c can be transmitted to the second sub-pixel SP2 through the second active layer ACT2 and the third data output line 220c. The signal flowing through the fourth data transmission line 120d can be transmitted to the fifth sub-pixel SP5 through the fifth active layer ACT5 and the fourth data output line 220d. Therefore, data output signals can be transmitted to the second sub-pixel SP2 and the fifth sub-pixel SP5. For example, green data signals can be selectively transmitted to the second sub-pixel SP2 and the fifth sub-pixel SP5.

[0102] The third data distribution line 130b can be disposed below the third data input line 130a. The third data input line 130a and the third data distribution line 130b can be connected to each other through contact holes. The third data distribution line 130b can be disposed below the fifth data transmission line 130c and the sixth data transmission line 130d. The third data distribution line 130b can be connected to the fifth data transmission line 130c and the sixth data transmission line 130d through contact holes. The signal flowing through the fifth data transmission line 130c can be transmitted to the third sub-pixel SP3 through the third active layer ACT3 and the fifth data output line 230c. The signal flowing through the sixth data transmission line 130d can be transmitted to the sixth sub-pixel SP6 through the sixth active layer ACT6 and the sixth data output line 230d. Therefore, data output signals can be transmitted to the third sub-pixel SP3 and the sixth sub-pixel SP6. For example, blue data signals can be selectively transmitted to the third sub-pixel SP3 and the sixth sub-pixel SP6.

[0103] Each of the first active layer ACT1, the second active layer ACT2, and the third active layer ACT3 can serve as a channel for transmitting data output signals to the first sub-pixels to the third sub-pixels SP1, SP2, and SP3 respectively in response to the first gate turn-on signal GO1 flowing through the first transmission line CLa.

[0104] Each of the fourth active layer ACT4, the fifth active layer ACT5, and the sixth active layer ACT6 can serve as a channel for transmitting data output signals to the fourth to sixth sub-pixels SP4, SP5, and SP6 respectively in response to the second gate turn-on signal GO2 flowing through the second transmission line CLb.

[0105] although Figure 7 The diagram shows first data distribution lines to third data distribution lines 110b, 120b, and 130b disposed below first data input lines to third data input lines 110a, 120a, and 130a, and first data transmission lines to sixth data transmission lines 110c, 110d, 120c, 120d, 130c, and 130d. However, other configurations are possible in the embodiments. For example, first data input lines to third data input lines 110a, 120a, and 130a may be disposed below first data distribution lines to third data distribution lines 110b, 120b, and 130b. Alternatively, for example, first data transmission lines to sixth data transmission lines 110c, 110d, 120c, 120d, 130c, and 130d may be disposed below first data distribution lines to third data distribution lines 110b, 120b, and 130b.

[0106] Figure 8 It shows along Figure 7 A sectional view of the section cut by line I-I'.

[0107] Reference Figure 6 to Figure 8 The display device may include a substrate SUB, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and a first switching transistor ST1. The first switching transistor ST1 may include a first active layer ACT1, a first transmission line CLa, a first data transmission line 110c, and a first data output line 210c.

[0108] In one embodiment, the substrate SUB may comprise plastic and may have flexible properties. Alternatively, in another embodiment, the substrate SUB may comprise glass, quartz, etc., and may have rigid properties.

[0109] The first active layer ACT1 may be disposed on the substrate SUB. The first active layer ACT1 may include a semiconductor material. In an embodiment, the first active layer ACT1 may include an oxide-based semiconductor material. Optionally, in an embodiment, the first active layer ACT1 may include a silicon-based semiconductor material.

[0110] The gate insulating layer GI can be disposed on the substrate SUB and simultaneously cover the first active layer ACT1. The gate insulating layer GI can include an inorganic insulating material. For example, the gate insulating layer GI can include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0111] The first transmission line CLa can be disposed on the gate insulating layer GI. The first transmission line CLa can include various conductive materials containing metals. For example, the first transmission line CLa can include copper, tungsten, titanium, etc.

[0112] The first interlayer insulating layer ILD1 can be disposed on the gate insulating layer GI and simultaneously cover the first transmission line CLa. The first interlayer insulating layer ILD1 may include an inorganic insulating material. For example, the first interlayer insulating layer ILD1 may include silicon oxide, silicon nitride, silicon oxynitride, etc.

[0113] The first data transmission line 110c and the first data output line 210c can be disposed on the first interlayer insulating layer ILD1. The first data transmission line 110c and the first data output line 210c can include various conductive materials containing metals.

[0114] The second interlayer insulating layer ILD2 can be disposed on the first interlayer insulating layer ILD1, simultaneously covering the first data transmission line 110c and the first data output line 210c. The second interlayer insulating layer ILD2 may include an organic insulating material. For example, the second interlayer insulating layer ILD2 may include polyimide.

[0115] Figure 9 The embodiment schematically illustrates the setting. Figure 1A block diagram showing the connection relationship of the demultiplexer circuit DC11 in the display device.

[0116] Reference Figure 9 The display device may include a first pixel P11, a second pixel P12, a third pixel P13, a first demultiplexer circuit DC11, and a first connection line 1100. The first demultiplexer circuit DC11 may include a first sub-demultiplexer circuit SDC11, a second sub-demultiplexer circuit SDC12, and a third sub-demultiplexer circuit SDC13.

[0117] In this embodiment, the first pixel P11 can be connected to a first sub-demultiplexer circuit SDC11. The first sub-demultiplexer circuit SDC11 can receive a first data input signal DI11 from the first connection line 1100. The first sub-demultiplexer circuit SDC11 can transmit a first data output signal DO11 to the first pixel P11.

[0118] In this embodiment, the second pixel P12 can be connected to a second sub-demultiplexer circuit SDC12. The second sub-demultiplexer circuit SDC12 can receive a second data input signal DI12 from the first connection line 1100. The second sub-demultiplexer circuit SDC12 can transmit a second data output signal DO12 to the second pixel P12.

[0119] In this embodiment, the third pixel P13 can be connected to the third sub-demultiplexer circuit SDC13. The third sub-demultiplexer circuit SDC13 can receive the third data input signal DI13 from the first connection line 1100. The third sub-demultiplexer circuit SDC13 can transmit the third data output signal DO13 to the third pixel P13.

[0120] In this embodiment, the first sub-demultiplexer circuit SDC11, the second sub-demultiplexer circuit SDC12, and the third sub-demultiplexer circuit SDC13 can selectively transmit data output signals. For example, when the first sub-demultiplexer circuit SDC11 transmits the first data output signal DO11 to the first pixel P11, the second sub-demultiplexer circuit SDC12 and the third sub-demultiplexer circuit SDC13 may not transmit the second data output signal DO12 and the third data output signal DO13 to pixels P12 and P13. Optionally, when the second sub-demultiplexer circuit SDC12 transmits the second data output signal DO12 to the second pixel P12, the first sub-demultiplexer circuit SDC11 and the third sub-demultiplexer circuit SDC13 may not transmit the first data output signal DO11 and the third data output signal DO13 to pixels P11 and P13.

[0121] The first sub-demultiplexer circuit SDC11, the second sub-demultiplexer circuit SDC12, and the third sub-demultiplexer circuit SDC13 can be a 1:3 demultiplexer circuit. The spacing between the first sub-demultiplexer circuit SDC11 and the third sub-demultiplexer circuit SDC13 can be determined based on the number of light-emitting stages and gate stages. However, although Figure 9 The diagram shows a first connection line 1100 connected to three sub-demultiplexer circuits SDC11, SDC12, and SDC13. However, in this embodiment, the first connection line 1100 may also be connected to four or more sub-demultiplexer circuits. At least one light-emitting stage and at least one gate stage may be disposed between the sub-demultiplexer circuits.

[0122] Figure 10 It is shown that it is set in Figure 1 An enlarged view of an embodiment of the demultiplexer circuit DC11 in the display device.

[0123] Reference Figure 10 The display device may include first pixels to third pixels P11, P12, and P13. Each of the first pixels to third pixels P11, P12, and P13 may include multiple sub-pixels. In an embodiment, the first pixel P11 may include first sub-pixels to third sub-pixels SP11, SP12, and SP13. For example, the first sub-pixel SP11 may display red, the second sub-pixel SP12 may display green, and the third sub-pixel SP13 may display blue. However, in an embodiment, the first pixel P11 may include four sub-pixels. Additionally, the first sub-pixels to third sub-pixels SP11, SP12, and SP13 may display magenta, cyan, and yellow, respectively. The first sub-pixels to third sub-pixels SP11, SP12, and SP13 may emit light of the same color, such as blue light. The light of the same color can be converted differently by color filters, color conversion patterns, etc., disposed on the first sub-pixels to third sub-pixels SP11, SP12, and SP13.

[0124] The second pixel P12 may include the fourth to sixth sub-pixels SP14, SP15, and SP16. The third pixel P13 may include the seventh to ninth sub-pixels SP17, SP18, and SP19. In an embodiment, the structures of the second pixel P12 and the third pixel P13 may be substantially the same as the structure of the first pixel P11.

[0125] The connection line 1100 may include a first sub-connection line to a third sub-connection line 1110, 1120 and 1130. The first sub-connection line to the third sub-connection line 1110, 1120 and 1130 may be connected to a first sub-demultiplexer circuit SDC11, a second sub-demultiplexer circuit SDC12 and a third sub-demultiplexer circuit SDC13.

[0126] The first sub-connection line 1110 can be connected to the first sub-pixel SP11, the fourth sub-pixel SP14, and the seventh sub-pixel SP17. Data output signals can be transmitted to the first sub-pixel SP11, the fourth sub-pixel SP14, and the seventh sub-pixel SP17. Red data signals can be selectively transmitted to the first sub-pixel SP11, the fourth sub-pixel SP14, and the seventh sub-pixel SP17. For example, when the first switching transistor ST11 is turned on, the first red data signal can be transmitted to the first sub-pixel SP11. Optionally, when the second switching transistor ST12 is turned on, the second red data signal can be transmitted to the fourth sub-pixel SP14. Optionally, when the third switching transistor ST13 is turned on, the third red data signal can be transmitted to the seventh sub-pixel SP17. In this embodiment, the first sub-pixel SP11, the fourth sub-pixel SP14, and the seventh sub-pixel SP17 can be selectively turned on.

[0127] The second sub-connection line 1120 can be connected to the second sub-pixel SP12, the fifth sub-pixel SP15, and the eighth sub-pixel SP18. Data output signals can be selectively transmitted to the second sub-pixel SP12, the fifth sub-pixel SP15, and the eighth sub-pixel SP18. Green data signals can be selectively transmitted to the second sub-pixel SP12, the fifth sub-pixel SP15, and the eighth sub-pixel SP18. For example, when the fourth switching transistor ST14 is turned on, the first green data signal can be transmitted to the second sub-pixel SP12. Optionally, when the fifth switching transistor ST15 is turned on, the second green data signal can be transmitted to the fifth sub-pixel SP15. Optionally, when the sixth switching transistor ST16 is turned on, the third green data signal can be transmitted to the eighth sub-pixel SP18. In this embodiment, the second sub-pixel SP12, the fifth sub-pixel SP15, and the eighth sub-pixel SP18 can be selectively turned on.

[0128] The third sub-connection line 1130 can be connected to the third sub-pixel SP13, the sixth sub-pixel SP16, and the ninth sub-pixel SP19. Data output signals can be selectively transmitted to the third sub-pixel SP13, the sixth sub-pixel SP16, and the ninth sub-pixel SP19. Blue data signals can also be selectively transmitted to the third sub-pixel SP13, the sixth sub-pixel SP16, and the ninth sub-pixel SP19. For example, when the seventh switching transistor ST17 is turned on, a first blue data signal can be transmitted to the third sub-pixel SP13. Optionally, when the eighth switching transistor ST18 is turned on, a second blue data signal can be transmitted to the sixth sub-pixel SP16. Optionally, when the ninth switching transistor ST19 is turned on, a third blue data signal can be transmitted to the ninth sub-pixel SP19. In this embodiment, the third sub-pixel SP13, the sixth sub-pixel SP16, and the ninth sub-pixel SP19 can be selectively turned on.

[0129] The first sub-demultiplexer circuit SDC11 may include a first switching transistor ST11, a fourth switching transistor ST14, and a seventh switching transistor ST17. The second sub-demultiplexer circuit SDC12 may include a second switching transistor ST12, a fifth switching transistor ST15, and an eighth switching transistor ST18. The third sub-demultiplexer circuit SDC13 may include a third switching transistor ST13, a sixth switching transistor ST16, and a ninth switching transistor ST19.

[0130] The first switching transistor ST11, the fourth switching transistor ST14, and the seventh switching transistor ST17 can be connected to the first transmission line CLc. The first transmission line CLc can transmit the first gate-on signal GO11 to the first sub-demultiplexer circuit SDC11. For example, the first transmission line CLc can transmit the first gate-on signal GO11 to the first switching transistor ST11, the fourth switching transistor ST14, and the seventh switching transistor ST17. Therefore, the first data output signal DO11 can be transmitted to the first pixel P11.

[0131] The second switching transistor ST12, the fifth switching transistor ST15, and the eighth switching transistor ST18 can be connected to the second transmission line CLd. The second transmission line CLd can transmit the second gate-on signal GO12 to the second sub-demultiplexer circuit SDC12. For example, the second transmission line CLd can transmit the second gate-on signal GO12 to the second switching transistor ST12, the fifth switching transistor ST15, and the eighth switching transistor ST18. Therefore, the second data output signal DO12 can be transmitted to the second pixel P12.

[0132] The third switching transistor ST13, the sixth switching transistor ST16, and the ninth switching transistor ST19 can be connected to the third transmission line CLe. The third transmission line CLe can transmit the third gate-on signal GO13 to the third sub-demultiplexer circuit SDC13. For example, the third transmission line CLe can transmit the third gate-on signal GO13 to the third switching transistor ST13, the sixth switching transistor ST16, and the ninth switching transistor ST19. Therefore, the third data output signal DO13 can be transmitted to the third pixel P13.

[0133] Figure 11 This is a view showing the distance between the demultiplexer circuit and the sub-demultiplexer circuit.

[0134] Reference Figure 9 and Figure 11The display device may further include a fourth pixel P21, a fifth pixel P22, a sixth pixel P23, a second demultiplexer circuit DC21, and a connecting line 2100. The second demultiplexer circuit DC21 may include a fourth sub-demultiplexer circuit SDC21, a fifth sub-demultiplexer circuit SDC22, and a sixth sub-demultiplexer circuit SDC23. However, in embodiments, other numbers of sub-demultiplexer circuits may be included in the demultiplexer circuits DC11 and DC21. For example, demultiplexer circuits DC11 and DC21 may also include four or more sub-demultiplexer circuits.

[0135] In this embodiment, the first sub-demultiplexer circuit SDC11 and the second sub-demultiplexer circuit SDC12 can be separated from each other by a third distance D3. The second sub-demultiplexer circuit SDC12 and the third sub-demultiplexer circuit SDC13 can be separated from each other by a fourth distance D4. The third distance D3 and the fourth distance D4 can be different from each other. For example, each of the third distance D3 and the fourth distance D4 can be determined based on the number of light-emitting stages and gate stages disposed between the sub-demultiplexer circuits SDC11, SDC12 and SDC13.

[0136] In this embodiment, the fourth sub-demultiplexer circuit SDC21 and the fifth sub-demultiplexer circuit SDC22 can be separated from each other by a fifth distance D5. The fifth sub-demultiplexer circuit SDC22 and the sixth sub-demultiplexer circuit SDC23 can be separated from each other by a sixth distance D6. The fifth distance D5 and the sixth distance D6 can be different from each other. For example, each of the fifth distance D5 and the sixth distance D6 can be determined based on the number of light-emitting stages and gate stages disposed between the sub-demultiplexer circuits SDC21, SDC22 and SDC23.

[0137] Furthermore, adjacent demultiplexer circuits DC11 and DC21 can be separated from each other by a seventh distance D7. Therefore, the third sub-demultiplexer circuit SDC13 and the fourth sub-demultiplexer circuit SDC21 can be separated from each other by a seventh distance D7.

[0138] In the embodiments, at least a portion of the third to seventh distances D3, D4, D5, D6, and D7 may be different. In other words, the third to seventh distances D3, D4, D5, D6, and D7 can be determined based on the number of light-emitting and gate stages disposed between the sub-demultiplexer circuits SDC11, SDC12, SDC13, SDC21, SDC22, and SDC23.

[0139] Figure 12 This is a view showing the distance between the demultiplexer circuit and the sub-demultiplexer circuits. Besides the second demultiplexer circuit DC21, which includes two sub-demultiplexer circuits SDC21 and SDC22, Figure 12 Can be withFigure 11 They are essentially the same. Therefore, descriptions of duplicate components will be omitted.

[0140] Reference Figure 12 , Figure 12 The second demultiplexer circuit DC21 may include two sub-demultiplexer circuits SDC21 and SDC22. Therefore, demultiplexer circuits DC11 and DC21 may include different numbers of sub-demultiplexer circuits. Even in the above case, the third distance D3, fourth distance D4, fifth distance D5, and seventh distance D7 can be determined based on the number of light-emitting and gate levels disposed between the sub-demultiplexer circuits SDC11, SDC12, SDC13, SDC21, and SDC22.

[0141] Although the inventive concept has been described with reference to embodiments, it will be apparent to those skilled in the art that various modifications and variations may be made without departing from the scope and field of the appended claims.

Claims

1. A display device, the display device comprising: The substrate includes a circular display area and a non-display area surrounding the display area; Multiple pixels, including a first pixel and a second pixel disposed in the display area of ​​the substrate; A first sub-demultiplexer circuit is connected to the first pixel and disposed in the non-display area to transmit a first data output signal to the first pixel; A second sub-demultiplexer circuit is connected to the second pixel and is disposed in the non-display area to transmit the second data output signal to the second pixel; A first connecting line is connected to the first sub-demultiplexer circuit and the second sub-demultiplexer circuit, and is disposed in the non-display area to transmit a first data input signal to the first sub-demultiplexer circuit and a second data input signal to the second sub-demultiplexer circuit. as well as Multiple gate stages are connected to the multiple pixels and disposed in the non-display area to transmit gate signals to the multiple pixels. Some of the gate levels are arranged between the first sub-demultiplexer circuit and the second sub-demultiplexer circuit along the arrangement direction of the first sub-demultiplexer circuit and the second sub-demultiplexer circuit.

2. The display device according to claim 1, wherein, The first pixel is set in the first pixel column, and the second pixel is set in the second pixel column.

3. The display device according to claim 1, further comprising: Multiple light-emitting levels are connected to the multiple pixels and disposed in the non-display area to transmit light-emitting signals to the multiple pixels. Some of the multiple light-emitting levels are disposed between the first sub-demultiplexer circuit and the second sub-demultiplexer circuit.

4. The display device according to claim 1, wherein, The first pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; the second pixel includes a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel; and the first connecting line includes a first sub-connecting line, a second sub-connecting line, and a third sub-connecting line.

5. The display device according to claim 4, wherein, The first sub-connection line is connected to the first sub-pixel and the fourth sub-pixel and transmits the data output signal to the first sub-pixel and the fourth sub-pixel; the second sub-connection line is connected to the second sub-pixel and the fifth sub-pixel and transmits the data output signal to the second sub-pixel and the fifth sub-pixel; and the third sub-connection line is connected to the third sub-pixel and the sixth sub-pixel and transmits the data output signal to the third sub-pixel and the sixth sub-pixel.

6. The display device according to claim 4, wherein, The first sub-connection line is connected to the first switching transistor connected to the first sub-pixel and the second switching transistor connected to the fourth sub-pixel; the second sub-connection line is connected to the third switching transistor connected to the second sub-pixel and the fourth switching transistor connected to the fifth sub-pixel; and the third sub-connection line is connected to the fifth switching transistor connected to the third sub-pixel and the sixth switching transistor connected to the sixth sub-pixel.

7. The display device according to claim 6, further comprising: A first transmission line is used to transmit a first gate-on signal to the first switching transistor, the third switching transistor, and the fifth switching transistor.

8. The display device according to claim 7, further comprising: The second transmission line is used to transmit the second gate turn-on signal to the second switching transistor, the fourth switching transistor, and the sixth switching transistor.

9. The display device according to claim 8, wherein, The first gate turn-on signal and the second gate turn-on signal are selectively transmitted.

10. The display device according to claim 1, wherein, The plurality of pixels also includes a third pixel and a fourth pixel disposed in the display area of ​​the substrate. The display device further includes: A third sub-demultiplexer circuit is connected to the third pixel and disposed in the non-display area to transmit a third data output signal to the third pixel; A fourth sub-demultiplexer circuit, connected to the fourth pixel and disposed in the non-display area, transmits a fourth data output signal to the fourth pixel; and A second connecting line, connected to the third and fourth sub-demultiplexer circuits, and disposed in the non-display area, transmits a third data input signal to the third sub-demultiplexer circuit and a fourth data input signal to the fourth sub-demultiplexer circuit. In this configuration, another portion of the gate levels is disposed between the second sub-demultiplexer circuit and the third sub-demultiplexer circuit, and yet another portion of the gate levels is disposed between the third sub-demultiplexer circuit and the fourth sub-demultiplexer circuit.

11. The display device according to claim 10, wherein, The first pixel is set in the first pixel column, the second pixel is set in the second pixel column, the third pixel is set in the third pixel column, and the fourth pixel is set in the fourth pixel column.

12. The display device according to claim 10, wherein, The distance between the first sub-demultiplexer circuit and the second sub-demultiplexer circuit connected to the first connection line is different from the distance between the third sub-demultiplexer circuit and the fourth sub-demultiplexer circuit connected to the second connection line.

13. The display device according to claim 10, further comprising: Multiple light-emitting levels are connected to the multiple pixels to transmit light-emitting signals to the multiple pixels. Among them, some of the multiple light-emitting levels are disposed between the first sub-demultiplexer circuit and the second sub-demultiplexer circuit, another portion of the multiple light-emitting levels are disposed between the second sub-demultiplexer circuit and the third sub-demultiplexer circuit, and yet another portion of the multiple light-emitting levels are disposed between the third sub-demultiplexer circuit and the fourth sub-demultiplexer circuit.

14. The display device according to claim 10, wherein, The third pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel; the fourth pixel includes a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel; and the second connecting line includes a first sub-connecting line, a second sub-connecting line, and a third sub-connecting line.

15. The display device according to claim 14, wherein, The first sub-connection line is connected to the first sub-pixel and the fourth sub-pixel and transmits the data output signal to the first sub-pixel and the fourth sub-pixel; the second sub-connection line is connected to the second sub-pixel and the fifth sub-pixel and transmits the data output signal to the second sub-pixel and the fifth sub-pixel; and the third sub-connection line is connected to the third sub-pixel and the sixth sub-pixel and transmits the data output signal to the third sub-pixel and the sixth sub-pixel.

16. The display device according to claim 14, wherein, The first sub-connection line is connected to the first switching transistor connected to the first sub-pixel and the second switching transistor connected to the fourth sub-pixel; the second sub-connection line is connected to the third switching transistor connected to the second sub-pixel and the fourth switching transistor connected to the fifth sub-pixel; and the third sub-connection line is connected to the fifth switching transistor connected to the third sub-pixel and the sixth switching transistor connected to the sixth sub-pixel.

17. The display device according to claim 16, further comprising: A first transmission line is used to transmit a first gate-on signal to the first switching transistor, the third switching transistor, and the fifth switching transistor.

18. The display device according to claim 17, further comprising: The second transmission line is used to transmit the second gate turn-on signal to the second switching transistor, the fourth switching transistor, and the sixth switching transistor.

19. The display device according to claim 18, wherein, The first gate turn-on signal and the second gate turn-on signal are selectively transmitted.

20. A display device, the display device comprising: The substrate includes a circular display area and a non-display area surrounding the display area; The first pixel to the nth pixel are disposed in the display area of ​​the substrate, wherein n is a natural number of 3 or greater; The first sub-demultiplexer circuit to the nth sub-demultiplexer circuit are respectively connected to the first pixel to the nth pixel and disposed in the non-display area, so as to transmit the first data output signal to the nth data output signal to the first pixel to the nth pixel respectively; A connecting line, connected to the first sub-demultiplexer circuit to the nth sub-demultiplexer circuit, and disposed in the non-display area, to transmit the first data input signal to the nth data input signal to the first sub-demultiplexer circuit to the nth sub-demultiplexer circuit, respectively; and Multiple gate stages are respectively connected to the first pixel to the nth pixel, and are arranged between the first sub-demultiplexer circuit and the nth sub-demultiplexer circuit along the arrangement direction of the first sub-demultiplexer circuit to transmit gate signals to the first pixel to the nth pixel respectively.

21. The display device according to claim 20, wherein, The first pixel to the nth pixel are respectively set in the first pixel column to the nth pixel column.

22. The display device according to claim 20, further comprising: Multiple light-emitting stages are disposed between the first sub-demultiplexer circuit and the nth sub-demultiplexer circuit.

23. The display device according to claim 20, wherein, Each pixel from the first pixel to the nth pixel includes a plurality of sub-pixels, and the connecting line includes a plurality of sub-connecting lines having a number corresponding to the number of the sub-pixels of each pixel.

Images