Display device and method of driving a display device

Abstract

The present invention relates to a display device and a method of driving the display device. The display device includes a display panel for displaying an image, a panel driver for driving the display panel, and a controller for controlling driving of the panel driver. The controller includes a first circuit for receiving frame data in synchronization with a vertical synchronization signal that determines a start point of a frame having an active period and a variable blank period during the active period, for shifting a position of the frame data to generate shifted data in response to a shift start signal, and for providing the shifted data to the panel driver. A number of the active periods of the vertical synchronization signal included in one period of the shift start signal is different from a number of the active periods of the vertical synchronization signal included in another period of the shift start signal.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate generally to display apparatuses, and more particularly, to a display apparatus capable of preventing image sticking and a method of driving the same. BACKGROUND

[0002] As display apparatuses, organic light emitting display apparatuses, liquid crystal display apparatuses, plasma display apparatuses, etc. are being used.

[0003] Among them, since the organic light emitting display apparatus adopts a self-emission element that allows an organic light emitting layer to emit light using recombination of electrons and holes, the organic light emitting display apparatus has advantages such as high brightness, ultra-thin thickness, etc.

[0004] The above information disclosed in this Background section is only for the purpose of understanding the background of the present inventive concepts, and therefore, it can contain information that does not constitute prior art. SUMMARY

[0005] The applicant recognized that when an organic light emitting display apparatus is driven for a long time in the same pattern, one or more light emitting elements can be pre-burned due to an increase in current stress, and thus, image sticking occurs in an area where a fixed pattern or logo is displayed for a long time.

[0006] The display apparatus and the illustrative method of driving the same constructed according to the principles and embodiments of the present application can effectively prevent image sticking and improve image sticking. For example, image shifting can be employed in which a display image is periodically shifted in a display apparatus supporting a variable frequency mode.

[0007] Additional features of the inventive concepts will be set forth in the description that follows, and in part will be apparent from the description, or can be learned by practice of the inventive concepts.

[0008] According to an aspect of the present application, a display apparatus includes a display panel for displaying an image, a panel driver for driving the display panel, and a controller for controlling driving of the panel driver. The controller includes a first circuit for receiving frame data in synchronization with a vertical synchronization signal that determines a start time point of a frame having an active period and a variable blank period during an active period, for shifting a position of the frame data to generate shifted data in response to a shift start signal, and for providing the shifted data to the panel driver. A number of active periods of the vertical synchronization signal included in one period of the shift start signal is different from a number of active periods of the vertical synchronization signal included in another period of the shift start signal.

[0009] The controller can further include a second circuit for counting the variable blank period based on the reference clock to generate a count value of the frame, for comparing an accumulated value obtained by accumulating the count value with a predetermined reference value, and for determining a point in time of activation of the shift start signal according to a result of the comparison.

[0010] The second circuit can include a shift determiner including a counter for counting a number of occurrences of the reference clock during the variable blank period to output a first count value, and a calculator for adding a pre-stored second count value of the active period to the first count value to calculate the count value.

[0011] The active period can have a substantially constant duration per frame, and the variable blank period can have a variable duration.

[0012] The controller can be configured to receive frame data in response to a data enable signal, and the counter can be configured to count a non-active period of the data enable signal to generate the first count value.

[0013] The controller can further include a first memory in which the second count value is stored.

[0014] The shift determiner can further include an adder for adding the count value to a previous accumulated value to output the accumulated value, and a comparator for comparing the accumulated value with the reference value, and for outputting a shift control signal according to a result of the comparison.

[0015] The controller can further include a second memory configured to receive the accumulated value output from the adder, and to update the previous accumulated value to the accumulated value.

[0016] The shift determiner can further include a signal generator for receiving the shift control signal to control the point in time of activation of the shift start signal, and for providing the shift start signal to the first circuit.

[0017] The shift determiner can further include a preliminary comparator for comparing the count value with the reference value.

[0018] The preliminary comparator can be configured to provide the count value to the adder when the count value is less than the reference value, and to output a pre-shift control signal when the count value is greater than the reference value.

[0019] The shift determiner can further include a signal generator for receiving the pre-shift control signal to control the point in time of activation of the shift start signal, and for providing the shift start signal to the first circuit.

[0020] The display panel can include a plurality of pixels each including a light emitting element.

[0021] The first circuit can include an image processor including a shift processor to determine a pixel shift amount based on shift setting information and to generate initial shift data obtained by shifting frame data according to the pixel shift amount and a shift direction, and a data compensator to compensate the initial shift data to generate shift data.

[0022] The data compensator can include a region setter to set a first compensation region and a second compensation region according to the pixel shift amount and the shift direction, a first sub compensator to scale up first sub shift data corresponding to the first compensation region among the initial shift data to generate first compensation data, and a second sub compensator to scale down second sub shift data corresponding to the second compensation region among the initial shift data to generate second compensation data.

[0023] According to an aspect of the present application, a method of driving a display apparatus includes receiving frame data in synchronization with a vertical synchronization signal that determines a start time point of a frame having an active period and a variable blank period during an active period, setting a period of a shift start signal based on the variable blank period, shifting the frame data in response to the shift start signal to generate shift data, converting the shift data into a data signal, and displaying an image using the data signal. A number of active periods of the vertical synchronization signal included in one period of the shift start signal is different from a number of active periods of the vertical synchronization signal included in another period of the shift start signal.

[0024] The step of setting the period of the shift start signal can include the steps of counting the variable blank period based on a reference clock to generate a count value of the frame, comparing an accumulated value obtained by accumulating the count value with a predetermined reference value, and determining an activation time point of the shift start signal according to a result of the comparison.

[0025] The step of determining the activation time point of the shift start signal can include the steps of receiving the count value of the frame, adding the count value to a previously accumulated value stored in advance to generate an accumulated value, comparing the accumulated value with a reference value to output a shift control signal according to a result of the comparison, and activating the shift start signal in response to the shift control signal.

[0026] The step of generating the count value of the frame can include the steps of counting a number of occurrences of the reference clock during the variable blank period to output a first count value, and adding a second count value of the active period stored in advance to the first count value to calculate the count value.

[0027] The active period can have a substantially constant duration per frame, and the variable blank period can have a variable duration.

[0028] In the frame, the variable blank period can be generated after the active period.

[0029] The step of receiving the frame data can include receiving the frame data in response to a data enable signal, and the step of outputting the first count value can include counting non-active periods of the data enable signal to generate the first count value.

[0030] The method can further include the steps of: receiving a cumulative value; and updating the previous cumulative value to the cumulative value.

[0031] The method can further include the step of comparing the count value with a reference value before generating the cumulative value.

[0032] The step of comparing the count value with the reference value can include the steps of: when the count value is less than the reference value, adding the count value to the previous cumulative value; and when the count value is greater than the reference value, outputting a preshift control signal.

[0033] The method can further include the step of activating a shift start signal in response to the preshift control signal.

[0034] The step of generating the shift data can include the steps of: determining a pixel shift amount based on shift setting information to generate initial shift data obtained by shifting the frame data according to the pixel shift amount and a shift direction; and compensating the initial shift data to generate the shift data.

[0035] The step of compensating the initial shift data can include the steps of: setting a first compensation region and a second compensation region according to the pixel shift amount and the shift direction; upscaling first sub-shift data corresponding to the first compensation region among the initial shift data to generate first compensation data; and downscaling second sub-shift data corresponding to the second compensation region among the initial shift data to generate second compensation data.

[0036] It is to be understood that both the foregoing general description and the following detailed description are explanatory and interpretative and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0037] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate illustrative embodiments of the application and together with the description serve to explain the principles of the application.

[0038] Figure 1is a block diagram of an embodiment of a display device according to the principles of the present application.

[0039] Figure 2 is Figure 1 a block diagram of an embodiment of a display panel of

[0040] Figure 3 is a waveform diagram showing illustrative frame data input to Figure 2 a display device in a variable frequency mode.

[0041] Figure 4 is Figure 1 a plan view of an embodiment of a display panel of

[0042] Figure 5 is Figure 2 a block diagram of an embodiment of a controller of

[0043] Figure 6 is Figure 5 a block diagram of an embodiment of a shift determiner of

[0044] Figure 7A is an illustrative waveform diagram showing the relationship between a vertical sync signal and a shift start signal as an input signal and an output signal, respectively, of a signal generator of Figure 6

[0045] Figure 7B is an illustrative waveform diagram showing the activation points of a shift start signal and a shift control signal as an output signal and an input signal, respectively, of a signal generator of Figure 6

[0046] Figure 8 is a block diagram of an embodiment of an image processor of Figure 5

[0047] Figure 9A and Figure 9B are views of an embodiment of a shift direction of an image according to the principles of the present application.

[0048] Figure 10 is a view showing an embodiment of pixel shifting according to an image shifting operation by an image processor of Figure 5

[0049] Figure 11 is an illustrative waveform diagram showing a refresh operation of a display device operating in an ultra-low frequency mode.

[0050] Figure 12 is Figure 5 a block diagram of another embodiment of a shift determiner of

[0051] Figure 13 is a waveform diagram showing illustrative frame data input to​​​​Figure 12 An illustrative waveform diagram of the output signal of the signal generator and the activation time points of the shift start signal and the pre-shift control signal of the input signal. DETAILED DESCRIPTION

[0052] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, the terms "embodiment" and "implementation" are interchangeable on a non-limiting example of an apparatus or method employing one or more of the inventive concepts disclosed herein. It will be apparent, however, that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring the various embodiments. In addition, various embodiments can be different but not necessarily mutually exclusive. For example, specific shapes, configurations, and characteristics of an embodiment can be used in another embodiment or implemented in another embodiment without departing from the inventive concepts.

[0053] Unless otherwise specified, the illustrated embodiments are to be understood as providing illustrative features of various details of some ways in which the inventive concepts can be implemented in practice. Accordingly, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects of various embodiments (hereinafter referred to as "elements"), either individually or collectively, can be combined, separated, interchanged, and / or rearranged without departing from the inventive concepts.

[0054] The use of cross-hatching and / or shading in the drawings is generally provided to make the boundaries and / or regions of the particular elements being presented more clearly for ease of understanding. As a result, no inference should be drawn from the use of cross-hatching and / or shading that a particular material, material property, dimension, ratio, or characteristic, etc., is associated with any particular element. In addition, for purposes of the description hereinafter, the

[0055] When an element or layer is referred to as being “on”, “connected to”, or “coupled to” another element or layer, it can be directly on, connected, or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element or layer is referred to as being “directly on”, “directly connected to”, or “directly coupled to” another element or layer, there are no intervening elements or layers present. In this regard, the term “connected” can refer to physical, electrical, and / or fluidic connectivity as can be appreciated by one skilled in the art in light of the disclosure. Further, the D1 axis, the D2 axis, and the D3 axis are not limited to three axes of a rectangular coordinate system such as the x-axis, the y-axis, and the z-axis, and can be interpreted in a broader sense. For example, the D1 axis, the D2 axis, and the D3 axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purpose of the present disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted to be any one of X, Y, Z, or an arbitrary combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0056] Although the terms “first”, “second”, etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0057] Spatially relative terms, such as “beneath”, “below”, “lower”, “under”, “above”, “upper”, “on”, “over”, “side” (as in “sidewall”), and the like, can be used herein for ease of description to describe one element’s or feature’s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. Well-known functions or constructions can not be described in detail for brevity.

[0058] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "having," "has," "with," or variants thereof are used in either the detailed description or the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." It should also be noted that, as used herein, the terms "substantially," "approximately," and other like terms are used as terms of approximation and not as terms of degree, and are employed herein to account for inherent variations in measurement, calculation, and / or other sources.

[0059] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as terms of art, which are defined in commonly used dictionaries are to take one of their ordinary meanings to one of skill in the relevant arts and are not to be interpreted by the dictionary definitions that are used in a manner that would tend to cause confusion between terms that in fact have had a well-established meaning in the relevant technology.

[0060] Figure 1 is a block diagram of an embodiment of an electronic device ED configured according to the principles of the present invention. Figure 2 is Figure 1 a block diagram of an embodiment of a display device DD. Figure 3 is a waveform diagram illustrating illustrative frame data input to Figure 2 a display device DD in a variable frequency mode. Figure 4 is Figure 1 a plan view of an embodiment of a display panel DP.

[0061] Referring to Figure 1 , the electronic device ED can include a main processor 10 and a display device DD. The display device DD can be a device configured to display an image, and the main processor 10 can control driving of the display device DD. As an example, the main processor 10 can be a graphics processing unit (GPU). The main processor 10 can apply an input image signal I_DAT and an input control signal I_CS to the display device DD to control a display operation of the display device DD.

[0062] The display device DD can include a display panel DP, a controller 100, and a panel driver 200. The display device DD can be a device that is activated in response to an electrical signal. The display device DD can be applied to various electronic products, such as a tablet computer, a notebook computer, a computer, a television, a smart phone, etc.

[0063] The controller 100 can receive an input image signal I_DAT and an input control signal I_CS from the main processor 10. The input image signal I_DAT can include a red image signal, a green image signal, and a blue image signal. The controller 100 can convert a data format of the input image signal I_DAT to generate image data RGB. The generated image data RGB can be provided to the panel driver 200. The input control signal I_CS can include a vertical synchronization signal Vsync (refer to Figure 3 ), a data enable signal DE (refer to Figure 3 ), a main clock signal, etc., however, embodiments should not be limited thereto or thereby. The controller 100 can generate a panel control signal based on the input control signal I_CS.

[0064] The controller 100 can operate in a variable frequency mode. Figure 3 is a waveform diagram illustrating frame data input to the display apparatus DD in the variable frequency mode. Figure 2 Referring to Figure 1 and Figure 3 , the main processor 10 can change durations of the blank periods BP1 to BP6 in each frame, and can apply the input image signal I_DAT to the controller 100 at a variable frame rate. The controller 100 operating in the variable frequency mode can provide the image data RGB to the panel driver 200 at a variable frame rate in synchronization, and thus can control the panel driver 200 so that images are displayed at a variable frame rate.

[0065] As shown in Figure 3 , a speed at which the main processor 10 renders the frame data FD1 to FD7 (i.e., an internal processing speed) can not be substantially constant. The rendering speed can vary according to the frame data FD1 to FD7. For example, the main processor 10 can render the first frame data FD1, the second frame data FD2, the fourth frame data FD4, the sixth frame data FD6, and the seventh frame data FD7 at a frequency of about 144 Hz, and can render the third frame data FD3 and the fifth frame data FD5 at a frequency of about 72 Hz. A time point at which the main processor 10 transmits the rendered frame data FD1 to FD7 to the controller 100 can coincide with or can be a time point at which rendering of the corresponding frame data FD1 to FD7 is completed.

[0066] In a case where the third frame data FD3 is rendered at a frequency of about 72 Hz, the main processor 10 can supply the second frame data FD2 to the controller 100 at a frequency of about 72 Hz. The main processor 10 can supply the second frame data FD2 to the controller 100 during the second active period AP2 of the second frame FP2, and the second blank period BP2 of the second frame FP2 can be maintained until rendering of the third frame data FD3 is completed. That is, the main processor 10 can supply the second frame data FD2 at a second frame rate in the second frame FP2. As an example, the first frame rate can be about 144 Hz, and the second frame rate can be about 72 Hz.

[0067] In a case where the third frame data FD3 is rendered at a frequency of about 72 Hz, the main processor 10 can supply the second frame data FD2 to the controller 100 at a frequency of about 72 Hz. The main processor 10 can supply the second frame data FD2 to the controller 100 during the second active period AP2 of the second frame FP2, and the second blank period BP2 of the second frame FP2 can be maintained until rendering of the third frame data FD3 is completed. That is, the main processor 10 can supply the second frame data FD2 at a second frame rate in the second frame FP2. As an example, the first frame rate can be about 144 Hz, and the second frame rate can be about 72 Hz.

[0068] In the illustrated embodiment, the duration of the first active period AP1 of the first frame FP1 and the duration of the second active period AP2 of the second frame FP2 can be substantially the same as each other. That is, the active periods AP1 to AP7 can have a substantially constant duration in each frame regardless of the frame rate. However, the duration of the first blank period BP1 of the first frame FP1 and the duration of the second blank period BP2 of the second frame FP2 can be different from each other. As an example, the duration of the second blank period BP2 can be greater than the duration of the first blank period BP1. That is, the blank periods BP1 to BP6 in each frame FP1 to FP6 can have different durations according to the frame rate. When the frame rate decreases, the duration of the corresponding blank period can increase. As described above, the pattern in which the durations of the blank periods BP1 to BP6 vary according to the frame rate is referred to as a variable frequency pattern, and the blank periods BP1 to BP6 having different durations from each other are referred to as variable blank periods. In each frame FP1 to FP6, each of the variable blank periods BP1 to BP6 can occur after a corresponding one of the active periods AP1 to AP6. In the variable frequency pattern, the main processor 10 can supply the input image signal I_DAT to the display device DD at irregular periods or at an irregular frequency.

[0069] The active periods AP1 to AP6 of the frames FP1 to FP6 are defined as active periods of the data enable signal DE, and the blank periods BP1 to BP6 of the frames FP1 to FP6 are defined as non-active periods of the data enable signal DE. In the variable frequency mode, the duration of the active periods of the data enable signal DE can be substantially constant regardless of the frame rate. The duration of the non-active periods of the data enable signal DE can vary depending on the frame rate. The vertical synchronization signal Vsync can be activated at the start time point of each frame FP1 to FP6. Depending on the frame rate, the active period of the vertical synchronization signal Vsync can also be variable.

[0070] Referring to Figure 2 The panel driver 200 can include a scan driver 210 and a data driver 220. The panel control signals can include a scan control signal SCS for controlling driving of the scan driver 210 and a data control signal DCS for controlling driving of the data driver 220.

[0071] The scan driver 210 can receive the scan control signal SCS from the controller 100. The scan control signal SCS can include a vertical clock signal and a vertical start signal that starts operation of the scan driver 210. The scan driver 210 can generate a plurality of scan signals SS (refer to FIG. 2) and can sequentially output the scan signals SS to the scan lines described below. In addition, the scan driver 210 can generate a plurality of emission control signals in response to the scan control signal SCS and can output the emission control signals to a plurality of emission control lines EML1 to EMLn described below. Figure 1

[0072] According to the illustrated embodiment, the scan driver 210 can include an initialization scan driver, a compensation scan driver, a write scan driver, and a black scan driver. The initialization scan driver outputs an initialization scan signal to an initialization scan line GIL1 to GILn of the display panel DP, and the compensation scan driver outputs a compensation scan signal to a compensation scan line GWL1 to GWLn of the display panel DP. The initialization scan driver and the compensation scan driver can be configured as independent circuits, respectively, or can be integrated into one circuit. When the initialization scan driver and the compensation scan driver are integrated into one circuit, the initialization scan signal can be defined as a previous scan signal, and the compensation scan signal can be defined as a current scan signal.

[0073] ​The write scan driver outputs a write scan signal to the write scan lines GCL1 to GCLn of the display panel DP, and the black scan driver outputs a black scan signal to the black scan lines GBL1 to GBLn of the display panel DP. The write scan driver and the black scan driver can be configured as independent circuits, or can be integrated into one circuit. When the write scan driver and the black scan driver are integrated into one circuit, the write scan signal can be defined as a current scan signal, and the black scan signal can be defined as a next scan signal.

[0074] In addition, Figure 2 The structure in which the scan lines and the emission control lines are connected to one scan driver 210 is illustrated, however, the embodiments should not be limited thereto or thereby. According to another embodiment of the present application, a scan driver 210 connected to the scan lines and an emission driver connected to the emission control lines can be provided as separate components.

[0075] The scan driver 210 can be built-in in the display panel DP. That is, the scan driver 210 can be formed in the display panel DP by a thin film process of forming the pixels PX11 to PXnm of the display panel DP.

[0076] The data driver 220 receives the data control signal DCS and the image data RGB from the controller 100. The data driver 220 converts the image data RGB into a data signal DS (refer to Figure 1 ), and outputs the data signal DS to a plurality of data lines DL1 to DLm described below. The data signal DS can be an analog voltage corresponding to a gray value of the image data RGB.

[0077] The display apparatus DD further includes a voltage generator for generating a voltage required for an operation of the display apparatus DD. In the illustrated embodiment, the voltage generator can generate a first power voltage ELVDD, a second power voltage ELVSS, and an initialization voltage Vint.

[0078] The display panel DP can include components that substantially generate an image IM (refer to Figure 4 ). As an example, the display panel DP can be an organic light emitting display panel. The display panel DP includes scan lines, the data lines DL1 to DLm, and the pixels PX11 to PXnm. The scan lines extend in the first direction DR1 and are spaced apart from each other in the second direction DR2. The data lines DL1 to DLm extend in the second direction DR2 and are spaced apart from each other in the first direction DR1. As an example, the scan lines include initialization scan lines GIL1 to GILn, compensation scan lines GWL1 to GWLn, write scan lines GCL1 to GCLn, and black scan lines GBL1 to GBLn.

[0079] Each of the pixels PX11 to PXnm is connected to a corresponding data line and a corresponding scan line. For example, a first pixel PX11 among the pixels PX11 to PXnm is connected to a first data line DL1, a first initialization scan line GIL1, a first compensation scan line GWL1, a first write scan line GCL1, and a first black scan line GBL1. A last pixel PXnm among the pixels PX11 to PXnm is connected to an mth data line DLm, an nth initialization scan line GILn, an nth compensation scan line GWLn, an nth write scan line GCLn, and an nth black scan line GBLn. That is, according to an example, each of the pixels PX11 to PXnm can be connected to four types of scan lines. However, the types of scan lines connected to each of the pixels PX11 to PXnm should not be limited or restricted thereby. That is, two or three types of scan lines can be connected to each of the pixels PX11 to PXnm.

[0080] The first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage Vint can be supplied to the display panel DP. Each of the pixels PX11 to PXnm can receive the first power supply voltage ELVDD, the second power supply voltage ELVSS, and the initialization voltage Vint.

[0081] Each of the pixels PX11 to PXnm includes a light emitting element and a pixel circuit unit that controls emission of the light emitting element. As an example, the light emitting element can be an organic light emitting diode.

[0082] Reference Figure 4 The display panel DP includes a display area DA through which the image IM is displayed and a non-display area NDA adjacent to the display area DA. The display area DA is an area through which the image IM is displayed, and the non-display area NDA is a bezel area through which the image IM is not displayed. Figure 4 A structure in which the non-display area NDA is disposed to surround the display area DA is illustrated, however, embodiments should not be limited or restricted thereby. The non-display area NDA can be adjacent to at least one side of the display area DA.

[0083] The image IM can be displayed through the display area DA. The image IM can include a first image IM1 and a second image IM2. The first image IM1 can be an image displayed at a fixed position at a certain gray level for a predetermined time or longer. The first image IM1 can be a still image, and the second image can be a video image or a still image. For example, the first image IM1 can include a broadcaster logo, a caption, a date, a time, etc. The first image IM1 can include a title of a program. Hereinafter, for convenience of explanation, all various images displayed at a fixed position at a certain gray level for a predetermined time or longer will be referred to as the first image IM1. The second image IM2 can be an image displayed through other areas of the display area DA than the area through which the first image IM1 is displayed.

[0084] An organic light emitting diode includes a plurality of electrodes and a light emitting layer disposed between the electrodes and including an organic material. When an area of the display area DA through which the first image IM1 is displayed is referred to as a first area, pixels in the first area can be burned out due to the first image IM1 being displayed through the same pixels for a long time. Accordingly, when an image different from the first image IM1 is displayed through the first area after the first image IM1 is displayed through the first area, the first image IM1 can remain in the first area, which is not intended, and this persistent first image IM1 phenomenon is referred to as "image sticking". The controller 100 can periodically perform an image shift operation to compensate for the image sticking.

[0085] Figure 5 is a block diagram of an embodiment of the controller 100 of Figure 2 and Figure 6 is a block diagram of an embodiment of the shift determiner 120 of Figure 5 Figure 7A is an illustrative waveform diagram showing a relationship between a vertical synchronization signal Vsync and a shift start signal S_STV, which are respectively an input signal and an output signal of the signal generator 125 of Figure 6 and Figure 7B is an illustrative waveform diagram showing activation points of a shift start signal S_STV and a shift control signal S_CS, which are respectively an output signal and an input signal of the signal generator 125 of Figure 6

[0086] Referring to Figure 3 and Figure 5 , the controller 100 can include a first circuit in the form of the image processor 110 and a second circuit in the form of the shift determiner 120. The image processor 110 can receive an input image signal I_DAT from the main processor 10 of Figure 1 . For example, referring to Figure 3 ​​The input image signal I_DAT can include frame data FD1 to FD6 received in each of frames FP1 to FP6. Each of frames FP1 to FP6 can include a corresponding active period in active periods AP1 to AP6 and a corresponding variable blank period in variable blank periods BP1 to BP6.

[0087] Image processor 110 can convert the input image signal I_DAT into image data RGB, and can provide the image data RGB to... Figure 1 The panel driver 200. As an example, the image processor 110 can perform an image shifting operation in response to a shift start signal S_STV. The image processor 110 can shift frame data FD1 to FD6 over a period of several frames starting from the time point when the shift start signal S_STV is activated, and can output the shifted frame data FD1 to FD6 as image data RGB. The image processor 110 can shift the display panel DP (reference) over a period of several frames. Figure 2 The frame data FD1 to FD6 are shifted by at least one pixel in the first direction DR1 and the second direction DR2 or in a third direction different from the first direction DR1 and the second direction DR2.

[0088] The shift determiner 120 can count the durations of the variable blank periods BP1 to BP6 in each frame FP1 to FP6 and determine the activation time of the shift start signal S_STV. That is, the shift start signal S_STV can be activated in association with the duration of the variable blank periods BP1 to BP6. The shift determiner 120 can receive a data enable signal DE and a vertical synchronization signal Vsync to generate the shift start signal S_STV.

[0089] refer to Figure 6 , Figure 7A and Figure 7B The shift determinant 120 may include a counter 121, a calculator 122, an adder 123, a comparator 124, and a signal generator 125.

[0090] Counter 121 can be based on the reference clock R_clk for variable blank periods BP1 to BP6 (reference). Figure 3 The counter 121 can count the occurrences of the reference clock R_clk and output a first count value CNT1. The counter 121 can receive a reference clock R_clk and a data enable signal DE to count the variable blank periods BP1 to BP6. The counter 121 can count the occurrences of the reference clock R_clk during the time period from the start of the inactive period BP1 of the data enable signal DE in the first frame FP1 (e.g., the current frame) to the start of the active period AP2 of the data enable signal DE in the second frame FP2 (e.g., the next frame).

[0091] The first count value CNT1 output from the counter 121 can be provided to a calculator 122. The calculator 122 can add the first count value CNT1 to a pre-stored second count value CNT2 of the active period, and can calculate a count value CNT3 in each frame. Since the active periods AP1 to AP7 of the frame have a substantially constant duration, the second count value CNT2 can have a fixed value. The shift determiner 120 can further include a first memory 126 in which the second count value CNT2 is stored. However, embodiments should not be limited thereto or thereby. That is, the first memory 126 can be provided as a separate component external to the shift determiner 120.

[0092] The adder 123 can receive the count value CNT3 from the calculator 122. The adder 123 can add the count value CNT3 to a previous accumulation value P_CNT, and can output an accumulation value F_CNT. The shift determiner 120 can further include a second memory 127 in which the previous accumulation value P_CNT is stored. The adder 123 can read out the accumulation value (i.e., the previous accumulation value P_CNT) of the previous frame (e.g., the first frame FP1) from the second memory 127, and can add the count value CNT3 to the previous accumulation value P_CNT to calculate the accumulation value F_CNT of the current frame (e.g., the second frame FP2).

[0093] The second memory 127 can receive the accumulation value F_CNT of the current frame FP2 output from the adder 123, and can update the previous accumulation value P_CNT to the accumulation value F_CNT. Figure 6 The structure in which the second memory 127 is disposed in the shift determiner 120 is illustrated, however, embodiments should not be limited thereto or thereby. That is, the second memory 127 can be provided as a separate component external to the shift determiner 120.

[0094] The comparator 124 can compare the accumulation value F_CNT with a predetermined reference value R_CNT, and can output a shift control signal S_CS according to a result of the comparison. Specifically, when the accumulation value F_CNT is less than the reference value R_CNT, the comparator 124 can deactivate the shift control signal S_CS, and when the accumulation value F_CNT is equal to or greater than the reference value R_CNT, the comparator 124 can activate the shift control signal S_CS. For example, as illustrated in FIG. 2, the shift control signal S_CS can be activated at a time point t1 at which the reference value R_CNT and the accumulation value F_CNT become the same. Figure 7B

[0095] ​The signal generator 125 can receive the vertical synchronization signal Vsync, and can receive the shift control signal S_CS from the comparator 124. The signal generator 125 can generate the shift start signal S_STV based on the vertical synchronization signal Vsync in response to the shift control signal S_CS. The vertical synchronization signal Vsync can be generated in each frame according to a frame rate. Referring to Figure 7B , the shift start signal S_STV can be generated in synchronization with the vertical synchronization signal Vsync during the active period S_AP of the shift control signal S_CS. The activated shift control signal S_CS can be deactivated in synchronization with a falling time point of the vertical synchronization signal Vsync. That is, the shift start signal S_STV can be activated in a period in which both the vertical synchronization signal Vsync and the shift control signal S_CS are activated, and can be deactivated in a period in which at least one of the vertical synchronization signal Vsync and the shift control signal S_CS is deactivated.

[0096] The shift determiner 120 can control an activation time point of the shift start signal S_STV in association with the variable blank periods BP1 to BP6. Accordingly, the number of active periods of the vertical synchronization signal Vsync included in each of the periods of the shift start signal S_STV can be variable. For example, referring to Figure 7A , the number of active periods of the vertical synchronization signal Vsync included in the i-th period T1 of the shift start signal S_STV can be "n", and the number of active periods of the vertical synchronization signal Vsync included in the j-th period T2 of the shift start signal S_STV can be "k". In this case, "n" and "k" can be integers equal to or greater than 1, and "n" and "k" can have values different from each other. The signal generator 125 can apply the shift start signal S_STV to the image processor 110, and the image processor 110 can initiate the image shift operation in response to the shift start signal S_STV. As an example, the active period of the shift start signal S_STV can be maintained during a predetermined number of frames in one period. In this case, the image processor 110 can not perform the image shift operation during the inactive period of the shift start signal S_STV, and can perform the image shift operation during the active period of the shift start signal S_STV.

[0097] Figure 8 is a block diagram of an embodiment of the image processor 110 of Figure 5 , and Figure 9A and Figure 9B are views of an embodiment of a shift direction of an image according to the principles of the present application. Figure 10 is a view illustrating a shift direction of an image according to the principles of the present application, and Figure 5a view of an embodiment of pixel shifting of an image shift operation performed by the image processor 110.

[0098] In Figure 8 In an embodiment, the image processor 110 includes a shift processor 111 and a data compensator 112.

[0099] The shift processor 111 performs an image shift operation on the input image signal I_DAT in response to a shift start signal S_STV. The shift processor 111 determines a pixel shift amount based on shift setting information, and generates initial shift data I_RGB obtained by shifting the input image signal I_DAT according to the pixel shift amount and a shift direction.

[0100] The data compensator 112 compensates the initial shift data I_RGB to generate final shift data F_RGB, and outputs the final shift data F_RGB as image data RGB (refer to FIG. 1). Figure 5 As an example, the data compensator 112 includes a region setter 112a, a compensator 112b, and a synthesizer 112c.

[0101] The region setter 112a can set a compensation region and a non-compensation region according to the pixel shift amount and the shift direction. As an example, the compensation region can include a first compensation region and a second compensation region. Among the initial shift data I_RGB, first shift data I_RGB1 corresponding to the non-compensation region can be directly provided to the synthesizer 112c without passing through the compensator 112b.

[0102] Second shift data I_RGB2 corresponding to the compensation region can be provided to the compensator 112b. The compensator 112b can compensate the second shift data I_RGB2 and can generate compensation data C_RGB. As an example, the second shift data I_RGB2 can include first sub-shift data I_RGB21 corresponding to the first compensation region and second sub-shift data I_RGB22 corresponding to the second compensation region. The first sub-shift data I_RGB21 can be provided to a first sub-compensator 112b_1, and the second sub-shift data I_RGB22 can be provided to a second sub-compensator 112b_2. The first sub-compensator 112b_1 can up-scale the first sub-shift data I_RGB21 to generate first compensation data C_RGB1, and the second sub-compensator 112b_2 can down-scale the second sub-shift data I_RGB22 to generate second compensation data C_RGB2.

[0103] The synthesizer 112c can receive the first shift data I_RGB1 from the region setter 112a, and can receive the first compensation data C_RGB1 and the second compensation data C_RGB2 from the first sub-compensator 112b_1 and the second sub-compensator 112b_2, respectively. The synthesizer 112c can synthesize the first shift data I_RGB1 and the first compensation data C_RGB1 and the second compensation data C_RGB2 to generate final shift data F_RGB. The final shift data F_RGB can be provided to the data driver 220 as image data RGB in a period in which the image shift operation is performed.

[0104] Referring to Figure 9A and Figure 9B , the image shift can be set in various ways. As shown in Figure 9A , the image shift can be set to be sequentially moved from an original position P0 at which an original image corresponding to the input image signal I_DAT is displayed, to the first position P1 to the ninth position P9 in a spiral pattern. A shift amount from each of the first position P1 to the ninth position P9 to the original position P0 can be defined as a pixel shift amount. The pixel shift amount can vary in units of at least one frame. The pixel shift amount can include at least one of a horizontal shift component and a vertical shift component. In a case where the original image is shifted from the original position P0 to the first position P1, the pixel shift amount can include only the horizontal shift component, and in a case where the original image is shifted from the original position P0 to the second position P2, the pixel shift amount can include the horizontal shift component and the vertical shift component. In this case, the horizontal shift component indicates a shift amount of the original image moved in a first direction DR1, and the vertical shift component indicates a shift amount of the original image moved in a second direction DR2.

[0105] As shown in Figure 9B , the image shift can be set to be moved from an original position P0 at which an original image corresponding to the input image signal I_DAT is displayed, to one of the first position P1 to the sixth position P6 in a number 8 pattern.

[0106] For example, referring to Figure 8 , Figure 9B and Figure 10 , after the first image shift operation is performed, the original image O_IM corresponding to the input image signal I_DAT can be shifted from the original position P0 to the first position P1. The first shifted image S_IM1 corresponding to the first shift data can be shifted to the third direction DR3 with respect to the original image O_IM. When the first image shift operation is performed, the pixel shift amount can include a first horizontal shift component Sh1 and a first vertical shift component Sv1.

[0107] In the first shifted image S_IM1, an area (hereinafter referred to as a "first area A1") which does not overlap the original image O_IM is a portion in which an actual image can not be displayed. In the original image O_IM, an area (hereinafter referred to as a "second area A2") which does not overlap the first shifted image S_IM1 is a portion in which there is no data to be displayed. Therefore, a compensation operation (e.g., scaling up or scaling down) is performed based on data corresponding to an overlapping area. Thus, data corresponding to the first area A1 is removed from the initial shifted data I_RGB, data corresponding to the second area A2 is generated, and thus the final shifted data F_RGB is completed.

[0108] After the second image shifting operation is performed, the original image O_IM corresponding to the input image signal I_DAT can be shifted from the original position P0 to a second position P2. A second shifted image S_IM2 corresponding to the second shifted data can be shifted to the first direction DR1 with respect to the original image O_IM. When the second image shifting operation is performed, a pixel shift amount can include a second horizontal shift component Sh2. In the second shifted image S_IM2, an area (hereinafter referred to as a "third area A3") which does not overlap the original image O_IM is a portion in which an actual image can not be displayed. In the original image O_IM, an area (hereinafter referred to as a "fourth area A4") which does not overlap the second shifted image S_IM2 is a portion in which there is no data to be displayed. Therefore, a compensation operation (e.g., scaling up or scaling down) is performed based on data corresponding to an overlapping area. Thus, data corresponding to the third area A3 is removed from the initial shifted data I_RGB, data corresponding to the fourth area A4 is generated, and thus the final shifted data F_RGB is completed.

[0109] After the third image shift operation is performed, the original image O_IM corresponding to the input image signal I_DAT can be shifted from the original position P0 to the third position P3. The third shifted image S_IM3 corresponding to the third shifted data can be shifted relative to the original image O_IM to the fourth direction DR4. When the third image shift operation is performed, the pixel shift amount can include a third horizontal shift component Sh3 and a second vertical shift component Sv2. In the third shifted image S_IM3, the region that does not overlap with the original image O_IM (hereinafter referred to as "fifth region A5") is the part of the actual image that may not be displayed. In the original image O_IM, the region that does not overlap with the third shifted image S_IM3 (hereinafter referred to as "sixth region A6") is the part in which no data to be displayed exists. Therefore, the compensation operation (e.g., scaling up or scaling down) is performed based on the data corresponding to the overlapping regions. Therefore, the data corresponding to the fifth region A5 is removed from the initial shift data I_RGB, the data corresponding to the sixth region A6 is generated, and thus, the final shift data F_RGB is completed.

[0110] Apart from Figure 9A and Figure 9B In addition to the embodiments shown, an image processor 110 (reference 110) is used. Figure 8 Image shifting operations can be performed in various ways.

[0111] Figure 11 This is an illustrative waveform diagram showing the refresh operation of a display device DD operating in an ultra-low frequency mode. Figure 12 yes Figure 5 A block diagram of another embodiment of the shift determiner 120. Figure 13 This shows that they are respectively as Figure 12 Illustrative waveform diagrams of the activation times of the shift start signal S_STV and the pre-shift control signal PS_CS of the output and input signals of the signal generator 125. Figure 12 and Figure 13 In the figures, the same reference numerals indicate Figure 6 and Figure 7B The same components are used, and therefore, detailed descriptions of the same components will be omitted to avoid repetition.

[0112] Display devices operating in ultra-low frequency mode (DD) (reference) Figure 1 A static image IM_A can be displayed during a predetermined time period T_R. For example, in ultra-low frequency mode, the display device DD can operate at a frequency below approximately 1 Hz. In ultra-low frequency mode, the time period T_R during which the static image IM_A is refreshed to another image IM_B can be longer than the predetermined shift period.

[0113] Hereinafter, a method of performing an image shift operation for a predetermined period in an ultra-low frequency mode will be described.

[0114] In Figure 12 and Figure 13 , the shift determiner 120 further includes a preliminary comparator 128. The preliminary comparator 128 receives the count value CNT3 from the calculator 122, and compares the received count value CNT3 with a predetermined reference value R_CNT.

[0115] When the count value CNT3 is less than the reference value R_CNT, the preliminary comparator 128 provides the count value CNT3 to the adder 123. When the count value CNT3 is provided to the adder 123, the adder 123 and the comparator 124 can operate similarly to those shown in Figure 6 and Figure 7B . When the count value CNT3 is equal to or greater than the reference value R_CNT, the preliminary comparator 128 can activate a pre-shift control signal PS_CS. For example, as shown in Figure 13 , the pre-shift control signal PS_CS can be activated after a time point t2 at which the reference value R_CNT becomes the same as the count value CNT3.

[0116] The signal generator 125 receives the vertical synchronization signal Vsync, and receives the pre-shift control signal PS_CS from the preliminary comparator 128. The signal generator 125 generates a shift start signal S_STV based on the vertical synchronization signal Vsync in response to the pre-shift control signal PS_CS. The shift start signal S_STV can be generated in synchronization with the vertical synchronization signal Vsync in an active period PS_AP of the pre-shift control signal PS_CS. The activated pre-shift control signal PS_CS can be deactivated in synchronization with a falling time point of the vertical synchronization signal Vsync. That is, the shift start signal S_STV is activated in a period in which both the vertical synchronization signal Vsync and the pre-shift control signal PS_CS are activated. According to Figure 13 , the number of active periods of the vertical synchronization signal Vsync included in one period of the shift start signal S_STV can be 1. As an example, the active period of the shift start signal S_STV can be maintained in a predetermined number of frames.

[0117] The signal generator 125 can provide the shift start signal S_STV to the image processor 110 (refer to Figure 5 ), and the image processor 110 can normally perform an image shift operation for a predetermined period in an ultra-low frequency mode in response to the shift start signal S_STV.

[0118] While specific embodiments and implementations have been described herein, other embodiments and modifications will be apparent to those of ordinary skill in the art once given the benefit of this description. Therefore, the inventive concept is not limited to the specific embodiments and implementations described herein, but only to the scope of the appended claims and various obvious modifications and equivalent arrangements that would be readily apparent to one of ordinary skill in the art having the benefit of this description.

Claims

1. A display apparatus comprising: a display panel configured to display an image; a panel driver configured to drive the display panel; and a controller configured to control driving of the panel driver; wherein the controller includes a first circuit configured to receive frame data in synchronization with a vertical synchronization signal that determines a start point of a frame having an active period and a variable blank period, to shift a position of the frame data to generate shifted data in response to a shift start signal, and to provide the shifted data to the panel driver, wherein a duration of the variable blank period varies according to a frame rate of the frame data received in a variable frequency mode, and a second circuit configured to determine an activation point of the shift start signal in association with the duration of the variable blank period; and wherein a number of active periods of the vertical synchronization signal included in one period of the shift start signal is different from a number of active periods of the vertical synchronization signal included in another period of the shift start signal. The second circuit is configured to count the variable blank period based on a reference clock to generate a count value of the frame, to compare an accumulated value obtained by accumulating the count value with a predetermined reference value, and to determine the activation point of the shift start signal according to a result of the comparison.

2. The display device according to claim 1, wherein The second circuit includes a shift determiner including:

3. The display device according to claim 2, wherein a counter configured to count a number of occurrences of the reference clock during the variable blank period to output a first count value; and a calculator configured to add a pre-stored second count value of the active period to the first count value to calculate the count value. The active period has a constant duration per frame, and the variable blank period has a variable duration.

4. The display device according to any one of claims 1 to 3, wherein In the frame, the variable blank period is generated after the active period.

5. The display device of claim 4, wherein, The controller is configured to receive the frame data in response to a data enable signal, and the counter is configured to count a non-active period of the data enable signal to generate the first count value.

6. The display device according to claim 3, wherein The controller further includes a first memory in which the second count value is stored.

7. The display device according to claim 3, wherein The shift determiner further includes:

8. The display device according to claim 3, wherein an adder configured to add the count value to a previous accumulated value to output the accumulated value; and a comparator configured to compare the accumulated value with the reference value, and to output a shift control signal according to a result of the comparison. The controller further includes a second memory configured to receive the accumulated value output from the adder, and to update the previous accumulated value to the accumulated value.

9. The display device of claim 8, wherein, The shift determiner further includes a signal generator configured to receive the shift control signal to control the activation point of the shift start signal, and to provide the shift start signal to the first circuit.

10. The display device of claim 8, wherein, ​ 11. The display device of claim 8, wherein, The shift determiner further comprises a preliminary comparator configured to compare the count value with the reference value.

12. The display device of claim 11, wherein, The preliminary comparator is configured to: provide the count value to the adder when the count value is smaller than the reference value; and output a pre-shift control signal when the count value is larger than the reference value.

13. The display device of claim 12, wherein, The shift determiner further comprises a signal generator configured to receive the pre-shift control signal to control the activation time point of the shift start signal, and to provide the shift start signal to the first circuit.

14. The display device of claim 1, wherein, The display panel comprises a plurality of pixels, each pixel comprising a light emitting element.

15. The display device of claim 14, wherein, The first circuit comprises an image processor comprising: a shift processor configured to determine a pixel shift amount based on shift setting information, and to generate initial shift data obtained by shifting the frame data according to the pixel shift amount and a shift direction; and a data compensator configured to compensate the initial shift data to generate the shift data.

16. The display device of claim 15, wherein, The data compensator comprises: a region setter configured to set a first compensation region and a second compensation region according to the pixel shift amount and the shift direction; a first sub-compensator configured to scale up first sub-shift data corresponding to the first compensation region among the initial shift data to generate first compensation data; and a second sub-compensator configured to scale down second sub-shift data corresponding to the second compensation region among the initial shift data to generate second compensation data.

17. A method of driving a display apparatus, the method comprising the steps of: receiving frame data in synchronization with a vertical synchronization signal that determines a start time point of a frame having an active period and a variable blank period, wherein a duration of the variable blank period varies according to a frame rate of the received frame data in a variable frequency mode; setting a period of a shift start signal based on the variable blank period; determining an activation time point of the shift start signal in association with the duration of the variable blank period; shifting the frame data in response to the shift start signal to generate shift data; converting the shift data into a data signal; and displaying an image using the data signal, wherein a number of active periods of the vertical synchronization signal included in one period of the shift start signal is different from a number of active periods of the vertical synchronization signal included in another period of the shift start signal.

18. The method of claim 17, wherein, The step of setting the period of the shift start signal comprises the steps of: counting the variable blank period based on a reference clock to generate a count value of the frame; wherein the step of determining the activation time point of the shift start signal comprises the steps of: comparing an accumulated value obtained by accumulating the count value with a predetermined reference value; and determining the activation time point of the shift start signal according to a result of the comparison.

19. The method of claim 18, wherein, The step of determining the activation time point of the shift start signal comprises the steps of: receiving the count value of the frame; adding the count value to a pre-stored previous accumulation value to generate the accumulation value; comparing the accumulation value to the reference value to output a shift control signal according to a result of the comparison; and activating the shift start signal in response to the shift control signal.

20. The method of claim 19, wherein, The step of generating the count value of the frame includes the steps of: counting occurrences of the reference clock during the variable blank period to output a first count value; and adding a pre-stored second count value of the active period to the first count value to calculate the count value.

21. The method of any one of claims 17-20, wherein, The active period has a constant duration per frame, and the variable blank period has a variable duration.

22. The method of claim 21, wherein, The variable blank period is generated after the active period in the frame.

23. The method of claim 20, wherein, The step of receiving the frame data includes receiving the frame data in response to a data enable signal, and the step of outputting the first count value includes counting non-active periods of the data enable signal to generate the first count value.

24. The method of claim 20, further comprising the steps of: receiving the accumulation value; and updating the previous accumulation value to the accumulation value.

25. The method of claim 20, further comprising the steps of: comparing the count value to the reference value before generating the accumulation value.

26. The method of claim 25, wherein, The step of comparing the count value to the reference value includes the steps of: adding the count value to the previous accumulation value when the count value is less than the reference value; and outputting a pre-shift control signal when the count value is greater than the reference value.

27. The method of claim 26, further comprising the steps of: activating the shift start signal in response to the pre-shift control signal.

28. The method of claim 17, wherein, The step of generating the shift data includes the steps of: determining a pixel shift amount based on shift setting information to generate initial shift data obtained by shifting the frame data according to the pixel shift amount and a shift direction; and compensating the initial shift data to generate the shift data.

29. The method of claim 28, wherein, The step of compensating the initial shift data includes the steps of: setting a first compensation region and a second compensation region according to the pixel shift amount and the shift direction; scaling up first sub-shift data corresponding to the first compensation region among the initial shift data to generate first compensation data; and scaling down second sub-shift data corresponding to the second compensation region among the initial shift data to generate second compensation data.

Images