semiconductor memory devices

Abstract

An embodiment provides a semiconductor memory device capable of improving processing capabilities. According to the embodiment, the semiconductor memory device includes a memory string NS, first to fourth select gate lines (SGDT, SGD, SGS, SGSB), first and second word lines WL, a bit line BL, and a source line SL. The memory string NS includes first to fourth select transistors (STT1, ST1, ST2, STB2), and first and second memory cells MC. An erase operation includes first and second modes. In the first mode (block erase mode), a first voltage Vera is applied to the bit line and source line, a second voltage Verasgdt and a third voltage Verasgd are applied to the first to fourth select gate lines, and a fourth voltage Verasgs and a fifth voltage Verasgsb are applied, respectively. A sixth voltage VDD is applied to the first and second word lines.

Description

[0001] [Related Applications]

[0002] This application claims priority from Japanese Patent Application No. 2020-147663 (filing date: September 2, 2020), and the present application incorporates all the contents of the basic application by reference. Technical Field

[0003] An embodiment of the present invention relates to a semiconductor memory device. Background Art

[0004] As a semiconductor storage device, a NAND (Not And) type flash memory is known. Summary of the Invention

[0005] Embodiments provide a semiconductor memory device capable of improving processing capability.

[0006] A semiconductor memory device according to an embodiment includes: a memory string including first to fourth select transistors and first and second memory cells, wherein the first select transistor, the second select transistor, the first memory cell, the second memory cell, the third select transistor, and the fourth select transistor are sequentially connected in series; first to fourth select gate lines connected to the gates of the first to fourth transistors, respectively; first and second word lines connected to the gates of the first and second memory cells, respectively; a bit line connected to the first select transistor; a source line connected to the fourth select transistor; and a row decoder configured to apply voltages to the first to fourth select gate lines and the first and second word lines. An erase operation includes a first mode for erasing data in the first and second memory cells and a second mode for erasing data in one of the first and second memory cells. In the first mode, a first voltage is applied to the bit line and the source line, a second voltage lower than the first voltage is applied to the first select gate line, which generates GIDL (gate induced drain leakage) in the first select transistor, a third voltage is applied to the second select gate line, a fourth voltage is applied to the third select gate line, a fifth voltage lower than the first voltage is applied to the fourth select gate line, which generates GIDL in the fourth select transistor, and a sixth voltage lower than the first to fifth voltages is applied to the first and second word lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram of a semiconductor memory device according to one embodiment.

[0008] Figure 2 This is a circuit diagram of a memory cell array included in a semiconductor memory device according to one embodiment.

[0009] Figure 3 This is a cross-sectional view of a memory cell array included in a semiconductor memory device according to one embodiment.

[0010] Figure 4 1 is a conceptual diagram showing the concentration distribution of impurities in the memory pillars MP included in the semiconductor memory device according to one embodiment.

[0011] Figure 5 This is a timing chart showing voltages of respective wirings in a block erase mode in a semiconductor memory device according to one embodiment.

[0012] Figure 6 This is a timing chart showing voltages of respective wirings in a subblock erase mode in a semiconductor memory device according to one embodiment.

[0013] Figure 7 This is a timing chart showing voltages of respective wirings in a subblock erase mode in a semiconductor memory device according to one embodiment. DETAILED DESCRIPTION

[0014] The following describes the embodiments with reference to the accompanying drawings. In the following description, components having substantially the same function and configuration are denoted by the same reference numerals, and repeated descriptions are provided only when necessary. Each embodiment described below illustrates an apparatus or method for realizing the technical concept of the embodiment. The technical concept of the embodiment does not specify the material, shape, structure, or configuration of the components as described below. The technical concept of the embodiment can be modified in various ways in the claims.

[0015] A semiconductor memory device according to an embodiment will be described below. A three-dimensional stacked NAND flash memory in which memory cell transistors are three-dimensionally stacked on a semiconductor substrate will be described as an example of a semiconductor memory device.

[0016] 1. Composition

[0017] 1.1 Overall Structure of a Semiconductor Memory Device

[0018] First, use Figure 1 An example of the overall structure of a semiconductor memory device will be described. Figure 1 This is an example of a block diagram showing the basic overall structure of a semiconductor memory device.

[0019] like Figure 1 As shown, the semiconductor memory device 1 includes a memory core unit 10 and a peripheral circuit unit 20 .

[0020] The memory core 10 includes a memory cell array 11 , a row decoder 12 , and a sense amplifier 13 .

[0021] The memory cell array 11 includes a plurality of blocks BLK (BLK0, BLK1, ...). Each block BLK includes a plurality of string units SU (in Figure 1 In the example, there are 4 string components SU0~SU3). For example, block BLK is the unit of erasing data. The data stored in the memory cell transistors contained in block BLK can be erased at one time. Furthermore, in this embodiment, block BLK can be divided into multiple areas (sub-blocks SBLK), and each area can be erased independently. Each NAND string NS in block BLK is divided corresponding to the number of sub-blocks SBLK. Moreover, the divided NAND strings NS are contained in different sub-blocks SBLK. Below, the case where block BLK includes 2 sub-blocks SBLK is described. The two sub-blocks SBLK are respectively expressed as "upper sub-block USBLK" and "lower sub-block LSBLK". For example, block BLK0 includes upper sub-block USBLK0 and lower sub-block LSBLK0. Block BLK1 includes upper sub-block USBLK1 and lower sub-block LSBLK1. In addition, the number of blocks BLK in the memory cell array 11, the number of sub-blocks SBLK, the number of string components SU in the block BLK, and the number of NAND strings NS in the string component SU are arbitrary.

[0022] The row decoder 12 decodes a row address received from an external controller (not shown). Based on the decoding result, the row decoder 12 selects row-direction wirings for the memory cell array 11. More specifically, the row decoder 12 applies voltages to various row-direction wirings (word lines and select gate lines) for selecting a row.

[0023] The sense amplifier 13 senses data read from any block BLK via the bit line during data reading, and applies a voltage corresponding to the write data to the memory cell array 11 via the bit line during data writing.

[0024] The peripheral circuit section 20 includes a sequencer 21 and a voltage generating circuit 22 .

[0025] The sequencer 21 controls the overall operation of the semiconductor memory device 1. More specifically, the sequencer 21 controls the voltage generating circuit 22, the row decoder 12, the sense amplifier 13, and the like during programming, reading, and erasing operations.

[0026] The voltage generating circuit 22 generates voltages for use in programming, reading, and erasing operations, and supplies the voltages to the memory cell array 11 , the row decoder 12 , the sense amplifier 13 , and the like.

[0027] 1.2 Circuit Structure of Memory Cell Array

[0028] Next, use Figure 2 The configuration of the memory cell array 11 will be described. Figure 2 1 is a circuit diagram of the string unit SU0 of the block BLK0. The other blocks BLK and string units SU also have the same structure.

[0029] like Figure 2 As shown, the string component SU0 of block BLK0 includes multiple NAND strings NS. Each NAND string NS includes, for example, 160 memory cell transistors MC0-MC159, 10 dummy memory cell transistors MCDD0-MCDD3, MCDU, MCDL, and MCDS0-MCDS3, and 13 selection transistors STT1a-STT1c, ST1a-ST1c, ST2a-ST2c, and STB2a-STB2d. Hereinafter, when no specific one of the memory cell transistors MC0-MC159 is specified, it is referred to as a memory cell transistor MC. When no specific one of the dummy memory cell transistors MCDD0-MCDD3 is specified, it is referred to as a dummy memory cell transistor MCDD. When no specific one of the dummy memory cell transistors MCDS0-MCDS3 is specified, it is referred to as a dummy memory cell transistor MCDS. When no specific one of the dummy memory cell transistors MCDD, MCDU, MCDL, and MCDS is specified, it is referred to as a dummy memory cell transistor MCD. When no specific selection transistor STT1a to STT1c is specified, it is expressed as STT1. When no specific selection transistor ST1a to ST1c is specified, it is expressed as ST1. When no specific selection transistor ST2a to ST2c is specified, it is expressed as ST2. When no specific selection transistor STB2a to STB2d is specified, it is expressed as STB2.

[0030] Memory cell transistor MC and dummy memory cell transistor MCD include a control gate and a charge storage layer. Memory cell transistor MC stores data nonvolatilely. Dummy memory cell transistor MCD has the same configuration as memory cell transistor MC but is used for dummy operations and not for data storage.

[0031] In addition, the memory cell transistor MC and the dummy memory cell transistor MCD can be a MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) type using an insulating film in the charge storage layer, or an FG (Floating Gate) type using a conductive layer in the charge storage layer. Below, in this embodiment, the MONOS type is used as an example for explanation. The number of memory cell transistors MC and dummy memory cell transistors MCD in the NAND string NS is arbitrary. It is also possible not to provide a dummy memory cell transistor MCD.

[0032] Select transistors ST1 and ST2 are used to select a string unit SU (NAND string NS). Select transistors STT1 and STB2, like select transistors ST1 and ST2, select string unit SU during write and read operations. Furthermore, select transistors STT1 and STB2 are used to generate a GIDL current during erase operations. The number of select transistors ST1, ST2, STT1, and STB2 is arbitrary, as long as there is at least one of each.

[0033] In NAND string NS, the current paths of memory cell transistor MC, dummy memory cell transistor MCD, and select transistors ST1, ST2, STT1, and STB2 are connected in series. More specifically, for example, the current paths are connected in series in the order of select transistors STB2a to STB2d and ST2a to ST2c, dummy memory cell transistors MCDS0 to MCDS3, memory cell transistors MC0 to MC79, dummy memory cell transistors MCDL and MCDU, memory cell transistors MC80 to MC159, dummy memory cell transistors MCDD3 to MCDD0, and select transistors ST1c to ST1a and STT1c to STT1a.

[0034] In this embodiment, the NAND string NS includes a lower string NSL corresponding to the lower sub-block LBLK, and an upper string NSU corresponding to the upper sub-block USBLK. Figure 2In the example, the lower string NSL includes memory cell transistors MC0-MC79, dummy memory cell transistors MCDS0-MCDS3 and MCDL, and select transistors ST2a-ST2c and STB2a-STB2d. The upper string NSU includes memory cell transistors MC80-MC159, dummy memory cell transistors MCDD0-MCDD3 and MCDU, and select transistors ST1a-ST1c and STT1a-STT1c. That is, during the erase operation of the lower sub-block LSBLK, the data in the memory cell transistors MC0-MC79 in block BLK can be erased. During the erase operation of the upper sub-block USBLK, the data in the memory cell transistors MC80-MC159 in block BLK can be erased.

[0035] The control gates of the memory cell transistors MC0 to MC159 in block BLK are respectively connected in common to word lines WL0 to WL159. More specifically, the memory cell transistors MC0 of the multiple NAND strings NS included in the string components SU0 to SU3 in block BLK0 are connected in common to word line WL0. The same applies to other memory cell transistors MC. In addition, the control gates of the dummy memory cell transistors MCDD0 to MCDD3, MCDU, MCDL, and MCDS0 to MCDS3 in block BLK are respectively connected in common to dummy word lines WLDD0 to WLDD3, WLDU, WLDL, and WLDS0 to WLDS3. Hereinafter, when any one of the word lines WL0 to WL159 is not specified, it is referred to as word line WL. When any one of the dummy word lines WLDD0 to WLDD3, WLDU, WLDL, and WLDS0 to WLDS3 is not specified, it is referred to as dummy word line WLD.

[0036] Word lines WL0 to WL159 and dummy word lines WLDD0 to WLDD3 , WLDU, WLDL, and WLDS0 to WLDS3 are connected to the row decoder 12 and are independently controlled.

[0037] The gates of the multiple select transistors STT1a-STT1c and ST1a-ST1c within a string unit SU are each commonly connected to a select gate line corresponding to the string unit SU. More specifically, the gates of the multiple select transistors STT1a-STT1c within string unit SU0 are each commonly connected to select gate lines SGDT0a-SGDT0c. The gates of the multiple select transistors ST1a-ST1c within string unit SU0 are each commonly connected to select gate lines SGD0a-SGD0c. Furthermore, select gate lines SGDT0a-SGDT0c are commonly connected to select gate line SGDT0. Select gate lines SGD0a-SGD0c are commonly connected to select gate line SGD0.

[0038] Similarly, the gates of the multiple selection transistors STT1a to STT1c in the string component SU1 (not shown) are respectively connected in common to the selection gate lines SGDT1a to SGDT1c. The gates of the multiple selection transistors ST1a to ST1c in the string component SU1 are respectively connected in common to the selection gate lines SGD1a to SGD1c. Furthermore, the selection gate lines SGDT1a to SGDT1c are connected in common to the selection gate line SGDT1. The selection gate lines SGD1a to SGD1c are connected in common to the selection gate line SGD1. Hereinafter, when not limited to the string component SU, the wiring equivalent to the selection gate lines SGDT0 and SGD0 of the string component SU0 will be described as the selection gate lines SGDT and SGD, respectively.

[0039] The select gate lines SGDT0 and SGD0 are connected to the row decoder 12 and are independently controlled. The same applies to the other string units SU1-SU3. Therefore, the row decoder 12 can apply different voltages to the select gate lines SGDT and SGD of each string unit SU. Furthermore, for example, the select gate lines SGDT0a-SGDT0c and SGD0a-SGD0c of string unit SU0 can also be independently controlled by the row decoder 12. The same applies to the other string units SU.

[0040] The gates of the multiple selection transistors STB2a~STB2d in the block BLK are commonly connected to one selection gate line SGSB. Similarly, the gates of the multiple selection transistors ST2a~ST2c in the block BLK are commonly connected to one selection gate line SGS. More specifically, the gates of the multiple selection transistors STB2a~STB2d in the string component SU0 are commonly connected to the selection gate lines SGSB0a~SGSB0d, respectively. The gates of the multiple selection transistors ST2a~ST2c in the string component SU0 are commonly connected to the selection gate lines SGS0a~SGS0c, respectively. Moreover, the selection gate lines SGSB0a~SGSB0d are commonly connected to the selection gate line SGSB. The selection gate lines SGS0a~SGS0c are commonly connected to the selection gate line SGS. The same is true for other string components SU. In addition, different selection gate lines SGSB and SGS can also be set for each string component SU.

[0041] Select gate lines SGSB and SGS are connected to the row decoder 12 and are independently controlled. Therefore, the row decoder 12 can apply different voltages to select gate lines SGSB and SGS. Furthermore, for example, select gate lines SGSB0a-SGSB0d and SGS0a-SGS0c of string unit SU0 can also be independently controlled by the row decoder 12. The same applies to the other string units SU.

[0042] The drains of the select transistors STT1a of the multiple NAND strings NS within the string unit SU are connected to different bit lines BL0 through BLn (n is an integer greater than or equal to 1). Hereinafter, when the bit lines BL0 through BLn are not limited, they will be referred to as bit lines BL. Each bit line BL is connected to a sense amplifier 13 and can be independently controlled.

[0043] The sources of the plurality of selection transistors STB2 a in the block BLK are commonly connected to the source line SL.

[0044] In other words, a string unit SU is a collection of NAND strings NS connected to different bit lines BL and to the same select gate lines SGDT and SGD. Furthermore, a block BLK is a collection of multiple string units SU that share a common word line WL. Furthermore, the memory cell array 11 is a collection of multiple blocks BLK that share a common bit line BL.

[0045] Write and read operations are performed collectively on multiple memory cell transistors MC connected to any word line WL in any string unit SU. Hereinafter, the group of memory cell transistors MC collectively selected during write and read operations is referred to as a "cell unit CU." Furthermore, the collection of single-bit data written to or read from a cell unit CU is referred to as a "page."

[0046] 1.3 Cross-sectional structure of memory cell array

[0047] Next, use Figure 3 The cross-sectional structure of the memory cell array 11 will be described. Figure 3 The example shows a cross section of one NAND string NS of the string component SU0. Figure 3 In FIG, a portion of the interlayer insulating film is omitted.

[0048] like Figure 3 As shown, an insulating layer 31 is formed on a semiconductor substrate 30. For example, a silicon oxide film (SiO2) is used for the insulating layer 31. Furthermore, circuits such as the row decoder 12 and the sense amplifier 13 may be provided in the region where the insulating layer 31 is formed, that is, between the semiconductor substrate 30 and the wiring layer 32.

[0049] On insulating layer 31, wiring layer 32 is formed. These wiring layers 32 extend in both the X direction, which is roughly parallel to semiconductor substrate 30, and the Y direction, which intersects the X direction, and function as source lines SL. Wiring layer 32 is made of a conductive material, such as an n-type semiconductor (e.g., silicon (Si)) doped with impurities. This embodiment uses phosphorus-doped polysilicon (P-doped poly-Si) as an example for wiring layer 32.

[0050] Above wiring layer 32, four wiring layers 33 extending in the X direction and functioning as select gate lines SGSB0a to SGSB0d from the bottom are stacked in a spaced-apart manner in the Z direction perpendicular to semiconductor substrate 30. Above four wiring layers 33, three wiring layers 34 extending in the X direction and functioning as select gate lines SGS0a to SGS0c from the bottom are stacked in a spaced-apart manner in the Z direction. Above three wiring layers 34, 170 wiring layers 35, functioning as dummy word lines WLDS0 to WLDS3, word lines WL0 to WL79, dummy word lines WLDL and WLDU, word lines WL80 to WL159, and dummy word lines WLDD3 to WLDD0 from the bottom are stacked in a spaced-apart manner in the Z direction. Furthermore, above the 170-layer wiring layer 35, three wiring layers 36 are stacked in the Z direction, extending in the X direction and functioning as select gate lines SGD0c to SGD0a from the bottom. Three wiring layers 37 are stacked in the Z direction, extending in the X direction and functioning as select gate lines SGDT0c to SGDT0a from the bottom. Wiring layers 33 to 37 can also be made of conductive materials such as metals, n-type semiconductors, or p-type semiconductors. In this embodiment, a stacked structure using phosphorus-doped polysilicon for wiring layer 33 and titanium nitride (TiN) / tungsten (W) for wiring layers 34 to 37 will be described. TiN, for example, functions as a barrier layer to prevent the reaction between W and SiO2 or as an adhesion layer to improve the adhesion of W when W is deposited using CVD (chemical vapor deposition).

[0051] A memory column MP that reaches the wiring layer 32 is provided in a manner that passes through the wiring layers 33 to 37. One memory column MP corresponds to one NAND string NS. The memory column MP includes, for example, two memory columns LMP and UMP. In this embodiment, for example, the memory column LMP corresponds to the lower string NSL, that is, the lower sub-block LBLK. The memory column LMP reaches the wiring layer 32 on the bottom surface through (through) the wiring layers 33 and 34, and the wiring layer 35 that functions as the dummy word lines WLDS0 to WLDS3, word lines WL0 to WL79, and dummy word lines WLDL. The memory column UMP corresponds to the upper string NSU, that is, the upper sub-block UBLK. The memory column UMP is provided on the memory column LMP, for example, through the wiring layer 35 that functions as the dummy word line WLDU, word lines WL80 to WL159, and dummy word lines WLDD3 to WLDD0, and the wiring layers 36 and 37. These memory pillars LMP and UMP have side steps and are connected in the Z-axis direction to form memory pillars MP. Hereinafter, the connection portion between the memory pillar LMP and the memory pillar UMP including the side step will also be referred to as a junction JCT. Figure 3 In the example shown in FIG, two memory pillars LMP and UMP are connected to form a memory pillar MP. However, the number of connected pillars in the Z-axis direction is arbitrary. The memory pillar MP may be a single-stage structure or a structure of three or more stages.

[0052] The memory pillar MP includes a blocking insulating film 38 , a charge storage layer 39 , a tunnel insulating film 40 , a semiconductor layer 41 , a core layer 42 , and a cap layer 43 .

[0053] More specifically, memory holes LMH corresponding to memory pillars LMP and memory holes UMH corresponding to memory pillars UMP are formed. A blocking insulating film 38, a charge storage layer 39, and a tunnel insulating film 40 are sequentially formed on the side surfaces of the memory holes UMH, as well as on a portion of the side surfaces and the bottom surface of the memory holes LMH. The interiors of the memory holes LMH and UMH are filled with a semiconductor layer 41 and a core layer 42. A cap layer 43 is provided above the memory holes UMH, on the semiconductor layer 41 and the core layer 42. The semiconductor layer 41 is a region for forming channels for the memory cell transistor MC, the dummy memory cell transistor MCD, and the select transistors ST1, STT1, ST2, and STB2. The blocking insulating film 38, the charge storage layer 39, and the tunnel insulating film 40 on the side surfaces of the memory holes LMH and UMH are formed so that the wiring layers 33 to 37 are not in contact with the semiconductor layer 41. Specifically, in the memory holes LMH and UMH, the blocking insulating film 38, the charge storage layer 39, and the tunnel insulating film 40 are formed on the side surfaces including the areas in contact with the wiring layers 33 to 37. Furthermore, the blocking insulating film 38, the charge storage layer 39, and the tunnel insulating film 40 are removed from a portion of the side surfaces of the memory holes LMH in the areas in contact with the wiring layer 32. As a result, a portion of the side surfaces of the semiconductor layer 41 are in contact with the wiring layer 32.

[0054] Memory pillars MP and wiring layer 35 functioning as word lines WL0 to WL159 form memory cell transistors MC0 to MC159. Similarly, memory pillars MP and wiring layer 35 functioning as dummy word lines WLDD0 to WLDD3, WLDU, WLDL, and WLDS0 to WLDS3 form dummy memory cell transistors MCDD0 to MCDD3, MCDU, MCDL, and MCDS0 to MCDS3. Memory pillars MP and wiring layer 37 functioning as select gate lines SGDT0a to SGDT0c form select transistors STT1a to STT1c. Memory pillars MP and wiring layer 36 functioning as select gate lines SGD0a to SGD0c form select transistors ST1a to ST1c. Memory pillars MP and wiring layer 34 functioning as select gate lines SGS0a to SGS0c form select transistors ST2a to ST2c. The memory pillars MP and the wiring layer 33 functioning as the selection gate lines SGSB0 a to SGSB0 d constitute the selection transistors STB2 a to STB2 d .

[0055] The blocking insulating film 38, the tunnel insulating film 40, and the core layer 42 are made of, for example, SiO2. The charge storage layer 39 is made of, for example, a silicon nitride film (SiN). The semiconductor layer 41 is made of, for example, polysilicon. The cap layer 43 is made of, for example, an n-type semiconductor.

[0056] Contact plugs 44 are formed on the cap layer 43. On the contact plugs 44, wiring layers 45 are formed, functioning as bit lines BL and extending in the Y direction. The contact plugs 44 and wiring layers 45 are made of a conductive material, such as a titanium (Ti) / TiN / W stacked structure or copper wiring.

[0057] In the above configuration, an n-type semiconductor may be used for the semiconductor layer 41 in the junction JCT region.

[0058] 2. Impurity concentration of memory column

[0059] Next, use Figure 4 The impurity concentration of the memory pillar will be described. Figure 4 is a conceptual diagram showing the concentration distribution of impurities in the semiconductor layer 41 of the memory pillar MP. Figure 4 In the example of FIG. 1 , the case of using arsenic (As) as an impurity for forming an n-type semiconductor is described.

[0060] like Figure 4 As shown, in the region of the semiconductor layer 41 where the channel of the selection transistor STT1 is formed (the region facing the selection gate lines SGDT0a to SGDT0c), As is doped by, for example, ion implantation. As a result, an n-type semiconductor is formed in the region corresponding to the selection transistor STT1 in the semiconductor layer 41. In this embodiment, during the erase operation, the selection transistors STT1 and STB2 are used to generate GIDL current. For example, in order to efficiently generate GIDL current in the selection transistor STT1, the channel region of the selection transistor STT1 is preferably doped with, for example, 1E19 atoms / cm 3 n-type semiconductor with impurities above 100%. In this embodiment, it is sufficient to form an n-type semiconductor in at least one channel region of the three selection transistors STT1a to STT1c. Therefore, in the semiconductor layer 41, As only needs to be doped from the upper surface of the memory column MP (top cover layer 43) to the lower side of the lower surface of the selection gate line SGDT0a. Once As diffuses to the area of ​​the semiconductor layer 41 corresponding to the selection transistor ST1 (lower side than the upper surface of the selection gate line SGD0a), the threshold voltage of the selection transistor ST1 will change, causing the selection action of the NAND string NS to malfunction. Therefore, in this embodiment, the diffusion depth of As is controlled by, for example, the acceleration voltage of ion implantation, so that As does not diffuse into the area of ​​the semiconductor layer 41 corresponding to the selection transistor ST1. Compared with P, the use of As can make the distribution of the semiconductor layer 41 in the Z direction (depth direction) steeper, and the control in the depth direction becomes easier. In addition, P can also be used instead of As.

[0061] In the region of the semiconductor layer 41 corresponding to the selection transistor STB2, an n-type semiconductor can be formed by diffusing P from the wiring layer 32 (phosphorus-doped polysilicon). In this case, P is not diffused into the region of the semiconductor layer 41 corresponding to the selection transistor STB2.

[0062] Furthermore, in this embodiment, to improve the cutoff characteristics of the select transistor ST1, boron (B) is doped into the region forming the channel of the select transistor ST1, for example, by ion implantation. If B diffuses into the region of the semiconductor layer 41 corresponding to the dummy memory cell transistor MCD (below the upper surface of the dummy word line WLDD0), the threshold voltage of the dummy memory cell transistor MCD will fluctuate. Therefore, in this embodiment, control is performed to prevent B from diffusing into the region of the semiconductor layer 41 corresponding to the dummy memory cell transistor MCD. Alternatively, B doping is not required.

[0063] 3. Erase Action

[0064] Next, the erase operation is described. The erase operation in this embodiment includes a block erase mode and a sub-block erase mode. The block erase mode selects one block (BLK) for erase. The sub-block erase mode selects either the upper sub-block (USBLK) or the lower sub-block (LSBLK) for erase.

[0065] The erase operation generally consists of an erase pulse application operation and an erase verification operation. The erase pulse application operation applies an erase pulse to lower the threshold voltage of the memory cell transistor MC. The erase verification operation determines whether the threshold voltage of the memory cell transistor MC has fallen below a target value after the erase pulse application operation. During the erase operation, the erase pulse application operation and the erase verification operation are repeated until the threshold voltage of the memory cell transistor MC is lowered to the erase level.

[0066] 3.1 Block Erase Mode

[0067] Next, use Figure 5 The block erase mode is described. Figure 5 1 is a timing chart showing the voltages of the respective wirings during the erase pulse application operation in the block erase mode.

[0068] like Figure 5As shown, first, at time t0, the row decoder 12 applies, for example, the power supply voltage VDD to the select gate lines SGDT, SGD, SGSB, and SGS, the word line WL, and the dummy word line WLD of the block BLK to be erased (hereinafter, also referred to as the "selected block BLK"). In addition, the row decoder 12 applies the voltage VDD to the word line WL and the dummy word line WLD of the block BLK not to be erased (hereinafter, also referred to as the "unselected block BLK"). In addition, the voltage of the word line WL and the dummy word line WLD may not be the voltage VDD. The voltage of the word line WL and the dummy word line WLD may also be a voltage lower than the voltage VDD so that the holes generated by GIDL are injected into the charge storage layer 39 of the corresponding memory cell transistor MC and the dummy memory cell transistor MCD. Alternatively, the row decoder 12 may not apply the voltage VDD to the word lines WL and the dummy word lines WLD of the unselected block BLK, but may place the word lines WL and the dummy word lines WLD of the unselected block BLK in a floating state.

[0069] Next, at time t1, voltage Vera is applied to source line SL and bit line BL. Voltage Vera is a high voltage used to generate GIDL. Row decoder 12 then applies voltage Vera to select gate lines SGD and SGS to suppress hole injection into charge storage layer 39 of select transistors ST1 and ST2. Alternatively, a voltage different from voltage Vera may be applied to select gate lines SGD and SGS. In this case, the voltages applied to select gate lines SGD and SGS may also differ. For example, a voltage higher than voltage VDD may be applied to select gate lines SGD and SGS.

[0070] Next, between times t2 and t3, the row decoder 12 applies voltage Verasgdt and voltage Verasgsb to the select gate lines SGDT and SGSB of the selection block BLK, respectively. Voltage Verasgdt is a high voltage for generating GIDL in the selection transistor STT1 and is a voltage lower than voltage Vera and higher than voltage VDD. Voltage Verasgsb is a high voltage for generating GIDL in the selection transistor STB2 and is a voltage lower than voltage Vera and higher than voltage VDD. Voltage Verasgdt and voltage Verasgsb can be different voltages or the same voltage. Thus, GIDL is generated in the select transistors STT1 and STB2 of the selection block BLK. Holes generated by GIDL are injected into the charge storage layer 39 of the memory cell transistor MC and the dummy memory cell transistor MCD in the selection block BLK. In other words, holes are supplied to the memory cell transistor MC and the dummy memory cell transistor MCD from the bit line BL side and the source line side (erasing data).

[0071] Furthermore, during the period from time t2 to t3, the row decoder 12 floats the word lines WL and dummy word lines WLD of the unselected blocks BLK. Since the word lines WL and dummy word lines WLD of the unselected blocks BLK are in a floating state, they are coupled to the semiconductor layer 41 (channel) to which voltage Vera is applied, and thus rise to, for example, voltage Vera. Consequently, holes are not supplied to the memory cell transistors MC and dummy memory cell transistors MCD of the unselected blocks BLK (data is not erased).

[0072] At time t3 , a refresh operation is performed, and the voltage VSS is applied to each wiring.

[0073] 3.2 Sub-block Erase Mode

[0074] Next, use Figure 6 and Figure 7 The sub-block erase mode is described. Figure 6 This is a timing chart showing the voltages of the respective wirings during the erase pulse application operation in the erase operation of the upper sub-block USBLK. Figure 7 1 is a timing chart showing voltages of respective wirings during an erase pulse application operation in an erase operation of the lower sub-block LSBLK.

[0075] First, the erasing operation of the upper sub-block USBLK is described.

[0076] like Figure 6 As shown, first, the action at time t0 is the same as the block erase mode ( Figure 5 )same.

[0077] Next, at time t1, voltage Vera is applied to source line SL and bit line BL. Row decoder 12 applies voltage Vera to select gate lines SGD, SGS, and SGSB. Alternatively, a voltage different from voltage Vera may be applied to select gate lines SGD, SGS, and SGSB. In this case, the voltages applied to select gate lines SGD, SGS, and SGSB may also be different.

[0078] Next, between times t2 and t3, the row decoder 12 applies voltage Verasgdt to the select gate line SGDT of the selected block BLK. Furthermore, the row decoder 12 floats the word line WL and dummy word line WLD on the lower sub-block LBLK side, which are not the target of erasure. Consequently, GIDL is generated in the select transistor STT1 between times t2 and t3. Since the word line WL and dummy word line WLD on the lower sub-block LSBLK side are in a floating state, they rise to, for example, voltage Vera through coupling with the semiconductor layer 41 to which voltage Vera is applied from the bit line BL side. In this state, holes generated by GIDL are injected into the charge storage layer 39 of the memory cell transistor MC and dummy memory cell transistor MCD on the upper sub-block USBLK side within the selected block BLK. In other words, holes (erasing data) are supplied to the memory cell transistor MC and dummy memory cell transistor MCD of the upper sub-block USBLK from the bit line BL side. On the other hand, the memory cell transistor MC and the dummy memory cell transistor MCD of the lower sub-block LSBLK are not supplied with holes (data is not erased).

[0079] At time t3 , a refresh operation is performed, and the voltage VSS is applied to each wiring.

[0080] Next, the erase operation of the lower sub-block LSBLK will be described.

[0081] like Figure 7 As shown, the action at time t0 is the same as Figure 5 and Figure 6 same.

[0082] Next, at time t1, voltage Vera is applied to source line SL and bit line BL. Row decoder 12 applies voltage Vera to select gate lines SGDT, SGD, and SGS. Alternatively, a voltage different from voltage Vera may be applied to select gate lines SGDT, SGD, and SGS. In this case, the voltages applied to select gate lines SGDT, SGD, and SGS may also be different.

[0083] Between times t2 and t3, the row decoder 12 applies voltage Verasgsb to the select gate line SGSB of the selected block BLK. Furthermore, the row decoder 12 floats the word line WL and dummy word line WLD on the upper sub-block UBLK side, which are not the target of erasure. Consequently, GIDL is generated in the select transistor STB2 between times t2 and t3. Since the word line WL and dummy word line WLD on the upper sub-block USBLK side are in a floating state, they rise to, for example, voltage Vera through coupling with the semiconductor layer 41, to which voltage Vera is applied from the source line SL. In this state, holes generated by GIDL are injected into the charge storage layer 39 of the memory cell transistor MC and dummy memory cell transistor MCD on the lower sub-block LSBLK side within the selected block BLK. In other words, holes (erasing data) are supplied to the memory cell transistor MC and dummy memory cell transistor MCD of the lower sub-block LSBLK from the source line SL. On the other hand, the memory cell transistors MC and the dummy memory cell transistors MCD of the upper sub-block USBLK are not supplied with holes (data is not erased).

[0084] At time t3 , a refresh operation is performed, and the voltage VSS is applied to each wiring.

[0085] 4. Effects of this embodiment

[0086] According to the configuration of this embodiment, the processing capability of the semiconductor memory device can be improved. This effect will be described in detail.

[0087] For example, during an erase operation, when holes are supplied to each memory cell transistor MC in the NAND string NS from the source line SL, if the length of the semiconductor layer 41 in the memory column MP becomes longer, it is very likely that the holes will not be fully supplied to the memory cell transistor MC near the bit line BL. Therefore, the processing time of the erase operation may be prolonged. In addition, by injecting a large number of holes into the memory cell transistors MC near the source line SL, the threshold voltage of these memory cell transistors MC may be put into an over-erased state, which is significantly shifted toward the negative voltage side. When writing data to the memory cell transistors MC in the over-erased state, the processing time of the write operation may be longer than when writing data to the memory cell transistors MC with a threshold voltage of approximately 0V.

[0088] In this regard, if the configuration of this embodiment is used, the NAND string NS includes selection transistors STT1 and STB2 for generating GIDL during the erase operation, and selection transistors ST1 and ST2 for selecting the NAND string NS. Moreover, different voltages can be applied to the selection gate lines SGDT, SGD, SGSB, and SGS. Thus, during the erase operation, holes can be supplied to each memory cell transistor MC in the NAND string NS from the source line SL side and the bit line BL side. Therefore, the processing time of the erase operation can be shortened. Furthermore, since over-erasure can be suppressed, the increase in the processing time of the write operation can be suppressed. Therefore, the processing capacity of the semiconductor memory device can be improved.

[0089] Furthermore, with the configuration of this embodiment, holes can be supplied to each memory cell transistor MC within the NAND string NS from either the bit line BL side or the source line SL side. Therefore, a sub-block erase operation can be performed. In other words, an erase operation can be performed on a selective area within the block BLK.

[0090] Furthermore, since sub-block erase operations can be performed, for example, when garbage collection is performed before an erase operation, the amount of valid data moved to unused blocks BLK can be reduced. This can suppress increases in garbage collection processing time, thereby improving the processing capacity of the semiconductor memory device.

[0091] Furthermore, according to the configuration of this embodiment, an n-type semiconductor can be formed in the channel region of the selection transistor STT1 of the semiconductor layer 41. This allows efficient generation of a GIDL current in the selection transistor STT1.

[0092] 5. Modifications, etc.

[0093] The semiconductor memory device of the embodiment includes: a memory string (NS), including 1st to 4th selection transistors and 1st and 2nd memory cells, and is formed by sequentially connecting the 1st selection transistor (STT1), the 2nd selection transistor (ST1), the 1st memory cell (MC159), the 2nd memory cell (MC0), the 3rd selection transistor (ST2) and the 4th selection transistor (STB2) in series; 1st to 4th selection gate lines (SGDT, SGD, SGS, SGSB), respectively connected to the gates of the 1st to 4th transistors; 1st and 2nd word lines (WL159, WL0), respectively connected to the gates of the 1st and 2nd memory cells; a bit line (BL), connected to the 1st selection transistor; a source line (SL), connected to the 4th selection transistor; and a row decoder (12), configured to apply voltage to the 1st to 4th selection gate lines and the 1st and 2nd word lines. The erase operation includes a first mode (block erase mode) for erasing data in first and second memory cells, and a second mode (sub-block erase mode) for erasing data in one of the first and second memory cells. In the first mode, a first voltage (Vera) is applied to the bit line and source line, a second voltage (Verasgdt) lower than the first voltage is applied to the first select gate line to generate GIDL in the first select transistor, a third voltage (Vera) is applied to the second select gate line, a fourth voltage (Vera) is applied to the third select gate line, a fifth voltage (Verasgsb) lower than the first voltage is applied to the fourth select gate line to generate GIDL in the fourth select transistor, and a sixth voltage (VDD) lower than the first to fifth voltages is applied to the first and second word lines.

[0094] By applying the above-described embodiment, a semiconductor memory device capable of improving processing performance can be provided.

[0095] In addition, the embodiment is not limited to the above-described embodiment, and various modifications are possible.

[0096] Furthermore, the term “connected” in the above embodiments also includes an indirect connection with other components such as transistors or resistors interposed therebetween.

[0097] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are intended to be included within the scope and spirit of the invention and within the scope of the invention set forth in the claims and their equivalents.

[0098] [Explanation of Symbols]

[0099] 1 Semiconductor memory device

[0100] 10 Memory core

[0101] 11 Memory Cell Array

[0102] 12-line decoder

[0103] 13 Sense amplifier

[0104] 20 Peripheral circuit unit

[0105] 21 Sequencer

[0106] 22 Voltage Generating Circuit

[0107] 30 semiconductor substrate

[0108] 31 Insulation layer

[0109] 32~37, 45 wiring layers

[0110] 38 barrier insulating film

[0111] 39 Charge storage layer

[0112] 40 Tunnel insulating film

[0113] 41 semiconductor layer

[0114] 42 core layer

[0115] 43 top cover layer

[0116] 44 Contact plug.

Claims

1. A semiconductor memory device comprising: a memory string comprising a first selection transistor, a second selection transistor, a third selection transistor, a fourth selection transistor, a first memory cell, and a second memory cell, wherein the first selection transistor, the second selection transistor, the first memory cell, the second memory cell, the third selection transistor, and the fourth selection transistor are sequentially connected in series; a first selection gate line, a second selection gate line, a third selection gate line, and a fourth selection gate line, connected to gates of the first selection transistor, the second selection transistor, the third selection transistor, and the fourth selection transistor, respectively; A first word line and a second word line are connected to the gates of the first memory cell and the second memory cell, respectively; a bit line connected to the first selection transistor; a source line connected to the fourth selection transistor; as well as a row decoder configured to apply voltages to the first selection gate line, the second selection gate line, the third selection gate line, and the fourth selection gate line, and the first word line and the second word line; The erasing operation includes: a first mode for erasing data in the first storage unit and the second storage unit; and a second mode for erasing data in one of the first storage unit and the second storage unit; In the first mode, a first voltage is applied to the bit line and the source line, a second voltage lower than the first voltage and generating GIDL in the first selection transistor is applied to the first selection gate line, a third voltage is applied to the second selection gate line, a fourth voltage is applied to the third selection gate line, a fifth voltage lower than the first voltage and generating GIDL in the fourth selection transistor is applied to the fourth selection gate line, and a sixth voltage lower than the first voltage, the second voltage, the third voltage, the fourth voltage, and the fifth voltage is applied to the first word line and the second word line.

2. The semiconductor memory device according to claim 1, wherein in the second mode, when erasing data of the first memory cell, the first voltage is applied to the bit line and the source line, the second voltage is applied to the first selection gate line, the third voltage is applied to the second selection gate line, the fourth voltage is applied to the third selection gate line and the fourth selection gate line, and the sixth voltage is applied to the first word line, so that the second word line is in a floating state.

3. A semiconductor memory device according to claim 1 or 2, wherein in the second mode, when erasing data of the second memory cell, the first voltage is applied to the bit line and the source line, the third voltage is applied to the first and second selection gate lines, the fourth voltage is applied to the third selection gate line, the fifth voltage is applied to the fourth selection gate line, the first word line is placed in a floating state, and the sixth voltage is applied to the second word line.

4. The semiconductor memory device according to claim 1 or 2, wherein a channel of the first selection transistor uses a semiconductor doped with As or P. 5 . The semiconductor memory device according to claim 4 , wherein a channel of the second selection transistor uses a B-doped semiconductor. 6 . The semiconductor memory device according to claim 1 , wherein the first voltage, the third voltage, and the fourth voltage are the same.

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