Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device comprises a first semiconductor layer (21) and a second semiconductor layer (22). The first semiconductor layer (21) is an n-type layer made of a gallium oxide-based semiconductor. The second semiconductor layer (22) is made of a gallium oxide-based semiconductor, is in contact with the first semiconductor layer (21), and is an n-type layer having an electrically active donor concentration higher than that of the first semiconductor layer (21). The difference between the donor concentration of the first semiconductor layer (21) and the donor concentration of the second semiconductor layer (22) is smaller than the difference between the electrically active donor concentration of the first semiconductor layer (21) and the electrically active donor concentration of the second semiconductor layer (22).

Description

Technical Field

[0001] The technology disclosed herein relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Patent Document 1 discloses a semiconductor device made of a gallium oxide-based semiconductor. The semiconductor device includes an n-type semiconductor layer and an i-type semiconductor layer. The i-type semiconductor layer is formed on the n-type semiconductor layer by chemical vapor deposition (CVD). The donor concentration in the i-type semiconductor layer is lower than that in the n-type semiconductor layer.

[0003] Prior art literature

[0004] [Patent Document]

[0005] [Patent Document 1] JP 2019-041107 A Summary of the Invention

[0006] In a gallium oxide-based semiconductor such as that in Patent Document 1, cracks are easily generated at the interface of the semiconductor layer. In addition, in the semiconductor device of Patent Document 1, the difference in lattice constant between the n-type semiconductor layer with a high donor concentration and the i-type semiconductor layer with a low donor concentration is large. Since semiconductor layers with significantly different lattice constants are in contact with each other, high stress is generated at the interface between the n-type semiconductor layer and the i-type semiconductor layer. Therefore, in the semiconductor device of Patent Document 1, cracks are likely to be generated at the interface between the n-type semiconductor layer and the i-type semiconductor layer. For example, during the manufacturing process or use of the semiconductor device, when the temperature of the semiconductor substrate changes, cracks may be generated at the interface between the n-type semiconductor layer and the i-type semiconductor layer. This embodiment proposes a technology for suppressing cracks at the interface between two semiconductor layers with different carrier concentrations in a semiconductor device made of a gallium oxide-based semiconductor.

[0007] The semiconductor device disclosed in this embodiment includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer is an n-type semiconductor layer made of a gallium oxide-based semiconductor. The second semiconductor layer is also made of a gallium oxide-based semiconductor, is in contact with the first semiconductor layer, and is an n-type semiconductor layer having an electrically active donor concentration higher than that of the first semiconductor layer. The difference between the donor concentrations of the first semiconductor layer and the second semiconductor layer is smaller than the difference between the electrically active donor concentrations of the first semiconductor layer and the second semiconductor layer.

[0008] The gallium oxide-based semiconductor is a semiconductor made of a compound including gallium and oxygen, and includes, for example, Ga2O3, (InAlGa)2O3, and the like.

[0009] Furthermore, the electrically active donor concentration refers to the concentration of electrically active donors among the donors contained in the semiconductor.

[0010] In addition, in this embodiment, "the difference between the donor concentration of the first semiconductor layer and the donor concentration of the second semiconductor layer" and "the difference between the electrically active donor concentration of the first semiconductor layer and the electrically active donor concentration of the second semiconductor layer" refer to the absolute values ​​of the differences.

[0011] In this semiconductor device, the concentration of electrically active donors in the second semiconductor layer is higher than the concentration of electrically active donors in the first semiconductor layer. Therefore, the carrier concentration of the second semiconductor layer is higher than the carrier concentration of the first semiconductor layer. That is, the semiconductor device has a structure in which a first semiconductor layer and a second semiconductor layer having different carrier concentrations are in contact with each other. In addition, in this semiconductor device, the difference between the donor concentration of the first semiconductor layer and the donor concentration of the second semiconductor layer is smaller than the difference between the electrically active donor concentration of the first semiconductor layer and the electrically active donor concentration of the second semiconductor layer. That is, the difference in donor concentration between the first semiconductor layer and the second semiconductor layer is not as large as the difference in electrically active donor concentration between them. Therefore, the difference in lattice constant between the first semiconductor layer and the second semiconductor layer is small. Therefore, the stress generated at the interface between the first semiconductor layer and the second semiconductor layer is small. Therefore, the generation of cracks at the interface between the first semiconductor layer and the second semiconductor layer is suppressed. In this way, by providing an electrically active donor concentration difference between the first semiconductor layer and the second semiconductor layer while reducing the donor concentration difference therebetween, a carrier concentration difference is provided between the first semiconductor layer and the second semiconductor layer, and stress generated at the interface therebetween can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description made with reference to the accompanying drawings. In the accompanying drawings:

[0013] Figure 1 is a cross-sectional view of the semiconductor device 10;

[0014] Figure 2 is a diagram showing the distribution of the donor concentration and the electrically active donor concentration in the semiconductor substrate 12 in the stacking direction;

[0015] Figure 3 is a flow chart showing a manufacturing method of the first embodiment;

[0016] Figure 4 is a cross-sectional view of semiconductor substrate 12 before processing and a graph showing the distribution of donor concentration and electroactive donor concentration in the stacking direction;

[0017] Figure 5 is a graph showing the change in electroactive donor concentration caused by annealing;

[0018] Figure 6 is a flow chart showing a manufacturing method of the second embodiment;

[0019] Figure 7 is a flow chart showing a manufacturing method of the third embodiment;

[0020] Figure 8 is a graph showing the distribution of the donor concentration and the electroactive donor concentration in the stacking direction in the semiconductor substrate of the comparative example;

[0021] Figure 9 is a cross-sectional view showing an example in which the structure of this embodiment is applied to a junction barrier Schottky diode;

[0022] Figure 10 is a cross-sectional view showing an example in which the structure of the present embodiment is applied to a pn junction diode; and

[0023] Figure 11 is a cross-sectional view showing an example in which the structure of the present embodiment is applied to a MOSFET. DETAILED DESCRIPTION

[0024] The following lists the technical elements disclosed in this article. The following technical elements are useful independently.

[0025] In the exemplary semiconductor device disclosed in this embodiment, the first semiconductor layer may include a transition layer in contact with the second semiconductor layer, and a drift layer in contact with the transition layer and separated from the second semiconductor layer by the transition layer. The electrically active donor concentration of the second semiconductor layer may be 1×10 18 / cm 3 or higher. The concentration of electroactive donors in the transition layer can be less than 1×10 18 / cm 3The concentration of electrically active donors in the drift layer may be less than that in the transition layer. The concentration of electrically active donors in the transition layer may be distributed so as to decrease from the second semiconductor layer toward the drift layer. In the stacking direction of the second semiconductor layer, the transition layer, and the drift layer, the rate of change of the concentration of electrically active donors in the transition layer may be 1×10 per 1 μm. 15 / cm 3 or greater. In the stacking direction, the change rate of the electroactive donor concentration in the drift layer can be less than 1×10 per 1 μm 15 / cm 3 The thickness of the transition layer may be 0.1 μm or greater.

[0026] By providing a thick transition layer in which the concentration of electrically active donors at the interface between the first and second semiconductor layers varies in this manner, stress generated at the interface between the first and second semiconductor layers is more effectively suppressed.

[0027] The semiconductor device disclosed in this embodiment can be manufactured using the following manufacturing method. This manufacturing method may include annealing an n-type semiconductor substrate made of a gallium oxide-based semiconductor to reduce the concentration of electrically active donors in a portion of the semiconductor substrate. In this step, a first semiconductor layer and a second semiconductor layer may be formed in the semiconductor substrate, wherein the first semiconductor layer includes a region with a reduced concentration of electrically active donors, and the second semiconductor layer has a higher concentration of electrically active donors than the first semiconductor layer and is in contact with the first semiconductor layer.

[0028] According to this manufacturing method, the difference between the donor concentration of the first semiconductor layer and the donor concentration of the second semiconductor layer can be reduced to less than the difference between the electrically active donor concentration of the first semiconductor layer and the electrically active donor concentration of the second semiconductor layer. Therefore, cracks at the interface between the first and second semiconductor layers can be suppressed.

[0029] In the exemplary manufacturing method disclosed herein, the step of annealing the semiconductor substrate may include the step of annealing the semiconductor substrate in an atmosphere containing oxygen.

[0030] In the exemplary manufacturing method disclosed herein, the step of annealing the semiconductor substrate may include the steps of implanting oxygen ions into the semiconductor substrate and annealing the semiconductor substrate before the step of implanting oxygen ions.

[0031] In the exemplary manufacturing method disclosed herein, the step of annealing the semiconductor substrate may include the steps of implanting at least one ion selected from the group consisting of H, Li, Be, N, Na, Mg, P, S, K, Ca, Cr, Mn, Fe, Co, Ni, Cu, Zn, As, Se, Rb, Sr, Ru, Rh, Pd, Ag, Cd, Sb, Te, Cs, Ba, Ir, Pt, Au, Hg, Ti, Pb, Bi, Po, Fr, and Ra into the semiconductor substrate, and annealing the semiconductor substrate after the step of implanting the at least one ion into the semiconductor substrate.

[0032] According to these manufacturing methods, the concentration of electrically active donors in a portion of the region (region to be the first semiconductor layer) in the semiconductor substrate can be reduced while suppressing a decrease in the donor concentration in the region.

[0033] In the manufacturing method of the example disclosed in this embodiment, the semiconductor substrate may be made of a β-type gallium oxide-based semiconductor. In this case, the interface between the first semiconductor layer and the second semiconductor layer may extend along the (001) plane or the (100) plane.

[0034] In β-type gallium oxide-based semiconductors, cleavage is likely to occur along the (001) or (100) plane. By applying the technology disclosed in this embodiment to a first semiconductor layer and a second semiconductor layer in which the interface extends along the (001) or (100) plane, stress generation at the interface, where cracks are likely to occur, can be suppressed.

[0035] (First embodiment)

[0036] Figure 1 The semiconductor device 10 shown in FIG is a Schottky barrier diode. The semiconductor device 10 includes a semiconductor substrate 12, an upper electrode 30, and a lower electrode 32. The semiconductor substrate 12 is made of β-type gallium oxide (β-Ga2O3). The semiconductor substrate 12 can also be made of another gallium oxide-based semiconductor (e.g., α-Ga2O3, (InAlGa)2O3, etc.). The upper electrode 30 contacts the upper surface 12a of the semiconductor substrate 12. The lower electrode 32 contacts the lower surface 12b of the semiconductor substrate 12.

[0037] The semiconductor substrate 12 includes a first semiconductor layer 21 and a second semiconductor layer 22. The first semiconductor layer 21 and the second semiconductor layer 22 are n-type. The first semiconductor layer 21 is disposed on the second semiconductor layer 22. Hereinafter, the interface between the first semiconductor layer 21 and the second semiconductor layer 22 is referred to as the interface 23. The first semiconductor layer 21 and the second semiconductor layer 22 include at least one of Si (silicon), Sn (tin), and Ge (germanium) as a donor. As will be described in detail later, the concentration of the electrically active donor in the second semiconductor layer 22 is higher than the concentration of the electrically active donor in the first semiconductor layer 21.

[0038] The second semiconductor layer 22 is disposed within a region including the lower surface 12b of the semiconductor substrate 12. The lower electrode 32 is in ohmic contact with the second semiconductor layer 22. The first semiconductor layer 21 includes a transition layer 24 and a drift layer 26. The transition layer 24 is disposed on the second semiconductor layer 22. The drift layer 26 is disposed on the transition layer 24. In other words, the transition layer 24 is disposed between the drift layer 26 and the second semiconductor layer 22. The transition layer 24 is in contact with the second semiconductor layer 22 and with the drift layer 26. The drift layer 26 is separated from the second semiconductor layer 22 by the transition layer 24. The electroactive donor concentration of the transition layer 24 is lower than that of the second semiconductor layer 22. The electroactive donor concentration of the drift layer 26 is lower than that of the transition layer 24. The drift layer 26 is disposed within a region including the upper surface 12a of the semiconductor substrate 12. The upper electrode 30 is in Schottky contact with the drift layer 26.

[0039] The Schottky barrier diode is composed of an upper electrode 30, a lower electrode 32, and a semiconductor substrate 12. When the potential of the upper electrode 30 is higher than the potential of the lower electrode 32, the Schottky barrier diode is turned on, and when the potential of the upper electrode 30 is lower than the potential of the lower electrode 32, the Schottky barrier diode is turned off. When the Schottky barrier diode is turned on, current flows from the upper electrode 30 to the lower electrode 32 via the drift layer 26, the transition layer 24, and the second semiconductor layer 22. In this way, when the Schottky barrier diode is turned on, current flows along the thickness direction of the semiconductor substrate 12. The electrical characteristics of the semiconductor substrate 12 change according to the relationship between the direction of current flow and the crystal orientation of the semiconductor substrate 12. The upper surface 12a of the semiconductor substrate 12 extends along the (001) plane or the (100) plane. As a result, the occurrence of loss in the path of the current flowing in the thickness direction of the semiconductor substrate 12 is suppressed.

[0040] Figure 2The distribution of donor concentration and the distribution of electrically active donor concentration in the stacking direction (hereinafter referred to as the stacking direction) of the second semiconductor layer 22, the transition layer 24 and the drift layer 26 are shown. The donor concentration is the concentration of donors (i.e., Si, Sn and Ge) included in the semiconductor substrate 12. The donors included in the semiconductor substrate 12 include electrically active donors and electrically inactive donors. Electrically active donors are donors that contribute to the generation of electrons as carriers. Inactive donors are donors that do not contribute to the generation of electrons as carriers. The electrically active donor concentration is the concentration of electrically active donors contained in the semiconductor substrate 12. As shown in FIG. Figure 2 As shown, the concentration of electrically active donors in the second semiconductor layer 22 is 1×10 18 / cm 3 or higher, the concentration of electrically active donors in the first semiconductor layer 21 is less than 1×10 18 / cm 3 In the second semiconductor layer 22, the concentration of electrically active donors is distributed at a substantially constant value. In the drift layer 26, the concentration of electrically active donors is close to 1×10 16 / cm 3 In the drift layer 26, the electroactive donor concentration is distributed at a substantially constant value. Therefore, in the stacking direction, the variation rate of the electroactive donor concentration in the drift layer 26 is less than 1×10 per 1 μm. 15 / cm 3 In the transition layer 24, the concentration of the electrically active donors decreases from the second semiconductor layer 22 toward the drift layer 26. In the stacking direction, the change rate of the concentration of the electrically active donors in the transition layer 24 is 1×10 15 / cm 3 As described above, the transition layer 24 is a layer in which the concentration of the electrically active donor changes between the drift layer 26 and the second semiconductor layer 22. The thickness of the transition layer 24 is 0.1 μm or more. Figure 2 The reference symbol ΔCad in represents the difference between the electrically active donor concentration of the first semiconductor layer 21 and the electrically active donor concentration of the second semiconductor layer 22. As described above, the concentration of electrically active donors in the first semiconductor layer 21 (particularly the drift layer 26) is much lower than the concentration of electrically active donors in the second semiconductor layer 22. Therefore, the difference ΔCad in the electrically active donor concentration is large.

[0041] like Figure 2 As shown, in the second semiconductor layer 22, the transition layer 24 and the drift layer 26, the donor concentration is 1×10 18 / cm 3The donor concentration of the first semiconductor layer 21 is substantially equal to or greater than the donor concentration of the second semiconductor layer 22. That is, the donor concentrations of the second semiconductor layer 22, the transition layer 24, and the drift layer 26 are substantially equal. Therefore, the difference ΔCd between the donor concentration of the first semiconductor layer 21 and the donor concentration of the second semiconductor layer 22 is substantially zero. Therefore, the difference ΔCd between the donor concentration of the first semiconductor layer 21 and the donor concentration of the second semiconductor layer 22 is less than the difference ΔCad between the electrically active donor concentration of the first semiconductor layer 21 and the electrically active donor concentration of the second semiconductor layer 22. In the second semiconductor layer 22, the electrically active donor concentration is substantially equal to the donor concentration. In the first semiconductor layer 21, the electrically active donor concentration is lower than the donor concentration.

[0042] As described above, in the semiconductor device 10, the difference ΔCd between the donor concentration of the first semiconductor layer 21 and the donor concentration of the second semiconductor layer 22 is substantially zero. Therefore, the difference in lattice constant between the first semiconductor layer 21 and the second semiconductor layer 22 is extremely small. Consequently, the stress generated at the interface 23 between the first semiconductor layer 21 and the second semiconductor layer 22 (i.e., the interface between the transition layer 24 and the second semiconductor layer 22) is small. Thus, by increasing the electrically active donor concentration difference ΔCad between the first semiconductor layer 21 and the second semiconductor layer 22 while reducing the donor concentration difference ΔCd between the first semiconductor layer 21 and the second semiconductor layer 22, the stress applied to the interface 23 can be suppressed while providing a difference in electrical characteristics between the first semiconductor layer 21 and the second semiconductor layer 22. Therefore, cracks are less likely to occur at the interface 23. As described above, the upper surface 12a of the semiconductor substrate 12 is a (001) plane or a (100) plane. Therefore, the interface 23 extends along the (001) plane or the (100) plane. In β-type gallium oxide, cleavage may occur along the (001) plane or the (100) plane. Therefore, when stress is applied to the interface 23, cracks may occur. By suppressing the stress applied to the interface 23 where cracks may occur, the reliability of the semiconductor device 10 is greatly improved. In addition, in the semiconductor device 10, the transition layer 24 in which the concentration of the electroactive donor changes significantly at the interface 23 has a thickness of 0.1 μm or more. By providing the transition layer 24 thicker in this way, the stress applied to the interface 23 can be more effectively suppressed. Therefore, the generation of cracks at the interface 23 can be more effectively suppressed.

[0043] Next, a method for manufacturing the semiconductor device 10 will be described. Figure 3 In the manufacturing method of the first embodiment shown, first, in step S2, a semiconductor substrate 12 made of β-type gallium oxide is prepared. Figure 4 As shown, a semiconductor substrate 12 is prepared, and the entire semiconductor substrate 12 has 1×10 18 / cm 3 or higher electroactive donor concentration and 1×1018 / cm 3 or higher donor concentration. Figure 4 Throughout the semiconductor substrate 12, the electrically active donor concentration and the donor concentration are distributed at substantially constant values. Figure 4 The upper surface 12a of the semiconductor substrate 12 is formed of a (001) plane or a (100) plane.

[0044] Next, in step S4, Figure 4 The semiconductor substrate 12 is annealed in an oxygen-containing atmosphere. An oxygen-containing atmosphere refers to an atmosphere containing oxygen as an element. For example, the semiconductor substrate 12 can be annealed in an atmosphere of oxygen, water vapor, or the like. Here, the semiconductor substrate 12 is annealed in a state where the upper surface 12a of the semiconductor substrate 12 is exposed to an oxygen-containing atmosphere. Then, oxygen diffuses from the upper surface 12a into the semiconductor substrate 12. When oxygen atoms diffuse into the gallium oxide semiconductor, oxygen affects the donors and the donors no longer provide electrons as carriers. That is, oxygen deactivates the donors. As a result, the concentration of electrically active donors in the region where oxygen diffuses in the semiconductor substrate 12 decreases. Here, the concentration of electrically active donors in the region near the upper surface 12a of the semiconductor substrate 12 decreases.

[0045] Figure 5 1 and 2 show the results of an experiment in which the semiconductor substrate 12 was annealed in oxygen as an example of the above-mentioned annealing step. Figure 5 In each graph of FIG, the vertical axis represents the depth of the semiconductor substrate 12 from the upper surface 12a, and the horizontal axis represents the concentration of the electrically active donor. Figure 5 As shown in (a), before annealing, the concentration of the electrically active donors in the semiconductor substrate 12 is about 2×10 16 / cm 3 .like Figure 5 As shown in (b), in the sample annealed at 1000°C for 5 minutes, the concentration of the electrically active donors in the semiconductor substrate 12 is reduced to about 7×10 15 / cm 3 In addition, if Figure 5 As shown in (c) and (d), the concentration of electrically active donors in the semiconductor substrate 12 is reduced to about 1×10 15 / cm3. In addition, Figure 5 In (c) and (d), the concentration of the electrically active donors decreases at deeper positions. As described above, annealing in oxygen can reduce the concentration of the electrically active donors in the semiconductor substrate 12.

[0046] As described above, by annealing the semiconductor substrate 12 in an oxygen-containing atmosphere, the concentration of electrically active donors can be reduced in a portion of the semiconductor substrate 12. The region where the concentration of electrically active donors is reduced during the annealing step provides the drift layer 26. In addition, the region where the concentration of electrically active donors is not reduced provides the second semiconductor layer 22. Furthermore, a transition layer 24 in which the concentration of electrically active donors varies along the stacking direction is formed between the drift layer 26 and the second semiconductor layer 22. Therefore, as Figure 2 As shown, the concentration of electrically active donors in the drift layer 26, the transition layer 24, and the second semiconductor layer 22 can be distributed. In addition, during this annealing step, the donors in the first semiconductor layer 21 become inactive, while the inactive donors remain in the first semiconductor layer 21. Therefore, as Figure 2 As shown, in the first semiconductor layer 21 , the concentration of the electrically active donors is reduced, but the concentration of the donors is hardly reduced.

[0047] Next, in step S6, an upper electrode 30 and a lower electrode 32 are formed on the surface of the semiconductor substrate 12. Thus, the semiconductor device 10 is completed.

[0048] As described above, according to the manufacturing method of the first embodiment, the electrically active donor concentration in the first semiconductor layer 21 (i.e., the drift layer 26 and the transition layer 24) is reduced while the donor concentration is hardly reduced. Therefore, there is almost no difference in the donor concentration between the first semiconductor layer 21 and the second semiconductor layer 22, and the stress applied to the interface 23 between the first semiconductor layer 21 and the second semiconductor layer 22 can be reduced. In addition, according to this manufacturing method, the electrically active donor concentration can be distributed between the first semiconductor layer 21 and the second semiconductor layer 22 so that the electrically active donor concentration changes relatively slowly. The transition layer 24 can be formed relatively thick. As a result, the stress applied to the interface 23 can be more effectively reduced. Therefore, the manufacturing method according to the first embodiment can suppress the generation of cracks at the interface 23.

[0049] (Second embodiment)

[0050] Next, a manufacturing method of the second embodiment will be described as a manufacturing method of the semiconductor device 10. Figure 6 In the manufacturing method of the second embodiment shown, first, in step S2, a Figure 4The semiconductor substrate 12 is formed. Next, in step S4a, oxygen ions are implanted into the upper surface 12a of the semiconductor substrate 12. Here, the oxygen ions are implanted into a depth range corresponding to the drift layer 26. Next, in step S4b, the semiconductor substrate 12 is annealed. In step S4b, for example, the semiconductor substrate 12 can be annealed in an inert gas. When the semiconductor substrate 12 is annealed, the oxygen implanted into the semiconductor substrate 12 in step S4a affects the donors, and the donors become inactive. This reduces the concentration of electrically active donors in the region where the oxygen was implanted.

[0051] As described above, by implanting oxygen ions into the semiconductor substrate 12 in step S4a and annealing the semiconductor substrate 12 in step S4b, the concentration of the electrically active donors is reduced in a portion of the semiconductor substrate 12. The region where the concentration of the electrically active donors is reduced in the annealing step provides the drift layer 26. In addition, the region where the concentration of the electrically active donors is not reduced provides the second semiconductor layer 22. In addition, the transition layer 24 in which the concentration of the electrically active donors varies along the stacking direction is formed between the drift layer 26 and the second semiconductor layer 22. Therefore, as Figure 2 As shown, the concentration of electrically active donors in the drift layer 26, the transition layer 24, and the second semiconductor layer 22 can be distributed. In addition, during this annealing step, the donors in the first semiconductor layer 21 become inactive, while the inactive donors remain in the first semiconductor layer 21. Therefore, as Figure 2 As shown, the concentration of the electrically active donors decreases in the first semiconductor layer 21, but the concentration of the donors hardly decreases. Thereafter, the semiconductor device 10 is completed by forming the upper electrode 30 and the lower electrode 32 in step S6 in the same manner as in the first embodiment.

[0052] As described above, according to the manufacturing method of the second embodiment, the concentration of electrically active donors in the first semiconductor layer 21 (i.e., the drift layer 26 and the transition layer 24) is reduced while the donor concentration is barely reduced. Furthermore, according to this manufacturing method, the transition layer 24 can be formed thicker. Consequently, the stress applied to the interface 23 can be reduced. Therefore, according to the manufacturing method of the second embodiment, the generation of cracks at the interface 23 can be suppressed.

[0053] (Third embodiment)

[0054] Next, a manufacturing method of the third embodiment will be described as a manufacturing method of the semiconductor device 10. Figure 7 In the manufacturing method of the third embodiment shown, first, in step S2, the same method as in the first embodiment is used to prepare Figure 4The semiconductor substrate 12 is formed. Next, in step S4c, ions are implanted into the upper surface 12a of the semiconductor substrate 12. Here, ions that act as acceptors in gallium oxide-based semiconductors are implanted. The implanted ions are at least one ion selected from the group consisting of H, Li, Be, N, Na, Mg, P, S, K, Ca, Cr, Mn, Fe, Co, Ni, Cu, Zn, As, Se, Rb, Sr, Ru, Rh, Pd, Ag, Cd, Sb, Te, Cs, Ba, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, and Ra. These elements behave similarly to acceptors in gallium oxide-based semiconductors. Next, in step S4d, the semiconductor substrate 12 is annealed. In step S4d, for example, the semiconductor substrate 12 can be annealed in an inert gas. When the semiconductor substrate 12 is annealed, the elements implanted into the semiconductor substrate 12 are activated in step S4c and behave like acceptors, which reduces the concentration of electrically active donors in the ion implantation region in step S4c.

[0055] As described above, by implanting ions into the semiconductor substrate 12 in step S4c and annealing the semiconductor substrate 12 in step S4d, the concentration of the electrically active donors in a portion of the semiconductor substrate 12 is reduced. The region where the concentration of the electrically active donors is reduced in the annealing step provides the drift layer 26. In addition, the region where the concentration of the electrically active donors is not reduced provides the second semiconductor layer 22. In addition, the transition layer 24 in which the concentration of the electrically active donors varies along the stacking direction is formed between the drift layer 26 and the second semiconductor layer 22. Therefore, as Figure 2 As shown, the concentration of electrically active donors in the drift layer 26, the transition layer 24 and the second semiconductor layer 22 can be distributed. Figure 2 As shown, the electrically active donor concentration can be reduced without almost decreasing the donor concentration in the drift layer 26 and the transition layer 24. Thereafter, the semiconductor device 10 is completed by forming the upper electrode 30 and the lower electrode 32 in step S6 in the same manner as in the first embodiment.

[0056] As described above, according to the manufacturing method of the third embodiment, the concentration of electrically active donors in the first semiconductor layer 21 (i.e., the drift layer 26 and the transition layer 24) is reduced while the donor concentration is barely reduced. Furthermore, according to this manufacturing method, the transition layer 24 can be formed thicker. Consequently, the stress applied to the interface 23 can be reduced. Therefore, the manufacturing method of the third embodiment can suppress the generation of cracks at the interface 23.

[0057] Comparative Example

[0058] Next, the manufacturing method of the comparative example will be described. In the manufacturing method of the comparative example, Figure 8As shown, a semiconductor substrate 60 corresponding to the second semiconductor layer 22 is prepared, and a drift layer 26 having a donor concentration lower than that of the semiconductor substrate 60 is formed on the semiconductor substrate 60 by epitaxial growth (e.g., CVD). When a semiconductor device is manufactured by this manufacturing method, the distributions of the donor concentration and the electrically active donor concentration in the second semiconductor layer 22 and the drift layer 26 are substantially the same. Therefore, at the interface 23x between the second semiconductor layer 22 and the drift layer 26, not only the electrically active donor concentration but also the donor concentration changes sharply. Therefore, the difference in lattice constant between the second semiconductor layer 22 and the drift layer 26 is large, and high stress is applied to the interface 23x. In addition, when the drift layer 26 is formed by epitaxial growth, mutual diffusion of donors cannot occur between the drift layer 26 and the second semiconductor layer 22. Therefore, the rate of change of the donor concentration at the interface 23x between the drift layer 26 and the second semiconductor layer 22 becomes extremely high. As a result, the thickness of the transition layer 24 between the drift layer 26 and the second semiconductor layer 22 becomes extremely thin (at Figure 8 , the thickness of the transition layer 24 is substantially zero). Therefore, stress is more likely to be applied to the interface 23x. In addition, when the drift layer 26 is formed by epitaxial growth, the crystal continuity between the drift layer 26 and the second semiconductor layer 22 is not very high, so that the strength of the interface 23x is not very high. Since the interface 23x having low strength is subjected to high stress as described above, cracks are likely to occur at the interface 23x in the manufacturing method of the comparative example. According to the manufacturing methods of the first to third embodiments described above, a difference in donor concentration is unlikely to occur between the first semiconductor layer 21 and the second semiconductor layer 22. In addition, according to the manufacturing methods of the first to third embodiments, a thick transition layer 24 can be formed. In addition, in the manufacturing methods of the first to third embodiments, since the second semiconductor layer 22 to the drift layer 26 are continuously formed in the bulk semiconductor, the strength of the interface 23 is high. Therefore, compared with the manufacturing method of the comparative example, the manufacturing methods according to the first to third embodiments can suppress the generation of cracks at the interface 23.

[0059] Furthermore, in the manufacturing method of the comparative example, epitaxial growth of the drift layer 26 requires a long time. Furthermore, epitaxial growth requires high temperatures. Therefore, the manufacturing method of the comparative example results in a high manufacturing cost for the semiconductor device. On the other hand, in the manufacturing methods of the first to third embodiments, since epitaxial growth is not used to form the drift layer 26, the semiconductor device 10 can be manufactured at a low cost.

[0060] Furthermore, in the manufacturing method of the comparative example, when epitaxially growing the drift layer 26, crystal defects may grow along the growth direction. Consequently, defects extending along the thickness direction of the drift layer 26 may occur. On the other hand, in the manufacturing methods of the first to third embodiments, since the drift layer 26 is not formed by epitaxial growth, the generation of defects in the drift layer 26 can be suppressed.

[0061] Furthermore, in the manufacturing method of the comparative example, when epitaxially growing the drift layer 26, the donor concentration may vary within the plane. On the other hand, in the manufacturing methods of the first to third embodiments, since the drift layer 26 is formed without epitaxial growth, variations in the donor concentration and the electrically active donor concentration within the plane of the drift layer 26 can be suppressed.

[0062] In the above embodiments, the Schottky barrier diode has been described as the semiconductor device 10. Alternatively, the technology disclosed herein may be applied to other semiconductor devices. For example, Figure 9 As shown, a junction barrier Schottky diode can be constructed by partially providing a p-type layer 80 in a range in contact with the upper electrode 30. In addition, for example, Figure 10 As shown in FIG. 1 , a pn junction diode can be constructed by providing a p-type layer 82 in the entire range in contact with the upper electrode 30. Figure 11 As shown, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is provided by providing a p-type body layer 90 , an n-type source layer 92 , a gate electrode 94 , a source electrode 96 , etc. on the drift layer 26 . Figures 9 to 11 The p-type layers of the semiconductor device shown in FIG. 4 can be formed by p-type ion implantation, embedded epitaxial growth, etc. These p-type layers can be made of a material different from that of the drift layer 26. Figure 11 The source layer 92 can be formed by n-type ion implantation, or can be formed by reactivating the donor by local annealing in an inert atmosphere. In addition, the technology disclosed in this embodiment can be applied to other semiconductor devices such as JFET (junction field effect transistor) and HEMT (high electron mobility transistor).

[0063] Furthermore, in the above-described embodiment, the donor concentration is equal between the first semiconductor layer 21 and the second semiconductor layer 22. Alternatively, the donor concentration of the first semiconductor layer 21 may be higher than that of the second semiconductor layer, and the donor concentration of the first semiconductor layer 21 may be lower than that of the second semiconductor layer 22. As long as the condition "the difference ΔCa between the donor concentration of the first semiconductor layer 21 and the donor concentration of the second semiconductor layer 22 is less than the difference ΔCad between the electrically active donor concentration of the first semiconductor layer 21 and the electrically active donor concentration of the second semiconductor layer 22" is satisfied, the donor concentration of the first semiconductor layer 21 and the donor concentration of the second semiconductor layer 22 may be distributed in any manner.

[0064] Furthermore, the above-described steps in the manufacturing direction of the first to third embodiments may be combined and performed.

[0065] Although several embodiments have been described in detail above, these embodiments are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and variations of the above-mentioned specific examples. The technical elements described in this specification or the drawings demonstrate technical utility individually or in various combinations and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technology illustrated in this specification or the drawings achieves multiple objectives simultaneously, and achieving one of these objectives itself has technical utility.

[0066] Although the present disclosure has been described with reference to the embodiments of the present disclosure, it should be understood that the present disclosure is not limited to these embodiments and configurations. The present disclosure is intended to cover various modifications and equivalent arrangements. In addition, although various combinations and configurations, other combinations and configurations including more, less, or only a single element are also within the spirit and scope of the present disclosure.

Claims

1. A semiconductor device comprising: a first semiconductor layer (21) having an N conductive type and made of a gallium oxide-based semiconductor; and A second semiconductor layer (22) made of a gallium oxide-based semiconductor, in contact with the first semiconductor layer (21), and having an N conductive type with an electrically active donor concentration higher than that of the first semiconductor layer (21), wherein: The difference between the donor concentration of the first semiconductor layer (21) and the donor concentration of the second semiconductor layer (22) is smaller than the difference between the electrically active donor concentration of the first semiconductor layer (21) and the electrically active donor concentration of the second semiconductor layer (22), wherein: The first semiconductor layer (21) comprises: a transition layer (24) in contact with the second semiconductor layer (22); and a drift layer (26) in contact with the transition layer (24) and separated from the second semiconductor layer (22) by the transition layer (24); The electroactive donor concentration of the second semiconductor layer (22) is 1×10 18 / cm 3 or higher; The electroactive donor concentration in the transition layer (24) is less than 1×10 18 / cm 3 ; The drift layer (26) has an electroactive donor concentration that is less than the electroactive donor concentration of the transition layer (24); The concentration of electrically active donors in the transition layer (24) is distributed to decrease from the second semiconductor layer (22) toward the drift layer (26); In the stacking direction of the second semiconductor layer (22), the transition layer (24) and the drift layer (26), the change rate of the electroactive donor concentration in the transition layer (24) is 1×10 15 / cm 3 or greater; In the stacking direction, the change rate of the electroactive donor concentration in the drift layer (26) is less than 1×10 15 / cm 3 ;and The transition layer (24) has a thickness of 0.1 μm or greater.

2. A method for manufacturing a semiconductor device, comprising: Reducing the concentration of electrically active donors in a portion of a semiconductor substrate (12) having an N conductive type and made of a gallium oxide-based semiconductor by annealing the semiconductor substrate (12); and A first semiconductor layer (21) provided by a region having a reduced electrically active donor concentration and a second semiconductor layer (22) having a higher electrically active donor concentration than the first semiconductor layer (21) and in contact with the first semiconductor layer (21) are formed in the semiconductor substrate (12), wherein: The first semiconductor layer (21) comprises: a transition layer (24) in contact with the second semiconductor layer (22); and a drift layer (26) in contact with the transition layer (24) and separated from the second semiconductor layer (22) by the transition layer (24); The electroactive donor concentration of the second semiconductor layer (22) is 1×10 18 / cm 3 or higher; The electroactive donor concentration in the transition layer (24) is less than 1×10 18 / cm 3 ; The drift layer (26) has an electroactive donor concentration that is less than the electroactive donor concentration of the transition layer (24); The concentration of electrically active donors in the transition layer (24) is distributed to decrease from the second semiconductor layer (22) toward the drift layer (26); In the stacking direction of the second semiconductor layer (22), the transition layer (24) and the drift layer (26), the change rate of the electroactive donor concentration in the transition layer (24) is 1×10 15 / cm 3 or greater; In the stacking direction, the change rate of the electroactive donor concentration in the drift layer (26) is less than 1×10 15 / cm 3 ;and The transition layer (24) has a thickness of 0.1 μm or greater.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: Annealing the semiconductor substrate (12) includes annealing the semiconductor substrate (12) in an oxygen-containing atmosphere.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: Annealing the semiconductor substrate (12) includes: implanting oxygen ions into the semiconductor substrate (12); and After the oxygen ions are implanted, the semiconductor substrate (12) is annealed.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: Annealing the semiconductor substrate (12) includes: implanting at least one ion selected from the group consisting of H, Li, Be, N, Na, Mg, P, S, K, Ca, Cr, Mn, Fe, Co, Ni, Cu, Zn, As, Se, Rb, Sr, Ru, Rh, Pd, Ag, Cd, Sb, Te, Cs, Ba, Ir, Pt, Au, Hg, Tl, Pb, Bi, Po, Fr, and Ra into the semiconductor substrate (12); and After implanting the at least one ion into the semiconductor substrate (12), the semiconductor substrate (12) is annealed.

6. The method for manufacturing a semiconductor device according to any one of claims 2 to 5, wherein: The semiconductor substrate (12) is made of a β-type gallium oxide-based semiconductor.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The interface between the first semiconductor layer (21) and the second semiconductor layer (22) extends along the (001) plane or the (100) plane.

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