A VDMOS ceramic packaging structure

Abstract

The application discloses a VDMOS ceramic packaging structure, comprising a first metal frame, a second metal frame, a ceramic shell, a heat-conducting integrated cover plate and a VDMOS chip; wherein the first metal frame comprises a first supporting section, a first upper horizontal section and a first lower horizontal section; and the second metal frame comprises a second supporting section, a second upper horizontal section and a second lower horizontal section. The application can guarantee excellent electrical and heat dissipation performance of the device and greatly improve the reliability under harsh environments such as high temperature and high humidity.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor packaging, and in particular relates to a VDMOS ceramic packaging structure. Background Art

[0002] High-power VDMOS devices have high operating current and power consumption, requiring low on-resistance, strong current-carrying capacity, and excellent heat dissipation in their packaging. Therefore, a common solution is to use a frame-type plastic encapsulation process. However, in harsh environments such as high temperature and high humidity, the reliability of plastic-encapsulated devices cannot meet these requirements. Ceramic packaging offers significant advantages in these areas.

[0003] However, existing ceramic packaging structures utilize printed wiring and laminated sintering processes. The thin wiring layers within the package cannot meet high current carrying requirements, often leading to failures due to melting. Furthermore, the wiring within the ceramic housing is made of highly resistive materials such as W / Mo, resulting in high on-resistance paths that significantly impact VDMOS device performance. These shortcomings restrict the application of ceramic packaging in high-current devices.

[0004] Currently, neither plastic packaging nor ceramic packaging can simultaneously take into account both reliability and performance, which seriously affects the application of VDMOS devices in high-reliability fields. Summary of the Invention

[0005] The technical problem solved by the present invention is to overcome the deficiencies of the prior art and provide a VDMOS ceramic packaging structure that greatly improves the reliability in harsh environments such as high temperature and high humidity while ensuring excellent electrical and heat dissipation performance of the device.

[0006] The object of the present invention is achieved through the following technical solutions: A VDMOS ceramic packaging structure, comprising: a first metal frame, a second metal frame, a ceramic housing, a heat-conducting integrated cover plate and a VDMOS chip; wherein the first metal frame comprises a first supporting section, a first upper transverse section and a first lower transverse section; wherein one end of the first upper transverse section is connected to the top of the first supporting section; one end of the first lower transverse section is connected to the middle of the first supporting section; the other end of the first upper transverse section passes through a side wall of the ceramic housing and is connected to the upper part of one end of the VDMOS chip; the other end of the first lower transverse section passes through a side wall of the ceramic housing and is connected to one end of the VDMOS chip The second metal frame includes a second supporting section, a second upper transverse section and a second lower transverse section; wherein, one end of the second upper transverse section is connected to the top of the second supporting section; one end of the second lower transverse section is connected to the middle of the second supporting section; the other end of the second upper transverse section passes through the other side wall of the ceramic shell and is connected to the upper part of the other end of the VDMOS chip; the other end of the second lower transverse section passes through the other side wall of the ceramic shell and is connected to the lower part of the other end of the VDMOS chip; the thermal conductive integrated cover plate is arranged at the opening of the ceramic shell, and the lower end of the thermal conductive integrated cover plate is connected to the upper surface of the VDMOS chip.

[0007] In the above-mentioned VDMOS ceramic packaging structure, the other end of the first upper transverse section passes through a side wall of the ceramic housing and is connected to the upper portion of one end of the VDMOS chip via a solder joint; the other end of the first lower transverse section passes through a side wall of the ceramic housing and is connected to the lower portion of one end of the VDMOS chip via a solder joint; the other end of the second upper transverse section passes through the other side wall of the ceramic housing and is connected to the upper portion of the other end of the VDMOS chip via a solder joint; and the other end of the second lower transverse section passes through the other side wall of the ceramic housing and is connected to the lower portion of the other end of the VDMOS chip via a solder joint.

[0008] In the above VDMOS ceramic packaging structure, the thermally conductive integrated cover plate is arranged at the opening of the ceramic housing by adhesive, and the lower end of the thermally conductive integrated cover plate is connected to the upper surface of the VDMOS chip by adhesive.

[0009] In the above-mentioned VDMOS ceramic packaging structure, the first metal frame and the second metal frame are both made of Kovar or copper materials, and the surfaces of the first metal frame and the second metal frame are both plated with nickel and gold.

[0010] In the above VDMOS ceramic packaging structure, the cross-sections of the first metal frame and the second metal frame are both circular or rectangular, and the cross-sectional area should meet 0.06mm 2 ~0.6mm 2 .

[0011] In the VDMOS ceramic packaging structure, the ceramic shell processing adopts a multilayer ceramic lamination process, the first metal frame and the second metal frame are compacted with a ceramic sheet, and are formed through sintering.

[0012] In the VDMOS ceramic packaging structure, the interconnection between the VDMOS chip and the first metal frame and the second metal frame adopts a solder coating reflow soldering process.

[0013] In the VDMOS ceramic packaging structure, during the VDMOS chip welding process, the solder is coated on the corresponding pad of the VDMOS chip, the VDMOS chip is placed at the corresponding position of the first metal frame and the second metal frame, and finally heating reflow is formed to form a firm welding point.

[0014] In the VDMOS ceramic packaging structure, the heat-conducting integrated cover plate is made of Kovar or copper material, and the surface of the heat-conducting integrated cover plate is plated with nickel and gold.

[0015] In the VDMOS ceramic packaging structure, during the bonding process of the heat-conducting integrated cover plate, the bonding glue is coated on the upper side of the VDMOS chip and the position of the ceramic shell sealing ring, the heat-conducting integrated cover plate is aligned and placed at the corresponding position, the heat-conducting area of the heat-conducting integrated cover plate is ensured to contact the surface of the VDMOS chip, and the sealing area of the heat-conducting integrated cover plate is ensured to contact the surface of the ceramic shell, and finally the bonding is formed in the two areas at the same time through high-temperature curing.

[0016] Compared with the prior art, the present application has the following beneficial effects:

[0017] (1) The present application uses a rough metal frame to replace a ceramic printed wiring, and embeds the frame into a ceramic body through a lamination process, and the frame as a current path can significantly improve the large current carrying capacity of the package;

[0018] (2) The present application uses a welding process to realize the interconnection of VDMOS and the frame, and the VDMOS source and drain are directly connected to the external path, so that the overall on-resistance is significantly reduced;

[0019] (3) The present application uses a direct contact cover plate, so that the heat of the device is directly and effectively conducted to the top of the package, and the thermal resistance of the device is significantly reduced;

[0020] (4) Compared with the same type of plastic package, this structure can greatly improve the reliability in harsh environments such as high temperature and high humidity while ensuring excellent electrical and heat dissipation performance of the device;

[0021] (5) The packaging process steps of the present application are simple, which reduces the time of chip bonding and curing, and greatly improves the packaging process efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0022] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0023] Figure 1 A schematic cross-sectional view of a VDMOS ceramic packaging structure of the present invention;

[0024] Figure 2 A side view of a ceramic packaging structure of a VDMOS ceramic packaging structure of the present invention;

[0025] Figure 3 A schematic cross-sectional view of a ceramic housing of a VDMOS ceramic packaging structure according to the present invention;

[0026] Figure 4 This is a cross-sectional schematic diagram of a VDMOS chip and a ceramic housing after welding in a VDMOS ceramic packaging structure of the present invention;

[0027] Figure 5 This is a top view of a VDMOS chip and a ceramic housing after welding in a VDMOS ceramic packaging structure of the present invention.

[0028] Figure 6 A schematic diagram of a ceramic package cover plate of a VDMOS ceramic package structure according to the present invention;

[0029] Figure 7 This is a top view of a VDMOS ceramic packaging structure after the cover is bonded;

[0030] Figure 8 This is another cross-sectional schematic diagram of a VDMOS ceramic package structure of the present invention. DETAILED DESCRIPTION

[0031] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art. It should be noted that, unless there is a conflict, the embodiments of the present disclosure and the features described in the embodiments can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0032] like Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 and Figure 5As shown, the VDMOS ceramic packaging structure includes: a first metal frame 11, a second metal frame 12, a ceramic housing 2, a heat-conducting integrated cover 3 and a VDMOS chip 4; wherein,

[0033] The first metal frame 11 includes a first support section 111, a first upper transverse section 112, and a first lower transverse section 113. One end of the first upper transverse section 112 is connected to the top of the first support section 111; one end of the first lower transverse section 113 is connected to the middle of the first support section 111; the other end of the first upper transverse section 112 passes through a side wall of the ceramic housing 2 and is connected to the upper portion of one end of the VDMOS chip 4; the other end of the first lower transverse section 113 passes through a side wall of the ceramic housing 2 and is connected to the lower portion of one end of the VDMOS chip 4.

[0034] The second metal frame 12 includes a second support section 121, a second upper transverse section 122, and a second lower transverse section 123. One end of the second upper transverse section 122 is connected to the top of the second support section 121. One end of the second lower transverse section 123 is connected to the middle of the second support section 121. The other end of the second upper transverse section 122 passes through the other side wall of the ceramic housing 2 and is connected to the upper portion of the other end of the VDMOS chip 4. The other end of the second lower transverse section 123 passes through the other side wall of the ceramic housing 2 and is connected to the lower portion of the other end of the VDMOS chip 4.

[0035] The heat-conducting integrated cover plate 3 is disposed at the opening of the ceramic housing 2 , and the lower end of the heat-conducting integrated cover plate 3 is connected to the upper surface of the VDMOS chip 4 .

[0036] The other end of the first upper transverse section 112 passes through a side wall of the ceramic housing 2 and is connected to the upper portion of one end of the VDMOS chip 4 via the solder joint 5. The other end of the first lower transverse section 113 passes through a side wall of the ceramic housing 2 and is connected to the lower portion of one end of the VDMOS chip 4 via the solder joint 5.

[0037] The other end of the second upper transverse section 122 passes through the other side wall of the ceramic housing 2 and is connected to the upper part of the other end of the VDMOS chip 4 through the solder joint 5; the other end of the second lower transverse section 123 passes through the other side wall of the ceramic housing 2 and is connected to the lower part of the other end of the VDMOS chip 4 through the solder joint 5.

[0038] The thermally conductive integrated cover plate 3 is disposed at the opening of the ceramic housing 2 via adhesive 6 , and the lower end of the thermally conductive integrated cover plate 3 is connected to the upper surface of the VDMOS chip 4 via adhesive 6 .

[0039] like Figure 4 As shown, it is necessary to precisely control the flat plate size L and the heat conducting column height H of the integrated cover plate 3, and the constraint relationship is as follows:

[0040] L1+2x1.2≥L≥L1+2x0.8

[0041] H=H1+Z1+Z2-Z3

[0042] Wherein, L is the size of the one-piece cover plate 3, L1 is the cavity size of the ceramic shell 2; H is the height of the heat conduction column of the one-piece cover plate 3, H1 is the distance from the cavity surface of the ceramic shell 2 to the lower surface of the second upper horizontal section 122, Z1 is the height of the frame and the chip solder joint, Z2 is the bonding thickness of the cover plate and the ceramic shell, and Z3 is the bonding thickness of the heat conduction column and the chip.

[0043] The above formula can ensure the cavity airtightness and reliable bonding of the heat conduction column.

[0044] As shown in Figure 5 and Figure 8 , the solder thickness Z1 and the solder amount V of the first metal frame 11 / second metal frame 12 and the chip 4 need to be accurately controlled, and the constraint relationship is as follows:

[0045]

[0046] Wherein, M is the effective welding length of the metal frame, W is the width of the metal frame, D is the distance between the upper and lower frames, and D1 is the thickness of the chip.

[0047] The formula can ensure that the chip and the upper and lower metal frames form a firm solder joint, and the adjacent solder joints will not be short-circuited due to excessive solder overflow.

[0048] The embodiment adopts a coarse metal frame to replace the ceramic printed wiring, and is embedded into the ceramic body through a lamination process; the interconnection between the source and drain levels of the VDMOS on the upper and lower frames is changed to a welding process, and the VDMOS source and drain levels are directly connected to the external path; a direct contact cover plate is used, so that the heat of the device is directly and effectively conducted to the top of the package.

[0049] The cross section of the coarse metal frame of the embodiment is much larger than that of the ceramic printed wiring, which can significantly improve the large current carrying capacity of the interconnection; the interconnection between the VDMOS and the shell is changed from a bonding wire to a welding process, which reduces the on-resistance of the bonding wire, and the on-resistance of the frame itself is also significantly reduced; and the heat dissipation cover plate and the chip are in direct contact, so that the heat of the device is directly and effectively conducted to the top of the package, which significantly reduces the thermal resistance of the device.

[0050] In this embodiment, the printed traces of a conventional ceramic housing are replaced with a thick metal frame. The ceramic housing serves as an insulating material, supporting the frame and forming a cavity space. The cover plate is connected to the VDMOS chip within the package cavity and forms a closed space with the surface of the ceramic housing. The VDMOS chip is in the housing, and the upper and lower poles of the chip are interconnected with the upper and lower metal frames respectively. The VDMOS chip and the metal frame are interconnected using a welding process. The cover plate is interconnected with the housing surface and the upper side of the chip using a bonding process.

[0051] like Figure 3 The figure shows the cross-section of the ceramic shell. Depending on the actual situation, you can choose Kovar or copper as the frame material, and the surface can be nickel-plated or gold-plated. The cross-section of the metal frame can be circular or rectangular, and the appropriate cross-sectional area (generally larger than 0.06mm) can be selected according to the current it carries. 2 ); The metal frame must be two layers, upper and lower, and the frame must be long enough inside the shell to extend above the chip inside the shell.

[0052] like Figure 3 The figure shows a cross-sectional diagram of the ceramic shell. The ceramic shell processing must adopt a multi-layer ceramic lamination process, compacting the two metal frames with upper and lower ceramic sheets, and forming a firm, airtight complete frame structure through sintering.

[0053] like Figure 4 and Figure 5 The figure shows a cross-sectional schematic diagram and a top view of the VDMOS chip and ceramic housing after welding. The VDMOS chip must be a VDMOS device with the source and drain on the upper and lower surfaces respectively; and the chip and metal frame are interconnected using a solder coating reflow process: during the chip welding process, solder is first coated on the corresponding pads of the chip, then the chip is placed in the corresponding position of the metal frame, and finally heated and reflowed to complete the welding.

[0054] like Figure 6 The figure shows a schematic diagram of a ceramic package cover. The cover is made of Kovar or copper and is nickel- and gold-plated on the surface. The cover should be convex in the middle and thinner around the edges. The size should be able to cover the cavity of the ceramic shell and be large enough to form a reliable connection with the edge of the ceramic body. After assembly, it is necessary to ensure that the central convexity of the cover is in firm contact with the chip surface after bonding.

[0055] like Figure 7 The figure shows the top view after the cover is bonded. Non-conductive adhesive is used to bond the cover to the chip and the housing surface. During the cover bonding process, the non-conductive adhesive is first applied to the upper side of the chip and the sealing ring of the ceramic housing. The cover is then aligned and placed in the corresponding position to ensure that the heat-conducting area of ​​the cover contacts the chip surface and the sealing area of ​​the cover contacts the surface of the ceramic housing. Finally, high-temperature curing is performed to form a reliable bond in both areas.

[0056] In summary, the VDMOS ceramic packaging structure of the present invention uses a thick metal frame instead of ceramic printed wiring, which can significantly improve the high-current carrying capacity of the package. A welding process is used to directly connect the VDMOS source and drain to the external path, significantly reducing the overall on-resistance. A direct contact cover is used to directly and effectively conduct device heat to the top of the package, significantly reducing the device thermal resistance. This structure can greatly improve the reliability of the device in harsh environments such as high temperature and high humidity while ensuring excellent electrical and heat dissipation performance. In addition, the corresponding packaging process steps are simple, reducing chip bonding and curing time, and greatly improving the efficiency of the packaging process.

[0057] Although the present invention has been disclosed above in terms of preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the scope of protection of the technical solutions of the present invention.

Claims

1. A VDMOS ceramic packaging structure, characterized in that include: A first metal frame (11), a second metal frame (12), a ceramic housing (2), a heat-conducting integrated cover plate (3), and a VDMOS chip (4); wherein, The first metal frame (11) comprises a first support section (111), a first upper transverse section (112) and a first lower transverse section (113); wherein one end of the first upper transverse section (112) is connected to the top of the first support section (111); one end of the first lower transverse section (113) is connected to the middle of the first support section (111); the other end of the first upper transverse section (112) passes through a side wall of the ceramic housing (2) and is connected to the upper part of one end of the VDMOS chip (4); the other end of the first lower transverse section (113) passes through a side wall of the ceramic housing (2) and is connected to the lower part of one end of the VDMOS chip (4); The second metal frame (12) comprises a second support section (121), a second upper transverse section (122) and a second lower transverse section (123); wherein one end of the second upper transverse section (122) is connected to the top of the second support section (121); one end of the second lower transverse section (123) is connected to the middle of the second support section (121); the other end of the second upper transverse section (122) passes through the other side wall of the ceramic housing (2) and is connected to the upper part of the other end of the VDMOS chip (4); the other end of the second lower transverse section (123) passes through the other side wall of the ceramic housing (2) and is connected to the lower part of the other end of the VDMOS chip (4); The heat-conducting integrated cover plate (3) is arranged at the opening of the ceramic housing (2), and the lower end of the heat-conducting integrated cover plate (3) is connected to the upper surface of the VDMOS chip (4); The other end of the first upper transverse section (112) passes through a side wall of the ceramic housing (2) and is connected to the upper portion of one end of the VDMOS chip (4) via a solder joint (5); the other end of the first lower transverse section (113) passes through a side wall of the ceramic housing (2) and is connected to the lower portion of one end of the VDMOS chip (4) via a solder joint (5); The other end of the second upper transverse section (122) passes through the other side wall of the ceramic housing (2) and is connected to the upper portion of the other end of the VDMOS chip (4) via a solder joint (5); the other end of the second lower transverse section (123) passes through the other side wall of the ceramic housing (2) and is connected to the lower portion of the other end of the VDMOS chip (4) via a solder joint (5); The heat-conducting integrated cover plate (3) is arranged at the opening of the ceramic housing (2) via adhesive (6), and the lower end of the heat-conducting integrated cover plate (3) is connected to the upper surface of the VDMOS chip (4) via adhesive (6); The constraint relationship between the plate size L of the heat-conducting integrated cover plate (3) and the height H of the heat-conducting column is as follows: L1+2×1.2≥L≥L1+2×0.8; H=H1+Z1+Z2-Z3; Wherein, L is the size of the heat-conducting integrated cover plate (3), L1 is the cavity size of the ceramic shell (2); H is the height of the heat-conducting column of the heat-conducting integrated cover plate (3), H1 is the distance from the cavity surface of the ceramic shell (2) to the lower surface of the second upper transverse section (122), Z1 is the height of the solder joint between the frame and the chip, Z2 is the bonding thickness between the cover plate and the ceramic shell, and Z3 is the bonding thickness between the heat-conducting column and the chip; The solder volume V is obtained by the following formula: Wherein, M is the effective welding length of the metal frame, W is the width of the metal frame, D is the distance between the upper and lower frames, and D1 is the chip thickness.

2. The VDMOS ceramic package structure according to claim 1, wherein: The first metal frame (11) and the second metal frame (12) are both made of Kovar or copper materials, and the surfaces of the first metal frame (11) and the second metal frame (12) are both nickel-plated and gold-plated.

3. The VDMOS ceramic package structure according to claim 1, wherein: The cross-sections of the first metal frame (11) and the second metal frame (12) are both circular or rectangular, and the cross-sectional area should meet 0.06mm 2 ~0.6mm 2 .

4. The VDMOS ceramic package structure according to claim 1, wherein: The ceramic housing (2) is processed by a multi-layer ceramic lamination process, wherein the first metal frame (11) and the second metal frame (12) are compacted with ceramic sheets and sintered.

5. The VDMOS ceramic package structure according to claim 1, wherein: The VDMOS chip (4) is interconnected with the first metal frame (11) and the second metal frame (12) by adopting a solder coating reflow process.

6. The VDMOS ceramic package structure according to claim 5, wherein: During the soldering process of the VDMOS chip (4), solder is first applied to the corresponding pads of the VDMOS chip, then the VDMOS chip is placed at corresponding positions of the first metal frame (11) and the second metal frame (12), and finally heated and reflowed to form a firm solder joint (5).

7. The VDMOS ceramic package structure according to claim 1, wherein: During the bonding process of the heat-conducting integrated cover plate (3), the bonding glue (6) is first applied to the upper side of the VDMOS chip (4) and the position of the sealing ring of the ceramic housing (2), and then the heat-conducting integrated cover plate (3) is aligned and placed in the corresponding position to ensure that the heat-conducting area of ​​the heat-conducting integrated cover plate (3) is in contact with the surface of the VDMOS chip (4), and the sealing area of ​​the heat-conducting integrated cover plate (3) is in contact with the surface of the ceramic housing (2), and finally, bonding is formed simultaneously in the two areas through high-temperature curing.

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