semiconductor memory devices

Abstract

An embodiment provides a semiconductor memory device that suppresses the collapse of memory cells and improves integration density. The semiconductor memory device of the embodiment includes: a first stacked body stacked along a first direction; a second stacked body stacked along the first direction; and a first structure including at least one memory structure and disposed between the first stacked body and the second stacked body. The at least one memory structure includes a first semiconductor film, a first charge storage film, a second semiconductor film, and a second charge storage film. The first stacked body and the second stacked body each include: a first portion, a second portion, and a third portion, each extending along a second direction intersecting the first direction, wherein the first portion is disposed between the second portion and the third portion in a third direction intersecting the first and second directions; a fourth portion connecting the first portion and the second portion; and a fifth portion connecting the first portion and the third portion; and the second portion of the first stacked body is disposed between the first portion of the second stacked body and the third portion of the second stacked body in the third direction.

Description

[0001] [Related Applications]

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2020-156442 (filing date: September 17, 2020), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments relate to a semiconductor memory device. Background Art

[0004] As a semiconductor memory device capable of storing data in a nonvolatile manner, a NAND (Not AND) type flash memory having a three-dimensional memory structure is known. Summary of the Invention

[0005] The problem to be solved by the present invention is to provide a semiconductor memory device that suppresses the collapse of memory cells and improves the integration density.

[0006] A semiconductor storage device of an embodiment comprises: a first stacked body comprising a plurality of first conductors stacked along a first direction; a second stacked body comprising a plurality of second conductors stacked along the first direction; and a first structure comprising at least one memory structure and arranged between the first stacked body and the second stacked body. The at least one memory structure includes: a first semiconductor film and a second semiconductor film, each extending along the first direction; a first charge storage film, extending along the first direction between the first stack and the first semiconductor film; and a second charge storage film, extending along the first direction between the second stack and the second semiconductor film; the first stack and the second stack respectively include: a first part, a second part and a third part, each extending along a second direction intersecting the first direction, wherein the first part is arranged between the second part and the third part in a third direction intersecting the first direction and the second direction; a fourth part connecting the first part to the second part; and a fifth part connecting the first part to the third part; and the second part of the first stack is arranged between the first part of the second stack and the third part of the second stack in the third direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 This is a block diagram showing the configuration of a memory system including a semiconductor memory device according to an embodiment.

[0008] Figure 2 FIG. 1 is a circuit diagram showing a memory cell array of a semiconductor memory device according to an embodiment.

[0009] Figure 3 This is a planar layout of a memory cell array of a semiconductor memory device according to an embodiment viewed from above.

[0010] Figure 4 is with Figure 3 The IV region corresponds to the planar layout of the semiconductor memory device.

[0011] Figure 5 is with Figure 4 The V region corresponds to the planar layout of the semiconductor memory device.

[0012] Figure 6 It is along Figure 5 A longitudinal cross-sectional view of the semiconductor memory device taken along line VI-VI.

[0013] Figure 7 This is a longitudinal cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the embodiment.

[0014] Figure 8 This is a longitudinal cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the embodiment.

[0015] Figure 9 It is along Figure 8 A lateral cross-sectional view of the memory cell array along line IX-IX.

[0016] Figure 10 This is a longitudinal cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the embodiment.

[0017] Figure 11 This is a longitudinal cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the embodiment.

[0018] Figure 12 It is along Figure 11 A lateral cross-sectional view of the memory cell array along line XII-XII.

[0019] Figure 13 It is a transverse cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the embodiment.

[0020] Figure 14 It is along Figure 13 A longitudinal cross-sectional view of the memory cell array along line XIV-XIV.

[0021] Figure 15 This is a longitudinal cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the embodiment.

[0022] Figure 16 It is along Figure 15 A transverse cross-sectional view of the memory cell array taken along line XVI-XVI.

[0023] Figure 17 This is a longitudinal cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the embodiment.

[0024] Figure 18 It is along Figure 17 A lateral cross-sectional view of the memory cell array along line XVIII-XVIII.

[0025] Figure 19 This is a longitudinal cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the embodiment.

[0026] Figure 20 It is along Figure 19 A lateral cross-sectional view of the memory cell array along line XX-XX.

[0027] Figure 21 It is a transverse cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the embodiment.

[0028] Figure 22 This is a longitudinal cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the embodiment.

[0029] Figure 23 It is a transverse cross-sectional view of a memory cell array for explaining the manufacturing steps of the semiconductor memory device according to the embodiment.

[0030] Figure 24 This is a planar layout of the memory cell array of the semiconductor memory device according to the first variation as viewed from above.

[0031] Figure 25 This is a planar layout of a memory cell array of the semiconductor memory device according to the second variation as viewed from above.

[0032] Figure 26 FIG. 1 is a planar layout of a memory cell array of a semiconductor memory device according to a third variation as viewed from above.

[0033] Figure 27 This is a planar layout of the memory cell array of the semiconductor memory device according to the fourth variation as viewed from above. DETAILED DESCRIPTION

[0034] The following describes the embodiments with reference to the accompanying drawings. Each embodiment exemplifies a device or method for embodying the technical concept of the invention. The drawings are schematic or conceptual, and the dimensions and ratios of the drawings may not necessarily be the same as those of the actual objects. The technical concept of the present invention is not determined by the shape, structure, or arrangement of the components.

[0035] In the following description, components having substantially the same function and configuration are denoted by the same reference numerals. The numerals following the letters constituting the reference numerals are used to distinguish between components having the same configuration and being referenced by reference numerals containing the same letters. Where it is not necessary to distinguish between components denoted by reference numerals containing the same letters, these components are referred to by reference numerals consisting solely of the letters.

[0036] In the following description, a cross section parallel to a build-up surface of a structure built on a substrate may be referred to as a "transverse cross section," and a cross section intersecting the build-up surface may be referred to as a "longitudinal cross section."

[0037] 1. Implementation Method

[0038] A semiconductor memory device according to an embodiment will be described.

[0039] 1.1 Composition

[0040] First, the configuration of a semiconductor memory device according to an embodiment will be described.

[0041] 1.1.1 Structure of a Semiconductor Memory Device

[0042] Figure 1 This is a block diagram for explaining the configuration of a memory system including a semiconductor memory device according to an embodiment.

[0043] The semiconductor storage device 1 is controlled by a memory controller 2 and is a NAND flash memory capable of storing data in a nonvolatile manner.

[0044] like Figure 1 As shown, the semiconductor memory device 1 includes, for example, a memory cell array 10 , a command register 11 , an address register 12 , a sequencer 13 , a driver module 14 , a row decoder module 15 , and a sense amplifier module 16 .

[0045] The memory cell array 10 includes a plurality of blocks BLK0 to BLKn (n is an integer greater than or equal to 1). Each block BLK is a collection of a plurality of memory cell transistors capable of storing data non-volatilely, and is used, for example, as a unit of data erasure. In other words, the data stored in the memory cell transistors contained in the same block BLK is erased at once. A plurality of bit lines and a plurality of word lines are provided in the memory cell array 10. Each memory cell transistor is associated with one bit line and one word line. The detailed structure of the memory cell array 10 will be described below.

[0046] The command register 11 stores the command CMD received by the semiconductor storage device 1 from the memory controller 2. The command CMD includes, for example, an instruction to cause the sequencer 13 to execute a read operation, a write operation, an erase operation, and the like.

[0047] The address register 12 stores address information ADD received by the semiconductor memory device 1 from the memory controller 2. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, the block address BA, the page address PA, and the column address CA are used to select a block BLK, a word line, and a bit line, respectively.

[0048] The sequencer 13 controls the overall operation of the semiconductor memory device 1. For example, based on the command CMD stored in the command register 11, the sequencer 13 controls the driver module 14, the row decoder module 15, and the sense amplifier module 16 to execute read, write, and erase operations.

[0049] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. The driver module 14 applies the generated voltages to signal lines corresponding to selected word lines based on, for example, the page address PA stored in the address register 12 .

[0050] The row decoder module 15 selects one block BLK based on the address information ADD received by the semiconductor memory device 1 from the memory controller 2. The row decoder module 15 also outputs a required voltage to the block BLK.

[0051] During a data read operation, the sense amplifier module 16 senses the threshold voltage of the memory cell transistor to be read within the memory cell array 10. The sense amplifier module 16 outputs the sensing result as read data DAT to the memory controller 2. During a data write operation, the sense amplifier module 16 transmits write data DAT received from the external memory controller 2 to the memory cell array 10.

[0052] The semiconductor memory device 1 is connected to the memory controller 2 via, for example, a NAND bus.

[0053] The NAND bus transmits and receives the command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn, ready / busy signal RBn, and input / output signal I / O, respectively, according to the NAND interface, via separate signal lines. Signal CLE notifies semiconductor memory device 1 that signal I / O flowing to semiconductor memory device 1 while signal CLE is at an "H" level is a command. Signal ALE notifies semiconductor memory device 1 that signal I / O flowing to semiconductor memory device 1 while signal ALE is at an "H" level is an address. Signal WEn instructs semiconductor memory device 1 to acquire signal I / O flowing to semiconductor memory device 1 while signal WEn is at an "L" level. Signal REn instructs semiconductor memory device 1 to output signal I / O. Signal RBn indicates whether semiconductor memory device 1 is in a ready state (accepting external commands) or a busy state (not accepting external commands). Signal I / O is, for example, an 8-bit signal.

[0054] Signals I / O are transmitted and received between the semiconductor memory device 1 and the memory controller 2 and include commands CMD, addresses ADD, and data DAT.

[0055] The semiconductor memory device 1 and the memory controller 2 described above can also be combined to form a memory system. As such a memory system, for example, SD (Secure Digital) TM Memory cards such as SD cards or SSDs (solid state drives).

[0056] 1.1.2 Composition of Memory Cell Array

[0057] Next, use Figure 2 The configuration of the memory cell array 10 will be described. Figure 2 2 is an equivalent circuit diagram of the memory cell array 10 according to the embodiment. Figure 2 The example shows one block BLK in the memory cell array 10, but the structures of other blocks BLK are the same.

[0058] like Figure 2 As shown, the block BLK includes, for example, 8 string components SU (SU0, SU1, SU2, SU3, ..., SU7). Figure 2 In the example of , four (SU0 to SU3) of the eight string components SU0 to SU7 are shown.

[0059] Each string unit SU includes multiple memory strings MS. Hereinafter, the memory strings MS within a string unit SUa (any of SU0, SU2, SU4, and SU6) and the memory strings MS within a string unit SUb (SU1, SU3, SU5, and SU7) are referred to as memory strings MSa and MSb, respectively. Furthermore, as necessary for other configurations and wiring, the suffix "a" is added to the portion corresponding to the string unit SUa, and the suffix "b" is added to the portion corresponding to the string unit SUb to distinguish them from each other.

[0060] Memory string MS includes, for example, eight memory cell transistors MC (MC0-MC7) and select transistors ST1 and ST2. Each memory cell transistor MC has a control gate and a charge storage film, storing data in a nonvolatile manner. The eight memory cell transistors MC are connected in series between the source of select transistor ST1 and the drain of select transistor ST2.

[0061] The gates of the select transistors STa1 included in the string units SUa (SU0, SU2, SU4, and SU6) are connected to select gate lines SGDa (SGD0, SGD2, SGD4, and SGD6), respectively. The gates of the select transistors STb1 included in the string units SUb (SU1, SU3, SU5, and SU7) are connected to select gate lines SGDb (SGD1, SGD3, SGD5, and SGD7), respectively. The select gate lines SGD0-SGD7 are independently controlled by the row decoder module 15.

[0062] Furthermore, the gates of the select transistors STa2 included in the string components SUa within the same block BLK are commonly connected to the select gate line SGSa, for example, and the gates of the select transistors STb2 included in the string components SUb within the same block BLK are commonly connected to the select gate line SGSb, for example. The select gate lines SGSa and SGSb can be commonly connected or independently controllable.

[0063] Furthermore, the control gates of the memory cell transistors MCa (MCa0-MCa7) included in the string unit SUa within the same block BLK are commonly connected to word lines WLa (WLa0-WLa7). Meanwhile, the control gates of the memory cell transistors MCb (MCb0-MCb7) included in the string unit SUb are commonly connected to word lines WLb (WLb0-WLb7). Word lines WLa and WLb are independently controlled by the row decoder module 15.

[0064] Furthermore, the drains of the select transistors ST1 of the memory strings MS located in the same column within the memory cell array 10 are commonly connected to a bit line BL (BL0 to BL(m-1), where m is a natural number). In other words, the bit line BL is commonly connected to one memory string MSa in each of the multiple string units SUa, and one memory string MSb in each of the multiple string units SUb. Furthermore, the sources of the multiple select transistors ST2 are commonly connected to a source line CELSRC.

[0065] In other words, a string unit SU is a collection of multiple memory strings MS, each connected to a different bit line BL and connected to the same select gate line SGD. The collection of memory cell transistors MC in a string unit SU that are commonly connected to the same word line WL is also called a unit unit CU. Furthermore, a block BLK is a collection of multiple string units SUa that share the same word lines WLa0 to WLa7 and multiple string units SUb that share the same word lines WLb0 to WLb7. Furthermore, the memory cell array 10 is a collection of multiple blocks BLK that share multiple bit lines BL.

[0066] In the memory cell array 10 , the select gate line SGS, the word line WL, and the select gate line SGD are sequentially stacked on a semiconductor substrate, thereby three-dimensionally stacking the memory cell transistor MC and the select transistors ST1 and ST2 .

[0067] 1.1.3 Layout of the Memory Cell Array

[0068] Next, use Figure 3 The layout of the memory cell array 10 according to the embodiment will be described.

[0069] Figure 3 FIG. 1 is an example of a planar layout of the memory cell array 10 in the semiconductor memory device 1 according to the embodiment. Figure 3 In order to make the figures easier to understand, components such as interlayer insulating films and wiring are omitted as appropriate. In the following description, two directions parallel to the surface of the semiconductor substrate and perpendicular to each other are referred to as the X direction and the Y direction, and a direction perpendicular to the plane (XY plane) including the X and Y directions is referred to as the Z direction (stack-up direction).

[0070] like Figure 3 As shown, the memory cell array 10 includes a cell region 100 and interconnection regions 200 (200a and 200b). The interconnection regions 200a and 200b are arranged at both ends of the cell region 100 along the X direction, sandwiching the cell region 100 along the X direction. In other words, the interconnection region 200a is arranged at one end of the cell region 100 in the X direction, and the interconnection region 200b is arranged at the other end of the cell region 100 in the X direction.

[0071] The cell region 100 and the wiring region 200a are provided with a plurality of first laminates arranged along the Y direction, and the cell region 100 and the wiring region 200b are provided with a plurality of second laminates arranged along the Y direction. The plurality of first laminates and the plurality of second laminates are separated from each other by a plurality of trench structures TST (TST1, TST2, and TST3) extending along the Z direction and a plurality of pillars STP1.

[0072] A set of one first laminate and one second laminate adjacent to each other in the X direction corresponds to, for example, one block BLK. In a plan view, the first and second laminates belonging to one block BLK have substantially the same shape and are, for example, arranged at positions that are point-symmetrical with respect to the center of the unit region 100 in which the first and second laminates are located.

[0073] The first stacked body is a structure in which select gate line SGSa, word lines WLa0 to WLa7, and select gate line SGDa are stacked along the Z direction. The second stacked body is a structure in which select gate line SGSb, word lines WLb0 to WLb7, and select gate line SGDb are stacked along the Z direction.

[0074] Select gate lines SGSa and SGSb are provided on the same layer, word lines WLai and WLbi (i is an integer from 0 to 7) are provided on the same layer, and select gate lines SGDa and SGDb are provided on the same layer. Furthermore, word lines WLa0 and WLb0 are provided on a layer above select gate lines SGSa and SGSb, word lines WLaj and WLbj (j is an integer from 1 to 7) are provided on a layer above word lines WLa(j-1) and WLb(j-1), and select gate lines SGDa and SGDb are provided on a layer above word lines WLa7 and WLb7.

[0075] In the following description, the select gate lines SGD and SGS, and the word lines WL may be collectively referred to as "build-up wiring."

[0076] First, the cell region 100 will be described.

[0077] In the cell region 100, a plurality of trench structures TST are arranged at intervals d1 along the X direction. The plurality of trench structures TST form three arrangement patterns with different combinations of lengths and positions along the X direction. Specifically, among the plurality of trench structures TST, a plurality of trench structures TST1 form a first arrangement pattern, a plurality of trench structures TST2 form a second arrangement pattern, and a plurality of trench structures TST3 form a third arrangement pattern. In both the first and second arrangement patterns, a plurality of trench structures TST1 and TST2, each having a length (2h+d1) along the X direction, are arranged at intervals d1. The trench structure TST1 and the trench structure TST2 are arranged at positions offset from each other by a length (h+d1) in the X direction. In the third arrangement pattern, a plurality of trench structures TST3, each having a length h along the X direction, are arranged at intervals d1. The positions of the two ends of the trench structure TST3 along the X direction are aligned with the positions of the two ends of the trench structures TST1 and TST2 along the X direction. The first arrangement pattern, the second arrangement pattern, and the third arrangement pattern of the trench structure TST are repeatedly arranged in sequence along the Y direction.

[0078] In addition, a plurality of pillars STP1 are provided in the cell region 100. These pillars STP1 have an elliptical shape, with a major axis parallel to the Y direction and a minor axis parallel to the X direction, when viewed from above. For example, the plurality of pillars STP1 are arranged so as to overlap with the ends of the trench structure TST3 and the ends of the trench structures TST1 or TST2 adjacent to the trench structure TST3 along the Y direction. Furthermore, the shape of the pillars STP1 when viewed from above is not limited to an elliptical shape and may also be a rectangular shape, for example. In this case, the pillars STP1 may have a shape with a long side parallel to the Y direction and a short side parallel to the X direction, when viewed from above.

[0079] By arranging the trench structure TST and the support pillars STP1 as described above, the first layered body and the second layered body are separated from each other.

[0080] In a top view, the first laminate and the second laminate each include four branched wiring regions of the same shape within the cell region 100. The four wiring regions of the first laminate correspond to the selection gate lines SGD0, SGD2, SGD4, and SGD6, respectively, and the four wiring regions of the second laminate correspond to the selection gate lines SGD1, SGD3, SGD5, and SGD7, respectively. The eight wiring regions corresponding to the selection gate lines SGD7 to SGD0 are arranged in sequence along the Y direction. Below, as an example of one wiring region, the wiring regions corresponding to the selection gate line SGD4 ( Figure 3 The shape corresponding to the oblique line portion in FIG. 1 is described.

[0081] The wiring area includes a central wiring section L1, multiple peripheral wiring sections L2 and L3, and multiple connecting sections J1 and J2. The central wiring section L1 and the multiple peripheral wiring sections L2 and L3 have the same width along the Y direction. In the following description, the central wiring section L1 and the multiple peripheral wiring sections L2 and L3 are simply referred to as wiring sections.

[0082] The central wiring portion L1 extends along the X-direction throughout the cell region 100 and is connected to the wiring region 200a. Furthermore, the central wiring portions L1 of the wiring regions corresponding to the select gate lines SGD0, SGD2, and SGD6 are connected to the wiring region 200a, similar to the case of the select gate line SGD4. The central wiring portions L1 of the wiring regions corresponding to the select gate lines SGD1, SGD3, SGD5, and SGD7 are connected to the wiring region 200b.

[0083] The multiple connection portions J1 are arranged along the X direction at intervals of (2h + d1) on one end side (+Y direction side) of the central wiring portion L1 in the Y direction. Each of the multiple connection portions J1 has a width d1 along the X direction and connects the corresponding peripheral wiring portion L2 to the central wiring portion L1.

[0084] The plurality of peripheral wiring sections L2 are arranged along the X direction on one end side of the central wiring section L1 in the Y direction. The lengths of the plurality of peripheral wiring sections L2 along the X direction are substantially equal. The plurality of peripheral wiring sections L2 are connected to the corresponding connection section J1 at their center positions along the X direction.

[0085] The multiple connection portions J2 are arranged in the X direction at intervals (2h + d1) on the other end side (-Y direction side) of the central wiring portion L1 in the Y direction, and are offset from the multiple connection portions J1 in the X direction by a length (h + d1). Each of the multiple connection portions J2 has a width d1 in the X direction and connects the corresponding peripheral wiring portion L3 to the central wiring portion L1.

[0086] The plurality of peripheral wiring sections L3 are arranged along the X direction at the other end of the central wiring section L1 in the Y direction, offset from the plurality of peripheral wiring sections L2 in the X direction by a length (h + d1). The length of each of the plurality of peripheral wiring sections L3 in the X direction is the same as that of the peripheral wiring section L2. The plurality of peripheral wiring sections L3 are connected to the corresponding connection section J2 at their center positions along the X direction.

[0087] The wiring region corresponding to the selection gate line SGD4 having the above-described shape is provided in the cell region 100 between the wiring region corresponding to the selection gate line SGD3 and the wiring region corresponding to the selection gate line SGD5. Specifically, the central wiring portion L1 of the selection gate line SGD4 is provided between the peripheral wiring portion L2 of the selection gate line SGD5 and the peripheral wiring portion L3 of the selection gate line SGD3. The peripheral wiring portion L2 of the selection gate line SGD4 is provided between the central wiring portion L1 and the peripheral wiring portion L3 of the selection gate line SGD3, with the connection portion J2 of the selection gate line SGD3 interposed with the support column STP1, so as to be aligned along the X direction. The peripheral wiring portion L3 of the selection gate line SGD4 is provided between the central wiring portion L1 and the peripheral wiring portion L2 of the selection gate line SGD5, with the connection portion J1 of the selection gate line SGD5 interposed with the support column STP1, so as to be aligned along the X direction.

[0088] Similarly, a wiring region corresponding to the selection gate line SGDk (k is an integer of 1≤k≤6) is provided in the cell region 100 between a wiring region corresponding to the selection gate line SGD(k−1) and a wiring region corresponding to the selection gate line SGD(k+1).

[0089] With this arrangement, the peripheral wiring portions L2 and L3 of the select gate line SGD are respectively arranged at substantially the same positions in the X direction as the peripheral wiring portions L2 and L3 of the other select gate lines SGD. Furthermore, the connection portions J1 and J2 of the select gate line SGD are respectively arranged at substantially the same positions in the X direction as the connection portions J1 and J2 of the other select gate lines SGD.

[0090] Furthermore, the wiring region corresponding to the select gate line SGD0 can be provided between the wiring region corresponding to the select gate line SGD1 and the wiring region corresponding to the select gate line SGD7 of another adjacent block BLK. The wiring region corresponding to the select gate line SGD7 can be provided between the wiring region corresponding to the select gate line SGD6 and the wiring region corresponding to the select gate line SGD0 of another adjacent block BLK. However, the semiconductor memory device of the embodiment is not limited to these. For example, dummy wiring may be provided in place of another block BLK.

[0091] Through the structure as described above, the first laminate is separated into four wiring areas (selection gate lines SGD0, SGD2, SGD4 and SGD6) extending from the wiring area 200a side in the unit area 100, and the second laminate is separated into four wiring areas (selection gate lines SGD1, SGD3, SGD5 and SGD7) extending from the wiring area 200b side.

[0092] Next, the connection area 200 will be described.

[0093] In wiring region 200, the first and second built-up bodies are formed in a stepped pattern. Specifically, the built-up wiring within the first and second built-up bodies extends longer in the X-direction as it is formed in lower layers, and all built-up wiring has a stepped region with no other built-up wiring arranged above it.

[0094] In the wiring region 200a, multiple first stacked bodies arranged along the Y direction are separated from each other by trench structures TST extending along the X direction. The stacked wiring in the first stacked body corresponding to the select gate line SGDa is separated into four select gate lines SGD0, SGD2, SGD4, and SGD6 by trench structures TST extending along the X direction. Select gate lines SGD0, SGD2, SGD4, and SGD6 have contacts CP0, CP2, CP4, and CP6, respectively, located on the corresponding terrace regions.

[0095] Word lines WLa0 to WLa7 (part of which is not shown) are provided with contacts CPWa0 to CPWa7 (part of which is not shown) on corresponding mesa regions, respectively.

[0096] Furthermore, regarding the selection gate line SGSa, a contact (not shown) is also provided on the corresponding mesa region (not shown).

[0097] In the wiring region 200b, multiple second stacked bodies arranged along the Y direction are separated from each other by trench structures TST extending along the X direction. The stacked wiring in the second stacked body corresponding to the select gate line SGDb is separated into four select gate lines SGD1, SGD3, SGD5, and SGD7 by trench structures TST extending along the X direction. Select gate lines SGD1, SGD3, SGD5, and SGD7 have contacts CP1, CP3, CP5, and CP7, respectively, located on the corresponding terrace regions.

[0098] Word lines WLb0 to WLb7 (partially not shown) are provided with contacts CPWb0 to CPWb7 (partially not shown) on corresponding mesa regions, respectively.

[0099] Furthermore, regarding the select gate line SGSb, a contact (not shown) is also provided on the corresponding mesa region (not shown).

[0100] With the above-described configuration, all build-up wiring can be led out from wiring region 200 to above memory cell array 10 .

[0101] 1.1.4 Memory Structure

[0102] Next, use Figure 4 The layout of the memory structure MST provided in the cell region 100 will be further described. Figure 4 is with Figure 3 Region IV corresponds to the planar layout of the part.

[0103] like Figure 4 As shown, in the region where the trench structure TST is in contact with the wiring portions L1 to L3, a plurality of memory structures MST ( Figure 4 The plurality of memory structures MST are arranged in a staggered manner on the plurality of trench structures TST. That is, with respect to the plurality of memory structures MST included in one of two trench structures TST adjacent in the Y direction, the plurality of memory structures MST included in the other trench structure TST are arranged at positions staggered by a length d2 in the X direction.

[0104] By configuring the plurality of memory structures MST as described above, the three memory structures MST respectively connected to the peripheral wiring portion L3, the central wiring portion L1 and the peripheral wiring portion L2 of the same selection gate line SGD are arranged in sequence along the Y direction at the same position along the X axis.

[0105] Above the memory structure MST, bit lines BL (partially not shown) are provided, extending in the Y direction and arranged in the X direction. The plurality of bit lines BL are connected to one memory structure MST in each string unit SU via contacts CP (partially not shown).

[0106] Specifically, three bit lines BL are provided for the multiple memory structures MST arranged in the Y direction at the same position along the X-axis. Among the multiple memory structures MST arranged in the Y direction at the same position along the X-axis, the three memory structures MST connected to the same select gate line SGD are each connected to a different one of the corresponding three bit lines BL. Thus, the multiple bit lines BL are connected to one memory structure MST in each string unit SU.

[0107] Below, using Figure 5 An example of the memory structure MST of the semiconductor memory device 1 according to the embodiment will be further described. Figure 5 is with Figure 4 The top view of the V region corresponds to the Figure 5 In order to make the figure easier to understand, constituent elements such as the bit line BL, the contact CP, and the interlayer insulating film are omitted as appropriate.

[0108] exist Figure 5, a configuration including two trench structures TST, three memory structures MST arranged in a staggered manner in each of the two trench structures TST, a pillar STP1, and select gate lines SGD0 and SGD1 is shown.

[0109] like Figure 5 As shown, one of the two trench structures TST (the trench structure TST on the +Y direction side) is provided in the peripheral wiring portion L2 ( Figure 5 SGD1 (L2)) and the peripheral wiring portion L3 ( Figure 5 between SGD0(L3) in .

[0110] This trench structure TST includes a tunnel insulating film 32b, a charge storage film 33b, and a blocking insulating film 34b on the peripheral wiring portion L2 side of the select gate line SGD1, and a tunnel insulating film 32a, a charge storage film 33a, and a blocking insulating film 34a on the peripheral wiring portion L3 side of the select gate line SGD0. Furthermore, the core component 30 is located in the center of this trench structure TST. Furthermore, the core component 30, the tunnel insulating films 32a and 32b, the charge storage films 33a and 33b, and the blocking insulating films 34a and 34b extend along the X direction throughout the entire trench structure TST.

[0111] The other of the two trench structures TST (the trench structure TST on the -Y direction side) is provided between the peripheral wiring portion L3 of the selection gate line SGD0 and the central wiring portion L1 of the selection gate line SGD1 arranged along the Y direction ( Figure 5 between SGD1(L1) in .

[0112] This other trench structure TST includes a tunnel insulating film 32a, a charge storage film 33a, and a blocking insulating film 34a on the peripheral wiring portion L3 side of the select gate line SGD0, and a tunnel insulating film 32b, a charge storage film 33b, and a blocking insulating film 34b on the central wiring portion L1 side of the select gate line SGD1. Furthermore, this other trench structure TST includes a core component 30 at its center. Furthermore, the core component 30, the tunnel insulating films 32a and 32b, the charge storage films 33a and 33b, and the blocking insulating films 34a and 34b extend along the X direction throughout the entirety of this other trench structure TST.

[0113] Furthermore, each of the two trench structures TST includes a semiconductor 31. The semiconductor 31 includes a plurality of first portions disposed between the tunnel insulating film 32a and the core component 30, a plurality of second portions disposed between the tunnel insulating film 32b and the core component 30, and a third portion (not shown) located below the core component 30. The first portions of the semiconductor 31 and the second portions of the semiconductor 31 corresponding to each other are connected by the third portion of the semiconductor 31, are formed at substantially the same position along the X direction, and have a length along the X direction that is less than the length d2.

[0114] The memory structure MST is formed in the following part in the trench structure TST, which includes, in sequence along the Y direction, a blocking insulating film 34a, a charge storage film 33a, a tunnel insulating film 32a, the first part of the semiconductor 31, the core component 30, the second part of the semiconductor 31, the tunnel insulating film 32b, the charge storage film 33b and the blocking insulating film 34b.

[0115] In the memory structure MST, the side of the core unit 30 that is closer to the select gate line SGD0 functions as the memory string MSa, and the side of the core unit 30 that is closer to the select gate line SGD1 functions as the memory string MSb. In other words, the memory structure MST included in each of the two trench structures TST has a portion that functions as the memory string MSa and a portion that functions as the memory string MSb.

[0116] Next, refer to Figure 6 , the structure of the cross section of the memory structure MST along the YZ plane is described. Figure 6 It is along Figure 5 A cross-sectional view of a semiconductor memory device taken along line VI-VI. Figure 6 , the figure shows a structure including the following parts: a memory structure MST within one of two trench structures TST adjacent in the Y direction; a portion within the other trench structure TST where the memory structure MST is not formed; and a plurality of conductors that function as various wirings connected to the memory structure MST.

[0117] like Figure 6 As shown, a conductor 21 serving as a source line CELSRC is provided above a semiconductor substrate 20. Conductor 21 comprises a conductive material, such as an n-type semiconductor or a metal material doped with impurities. Alternatively, conductor 21 may have a laminated structure of semiconductor and metal. Furthermore, circuits such as the row decoder module 15 and the sense amplifier module 16 may be provided between the semiconductor substrate 20 and conductor 21.

[0118] Above conductor 21, conductor 22a, which functions as select gate line SGSa, and conductor 22b, which functions as select gate line SGSb, are stacked on the same layer along the Z direction, with insulators (not shown) interposed between them. Above conductor 22a, eight layers of conductor 23a, which function as word lines WLa0 to WLa7, are stacked along the Z direction, with insulators (not shown) interposed between them. Similarly, above conductor 22b, eight layers of conductor 23b, which function as word lines WLb0 to WLb7, are stacked along the Z direction, with insulators (not shown) interposed between them. Above conductors 23a and 23b, conductors 24a, which function as select gate line SGD0, and conductors 24b, which function as select gate line SGD1, are stacked along the Z direction, respectively, with insulators (not shown) interposed between them.

[0119] Conductors 22a-24a and 22b-24b include a conductive material, such as an n-type semiconductor or p-type semiconductor or a metal material to which impurities are added. For example, conductors 22a-24a and 22b-24b may include a structure in which tungsten (W) is covered with titanium nitride (TiN). Titanium nitride functions as a barrier layer to prevent a reaction between tungsten and silicon oxide (SiO2) or as a layer to improve the adhesion of tungsten when forming a tungsten film using CVD (chemical vapor deposition). Furthermore, the conductive material of conductors 22a-24a and 22b-24b may be further covered with aluminum oxide (AlO).

[0120] Conductors 27 are provided above conductors 24a and 24b via an insulator (not shown). Conductors 27 extend in the Y direction and are arranged in a plurality of lines along the X direction, each serving as a bit line BL. Conductors 27 are made of copper (Cu), for example.

[0121] The core member 30 extends in the Z direction, with its upper end included in a layer above the conductors 24a and 24b and its lower end included in a layer below the conductors 22a and 22b. The core member 30 includes, for example, silicon oxide (SiO2).

[0122] In the memory structure MST within the trench structure TST, the first portion of the semiconductor 31 covers one of the two side surfaces of the core component 30 along the XZ plane, and the second portion of the semiconductor 31 covers one of the two side surfaces of the core component 30 along the XZ plane. The third portion of the semiconductor 31 covers the lower surface of the core component 30 and is in contact with the lower end of the first portion of the semiconductor 31, the lower end of the second portion of the semiconductor 31, and the conductor 21. The upper ends of the first and second portions of the semiconductor 31 reach the same position as the upper end of the core component 30. The semiconductor 31 is composed of, for example, polycrystalline silicon.

[0123] In the memory structure MST within the trench structure TST, the tunnel insulating film 32 a covers one of the two side surfaces of the semiconductor 31 along the XZ plane, and the tunnel insulating film 32 b covers the other of the two side surfaces of the semiconductor 31 along the XZ plane.

[0124] In the region within the trench structure TST where the memory structure MST is not formed, the tunnel insulating film 32a covers one of the two side surfaces of the core component 30 along the XZ plane, and the tunnel insulating film 32b covers the other of the two side surfaces of the core component 30 along the XZ plane. The upper ends of the tunnel insulating films 32a and 32b reach the same position as the upper ends of the core component 30 and the semiconductor 31, and are composed of, for example, silicon oxide (SiO2).

[0125] The charge storage film 33a covers the side surface of the tunnel insulating film 32a along the XZ plane, and the charge storage film 33b covers the side surface of the tunnel insulating film 32b along the XZ plane. The upper ends of the charge storage films 33a and 33b reach the same position as the upper ends of the core component 30 and the semiconductor 31.

[0126] The blocking insulating film 34a covers the side surfaces of the charge storage film 33a along the XZ plane, and the blocking insulating film 34b covers the side surfaces of the charge storage film 33b along the XZ plane. The upper ends of the blocking insulating films 34a and 34b reach the same position as the upper ends of the core component 30 and the semiconductor 31. The blocking insulating film 34a is in contact with each of the conductors 22a to 24a. The blocking insulating film 34b is in contact with each of the conductors 22b to 24b.

[0127] The charge storage films 33a and 33b are made of, for example, silicon nitride (SiN), and the block insulating films 34a and 34b are made of, for example, silicon oxide (SiO2).

[0128] Semiconductor 25, for example, comprises polycrystalline silicon and covers the upper surface of core component 30, the upper surface of semiconductor 31, and the upper surfaces of tunnel insulating films 32a and 32b. Thus, semiconductor 31 forms two parallel current paths between semiconductor 25 and conductor 21, arranged along the Y-axis and interposed between core component 30. In other words, semiconductor 25 functions as a junction JCT of the current paths.

[0129] Columnar conductors 26 functioning as contacts CP are provided on the upper surface of the semiconductor 25. The upper surface of each conductor 26 is in contact with and electrically connected to a corresponding conductor 27.

[0130] In the memory structure MST described above, the portion where the memory structure MST intersects conductor 22a functions as a select transistor STa2, and the portion where the memory structure MST intersects conductor 22b functions as a select transistor STb2. The portion where the memory structure MST intersects conductor 23a functions as a memory cell transistor MCa, and the portion where the memory structure MST intersects conductor 23b functions as a memory cell transistor MCb. The portion where the memory structure MST intersects conductor 24a functions as a select transistor STa1, and the portion where the memory structure MST intersects conductor 24b functions as a select transistor STb1.

[0131] Specifically, semiconductor 31 serves as the channel and well regions for select transistors STa1 and STb1, memory cell transistors MCa and MCb, and select transistors STa2 and STb2. Charge storage film 33a serves as the charge storage layer for memory cell transistor MCa, and charge storage film 33b serves as the charge storage layer for memory cell transistor MCb. Thus, memory structure MST functions as a pair of two memory strings MSa and MSb, for example.

[0132] In addition, the structure of the memory structure MST described above is only an example, and the memory structure MST may also have other structures. For example, the number of conductors 23 is based on the number of word lines WL, which can be designed to be any number. It is also possible to allocate any number of conductors 22 and 24 to the selection gate lines SGS and SGD, respectively. When multiple layers of conductors 22 are allocated to the selection gate line SGS, different conductors may be used for the multiple layers of conductors 22. It is also possible to set any number of conductors that function as dummy word lines (not shown) between the bottom word line WL and the selection gate line SGS, and between the top word line WL and the selection gate line SGD. The semiconductor 25 and the conductor 27 may be electrically connected via two or more contacts, or may be electrically connected via other wiring.

[0133] 1.2 Method for Manufacturing a Semiconductor Memory Device

[0134] Hereinafter, an example of a manufacturing process of a memory cell array in a semiconductor memory device according to an embodiment will be described. Figures 7 to 12 、 Figures 14 to 23 An example of a cross-sectional structure including a structure corresponding to a memory cell array in a manufacturing step of a semiconductor memory device according to an embodiment is shown, Figure 13 An example of a planar structure including a structure corresponding to a memory cell array in a manufacturing step of a semiconductor memory device according to an embodiment is shown. Figure 7 、 Figure 8 、 Figure 10、 Figure 11 、 Figure 14 、 Figure 15 、 Figure 17 、 Figure 19 and Figure 22 The regions shown in the cross-sectional views of the various manufacturing steps correspond to Figure 6 In addition, Figure 9 The cross-sectional views of the manufacturing steps shown are along Figure 8 A portion of the cross-sectional view of line IX-IX corresponds to Figure 5 area, Figure 12 、 Figure 16 、 Figure 18 、 Figure 21 and Figure 23 Corresponding to Figure 9 In addition, Figure 13 The top view of the manufacturing step shown corresponds to Figure 5 In addition, Figure 20 The cross-sectional views of the manufacturing steps shown are along Figure 19 A portion of the cross-sectional view of the XX-XX line corresponds to Figure 5 area.

[0135] First, if Figure 7 As shown, sacrificial material 43, 8 layers of sacrificial material 44, and sacrificial material 45 corresponding to the selection gate line SGS, word lines WL0 to WL7, and selection gate line SGD are stacked. Specifically, first, an insulator 41 and a conductor 21 are stacked in sequence on the semiconductor substrate 20. An insulator 42 and sacrificial material 43 are stacked in sequence on the conductor 21. On the sacrificial material 43, the insulator 42 and the sacrificial material 44 are stacked alternately multiple times ( Figure 7 In the example, 8 times.) The insulator 42 and the sacrificial material 45 are sequentially stacked on the sacrificial material 44. Then, the insulator 46 is further stacked on the sacrificial material 45.

[0136] Insulators 41, 42, and 46 include silicon oxide, for example, and sacrificial materials 43, 44, and 45 include silicon nitride, for example. The number of layers forming sacrificial materials 43, 44, and 45 corresponds to the number of stacked select gate lines SGS, word lines WL, and select gate lines SGD.

[0137] Then, if Figure 8 As shown, it will be Figure 7In the laminate formed in the steps shown, the region designated for forming the trench structure TST is removed to form the trench MT. Specifically, a mask is first formed using photolithography to open the region corresponding to the trench structure TST. Then, the trench MT is formed by anisotropic etching using the formed mask. The lower end of the trench MT reaches the conductor 21, for example. The anisotropic etching method used in this step is, for example, RIE (Reactive Ion Etching).

[0138] Figure 9 Indicates along Figure 8 The cross-sectional view of the IX-IX line. Figure 9 As shown in FIG. 1 , by this step, a linear trench MT and a portion of the laminated body including the sacrificial material 45 across the trench MT in the Y direction are formed. Figure 3 As shown, the build-up wiring has a shape extending longer than the trench structure TST in the X direction. Therefore, the portion of the build-up body including the sacrificial material 45 is not separated by the trench MT.

[0139] Then, if Figure 10 As shown, the blocking insulating film 34 , the charge storage film 33 , and the tunnel insulating film 32 are formed over the entire surface including the interior of the trench MT.

[0140] Then, if Figure 11 As shown, semiconductor 31 is further formed. Specifically, blocking insulating film 34, charge storage film 33, and tunnel insulating film 32 formed at the lower end of trench MT are removed, exposing conductor 21. As a result, blocking insulating film 34 is separated into blocking insulating film 34a and blocking insulating film 34b between insulators 42 and 46 and sacrificial materials 43, 44, and 45. Furthermore, charge storage film 33 is separated into charge storage film 33a in contact with blocking insulating film 34a and charge storage film 33b in contact with blocking insulating film 34b. Furthermore, tunnel insulating film 32 is separated into tunnel insulating film 32a in contact with charge storage film 33a and tunnel insulating film 32b in contact with charge storage film 33b. The etching process in this step is, for example, RIE.

[0141] Next, the semiconductor 31 is formed in the trench MT. Thus, the semiconductor 31 has two parts, one of which is in contact with the conductor 21, and the other is in contact with the blocking insulating film 34a on one of the two XZ planes in the trench MT, with the charge storage film 33a and the tunnel insulating film 32a interposed therebetween.

[0142] Figure 12 Indicates along Figure 11 The cross-sectional view of the XII-XII line. Figure 12As shown, through this step, in two parts of the space between the sacrificial materials 45, one on the sacrificial material 45 side and the other on the sacrificial material 45 side, a blocking insulating film 34a (34b), a charge storage film 33a (33b), a tunnel insulating film 32a (32b) and a semiconductor 31 are formed in sequence along the Y axis.

[0143] Then, if Figure 13 As shown, a protective material 50 is formed over the entire surface including the trench MT, and then a mask 60 is formed on the protective material 50. The mask 60 opens a region 61 in the X direction across a predetermined region where the memory structure MST is to be formed. Figure 13 In FIG. 1 , a cross-sectional structure in a layer where the sacrificial material 45 is provided below the protective material 50 is indicated by a dotted line.

[0144] Specifically, first, the protective material 50 is embedded in the trench MT so that the entire surface including the trench MT is covered with the protective material 50 film. The protective material 50 film can be, for example, a spin-on-carbon (SOC) film. Then, a mask 60 is formed on the protective material 50 film. This mask 60 has staggered openings in predetermined regions 61 of the structure formed in the trench MT where the memory structure MST will not be formed. For example, tetraethoxysilane (TEOS) is used as the mask 60.

[0145] Figure 14 Indicates along Figure 13 The cross-sectional view of the XIV-XIV line. Figure 14 As shown, through this step, a mask 60 is formed. The mask 60 protects a region where the memory structure MST is to be formed and opens a region 61 that is spaced apart from the region in the X direction.

[0146] Then, if Figure 15 As shown, semiconductor 31 in the region designated for forming memory structure MST within trench MT is not removed, but remains. Meanwhile, semiconductor 31 in opening region 61 of mask 60 is selectively removed. Specifically, anisotropic etching using mask 60 removes protective material 50 in opening region 61 of mask 60. The anisotropic etching in this step is, for example, RIE. This step forms a space in opening region 61 of mask 60, bounded by two XZ planes where semiconductor 31 is exposed within trench MT and two YZ planes formed by protective material 50 buried within trench MT.

[0147] Next, isotropic etching is performed within this space using the two YZ planes formed by the protective material 50 as masks to selectively remove the semiconductors 31 on the two exposed XZ planes. The isotropic etching in this step can be performed by, for example, wet etching or dry etching. After the exposed semiconductors 31 are selectively removed, the protective material 50 and mask 60 are removed by ashing or the like.

[0148] Figure 16 Indicates along Figure 15 The cross-sectional view of the XVI-XVI line. Figure 16 As shown, through this step, the semiconductor 31 in the trench MT corresponding to the opening region 61 of the mask 60 is selectively removed, leaving the predetermined region ( Figure 16 The semiconductor 31 in the region surrounded by the dotted line (inside) remains in the trench MT.

[0149] Then, if Figure 17 As shown, after the core component 30 is formed and the trench MT is filled, the structure is flattened by CMP (Chemical Mechanical Polishing) or the like, thereby removing the portion above the insulator 46 .

[0150] Figure 18 Indicates along Figure 17 The cross-sectional view of the XVIII-XVIII line. Figure 18 As shown, through this step, in the predetermined area ( Figure 18 In the space between the sacrificial materials 45 (the area surrounded by the dotted lines), a blocking insulating film 34a, a charge storage film 33a, a tunnel insulating film 32a, a semiconductor 31, a core component 30, a semiconductor 31, a tunnel insulating film 32b, a charge storage film 33b and a blocking insulating film 34b are formed in sequence along the Y axis.

[0151] Then, if Figure 19 As shown, semiconductor 25 is formed on the upper surface of the structure that fills trench MT in a region designated for forming memory structure MST. Specifically, an insulator 47 is first formed over the entire surface, and then a mask is formed using photolithography to open the region corresponding to semiconductor 25. Anisotropic etching using the formed mask is then performed to form a hole in the region designated for semiconductor 25, exposing semiconductor 31. By embedding semiconductor 25 in this hole, semiconductor 31 is electrically connected to semiconductor 25.

[0152] Figure 20 Indicates along Figure 19 The cross-sectional view of the XX-XX line. Figure 20In FIG. 1 , the dotted line indicates the cross-sectional structure of the layer where the sacrificial material 45 is provided below the semiconductor 25. Figure 20 As shown, through this step, in the predetermined region for forming the memory structure MST, the first portion of the semiconductor 31 and the second portion of the semiconductor 31 are covered by a single semiconductor 25. Thus, the first portion of the semiconductor 31 and the second portion of the semiconductor 31 are connected in parallel between the semiconductor 25 and the conductor 21.

[0153] Then, if Figure 21 As shown, a hole STH is formed in the region where the support STP1 is to be formed, separating the portion sandwiched between the structures embedded in two adjacent trenches MT in the Y direction along the X direction. The hole STH separates the sacrificial material 45 into two portions 45a and 45b. Furthermore, the sacrificial materials 45a and 45b are exposed in the hole STH.

[0154] In addition, although Figure 21 Although not shown, similar to sacrificial material 45, sacrificial materials 43 and 44 are separated into two parts 43a and 43b, and 44a and 44b, respectively. Furthermore, similar to sacrificial materials 45a and 45b, sacrificial materials 43a and 43b, and 44a and 44b are exposed in hole STH. Furthermore, insulators 42 and 46 are separated into insulators 42a and 42b, and insulators 46a and 46b, respectively. The etching process in this step is, for example, RIE, an anisotropic etching process that etches all materials of the structure filling trench MT at the same rate.

[0155] Then, if Figure 22 As shown, through the hole STH, the sacrificial materials 43a, 44a and 45a are replaced by the conductors 22a, 23a and 24a, respectively, and the sacrificial materials 43b, 44b and 45b are replaced by the conductors 22b, 23b and 24b, respectively. Figure 22 is with Figure 6 1 is a cross-sectional view of the memory cell array 10 corresponding to the region shown. Specifically, sacrificial materials 43a, 44a, 45a, 43b, 44b, and 45b are selectively removed by wet etching or dry etching through hole STH. Then, conductors 22a and 22b are formed in the spaces left after sacrificial materials 43a and 43b are removed, respectively. Conductors 23a and 23b are formed in the spaces left after sacrificial materials 44a and 44b are removed, respectively. Conductors 25a and 25b are formed in the spaces left after sacrificial materials 45a and 45b are removed, respectively.

[0156] Then, if Figure 23 As shown, the hole STH is filled with an insulator 39. The insulator 39 functions as a support pillar STP1 of the memory cell array 10.

[0157] Through the above steps, memory strings MSa and MSb are formed in the region where memory structure MST is to be formed. Subsequently, memory cell array 10 is formed by forming conductors 26 and 27, and forming contacts with conductors 22a and 22b, 23a and 23b, and 24a and 24b.

[0158] Furthermore, the manufacturing steps described above are merely examples, and other processing may be inserted between the manufacturing steps, or the order of the manufacturing steps may be reversed.

[0159] 1.3 Effects of the Embodiment According to the embodiment, it is possible to suppress the collapse of the semiconductor memory device and improve the integration density. The effects of the embodiment will be described below.

[0160] The first laminate includes four branch wiring regions corresponding to select gate lines SGDa (SGD0, SGD2, SGD4, and SGD6), and the second laminate includes four branch wiring regions corresponding to select gate lines SGDb (SGD1, SGD3, SGD5, and SGD7). The wiring regions included in the first and second laminates each include a central wiring portion L1, multiple peripheral wiring portions L2 and L3, and multiple connectors J1 and J2. The multiple peripheral wiring portions L2 and L3 are connected to the central wiring portion L1 at both ends of the central wiring portion L1 along the Y direction via multiple connectors J1 and J2. The peripheral wiring portion L2 (or peripheral wiring portion L3) of the wiring area corresponding to one selection gate line SGD is arranged in the X direction with the connection portion J2 (or connection portion J1) of the wiring area corresponding to the adjacent selection gate line SGD interposed with the pillar STP1, and is provided between the central wiring portion L1 of the wiring area corresponding to the adjacent selection gate line SGD and the peripheral wiring portion L3 (or peripheral wiring portion L2) of the wiring area corresponding to the adjacent selection gate line SGD. The pillar STP1 has, for example, an elliptical shape with a major axis parallel to the Y direction and a minor axis parallel to the X direction. If the shape of the wiring area and the shape of the pillar STP1 is such, the axial length of the pillar STP1 along the Y direction can be ensured, and the interval between adjacent trench structures TST in the Y direction can be shortened. In other words, even in the case where the interval between adjacent trench structures TST in the Y direction is short, in the manufacturing step Figure 22 In the illustrated steps, the length of the hole STH formed in the region corresponding to the pillar STP1 along the Y direction can be sufficiently ensured. Therefore, when the sacrificial material is replaced with a conductive body, clogging of the hole STH can be suppressed. As a result, the size of the memory cell array 10 can be reduced, thereby increasing the integration density.

[0161] In addition, if the wiring area is structured as described above, then in the manufacturing step Figure 8 After trench MT is formed in the illustrated step, the portions corresponding to the plurality of connections J1 and J2 of the wiring region can be used to support the portions corresponding to the central wiring portion L1 of the wiring region at both ends along the Y direction. This can prevent the memory cell array 10 from collapsing during the manufacturing process.

[0162] In addition, the plurality of connection parts J1 are arranged along the X direction at a predetermined interval. The plurality of connection parts J2 are arranged along the X direction at the same interval as the plurality of connection parts J1, and are arranged at positions staggered relative to the plurality of connection parts J1 along the X direction. In this way, the connection parts J1 and the connection parts J2 can be dispersed along the X direction at both ends of the central wiring part L1 in the Y direction. The shape of the wiring area can also suppress the manufacturing process. Figure 8 The steps of the collapse of the memory cell array 10 are shown.

[0163] 2. Variations

[0164] Various modifications can be made to the embodiments described above.

[0165] A semiconductor memory device according to a variation is described below. Descriptions of the same configurations and manufacturing steps as those in the embodiment are omitted, and the description will focus on configurations and manufacturing steps that differ from those in the embodiment. Furthermore, similar to the embodiment, the semiconductor memory device according to the variation can suppress collapse of the semiconductor memory device and improve integration density.

[0166] 3.1 Variation 1

[0167] In the above embodiment, the first and second laminates are separated by the trench structure TST and the support pillars STP1, but the present invention is not limited thereto. For example, the first and second laminates may be separated by the trench structure TST, and a plurality of support pillars STP1 may be provided in the wiring area.

[0168] use Figure 24 A semiconductor memory device according to a first variation will be described. Figure 24 Corresponding to the embodiment Figure 3 .

[0169] like Figure 24 As shown, in the first variation, in addition to the plurality of trench structures TST1 to TST3 extending along the X direction, a plurality of trench structures TST4 extending along the Y direction are further provided. The plurality of trench structures TST4 are provided so as to connect an end portion of the trench structure TST3 provided along the X direction to an end portion of the trench structure TST1 or TST2 adjacent to the trench structure TST3 along the Y direction.

[0170] According to this arrangement, in the first modification, the first stacked body and the second stacked body are separated from each other by arranging the plurality of trench structures TST1 to TST3 extending along the X direction and the plurality of trench structures TST4 extending along the Y direction.

[0171] In the first variation, a plurality of support posts STP1 having a shape similar to that of the embodiment are provided in the plurality of connection portions J1 and J2. For example, the plurality of support posts STP1 are provided at the center of the corresponding connection portion J1 (or connection portion J2) along the X direction so as not to separate the corresponding peripheral wiring portion L2 (or peripheral wiring portion L3) from the central wiring portion L1.

[0172] Next, a method for manufacturing the semiconductor memory device 1 according to the first modification will be described.

[0173] The semiconductor memory device 1 of the first variation can be realized by Figures 7 to 23 are manufactured using substantially the same steps.

[0174] In the first variation, Figure 8 In the step of removing the trench structures TST1 to TST3, the region planned for forming the trench structures TST4 is also removed, thereby forming trenches MT. Furthermore, through this step, the sacrificial materials 43, 44, and 45, and the insulators 42 and 46 are separated by trenches MT into two portions 43a and 43b, 44a and 44b, 45a and 45b, 42a and 42b, and 46a and 46b, respectively.

[0175] According to the first variation, the first and second stacked bodies are separated from each other by the plurality of trench structures TST1 to TST4, and a plurality of pillars STP1 are provided, one at each of the plurality of connections J1 and J2 in the wiring region. This prevents an increase in the area occupied by the pillars STP1, thereby preventing a decrease in the area within the trench structure TST where the memory structure MST can be provided. Consequently, the integration density can be further improved.

[0176] 2.2 Variation 2

[0177] In the first variation, an example is shown in which the first and second laminates are separated by a plurality of trench structures TST1 to TST4, but the present invention is not limited thereto. For example, the first and second laminates may be separated by a plurality of support pillars STP1 in addition to being separated by the plurality of trench structures TST1 to TST4. Below, descriptions of configurations identical to those in the first variation are omitted, and descriptions of configurations different from those in the first variation are primarily provided. Furthermore, the semiconductor memory device of the second variation can be manufactured using manufacturing steps substantially identical to those in the embodiment and the first variation, and therefore, descriptions thereof are omitted.

[0178] use Figure 25 The layout of the memory cell array of the semiconductor memory device 1 according to the second modification will be described. Figure 25 Corresponding to the embodiment Figure 3 .

[0179] like Figure 25 As shown, in the second variation, a plurality of groove structures TST4 are respectively arranged in a manner of connecting one end side (+X direction side) of the groove structure TST1 in the X direction and one end side (+X direction side) of the groove structure TST3 adjacent to the groove structure TST1 in the Y direction, and one end side (+X direction side) of the groove structure TST2 in the X direction and one end side (+X direction side) of the groove structure TST3 adjacent to the groove structure TST2 in the Y direction.

[0180] Multiple pillars STP1 are respectively arranged in a manner of connecting the other end side (-X direction side) of the groove structure TST1 in the X direction and the other end side (-X direction side) of the groove structure TST3 adjacent to the groove structure TST1 along the Y direction, and the other end side (-X direction side) of the groove structure TST2 in the X direction and the other end side (-X direction side) of the groove structure TST3 adjacent to the groove structure TST2 along the Y direction.

[0181] According to such an arrangement, in the second modification, the first stacked body and the second stacked body are separated from each other by arranging the plurality of trench structures TST1 to TST4 and the plurality of pillars STP1.

[0182] This configuration can also produce the same effects as those of the first modified example.

[0183] 2.3 Variation 3

[0184] In the first variation, an example is shown in which each of the plurality of pillars STP1 is disposed within the plurality of connecting portions J1 and J2, but the present invention is not limited thereto. For example, the plurality of pillars STP1 may be disposed so as to divide the trench structure TST. Below, descriptions of configurations equivalent to those in the first variation are omitted, and descriptions of configurations different from those in the first variation are primarily provided. Furthermore, the semiconductor memory device 1 of the third variation can be manufactured using manufacturing steps substantially equivalent to those in the embodiment, the first variation, and the second variation, and therefore, descriptions thereof are omitted.

[0185] use Figure 26 The layout of the memory cell array of the semiconductor memory device 1 according to the third modification will be described. Figure 26 Corresponding to the embodiment Figure 3 .

[0186] like Figure 26 As shown, in the third variation, a plurality of pillars STP1 are provided to divide the trench structure TST1 and the trench structure TST2. The plurality of pillars STP1 are respectively arranged at the center position of the corresponding trench structure TST1 or trench structure TST2 along the X direction.

[0187] Even with this configuration, the same effects as those of the first and second modified examples can be achieved.

[0188] 2.4 Variation 4

[0189] In the third variation, the first and second laminates are separated by the plurality of trench structures TST1 to TST4, but the present invention is not limited thereto. For example, the first and second laminates may be separated by a plurality of trench structures TST1 to TST3 extending in the X direction and a plurality of struts STP2 that are smaller than the plurality of struts STP1 in a plan view.

[0190] use Figure 27 A semiconductor memory device 1 according to a fourth variation will be described. Figure 27 Corresponding to the embodiment Figure 3 In addition, the following description of the configuration equivalent to the third modification example is omitted, and the description will mainly focus on the configuration different from the third modification example.

[0191] like Figure 27As shown, in the fourth variation, a plurality of pillars STP2 are provided. These pillars STP2 are smaller than the plurality of pillars STP1 in a plan view and, like the plurality of pillars STP1, have an elliptical shape with a major axis parallel to the Y direction and a minor axis parallel to the X direction. For example, the plurality of pillars STP2 have a length in the major axis that is the same as that of the plurality of pillars STP1, but a shorter length in the minor axis than that of the plurality of pillars STP1. For example, the plurality of pillars STP2 are provided so as to overlap with an end portion of the trench structure TST3 and an end portion of the trench structure TST1 or TST2 adjacent to the trench structure TST3 in the Y direction.

[0192] According to this arrangement, in the fourth variation, the first and second layered bodies are separated from each other by arranging the plurality of trench structures TST extending in the X direction and the plurality of pillars STP2 smaller than the plurality of pillars STP1.

[0193] Next, a method for manufacturing the semiconductor memory device 1 according to the fourth modification will be described.

[0194] The semiconductor memory device 1 of the fourth variation can be realized by Figures 7 to 23 are manufactured using substantially the same steps.

[0195] Furthermore, in the fourth variation, Figure 21 In the step of forming the plurality of pillars STP1 and STP2, corresponding holes STH are formed in the predetermined areas. This step separates the sacrificial materials 43, 44, and 45, and the insulators 42 and 46 into two parts 43a and 43b, 44a and 44b, 45a and 45b, 42a and 42b, and 46a and 46b, respectively.

[0196] In addition, in the fourth variation, Figure 22 In the step, the sacrificial materials 43a, 43b, 44a, 44b, 45a and 45b are replaced with the conductors 22a, 22b, 23a, 23b, 24a and 24b respectively through the holes STH corresponding to the pillars STP1 and STP2 respectively.

[0197] According to the fourth variation, in addition to the plurality of supports STP1, a plurality of supports STP2 having a shorter length in the short axis direction (X direction) than the plurality of supports STP1 are provided. Figure 22 In the step of , the holes STH corresponding to the plurality of support posts STP2 can assist in the replacement of the sacrificial material to the conductor via the holes STH corresponding to the support posts STP1 , thereby alleviating the load of the step of replacing the sacrificial material to the conductor.

[0198] 3. Others

[0199] In addition, the above-described embodiment and the first to fourth modified examples can be modified in various ways.

[0200] For example, in the above embodiment and the first to fourth variations, the charge storage films 33a and 33b are described as being formed as continuous films within the memory strings MSa and MSb, respectively. However, the present invention is not limited thereto. For example, the charge storage film 33a may be provided separately and individually for each of the multiple memory cell transistors MCa within the memory string MSa, and the charge storage film 33b may be provided separately and individually for each of the multiple memory cell transistors MCb within the memory string MSb. In this case, the separately provided charge storage films may include polysilicon or a metal containing at least one selected from titanium (Ti), tungsten (W), and ruthenium (Ru).

[0201] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in a variety of other ways, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments and their variations are intended to be within the scope and spirit of the invention and are also intended to be within the scope of the invention as set forth in the claims and their equivalents.

[0202] [Explanation of Symbols]

[0203] 1 Semiconductor memory device

[0204] 10 memory cell array

[0205] 11 Instruction register

[0206] 12 Address registers

[0207] 13 Sequencer

[0208] 14 Driver Module

[0209] 15-line decoder module

[0210] 16 Sense Amplifier Modules

[0211] 20 semiconductor substrate

[0212] 21, 22a-24a, 22b-24b, 26, 27 Conductors

[0213] 25, 31 Semiconductors

[0214] 30 core components

[0215] 32, 32a, 32b tunnel insulating film

[0216] 33, 33a, 33b Charge storage membrane

[0217] 34, 34a, 34b: barrier insulating film

[0218] 41, 42, 42a, 42b, 46, 46a, 46b insulators

[0219] 43, 43a, 43b, 44, 44a, 44b, 45, 45a, 45b Sacrificial materials

[0220] MSa, MSb memory strings

[0221] CU unit components

[0222] SU string components

[0223] TST, TST1, TST2, TST3, TST4 groove structures

[0224] STP1, STP2 pillars.

Claims

1. A semiconductor memory device comprising: a first laminate including a plurality of first conductors laminated along a first direction; a second laminate including a plurality of second conductors laminated along the first direction; and a first structure including at least one memory structure and disposed between the first stacked body and the second stacked body; The at least one memory structure comprises: The first semiconductor film and the second semiconductor film extend along the first direction respectively; a first charge storage film extending along the first direction between the first stacked body and the first semiconductor film; and a second charge storage film extending along the first direction between the second stacked body and the second semiconductor film; The first layered body and the second layered body each include: The first portion, the second portion, and the third portion each extend along a second direction intersecting the first direction, wherein the first portion is provided between the second portion and the third portion in a third direction intersecting the first direction and the second direction; Part 4, connecting the first part with the second part; and Part 5 connects the first part to the third part; and The second portion of the first layered body is provided between the first portion of the second layered body and the third portion of the second layered body in the third direction.

2. The semiconductor memory device according to claim 1, wherein In each of the first layered body and the second layered body, the fourth portion and the fifth portion are provided at positions different from each other along the second direction.

3. The semiconductor memory device according to claim 2, wherein The second portion of the first layered body and the second portion of the second layered body are arranged along the third direction, The third portion of the first layered body and the third portion of the second layered body are arranged along the third direction, and in each of the first layered body and the second layered body, The second portion includes: a first sub-portion and a second sub-portion, each extending along the second direction; and a third sub-portion, connected to the fourth portion between the first sub-portion and the second sub-portion; The third portion includes: a first sub-portion and a second sub-portion, each extending along the second direction; and a third sub-portion connected to the fifth portion between the first sub-portion and the second sub-portion; The first sub-portion of the second portion and the second sub-portion of the third portion are arranged along the third direction.

4. The semiconductor memory device according to claim 3, wherein The first structure further includes a first insulator that extends along the first direction between the fourth portion of the first laminate and the third portion of the second laminate and is different from the memory structure.

5. The semiconductor memory device according to claim 4, wherein The first structure further includes a second insulator that extends along the first direction between the second portion of the first laminate and the fifth portion of the second laminate and is different from the memory structure. The semiconductor memory device according to claim 3 , wherein The first structure further comprises: a third insulator extending along the first direction between the third sub-portion of the second portion of the first laminate and the first portion of the second laminate and different from the memory structure; and A fourth insulator extends along the first direction between the first portion of the first laminate and the third sub-portion of the third portion of the second laminate, and is different from the memory structure.

7. The semiconductor memory device according to claim 5, wherein The first structure further comprises: a fifth insulator extending along the first direction between the third sub-portion of the second portion of the first laminate and the first portion of the second laminate, and different from the memory structure; and A sixth insulator extends along the first direction between the first portion of the first laminate and the third sub-portion of the third portion of the second laminate, and is different from the memory structure.

8. The semiconductor memory device according to claim 7, wherein The lengths of the first insulator and the second insulator along the second direction are shorter than the lengths of the fifth insulator and the sixth insulator along the second direction.

9. The semiconductor memory device according to any one of claims 1 to 3, wherein The first structure further comprises: a seventh insulator extending along the first direction within the fourth portion of the first laminate; an eighth insulator extending along the first direction within the fifth portion of the first laminate; a ninth insulator extending along the first direction within the fourth portion of the second laminate; and The tenth insulator extends along the first direction within the fifth portion of the second laminate.

10. The semiconductor memory device according to any one of claims 1 to 8, further comprising: a third laminate including a plurality of third conductors laminated along the first direction; and a second structure including at least one memory structure and disposed between the first stack and the second stack; The at least one memory structure within the second structure includes: a second semiconductor film extending along the first direction; a third charge storage film extending along the first direction between the first stack and the second semiconductor film; and a fourth charge storage film extending along the first direction between the third stacked body and the second semiconductor film; The third layered body comprises: The first part, the second part and the third part extend along the second direction respectively, wherein The first portion is provided between the second portion and the third portion in the third direction, Part 4, connecting the first part with the second part; and Part 5 connects the first part to the third part; and The third portion of the first layered body is provided between the first portion of the third layered body and the second portion of the third layered body in the third direction.

11. The semiconductor memory device according to claim 10, wherein The at least one memory structure in the first structure includes a first memory structure and a second memory structure. The at least one memory structure in the second structure includes a third memory structure, and the first memory structure, the second memory structure, and the third memory structure are arranged along the third direction. The first memory structure is provided between the second portion of the first laminate and the first portion of the second laminate. The second memory structure is provided between the first portion of the first laminate and the third portion of the second laminate, and The third memory structure is provided between the third portion of the first stacked body and the second portion of the third stacked body.

12. The semiconductor memory device according to claim 11, wherein The at least one memory structure in the first structure further includes a fourth memory structure, The at least one memory structure in the second structure further includes a fifth memory structure and a sixth memory structure, The fourth memory structure, the fifth memory structure, and the sixth memory structure are arranged along the third direction. The fourth memory structure is provided between the second portion of the first laminate and the third portion of the second laminate. The fifth memory structure is provided between the first portion of the first laminate and the second portion of the third laminate. The sixth memory structure is provided between the third portion of the first laminate and the first portion of the third laminate, and The fourth memory structure, the fifth memory structure, and the sixth memory structure are provided at different positions along the second direction relative to the first memory structure, the second memory structure, and the third memory structure.

13. The semiconductor memory device according to any one of claims 1 to 8, wherein The second layered body further comprises: The sixth portion, the seventh portion, and the eighth portion extend along the second direction, respectively, wherein: The sixth portion is provided between the seventh portion and the eighth portion in the third direction, Part 9, connecting the part 6 and the part 7; Part 10, connecting the part 6 and the part 8; and Part 11 connects said Part 1 to said Part 6; and The third portion of the first layered body is provided between the sixth portion of the second layered body and the seventh portion of the second layered body in the third direction.

14. The semiconductor memory device according to claim 13, wherein The at least one memory structure includes a first memory structure, a second memory structure, and a third memory structure arranged along the third direction. The first memory structure is provided between the second portion of the first laminate and the first portion of the second laminate. The second memory structure is provided between the first portion of the first laminate and the third portion of the second laminate, and The third memory structure is provided between the third portion of the first stacked body and the seventh portion of the second stacked body.

15. The semiconductor memory device according to claim 14, wherein The at least one memory structure further includes a fourth memory structure, a fifth memory structure, and a sixth memory structure arranged along the third direction. The fourth memory structure is provided between the second portion of the first laminate and the third portion of the second laminate. The fifth memory structure is provided between the first portion of the first laminate and the seventh portion of the second laminate. The sixth memory structure is provided between the third portion of the first laminate and the sixth portion of the second laminate, and The fourth memory structure, the fifth memory structure, and the sixth memory structure are provided at different positions along the second direction relative to the first memory structure, the second memory structure, and the third memory structure.

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