Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes providing a substrate including a device region, forming a first well within the substrate, forming a select gate and storage gates on both sides of the select gate on the device region after forming the first well, forming a second well within the substrate on both sides of the select gate and storage gates after forming the select gate and storage gates, and part of the second well is also located at the bottom of the storage gate. One lithography can be reduced, and direct injection to the select gate channel is avoided, thereby improving device performance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. BACKGROUND

[0002] SONOS (Semiconductor-Oxide-Nitride-Oxide-Semiconductor) technology, which has low operating voltage and better COMS process compatibility, is widely used in various embedded electronic products, such as financial IC cards, automotive electronics, and the like.

[0003] In the prior art, in a mirror bit SONOS device structure, a storage tube-selecting tube-storage tube back-to-back adjacent structure is adopted, the storage tube and the selecting tube are separated by an isolation oxide layer, and the three devices share a P-type well and source-drain.

[0004] However, in the method for forming the above structure, different threshold voltages of the selecting tube and the storage tube are formed by twice implantation, the number of photolithography is large, and repeated doping of the device channel greatly reduces the mobility of the device channel and degrades the performance of the device. SUMMARY

[0005] The technical problem solved by the present application is to provide a method for forming a semiconductor structure, which adjusts the threshold voltage of the selecting gate by first performing ion implantation on a substrate, and then performs LDD oblique angle implantation to adjust the threshold voltage of the storage gate, so as to reduce the number of photolithography and avoid direct implantation on the channel of the selecting gate, thereby improving the performance of the device.

[0006] To solve the above technical problem, the technical solution of the present application provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising: a device region; forming a first well in the substrate; after forming the first well, forming a selecting gate and storage gates located on both sides of the selecting gate on the device region; after forming the selecting gate and the storage gates, forming a second well in the substrate on both sides of the selecting gate and the storage gates, and part of the second well is also located at the bottom of the storage gate.

[0007] Optionally, the process for forming the second well is an ion implantation process, and the process parameters for forming the second well include: an implantation energy range of 2keV-100keV, an implantation dose range of 1x1013cm-2-5x1013cm-2, an implantation direction perpendicular to the channel width direction, and an included angle between the implantation direction and the sidewall of the storage gate ranging from 15 degrees to 45 degrees. 12 -2 14 -2

[0008] ​​​​Optionally, the first well is doped with first ions; and the second well is doped with second ions, and the second ions have the same conductivity type as the first ions.

[0009] Optionally, the first ions are P-type ions, and the second ions are P-type ions; or the first ions are N-type ions, and the second ions are N-type ions.

[0010] Optionally, the method further comprises, after forming the first well and before forming the select gate, forming a first gate dielectric layer on the device region.

[0011] Optionally, the first gate dielectric layer comprises a first oxide layer on the substrate surface, a first nitride layer on the first oxide layer surface, and a second oxide layer on the first nitride layer surface.

[0012] Optionally, the method of forming the storage gate and the select gate comprises: forming a first gate material layer on the substrate, the first gate material layer being on the first gate dielectric layer; forming a mask layer on the first gate material layer, the mask layer having a first opening on the device region, the first opening exposing part of the first gate material layer; forming a first sidewall on the first opening sidewall; etching the first gate material layer and the first gate dielectric layer until the substrate surface is exposed, using the mask layer and the first sidewall as masks, to form a second opening in the first gate material layer and the first gate dielectric layer; forming a second sidewall on the first sidewall sidewall and the second opening sidewall; after forming the second sidewall, forming a select gate in the first opening and the second opening; after forming the select gate, removing the mask layer; after removing the mask layer, etching the first gate material layer and the first gate dielectric layer using the first sidewall as a mask, to form a storage gate and a third sidewall between the first sidewall and the substrate.

[0013] Optionally, the substrate further comprises a logic region.

[0014] Optionally, the method further comprises: after forming the first gate dielectric layer, forming a second gate dielectric layer on the logic region; the first gate material layer is further on the second gate dielectric layer; after removing the mask layer, etching part of the first gate material layer on the logic region to form a logic gate layer on the logic region.

[0015] Optionally, the material of the second gate dielectric layer comprises an oxide.

[0016] Optionally, further comprising: forming a third gate dielectric layer in the first and second openings after forming the second sidewall and before forming the select gate, the third gate dielectric layer being between the substrate and the select gate.

[0017] Optionally, the method of forming the first sidewall comprises: forming a first sidewall material layer on the mask layer after forming the mask layer, the first sidewall material layer having a third opening in the first opening; and etching back the first sidewall material layer to form the first sidewall on the sidewall of the first opening.

[0018] Optionally, the method of forming the second sidewall comprises: forming a second sidewall material layer in the second opening and on the mask layer and the first sidewall after forming the second opening; and etching back the second sidewall material layer to form the second sidewall on the sidewall of the second opening and the sidewall of the first sidewall.

[0019] Optionally, the material of the mask layer comprises: silicon nitride.

[0020] Optionally, the material of the select gate comprises: polysilicon.

[0021] Optionally, the material of the storage gate comprises: polysilicon.

[0022] Compared with the prior art, the technical scheme of the present application has the following beneficial effects:

[0023] In the method of forming a semiconductor structure provided by the present application, the second well is formed after the formation of the select gate and the storage gate, and the formation process of the second well avoids direct ion implantation on the channel of the select gate, thereby improving the mobility of the channel and the performance of the device. In addition, the formation of the second well is performed by ion implantation with the select gate and the storage gate as a mask, which can reduce one-time photolithography and simplify the process.

[0024] Further, the process parameters for forming the second well include: an implantation energy range of 2keV-100keV and an implantation dose range of 1x1011e 12 cm -2 -5x1011e 14 cm -2 , which belongs to a light-doped ion implantation process. Therefore, the formation process of the second well can avoid direct doping on the channel of the select gate, thereby improving the mobility of the channel and the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figures 1 to 4 is a structural schematic diagram of a storage unit structure formation process.

[0026] Figures 5 to 19 Figure 1 is a schematic diagram of a structure for a semiconductor structure formation process according to an embodiment of the present application. DETAILED DESCRIPTION

[0027] As described in the background section, the different threshold voltages of the select transistor and the storage transistor are formed by twice implantation, and the multiple times of photolithography and repeated doping of the device channel greatly reduce the mobility of the device channel and degrade the performance of the device.

[0028] Figures 1 to 4 Figure 2 is a schematic diagram of a structure for a memory cell structure formation process according to an embodiment of the present application.

[0029] Referring to Figure 1 A substrate 100 is provided, which includes a device region A and a logic region B, and a first well 101 is formed in the device region A by an ion implantation process.

[0030] Referring to Figure 2 A first gate structure 109 is formed on the substrate 100, which has a first opening 108 in the device region A, and the first opening 108 exposes part of the substrate 100.

[0031] Referring to Figure 3 A second well 110 is formed in the first opening 108 by ion implantation with the second mask layer 107 as a mask.

[0032] Referring to Figure 4 After the second well 110 is formed, a select gate 117 is formed in the first opening 108, and the first gate structure 109 is etched to form a storage gate 111.

[0033] In this embodiment, the entire channel region is doped in the process of forming the first well 101, and the threshold voltage of the select gate and the threshold voltage of the storage gate of the semiconductor are adjusted. The channel of the select gate is doped again in the process of forming the second well 110, and the threshold voltage of the select gate is adjusted. The repeated doping of the device channel greatly reduces the mobility of the device channel, thereby degrading the performance of the device.

[0034] In addition, the second mask layer 107 is needed to be patterned in this embodiment to form the second well 110, and the number of times of photolithography patterning is relatively large.

[0035] To solve the technical problem, since the second well is formed after the formation of the select gate and the storage gate in the technical scheme of the present application, the forming process of the second well avoids direct ion implantation on the select gate channel, thereby improving the mobility of the channel and the performance of the device. In addition, since the formation of the second well is ion implantation with the select gate and the storage gate as a mask, one photolithography can be reduced, and the process is simplified.

[0036] To make the above-mentioned purposes, features and benefits of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0037] Figures 5 to 19 The structure schematic diagram of the forming process of the semiconductor structure in the embodiment of the present application.

[0038] Please refer to Figure 5 , a substrate 100 is provided, which comprises a device area A.

[0039] In the embodiment, the material of the substrate 200 is silicon.

[0040] In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI). Among them, the multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP.

[0041] The device area A provides a process platform for the subsequent formation of a SONOS device.

[0042] Please refer to Figure 6 , a first well 101 is formed in the substrate 100. The first well 101 is doped with a first ion.

[0043] In the embodiment, the process of forming the first well 101 is ion implantation process.

[0044] The first ion includes P-type ion or N-type ion. In the embodiment, the first ion includes boron.

[0045] The threshold voltage of the select gate can be adjusted by forming the first well 101.

[0046] Please refer to Figure 7 , after the formation of the first well 101, a first gate dielectric layer 104 is formed on the device area A.

[0047] The first gate dielectric layer 104 is used to form the subsequent third side wall.

[0048] The first gate dielectric layer 104 is of an ONO structure, and the structure of the first gate dielectric layer 104 includes a first oxide layer on the surface of the substrate 100, a first nitride layer on the surface of the first oxide layer, and a second oxide layer on the surface of the first nitride layer. In this embodiment, the material of the first oxide layer includes silicon oxide, the material of the first nitride layer includes silicon nitride, and the material of the second oxide layer includes silicon oxide. The forming process of the first gate dielectric layer 104 includes a thermal oxidation process, an atomic layer deposition process, or a chemical vapor deposition process.

[0049] Please refer to Figure 5 , the substrate 200 further includes a logic region B.

[0050] The logic region B provides a process platform for forming a logic device subsequently.

[0051] Please refer to Figure 8 , after the first gate dielectric layer 104 is formed, a second gate dielectric layer 105 is formed on the logic region B.

[0052] The second gate dielectric layer 105 is used to isolate the substrate and a logic gate layer subsequently.

[0053] In this embodiment, the material of the second gate dielectric layer 105 includes an oxide.

[0054] Next, after the first well 101 is formed, a select gate and storage gates on both sides of the select gate are formed on the device region A. The forming method of the storage gate and the select gate is specifically described in Figures 9 to 18 .

[0055] Please refer to Figure 9 , a first gate material layer 106 is formed on the substrate 100, the first gate material layer 106 is on the first gate dielectric layer 104, and the first gate material layer 106 is also on the second gate dielectric layer 105; a mask layer 107 is formed on the first gate material layer 106, the mask layer 107 has a first opening 108 on the device region A, and the first opening 108 exposes part of the first gate material layer 106.

[0056] The first gate material layer 106 is used to form a storage gate and a logic gate layer subsequently.

[0057] In this embodiment, the material of the first gate material layer 106 includes polysilicon.

[0058] The forming method of the mask layer 107 includes: forming a first mask material layer on the first gate material layer 106; forming a photoresist layer on the first mask material layer, the photoresist layer has an opening on the device area A; taking the patterned photoresist layer as a mask, etching the first mask material layer until part of the first gate material layer 106 is exposed, thereby forming the mask layer 107.

[0059] In this embodiment, the material of the mask layer 107 includes silicon nitride.

[0060] Next, a first sidewall is formed on the sidewall of the first opening 108. The forming method of the first sidewall is described in detail in the following Figure 10 and Figure 11 .

[0061] After the mask layer 107 is formed, a first sidewall material layer 110 is formed on the mask layer 107, and the first sidewall material layer 110 has a third opening 111 in the first opening 108, as described in the following Figure 10

[0062] The first sidewall material layer 110 is used to form a subsequent first sidewall.

[0063] In this embodiment, the material of the first sidewall material layer 110 includes oxide.

[0064] The first sidewall material layer 110 is etched to form a first sidewall 109 on the sidewall of the first opening 108, as described in the following Figure 11

[0065] In this embodiment, the material of the first sidewall 109 includes oxide.

[0066] The first sidewall 109 and the mask layer 107 are used as masks to form a storage gate and a third sidewall subsequently.

[0067] The first gate material layer 106 and the first gate dielectric layer 104 are etched until the surface of the substrate 100 is exposed, and a second opening 112 is formed in the first gate material layer 106 and the first gate dielectric layer 104, as described in the following Figure 12

[0068] The method of etching the first gate material layer 106 and the first gate dielectric layer 104 includes a dry etching process.

[0069] Next, a second sidewall is formed on the sidewall of the first sidewall 109 and the sidewall of the second opening 112. The forming method of the second sidewall is described in the following Figure 13 and Figure 14 ​​​.

[0070] Referring to Figure 13 After forming the second opening 112, a second sidewall material layer 114 is formed in the second opening 112 and on the mask layer 107 and the first sidewall 109, the second sidewall material layer 114 having a fourth opening 115 in the second opening 112.

[0071] The second sidewall material layer 114 is used to form a subsequent second sidewall.

[0072] In this embodiment, the material of the second sidewall material layer includes oxide.

[0073] Referring to Figure 14 The second sidewall material layer 114 is etched to form a second sidewall 113 on the sidewall of the first sidewall 109 and the sidewall of the second opening 112.

[0074] The method of etching the second sidewall material layer 114 includes a dry etching process.

[0075] In this embodiment, the material of the second sidewall 113 includes oxide.

[0076] The second sidewall 113 is used to isolate a subsequent select gate and a storage gate.

[0077] Referring to Figure 15 After forming the second sidewall 113, a third gate dielectric layer 117 is formed in the first opening 108 and the second opening 112.

[0078] The third dielectric layer 117 is used to isolate the substrate and a subsequently formed select gate.

[0079] In this embodiment, the material of the third dielectric layer 117 includes oxide.

[0080] Referring to Figure 16 After forming the second sidewall 113, a select gate 102 is formed in the first opening 108 and the second opening 112.

[0081] The third gate dielectric layer 117 is located between the substrate 100 and the select gate 102.

[0082] In this embodiment, the material of the select gate includes polysilicon.

[0083] Referring to Figure 17 After forming the select gate 102, the mask layer 107 is removed.

[0084] Referring to Figure 18After the mask layer 107 is removed, the first gate material layer 106 and the first gate dielectric layer 104 are etched with the first side wall 109 as a mask to form a storage gate 103 and a third side wall 118 between the first side wall 109 and the substrate 100.

[0085] The method of etching the first gate material layer 106 and the first gate dielectric layer 104 includes a dry etching process.

[0086] In the embodiment, the material of the storage gate 103 includes polysilicon.

[0087] Please continue to refer to Figure 18 After the mask layer 107 is removed, part of the first gate material layer 106 on the logic region B is etched to form a logic gate layer 119 on the logic region B.

[0088] The method of etching the first gate material layer 106 includes a dry etching process.

[0089] Please refer to Figure 19 After the selection gate 102 and the storage gate 103 are formed, a second well 120 is formed in the substrate 100 on both sides of the selection gate 102 and the storage gate 103, and part of the second well 120 is also located at the bottom of the storage gate 103.

[0090] In the embodiment, the process of forming the second well 120 is an ion implantation process, and the process parameters of forming the second well 120 include: an implantation energy range of 2 keV to 100 keV, an implantation dose range of 1 x e 12 cm -2 ~ 5 x e 14 cm -2 , an implantation direction perpendicular to the channel width direction, and an included angle between the implantation direction and the sidewall of the storage gate ranging from 15 degrees to 45 degrees.

[0091] In the embodiment, the second well 120 is doped with second ions, and the second ions have the same conductivity type as the first ions. The second ions include P-type ions or N-type ions. When the first ions are P-type ions, the second ions are P-type ions. When the first ions are N-type ions, the second ions are N-type ions. In the embodiment, the second ions include boron.

[0092] Since the second well 120 is formed after the formation of the select gate 102 and the storage gate 103, and the process parameter for forming the second well 120 is light doping ion implantation, the formation of the second well avoids direct ion implantation to the channel of the select gate 102, so as to improve the mobility of the channel and the performance of the device.

[0093] In addition, since the formation of the second well 120 is ion implantation with the select gate 102 and the storage gate 103 as masks, one photolithography can be reduced and the process is simplified.

[0094] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above embodiments. Any person skilled in the art, without departing from the spirit and scope of the present application, can make various modifications and changes, and the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising: a device region and a logic region; A first well is formed within the substrate; After the first well is formed, a first gate dielectric layer is formed on the device region; A method for forming a select gate and a memory gate located on both sides of the select gate on the device region includes: forming a first gate material layer on the substrate, the first gate material layer being located on a first gate dielectric layer; forming a mask layer on the first gate material layer, the mask layer having a first opening located on the device region, the first opening exposing a portion of the first gate material layer; forming a first sidewall on the sidewall of the first opening; using the mask layer and the first sidewall as masks, etching the first gate material layer and the first gate dielectric layer until the substrate surface is exposed, forming a second opening in the first gate material layer and the first gate dielectric layer; forming a second sidewall on the sidewall of the first sidewall and the sidewall of the second opening; after forming the second sidewall, forming a select gate in the first opening and the second opening; after forming the select gate, removing the mask layer; after removing the mask layer, etching the first gate material layer and the first gate dielectric layer using the first sidewall as a mask, forming a memory gate and a third sidewall between the first sidewall and the substrate; After the select gate and the storage gate are formed, a second well is formed in the substrate on both sides of the select gate and the storage gate, and a portion of the second well is also located at the bottom of the storage gate.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process for forming the second well is an ion implantation process, and the process parameters for forming the second well include: an implantation energy range of 2keV to 100keV, and an implantation dose range of 1×e. 12 cm -2 ~5×e 14 cm -2 The injection direction is perpendicular to the channel width direction, and the angle between the injection direction and the sidewall of the memory gate is in the range of 15 degrees to 45 degrees.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The first well is doped with a first ion; the second well is doped with a second ion, and the second ion has the same conductivity type as the first ion.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, The first ion is a P-type ion, and the second ion is a P-type ion; or, the first ion is an N-type ion, and the second ion is an N-type ion.

5. The method for forming a semiconductor structure as described in claim 1, characterized in that, The structure of the first gate dielectric layer includes: a first oxide layer located on the surface of the substrate, a first nitride layer located on the surface of the first oxide layer, and a second oxide layer located on the surface of the first nitride layer.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: After the first gate dielectric layer is formed, a second gate dielectric layer is formed on the logic region; the first gate material layer is also located on the second gate dielectric layer. After removing the mask layer, a portion of the first gate material layer on the logic region is etched to form a logic gate layer on the logic region.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The material of the second gate dielectric layer includes oxides.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, Also includes: After the second sidewall is formed and before the select gate is formed, a third gate dielectric layer is formed in the first opening and the second opening, the third gate dielectric layer being located between the substrate and the select gate.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of forming the first sidewall includes: after forming the mask layer, forming a first sidewall material layer on the mask layer, the first sidewall material layer having a third opening within the first opening; and etching back the first sidewall material layer to form a first sidewall on the sidewall of the first opening.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method of forming the second sidewall includes: after forming the second opening, forming a second sidewall material layer in the second opening and in the mask layer and the first sidewall, the second sidewall material layer having a fourth opening in the second opening; and etching back the second sidewall material layer to form a second sidewall in the sidewall of the first sidewall and the sidewall of the second opening.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the mask layer includes silicon nitride.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the selected gate includes polycrystalline silicon.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the storage gate includes polycrystalline silicon.

Images