Display panel and display device

Abstract

The present application provides a display panel and a display device. The display panel includes a first display area and a second display area, and the sub-pixel density of the first display area is less than that of the second display area; the first display area includes a wiring area and pixel rows extending in a first direction, the pixel rows include a plurality of pixel areas, one pixel area includes n sub-pixels and n pixel circuits, and the first wiring area is located between two adjacent pixel areas in a second direction; the signal lines extending in the second direction include a first line segment located in the first wiring area and a second line segment located in the pixel area, and the second line segment is electrically connected to the pixel circuit; for adjacent first and second pixel rows, the first pixel row includes N sub-pixels, the second pixel row includes M sub-pixels, and N ≤ M; the total number of the first line segments between the first pixel row and the second pixel row is less than N. The present application can increase the area of the light-transmitting area of the first display area and improve the diffraction phenomenon when light penetrates the first display area.

Description

[0001] This application is a divisional application of the application with the application date of November 29, 2019, application number 201911207034.7, and invention creation name "display panel and display device". Technical Field

[0002] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0003] With the development of display technologies, people not only require a smooth usage experience for electronic products they use, but also have higher and higher requirements for visual experience, and a high screen-to-body ratio has become the current research direction. For electronic products, the setting of optical devices such as front cameras will inevitably occupy a certain amount of space, thus affecting the screen-to-body ratio. In order to increase the screen-to-body ratio and achieve a full-screen display, researchers consider implementation solutions for under-screen optical devices.

[0004] An optical device is disposed below the film layer where the light-emitting device of the display panel is located, that is, the optical device is disposed in the display area. When display is required, the position where the optical device is located can be normally displayed; when the optical device needs to be used, light penetrates the display panel and reaches the optical device and is finally utilized by the optical device. The optical device is disposed under the screen, and light needs to penetrate the film layer structure of the display panel to be utilized by the optical device. Evaluating the current implementation solutions for under-screen optical devices finds that the imaging quality of under-screen optical devices is poor and it is difficult to meet the needs of users. Summary of the Invention

[0005] Embodiments of the present invention provide a display panel and a display device to solve the technical problem that the imaging quality of the existing under-screen optical device is poor and it is difficult to meet the needs of users.

[0006] To solve the above technical problem, in a first aspect, the present invention provides a display panel. The display area of the display panel includes a first display area and a second display area. The display area includes a plurality of sub-pixels. The density of the plurality of sub-pixels in the first display area is less than the density of the plurality of sub-pixels in the second display area;

[0007] The first display area includes a plurality of routing areas and a plurality of pixel rows extending in a first direction. One pixel row includes a plurality of pixel areas arranged in the first direction. One pixel area includes n sub-pixels and n pixel circuits, where n is a positive integer. The sub-pixels are electrically connected to the pixel circuits. The plurality of routing areas includes a plurality of first routing areas. One first routing area is located between two adjacent pixel areas in a second direction, and the second direction intersects the first direction;

[0008] The first display area further includes a plurality of signal lines extending in the second direction. When driving the display panel for display, a constant voltage signal is provided to the signal lines. The signal lines include a first line segment and a second line segment. The first line segment is located in the first routing area, and the second line segment is located in the pixel area. In the pixel area, the second line segment is electrically connected to the pixel circuit; wherein,

[0009] The pixel rows include adjacent first pixel row and second pixel row. The first pixel row includes N sub-pixels, and the second pixel row includes M sub-pixels. Both N and M are positive integers, and N ≤ M; the total number of the first line segments in the plurality of first routing areas between the first pixel row and the second pixel row is less than N.

[0010] Based on the same inventive concept, in a second aspect, the present invention further provides a display device, including any one of the display panels provided by the present invention.

[0011] The display panel and the display device provided by the embodiments of the present invention have the following beneficial effects:

[0012] The design of the present application reduces the number of signal lines between adjacent first pixel row and second pixel row, can reduce the area of the non-light-transmitting area in the first display area, that is, can correspondingly increase the area of the light-transmitting area in the first display area, thereby improving the light transmittance of the first display area. Applied in the solution of the under-screen optical device, it can increase the amount of light received by the under-screen optical device and improve the optical performance of the optical device. In addition, when light penetrates the first display area, various routings arranged in the first display area can form a diffraction grating, which will have a diffraction effect on the light. For example, when the under-screen optical device is a camera, the diffraction phenomenon will affect the imaging quality of the camera. By reducing the number of signal lines between two adjacent pixel rows, the embodiments of the present application can also improve the diffraction phenomenon when light penetrates the first display area to a certain extent, and further improve the optical performance of the optical device. Description of the Drawings

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings.

[0014] Figure 1 It is a schematic diagram of an optional implementation manner of the display panel provided by the embodiments of the present application;

[0015] Figure 2 For Figure 1 The enlarged view at the position of area Q in

[0016] Figure 3A partial schematic diagram of the first display area of the display panel provided by an embodiment of the present application;

[0017] Figure 4 A partial schematic diagram of a display panel in the related art;

[0018] Figure 5 A partial schematic diagram of an alternative embodiment of the first display area of the display panel provided by an embodiment of the present application;

[0019] Figure 6 A partial schematic diagram of another alternative embodiment of the first display area of the display panel provided by an embodiment of the present application;

[0020] Figure 7 A partial schematic diagram of another alternative embodiment of the first display area of the display panel provided by an embodiment of the present application;

[0021] Figure 8 A partial schematic diagram of another alternative embodiment of the first display area of the display panel provided by an embodiment of the present application;

[0022] Figure 9 A partial schematic diagram of another alternative embodiment of the first display area of the display panel provided by an embodiment of the present application;

[0023] Figure 10 A partial schematic diagram of another alternative embodiment of the first display area provided by an embodiment of the present application;

[0024] Figure 11 A partial schematic diagram of another alternative embodiment of the first display area provided by an embodiment of the present application;

[0025] Figure 12 A partial schematic diagram of another alternative embodiment of the first display area of the display panel provided by an embodiment of the present application;

[0026] Figure 13 A partial schematic diagram of another alternative embodiment of the first display area of the display panel provided by an embodiment of the present application;

[0027] Figure 14 A schematic diagram of another alternative embodiment of the first display area of the display panel provided by an embodiment of the present application;

[0028] Figure 15 A schematic diagram of the display device provided by an embodiment of the present application. Detailed implementation manners

[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0030] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The singular forms "a", "the", and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0031] Based on the technical problems existing in the related art, the embodiments of the present application provide a display panel and a display device. By reducing the number of line segments between two adjacent pixel rows in the display area corresponding to the optical device (the first display area in the present application), the area of the light-transmitting area in the first display area can be increased, the light transmittance of the first display area can be improved, that is, when applying the under-screen optical device solution, the amount of light received by the optical device can be increased. At the same time, the diffraction phenomenon of light penetrating the first display area can be improved, and the optical performance of the under-screen optical device can be enhanced.

[0032] Figure 1 It is a schematic diagram of an optional implementation manner of the display panel provided by the embodiments of the present application. Figure 2 For Figure 1 the enlarged view at the position of area Q in Figure 1 As shown, the display area AA of the display panel includes a first display area AA1 and a second display area AA2. The display area includes a plurality of sub-pixels sp. As Figure 2 shown, the density of the plurality of sub-pixels sp in the first display area AA1 is less than the density of the plurality of sub-pixels sp in the second display area AA2; Figure 1Only schematically shows that the second display area AA2 surrounds the first display area AA1. Optionally, the second display area AA2 may also semi-surround the first display area AA1. In the embodiments of the present invention, the shape of the first display area AA1 is not limited and may be any one of a circle, an ellipse, a triangle, or a polygon. The display panel provided by the embodiments of the present application may be an organic light-emitting display panel, and the organic light-emitting display panel includes an array layer and a light-emitting layer located above the array layer. The light-emitting layer includes a plurality of light-emitting devices, and one sub-pixel sp includes one light-emitting device. The density of the plurality of sub-pixels sp in the first display area AA1 is less than the density of the plurality of sub-pixels sp in the second display area AA2, that is, the density of the plurality of light-emitting devices in the first display area AA1 is less than the density of the plurality of light-emitting devices in the second display area AA2. Then the light transmittance per unit area of the first display area AA1 is greater than the light transmittance per unit area of the second display area AA2. Applied in the under-screen optical device solution, the optical device can be disposed below the first display area AA1 to ensure that when the optical device is enabled, the optical device can receive sufficient light. Among them, during display, the first display area AA1 can be used to display information such as notification symbols, battery symbols, network symbols, time, etc.

[0033] Figure 3 It is a partial schematic diagram of the first display area of the display panel provided by the embodiments of the present application. As Figure 3 shown, the first display area AA1 includes a plurality of routing areas ZQ and a plurality of pixel rows PH extending along the first direction x. One pixel row PH includes a plurality of pixel areas PQ arranged in the first direction x. One pixel area includes n sub-pixels sp and n pixel circuits DL, where n is a positive integer. n can be an integer such as 1, 2, 3, or 4, and the sub-pixel sp is electrically connected to the pixel circuit DL correspondingly. Figure 3 Only schematically shows that one pixel area includes 3 sub-pixels sp and 3 pixel circuits DL. Optionally, one pixel area may include 1 sub-pixel and 1 pixel circuit, or one pixel area may include 4 sub-pixels and 4 pixel circuits. The division of the pixel area is related to the arrangement manner of the sub-pixels in the first display area, and the arrangement manner of the sub-pixels can be related to the display method of the display panel. The embodiments of the present invention are applicable to display panels designed using any one of the sub-pixel arrangement manners.

[0034] The plurality of routing areas ZQ includes a plurality of first routing areas ZQ1. One first routing area ZQ is located between two pixel areas PQ adjacent in the second direction y. The second direction y intersects with the first direction x. The routing area ZQ is also the area used to set the routing, and can centrally set the routing between two pixel areas PQ adjacent in the second direction y in the routing area ZQ.

[0035] The first display area AA1 further includes a plurality of signal lines X extending along the second direction y. When driving the display panel to display, a constant voltage signal is provided to the signal lines X. In one embodiment, the signal line X is a positive power supply signal line. When driving the sub-pixel to display, the positive power supply signal line provides a constant voltage signal to the pixel circuit. In one embodiment, the signal line X is a reset signal line. When driving the sub-pixel to display, the reset signal line provides a constant reset signal to the pixel circuit.

[0036] The signal line X includes a first segment D1 and a second segment D2. The first segment D1 is located in the first routing area ZQ1, and the second segment D2 is located in the pixel area PQ. In the pixel area PQ, the second segment D2 is electrically connected to the pixel circuit DL. In the figure, a black solid dot is used to indicate the electrical connection between the second segment D2 and the pixel circuit DL; among them,

[0037] The pixel row PH includes adjacent first pixel row PH1 and second pixel row PH2. The first pixel row PH1 includes N sub-pixels, and the second pixel row PH2 includes M sub-pixels. Both N and M are positive integers, and N ≤ M; between the first pixel row PH1 and the second pixel row PH2, the total number of the first segments D1 in the plurality of first routing areas ZQ1 is less than N. According to the different shapes of the first display area, the number of sub-pixels in two adjacent pixel rows located in the first display area may be the same or different. In the embodiment of the present invention, when the number of sub-pixels in the first pixel row PH1 is equal to the number of sub-pixels in the second pixel row PH2, the total number of the first segments D1 between the two pixel rows is less than the number of sub-pixels in one pixel row; when the number of sub-pixels in the first pixel row PH1 is less than the number of sub-pixels in the second pixel row PH2, the total number of the first segments D1 between the two pixel rows is less than the number of sub-pixels in the first pixel row PH1. Figure 3 The complete first pixel row PH1 and the complete second pixel row PH2 in the first display area AA1 are not shown in the figure. Only at a local position schematically shown in the figure, this local area schematically shows 12 sub-pixels sp in the first pixel row PH1 and 12 sub-pixels sp in the second pixel row PH2, and there are 8 first segments D1 between the first pixel row PH1 and the second pixel row PH2 in this local area, that is, in the embodiment of the present application, the number of the first segments D1 between two adjacent pixel rows is designed to be reduced.

[0038] In one embodiment, the signal line X is a positive power supply signal line. When driving the sub-pixel to display, the positive power supply signal line provides a constant voltage signal to the pixel circuit. The first display area further includes a data line having the same extension direction as the signal line X. When driving the sub-pixel to display, the data line provides a data signal to the pixel circuit. Then, the data line is also included in the first routing area ZQ1, which is not shown in the figure.

[0039] In another embodiment, the signal line X is a reset signal line. When driving the sub-pixels to display, the reset signal line provides a constant reset signal to the pixel circuit. In the first display area, there are also a gate scan line and a light emission control signal line extending in the same direction as the signal line X. In the first routing area ZQ1, there are also a gate scan line and a light emission control signal line, which are not shown in the figure.

[0040] Figure 4 It is a partial schematic diagram of a display panel in the related art. As Figure 4 shown, it shows a signal line X' extending in the second direction y and a pixel row PH' extending in the first direction x. The pixel row PH' includes a plurality of sub-pixels sp' arranged in the first direction x and a pixel circuit DL' electrically connected to the sub-pixel sp'. The conventional design of those skilled in the art is that a plurality of pixel circuits DL' arranged in the second direction y are electrically connected to the same signal line X'. The signal line X' includes a first line segment D1' and a second line segment D2'. The second line segment D2' is electrically connected to the pixel circuit DL', and the first line segment D1' is located between two adjacent pixel rows PH'. In the partial area shown in the figure, two adjacent pixels and each area including 12 sub-pixels sp' have 12 first line segments D1' between the corresponding two pixel rows.

[0041] When applied to a display panel in which the display area includes a first display area and a second display area as schematically shown in the embodiments of the present application (i.e., the solution of the under-screen optical device), the design solution that those skilled in the art can easily think of without creative labor is to still adopt the above Figure 4The design method in [reference]. The inventor of the present application has improved the design in the related technology through creative labor. The design reduces the number of signal lines (i.e., the first line segments in the present application) between two adjacent pixel rows. Since signal lines are usually made of metal materials, in the solution applied to the under-screen optical device, when light penetrates the display panel from the first display area, the area where the signal lines are located has a light-shielding property, that is, the area occupied by the signal lines belongs to the non-transparent area. The embodiment of the present application can reduce the area of the non-transparent area in the first display area, that is, can correspondingly increase the area of the transparent area (i.e., the area where light can penetrate. When understanding, the transparent area and the non-transparent area are two relative concepts, and the transmittance of the transparent area is greater than that of the non-transparent area) in the first display area, thereby improving the transmittance of the first display area. When applied to the solution of the under-screen optical device, it can increase the amount of light received by the under-screen optical device and improve the optical performance of the optical device. In addition, when light penetrates the first display area, various traces arranged in the first display area can form a diffraction grating, which will have a diffraction effect on light. For example, when the under-screen optical device is a camera, the diffraction phenomenon will affect the imaging quality of the camera. The embodiment of the present application reduces the number of signal lines between two adjacent pixel rows, and can also improve the diffraction phenomenon when light penetrates the first display area to a certain extent, further improving the optical performance of the optical device.

[0042] In the first display area of the display panel provided by the embodiment of the present application, by reducing the number of the first line segments between two adjacent pixel areas, the area of the transparent area in the first display area can be increased, and at the same time, the diffraction phenomenon generated when light penetrates the first display area can be improved. After reducing the number of the first line segments (partial line segments of the signal lines) in the first trace area, it can be as shown above Figure 3 As shown, the second line segment D2 in the pixel area PQ is electrically connected to the same first line segment D1 to input a signal to the second line segment D2 to drive the corresponding sub-pixel to display, so as to ensure that each sub-pixel in the first display area can be normally displayed. The following embodiments will give a detailed example of the technical solution provided by the present application.

[0043] In some alternative embodiments, among multiple first routing areas between a first pixel row and a second pixel row, there is included: a first A routing area; in the first pixel row and the second pixel row, there are included: an A pixel area adjacent to the first A routing area, and the A pixel area includes n second line segments; wherein, the first A routing area includes p first line segments, p is an integer, and n > p ≥ 0. That is, the number of first line segments in the first A routing area adjacent to the A pixel area is less than the number of second line segments in the A pixel area. Among them, the A pixel area may be located in the first pixel row, or may also be located in the second pixel row, or there may be A pixel areas included in both the first pixel row and the second pixel row. When p = 0, that is, no first line segments are provided in the first A routing area. By setting the number of first line segments in the first routing area adjacent to the pixel area to be less than the number of second line segments in the pixel area, that is, less than the number of sub-pixels in the pixel area, the number of first line segments between two adjacent pixel rows is reduced, achieving an increase in the light-transmitting area of the first display area and improving the diffraction phenomenon generated by light penetrating the first display area.

[0044] In one embodiment, a pixel area includes 1 sub-pixel and 1 pixel circuit, that is, n = 1. Among the multiple first routing areas in the first display area, there is a first A routing area, and no first line segments are provided in the first A routing area, that is, p = 0. Figure 5 This is a partial schematic diagram of an alternative embodiment of the first display area of the display panel provided by the embodiment of the present application. As Figure 5 shown, a pixel area PQ includes 1 sub-pixel sp and 1 pixel circuit DL, then the pixel area PQ includes 1 second line segment D2. In the figure, the first routing ZX in the first display area that extends in the same direction as the signal line X is shown. Among them, when the signal line X is a positive power supply line, the first routing ZX is a data line; when the signal line X is a reset signal line, the first routing ZX is a gate scan line or a light emission control signal line. In the figure, the signal line X is shown as a thick line and the first routing ZX is shown as a thin line, only for distinguishing the two types of lines, and not as a limitation on the line width in the actual product. The first routing area ZQ1 extending in the second direction y includes a first A routing area ZQ1a, and no first line segments D1 are provided in the first A routing area ZQ1. The A pixel area PQa adjacent to the first A routing area ZQ1a includes 1 second line segment D2. That is, at least part of the signal line X is cut off at the position of the first A routing area ZQ1a, reducing the number of signal lines X (i.e., the first line segments D1) between two adjacent pixel rows, which can increase the light-transmitting area of the first display area and improve the diffraction phenomenon generated by light penetrating the first display area.

[0045] Figure 5In the corresponding embodiment, the signal line X that provides signals for the pixel circuit in the first P pixel region PQa is cut off at the position of the first P wiring region ZQ1 a. Then, how to input signals to the second segment D2 in the first P pixel region PQa during the display stage? In order to ensure that the sub-pixels in the first P pixel region PQa can still be normally displayed, the present application further proposes a solution. Continue to refer to Figure 5 As shown, the wiring region further includes a plurality of second wiring regions ZQ2. One second wiring region ZQ2 is located between two adjacent pixel regions PQ in the first direction x; the first display region further includes a plurality of auxiliary signal lines FX extending along the first direction x, and partial segments of the auxiliary signal lines FX are located in the second wiring regions ZQ2. The pixel row PH further includes: a second P pixel region PQb adjacent to the first P pixel region PQa, and the first P pixel region PQa and the second P pixel region PQb are located in the same pixel row PH; the second segments D2 located in the first P pixel region PQa and the second P pixel region PQb are electrically connected through the auxiliary signal lines FX. In the figure, black solid dots are used to indicate that the two second segments D2 are electrically connected through the auxiliary signal lines FX. The extending direction of the auxiliary signal lines FX intersects with the extending direction of the signal line X, and they are electrically connected at the overlapping position of the auxiliary signal lines FX and the signal line X (that is, at the position defined as the second segment D2 in the present application), so as to transmit the same voltage signal on the auxiliary signal lines FX and the signal line X. The auxiliary signal lines FX are equivalent to being connected in parallel with the signal line X, which can reduce the overall resistance and thus reduce the power consumption loss. At the same time, when driving the sub-pixels to display, the auxiliary signal lines FX can input voltage signals to the second segments D2 in the first P pixel region PQa, so that the sub-pixels in the first P pixel region PQa can be normally displayed.

[0046] In some alternative embodiments, p≠0, at least two second segments in the first P pixel region are electrically connected to the same first segment in the first P wiring region. When the number of sub-pixels in the pixel region is greater than or equal to 2, two or more second segments need to be provided in the pixel region. By setting at least two second segments in the first P pixel region to be electrically connected to the same first segment, the number of first segments provided between two adjacent pixel rows can be reduced.

[0047] In one embodiment, n = 3, that is, the first P pixel region includes 3 second segments, and 2 second segments in the first P pixel region are electrically connected to the same first segment in the first P wiring region. Then, there are 2 first segments in the first P wiring region adjacent to the first P pixel region, that is, p = 2.

[0048] Specifically, taking Figure 6 shown as an example, Figure 6 is a partial schematic diagram of an alternative embodiment of the first display region of the display panel provided by the embodiment of the present application. As Figure 6As shown, the first pixel region PQa includes 3 second line segments D2, that is, n = 3. Two adjacent pixel rows (i.e., the first pixel row and the second pixel row) in the figure both include the first pixel region PQa. For the sake of clearly showing various wiring in the schematic diagram, only the pixel circuit DL is shown in the pixel region. Two second line segments D2 in the first pixel region are electrically connected to the same first line segment D1 in the first wiring region ZQ1a of the first type. Another second line segment D2 in the first pixel region PQa is electrically connected to another first line segment D1 in the first wiring region ZQ1a of the first type. The first wiring region ZQ1a of the first type includes 2 first line segments. The first wiring ZX in the same extending direction as the signal line X in the first display region is shown in the figure. The number of the first wiring ZX in a pixel region is the same as the number of sub-pixels in this pixel region. In this embodiment, a pixel region includes 3 first wiring ZX. In this embodiment, by setting two second line segments in the first pixel region to be connected to the same first line segment, the number of first line segments in the first wiring region of the first type adjacent to the first pixel region is reduced, that is, the area of the non-display region in the first display region is reduced, and correspondingly, the area of the light-transmitting region in the first display region is increased. At the same time, reducing the number of first line segments in the first wiring region of the first type is also beneficial to improving the diffraction phenomenon generated by light penetrating the first display region.

[0049] Figure 6 In the partial region of the first display region shown in the figure, it includes a conventional pixel region and a conventional first wiring region. Among them, the number of second line segments in the conventional pixel region, that is, in the pixel region, is the same as the number of first line segments in the corresponding conventional first wiring region, that is, only the number of first line segments in part of the first wiring region is reduced. Optionally, in an embodiment, it may also be that all pixel regions in the first display region are the first pixel regions, and all first wiring regions are the first wiring regions of the first type, which are not shown in the drawings here.

[0050] In an embodiment, n = 3, that is, the first pixel region includes 3 second line segments. The 3 second line segments in the first pixel region are electrically connected to the same first line segment in the first wiring region of the first type. Then, there is 1 first line segment in the first wiring region of the first type adjacent to the first pixel region, that is, p = 1.

[0051] Specifically, taking Figure 7 shown as an example, Figure 7 is a partial schematic diagram of another alternative embodiment of the first display region of the display panel provided by the embodiment of the present application. As Figure 7 shown, the first pixel region PQa includes 3 second line segments D2, that is, n = 3. As described above Figure 6The corresponding embodiments are the same. In the figure, the first trace ZX in the first display area that extends in the same direction as the signal line X is schematically shown. The three second line segments D2 in the first pixel area are electrically connected to the same first line segment D1 in the first first trace area ZQ1a, and the first first trace area ZQ1a includes one first line segment D1. In this embodiment, by arranging the three second line segments in the first pixel area to be connected to the same first line segment, the number of first line segments in the first first trace area adjacent to the first pixel area is reduced, that is, the area of the non-display area in the first display area is reduced, and correspondingly, the area of the light-transmitting area in the first display area is increased. At the same time, reducing the number of first line segments in the first first trace area is also beneficial to improving the diffraction phenomenon generated by light penetrating the first display area.

[0052] Figure 7 In the partial area of the first display area schematically shown, it includes a conventional pixel area and a conventional first trace area. Among them, the number of second line segments in the conventional pixel area, that is, in the pixel area, is the same as the number of first line segments in the corresponding conventional first trace area, that is, only the number of first line segments in some of the first trace areas is reduced. Optionally, in one embodiment, all the pixel areas in the first display area may be first pixel areas, and all the first trace areas may be first first trace areas, which are not shown in the drawings here.

[0053] Furthermore, the pixel area further includes a connection line, and the connection line includes a first connection line; the first connection line is located in the first pixel area, and at least two second line segments in the first pixel area are electrically connected to the first connection line through vias, and the same first line segment electrically connected to the at least two second line segments is electrically connected to the first connection line through a via. Thus, at least two second line segments in the first pixel area are electrically connected to the same first line segment. You can continue to refer to the above Figure 6 or Figure 7 as shown. As Figure 6 shown, the connection line includes a first connection line L1. The first connection line L1 is located in the first pixel area PQa. Two second line segments D2 in the first pixel area PQa are electrically connected to the first connection line L1 through vias, and the same first line segment D1 electrically connected to the two second line segments D2 is electrically connected to the first connection line L1 through a via. The vias in the figure are indicated by black solid dots. As Figure 7 shown, the connection line includes a first connection line L1. The first connection line L1 is located in the first pixel area PQa. Three second line segments D2 in the first pixel area PQa are electrically connected to the first connection line L1 through vias, and the same first line segment D1 electrically connected to the three second line segments D2 is electrically connected to the first connection line L1 through a via. The vias in the figure are indicated by black solid dots. Through the arrangement of the first connection line, at least two second line segments in the first pixel area are electrically connected to the same first line segment, and further, the number of first line segments arranged in the first first trace area adjacent to the first pixel area is reduced.

[0054] In some embodiments, a pixel region includes 4 sub-pixels sp and 4 pixel circuits. Optionally, the 4 second line segments in the first pixel region are all electrically connected to the same first line segment in the first routing region of the first pixel. Then, only 1 first line segment needs to be provided in the first routing region of the first pixel. Optionally, 3 second line segments in the first pixel region are electrically connected to the same first line segment in the first routing region of the first pixel. Then, 2 first line segments can be provided in the first routing region of the first pixel. Optionally, 2 second line segments in the first pixel region are electrically connected to the same first line segment in the first routing region of the first pixel. Then, 2 first line segments can be provided in the first routing region of the first pixel. In the above embodiments, the connection manner between the second line segments in the first pixel region and the first line segments in the first routing region of the first pixel adopts the same principle as the above Figure 6 or Figure 7 which is the same, and can be understood by referring to the above embodiments, and will not be elaborated here.

[0055] In some alternative embodiments, p = 0; that is, no first line segment is provided in the first routing region adjacent to the first pixel region. Still taking a pixel region including 3 sub-pixels and 3 pixel circuits as an example, that is, n = 3. Figure 8 This is a partial schematic diagram of another alternative embodiment of the first display region of the display panel provided by the embodiment of the present application. As Figure 8 shown, the pixel region PQ further includes a connection line, and the connection line includes a second connection line L2. The second connection line L2 is located in the first pixel region PQa, and the 3 second line segments D2 in the first pixel region PQa are all electrically connected to the second connection line L2. In this embodiment, no first line segment is provided in the first routing region adjacent to the first pixel region, which can greatly reduce the number of first line segments (i.e., signal lines) in two adjacent pixel regions.

[0056] Furthermore, in this embodiment, since no first line segment is provided in the first routing region adjacent to the first pixel, a voltage signal can be input to the second line segment in the first pixel region through the auxiliary signal line in the display panel. Thus, during display, the second line segment can provide a voltage signal to the pixel circuit to drive the sub-pixel for display. Continue to refer to Figure 8As shown, the routing area further includes a plurality of second routing areas ZQ2, and one second routing area ZQ2 is located between two adjacent pixel areas PQ in the first direction x; the first display area further includes a plurality of auxiliary signal lines FX extending along the first direction x, and partial line segments of the auxiliary signal lines FX are located in the second routing area ZQ2; in the first pixel row and the second pixel row (not marked in the figure, that is, two adjacent pixel rows), it further includes: a second pixel area PQb adjacent to the first pixel area PQa, and the first pixel area PQa and the second pixel area PQb are located in the same pixel row; second line segments D2 located in the first pixel area PQa and the second pixel area PQab are electrically connected through the auxiliary signal line FX. The extending direction of the auxiliary signal line FX intersects with the extending direction of the signal line X. At the overlapping position of the auxiliary signal line FX and the signal line X, that is, at the overlapping position of the auxiliary signal line FX and the second line segment D2, the auxiliary signal line FX is electrically connected to the second line segment D2. During the process of driving the display panel for display, a voltage signal is transmitted to the second line segment D2 through the auxiliary signal line FX, so as to enable the normal display of the sub-pixels in the first pixel area. At the same time, the auxiliary signal line FX is equivalent to being connected in parallel with the signal line X, which can reduce the overall resistance and is beneficial to reducing power consumption loss.

[0057] In some alternative embodiments, among the plurality of first routing areas between the first pixel row and the second pixel row, it includes: a first second routing area adjacent to the first first routing area; in the first pixel row and the second pixel row, it further includes: a second pixel area adjacent to the first pixel area, and the second pixel area is adjacent to the first second routing area; the second pixel area includes n second line segments, and the first second routing area includes q first line segments, q is an integer, and n≥q>p. When q = n, the number of first line segments in the first second routing area is the same as the number of second line segments in the second pixel area, that is, the number of first line segments in the first second routing area is not reduced. When n>q, the number of first line segments in the first second routing area is less than the number of second line segments in the second pixel area, that is, by reducing the number of first line segments in the first second routing area, the area of the non-light-transmitting area in the first display area is further reduced, so as to correspondingly increase the area of the light-transmitting area in the first display area. At the same time, it can also further improve the diffraction phenomenon generated by the light transmitting through the first display area.

[0058] In one embodiment, q = n; the n second line segments in the second pixel area are respectively electrically connected to the q first line segments located in the first second routing area. Still taking a pixel area including 3 sub-pixels and 3 pixel circuits as an example, that is, n = 3. For further reference, see the above Figure 6 For illustration, the second pixel area PQb adjacent to the first pixel area PQa includes 3 second line segments, and the first second routing area ZQ1b adjacent to the second pixel area PQb includes 3 first line segments, that is, q = n. For further reference, see the above Figure 7As shown in the figure, the second pixel region PQb adjacent to the first pixel region PQa includes three second line segments, and the first second wiring region ZQ1b adjacent to the second pixel region PQb includes three first line segments, that is, q = n. In this embodiment, by reducing the number of first line segments in some of the first wiring regions in the first display region, the area of the non-light-transmitting region of the first display region is reduced, and correspondingly, the area of the light-transmitting region of the first display region is increased. When applied to the under-screen optical device solution, the amount of light received by the under-screen optical device can be improved. At the same time, reducing the number of first line segments can also improve the diffraction phenomenon generated when light penetrates the first display region to a certain extent.

[0059] In one embodiment, q < n; at least two second line segments in the second pixel region are electrically connected to the same first line segment in the first second wiring region. Still taking a pixel region including three sub-pixels and three pixel circuits as an example, that is, n = 3. Figure 9 This is a partial schematic diagram of another optional embodiment of the first display region of the display panel provided by the embodiment of the present application. As Figure 9 shown, the three second line segments D2 in the first pixel region PQa are electrically connected to the same first line segment D1 in the first first wiring region ZQ1a, and the first first wiring region ZQ1a includes one first line segment D1. Two second line segments D2 in the second pixel region PQb are electrically connected to the same first line segment D1 in the first second wiring region ZQ1b, and another second line segment D2 in the second pixel region PQb is electrically connected to another first line segment D1 in the first second wiring region ZQ1b, and the first second wiring region ZQ1b includes two first line segments D1. In this embodiment, the number of first line segments in the first wiring regions corresponding to two adjacent pixel regions is reduced respectively to reduce the area of the non-light-transmitting region in the first display region, thereby correspondingly increasing the area of the light-transmitting region of the first display region. At the same time, the diffraction phenomenon generated when light penetrates the first display region can be improved.

[0060] Figure 9 It is schematically shown that the arrangement of the second line segments in the second pixel region and the first line segments in the first second wiring region is different from the arrangement of the second line segments in the first pixel region and the first line segments in the first first wiring region. Optionally, it may also be that the three second line segments D2 in the first pixel region PQa are electrically connected to the same first line segment D1 in the first first wiring region ZQ1a, and the first first wiring region ZQ1a includes one first line segment D1. At the same time, the three second line segments D2 in the second pixel region PQb are electrically connected to the same first line segment D1 in the first second wiring region ZQ1b, and the first second wiring region ZQ1b includes one first line segment D1.

[0061] Further, reference may be continued to the above Figure 9As shown, the pixel region further includes connection lines, and the connection lines include a third connection line L3. The third connection line L3 is located in the second pixel region PQb. At least two second line segments D2 in the second pixel region PQb are electrically connected to the third connection line L3 through vias respectively, and the same first line segment D1 electrically connected to the at least two second line segments D2 is electrically connected to the third connection line L3 through a via. In the figure, only black solid dots are used to indicate the via connections. Through the setting of the third connection line, at least two second line segments in the second pixel region are electrically connected to the same first line segment, ensuring that signals can be normally provided to the second line segments in the display region, and further ensuring that each sub-pixel in the second pixel region can be normally displayed.

[0062] Further, based on the above Figure 6 corresponding embodiment, auxiliary signal lines can also be provided in the first display region. Figure 10 It is a partial schematic diagram of another alternative embodiment of the first display region provided by the embodiment of the present application. As Figure 10 shown, the routing region further includes a plurality of second routing regions ZQ2. One second routing region ZQ2 is located between two adjacent pixel regions PQ in the first direction x. The first display region further includes a plurality of auxiliary signal lines FX extending along the first direction x. Part of the line segments of the auxiliary signal lines FX are located in the second routing region ZQ2. The second line segments D2 of the first pixel region PQa and the second pixel region PQb located in the same pixel row are electrically connected through the auxiliary signal lines FX. The extending direction of the auxiliary signal lines FX intersects with the extending direction of the signal line X. At the overlapping position of the auxiliary signal lines FX and the signal line X, that is, at the overlapping position of the auxiliary signal lines FX and the second line segment D2, the auxiliary signal lines FX are electrically connected to the second line segment D2. The auxiliary signal lines FX are equivalent to being connected in parallel with the signal line X, which can reduce the overall resistance and is beneficial to reducing power consumption loss.

[0063] In one embodiment, q = 1 and p = 0. That is, in the two first routing regions corresponding to two adjacent pixel regions respectively: one first routing region is provided with one first line segment, and the other first routing region is not provided with a first line segment. Still taking a pixel region including 3 sub-pixels and 3 pixel circuits as an example, that is, taking n = 3 as an example. Figure 11 It is a partial schematic diagram of another alternative embodiment of the first display region provided by the embodiment of the present application. As Figure 11As shown, the three second line segments D2 in the PQa of the first pixel region are electrically connected through the second connection line L2, and the first connection line L1 is not provided in the first routing region of the first pixel region. In the second pixel region adjacent to the PQa of the first pixel region: the three second line segments D2 are electrically connected to the same first line segment D1 through the third connection line L3, and one first line segment D1 is provided in the first routing region of the second pixel region. In the two adjacent first routing regions, the total number of the first line segments can be reduced by more than 80%, the area of the non-transmissive region in the first display region can be reduced to a large extent, and correspondingly, the area of the transmissive region is increased. At the same time, the diffraction phenomenon generated when light penetrates the first display region can be effectively improved.

[0064] In the display panel provided by the embodiment of the present application, the display region further includes a plurality of scan lines and a plurality of data lines; the pixel circuit further includes a pixel capacitor. The display panel includes a substrate, a first metal layer, a capacitive metal layer, and a second metal layer located on the substrate. The scan lines are located in the first metal layer, one electrode plate of the pixel capacitor is located in the capacitive metal layer, and the data lines are located in the second metal layer. The signal line can be a positive power supply line or a reset signal line. For different situations, the film layer position of the signal line in the panel is different. When setting the connection lines (i.e., the first connection line, the second connection line, and the third connection line in the above embodiment), the film layer position where the connection lines are located also needs to be set accordingly.

[0065] In one embodiment, taking the signal line as a positive power supply line, the signal line is located in the second metal layer, and the connection line is located in the first metal layer as an example, Figure 12 This is a partial schematic diagram of another alternative embodiment of the first display region of the display panel provided by the embodiment of the present application. As Figure 12 shown, three pixel circuits in a pixel region are schematically shown. Taking the three second line segments D2 in the pixel region being electrically connected through the connection line L as an example. The scan line S is located in the first metal layer M1, where the scan line includes a gate scan line and a light emission control signal line, which are not distinguished in the figure; one electrode plate C of the pixel capacitor is located in the capacitive metal layer MC; the data line D is located in the second metal layer M2, and the reset signal line Ref is also schematically shown in the figure. The reset signal line Ref extends along the first direction x and is located in the capacitive metal layer MC. The signal line X (i.e., the second line segment D2) is located in the second metal layer M2, the connection line L is located in the first metal layer M1, and the second line segment D2 is electrically connected to the connection line L through the via O1. The connection line L electrically connects the second line segments D2 arranged in the first direction x, so the connection line L extends in the first direction x. By setting the connection line L in the first metal layer M1, while the connection line L realizes the electrical connection of at least two second line segments D2 in the pixel region, its setting will not cause a short circuit between the connection line L and the data line D extending in the second direction y.

[0066] In another embodiment, the connection line L can also be located in the capacitive metal layer MC; it can also ensure that there is no short circuit between the connection line L extending in the first direction x and the data line D extending in the second direction y.

[0067] Furthermore, when the signal line is a positive power supply line and the signal line is located in the second metal layer, an auxiliary signal line is further provided in the first display area, and the auxiliary signal line is located in the capacitive metal layer. Figure 13 It is a partial schematic diagram of another alternative embodiment of the first display area of the display panel provided by the embodiment of the present application. As Figure 13 shown, three pixel circuits in a pixel area are schematically shown. The auxiliary signal line FX and the signal line X are electrically connected through the second via O2, and the auxiliary signal line FX is located in the capacitive metal layer MC. The extending direction of the auxiliary signal line FX intersects with the extending direction of the signal line X. The capacitive metal layer MC is usually used to set one plate of the pixel capacitor and the reset signal line Ref. Setting the auxiliary signal line FX in the capacitive metal layer MC will not affect the original wiring setting in the display panel. At the same time, forming a parallel circuit structure between the auxiliary signal line FX and the signal line X is beneficial to reducing the resistance, and further reducing the power consumption loss. In addition, in the embodiment where the first segment is not provided in the corresponding first A wiring area adjacent to the A pixel area, the auxiliary signal line FX can be electrically connected to the corresponding second segment in the A pixel area, and in the display area, a voltage signal is provided to the second segment, so as to ensure that each sub-pixel in the A pixel area can be normally displayed.

[0068] In another embodiment, the signal line is a reset signal line, the signal line is located in the capacitive metal layer, and the connection line is located in the second metal layer. In this embodiment, when the connection line connects at least two second segments in the same pixel area, it will overlap with the scan line in the pixel area. Through reasonable design, the connection line is set in the second metal layer to avoid short circuit between the connection line and the scan line.

[0069] In the embodiment where the signal line is a reset signal line and the signal line is located in the capacitive metal layer, further, an auxiliary signal line can be provided in the display panel, and the auxiliary signal line is set in the second metal layer. The auxiliary signal line and the signal line are electrically connected through a via. The extending direction of the auxiliary signal line intersects with the extending direction of the signal line. The auxiliary signal line can form a parallel circuit structure with the signal line, which is beneficial to reducing the resistance, and further reducing the power consumption loss. In addition, in the embodiment where the first segment is not provided in the corresponding first A wiring area adjacent to the A pixel area, the auxiliary signal line can be electrically connected to the corresponding second segment in the A pixel area, and in the display area, a voltage signal is provided to the second segment, so as to ensure that each sub-pixel in the A pixel area can be normally displayed.

[0070] Furthermore, the first display area of the display panel provided by the embodiment of the present application further includes a light-shielding layer. Figure 14Another alternative embodiment diagram of the first display area of the display panel provided by the embodiments of the present application is shown as Figure 14 As described, in the direction perpendicular to the display panel, the light-shielding layer covers the wiring area (not marked in the figure). Actually, between two adjacent pixel areas PQ in the first direction x, there is a second wiring area, and between two adjacent pixel areas PQ in the second direction y, there is a first wiring area. The figure schematically shows that the light-shielding layer includes a first light-shielding layer SD1 covering the first wiring area and a second light-shielding layer SD2 covering the second wiring area. When applied to the under-screen optical device solution, there are gaps between the wirings in the wiring area. When light penetrates the first display area, these wiring gaps will cause diffraction of light, which affects the optical performance of the optical device. The light-shielding layer provided by the embodiments of the present application can block the wiring area, thereby improving the diffraction effect when light penetrates the first display area and enhancing the optical performance of the optical device. In addition, in the embodiments of the present application, the total number of the first line segments between two adjacent pixel rows is reduced, so the area of at least part of the first wiring area is reduced. When setting the light-shielding layer, the area of the light-shielding layer can be correspondingly reduced, thereby correspondingly increasing the area of the light-transmitting area of the first display area. When applied to the under-screen optical device solution, the amount of light received by the optical device can be increased.

[0071] In one embodiment, only the first light-shielding layer can be provided to block the first wiring area. In another embodiment, only the second light-shielding layer can also be provided to block the second wiring area.

[0072] The display panel provided by the embodiments of the present application includes a substrate, an array layer above the substrate, and a display layer above the array layer. Among them, the pixel circuit is located in the array layer. The light-shielding layer can be located on the side of the array layer away from the substrate. Alternatively, the light-shielding layer can be located in the display layer, and the display layer includes an anode, a light-emitting layer, and a cathode. The light-shielding layer can be in the same film layer as the anode, and the light-shielding layer can be fabricated in the same etching process as the anode during fabrication. Alternatively, a metal film layer can also be added to the film layer structure of the display panel to fabricate the light-shielding layer separately.

[0073] It should be noted that the display panels provided in any of the above embodiments of the present application can all apply the setting scheme of the light-shielding layer, which will not be elaborated here.

[0074] Based on the same inventive concept, the present application also provides a display device. Figure 15 A schematic diagram of the display device provided by the embodiments of the present application is shown as Figure 15 As described, the display device includes the display panel 100 provided in any of the above embodiments. Among them, the specific structure of the display panel 100 has been described in detail in the above embodiments and will not be elaborated here. Of course, Figure 15The display device shown is only for illustrative purposes, and the display device can be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e - book reader, or a television, etc.

[0075] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

[0076] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display area of the display panel includes a first display area and a second display area, where the second display area surrounds the first display area or semi - surrounds the first display area; the display area includes a plurality of sub - pixels, and the density of the plurality of sub - pixels in the first display area is less than the density of the plurality of sub - pixels in the second display area; The first display area includes a plurality of wiring areas and a plurality of pixel rows extending in a first direction. One pixel row includes a plurality of pixel areas arranged in the first direction. One pixel area includes n sub - pixels and n pixel circuits, where n is a positive integer, and the sub - pixels are electrically connected to the pixel circuits. The plurality of wiring areas include a plurality of first wiring areas, and one first wiring area is located between two adjacent pixel areas in a second direction, and the second direction intersects the first direction; The first display area further includes a plurality of signal lines extending in the second direction. When driving the display panel for display, a constant voltage signal is provided to the signal lines. The signal lines include a first segment and a second segment. The first segment is located in the first wiring area, and the second segment is located in the pixel area. In the pixel area, the second segment is electrically connected to the pixel circuit; where, The pixel row includes adjacent first and second pixel rows. The first pixel row includes N sub - pixels, and the second pixel row includes M sub - pixels. Both N and M are positive integers, and N≤M; the total number of the first segments in the plurality of first wiring areas between the first pixel row and the second pixel row is less than N; Among the plurality of first wiring areas between the first pixel row and the second pixel row, there is a first A wiring area; In the first pixel row and the second pixel row, there is an A pixel area adjacent to the first A wiring area. The A pixel area includes n second segments; where, The first A wiring area includes p first segments, where p is an integer, and n>p≥0; p＝0； The pixel area further includes a connection line, and the connection line includes a second connection line. The second connection line is located in the A pixel area, and the n second segments in the A pixel area are all electrically connected to the second connection line; The wiring area further includes a plurality of second wiring areas, and one second wiring area is located between two adjacent pixel areas in the first direction; The first display area further includes a plurality of auxiliary signal lines extending in the first direction, and a partial segment of the auxiliary signal line is located in the second wiring area; In the first pixel row and the second pixel row, there is also a B pixel area adjacent to the A pixel area, and the A pixel area and the B pixel area are located in the same pixel row; The second segments located in the A pixel area and the B pixel area are electrically connected through the auxiliary signal line.

2. The display panel according to claim 1, wherein, Among the plurality of first wiring areas between the first pixel row and the second pixel row, there is a first B wiring area adjacent to the first A wiring area; The first pixel row and the second pixel row further include: a second pixel region adjacent to the first pixel region, and the second pixel region is adjacent to the first second wiring region; The second pixel region includes n second line segments, and the first second wiring region includes q first line segments, where q is an integer, and n≥q>p.

3. The display panel according to claim 2, wherein q = n; The n second line segments in the second pixel region are respectively electrically connected to the q first line segments located in the first second wiring region.

4. The display panel according to claim 2, wherein q < n; At least two of the second line segments in the second pixel region are electrically connected to the same first line segment in the first second wiring region.

5. The display panel according to claim 4, wherein The pixel region further includes a connection line, and the connection line includes a third connection line; The third connection line is located in the second pixel region, and at least two of the second line segments in the second pixel region are respectively electrically connected to the third connection line through vias, and the same first line segment electrically connected to the at least two second line segments is electrically connected to the third connection line through a via.

6. The display panel according to claim 5, wherein The display region further includes a plurality of scan lines and a plurality of data lines; The pixel circuit further includes a pixel capacitor; The display panel includes a substrate, a first metal layer, a capacitor metal layer, and a second metal layer located on the substrate. The scan line is located in the first metal layer, one plate of the pixel capacitor is located in the capacitor metal layer, and the data line is located in the second metal layer; wherein, The signal line is located in the second metal layer, and the connection line is located in the first metal layer or in the capacitor metal layer; or; The signal line is located in the capacitor metal layer, and the connection line is located in the second metal layer.

7. The display panel according to claim 2, wherein The wiring region further includes a plurality of second wiring regions, and one second wiring region is located between two adjacent pixel regions in the first direction; The first display region further includes a plurality of auxiliary signal lines extending in the first direction, and partial line segments of the auxiliary signal lines are located in the second wiring region; The first pixel region and the second pixel region are located in the same pixel row, and the second line segments respectively located in the first pixel region and the second pixel region are electrically connected through the auxiliary signal lines.

8. The display panel according to claim 7, wherein The display region further includes a plurality of scan lines and a plurality of data lines; The pixel circuit further includes a pixel capacitor; The display panel includes a substrate, a first metal layer, a capacitor metal layer, and a second metal layer located on the substrate. The scan line is located in the first metal layer, one plate of the pixel capacitor is located in the capacitor metal layer, and the data line is located in the second metal layer; wherein, The signal line is located in the second metal layer, and the auxiliary signal line is located in the capacitive metal layer; alternatively, the signal line is located in the capacitive metal layer, and the auxiliary signal line is located in the second metal layer.

9. The display panel according to claim 2, wherein q = 1, p = 0.

10. The display panel according to claim 1, wherein The first display area further includes a light-shielding layer, and in a direction perpendicular to the display panel, the light-shielding layer covers the wiring area.

11. A display device, characterized in that, A display panel including any one of claims 1 to 10.

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