A logic control method of a ferroelectric domain wall device and a logic device

Abstract

An embodiment of the present application provides a logic control method and logic device of a ferroelectric domain wall device, the method comprising: a charged metal probe realizes an equivalent electric field upward in a plane or downward in a plane on a ferroelectric material layer through different scanning methods to realize the input of a high-level logic value "1" or a low-level logic value "0"; the ferroelectric domain wall device, a voltmeter and a power supply are electrically connected to form a first closed loop; when the metal probe scans the ferroelectric material layer in a first direction, the equivalent electric field of the first closed loop is upward, the input is a high-level logic value "1", the domain wall is connected, and the storage state and output value of the ferroelectric domain wall device are recorded as a low-level logic value "0"; when the metal probe scans the ferroelectric material layer in a second direction, the equivalent electric field of the first closed loop is downward, the input is a low-level logic value "0", the domain wall is disconnected, and the storage state and output value of the ferroelectric domain wall device are recorded as a high-level logic value "1".

Description

Technical Field

[0001] The present application relates to the field of computer storage technology, and more specifically, to a logic control method of a ferroelectric domain wall device and a logic device. Background Art

[0002] Current commercial computers use the "von Neumann" architecture, which means that computing and storage are separated. This leads to a lot of redundant time caused by repeated data exchange and speed differences between the two, which is called the "storage wall", and directly leads to a decrease in the computing speed of the entire chip system and an increase in power consumption. In order to solve this problem, new electronic devices that integrate storage and logic operations are currently in demand. Allwood et al. can achieve equivalent logic operations by regulating the magnetic moment in magnetic nanostructures through spatial dynamic magnetic fields, and store the direction of the magnetic moment as information to achieve the integration of storage and operation. However, due to the limitations of the preparation process of magnetic nanowires, a logic unit is currently in the size range of 10μm, which is not conducive to the miniaturization and high-density integration of devices. In addition, the spatial magnetic field control method also has very high energy consumption. At present, Luo et al. use the current-driven spin-orbit coupling in special magnetic multilayer films to realize the flipping process of ferromagnetic domain walls, that is, to control the transition from spin-down to spin-up domain walls to spin-up to spin-down domain walls, and combine nano-etching technology to prepare different magnetic nanostructures, and realize the storage of 0 and 1 information by flipping the magnetic domain walls of different branches with current, and realize different logical operations and the series connection of logical units by selecting the magnetic moments at different positions on the nanowire as input and output signals. However, the planar structure makes the size of a device unit from a few microns to tens of microns, making miniaturization difficult. The current density to drive the domain wall flipping is as high as 10 11 -10 12 A / m 2 , and requires a lot of power consumption.

[0003] Ferroelectric domain walls are conductive, and the electric field can be used to write or erase the domain walls, or to transform the domain walls with low conductivity into domain walls with high conductivity. Based on such experimental phenomena, Sharma, Jiang and others prepared domain wall memories with planar electrodes; Jiang and others prepared transistor structures to generate and erase conductive domain walls, thereby realizing the conversion between the high and low resistance states between the source and drain, and realizing the information storage of 0 and 1; Ma and others prepared domain wall memories with vertical electrode structures. However, the realization of logical operations such as "AND", "OR" and "NOT" based on the regulation of conductive domain walls has not yet been designed and implemented. Summary of the invention

[0004] In view of this, the present application proposes a logic control method of a ferroelectric domain wall device and a logic device.

[0005] In a first aspect, the present application provides a logic control method of a ferroelectric domain wall device, wherein the ferroelectric domain wall device comprises a single crystal substrate layer, a bottom electrode layer and a ferroelectric material layer, and the method comprises:

[0006] The charged metal probe realizes an equivalent electric field upward in the plane or downward in the plane on the ferroelectric material layer through different scanning modes, so as to realize the input of a high-level logic value "1" or a low-level logic value "0";

[0007] The ferroelectric domain wall device, the voltmeter and the power supply are electrically connected to form a first closed loop;

[0008] When the metal probe scans the ferroelectric material layer in a first direction, the equivalent electric field of the first closed loop is upward, the input is the high-level logic value "1", the domain wall is connected, and the storage state and output value of the ferroelectric domain wall device are recorded as the low-level logic value "0";

[0009] When the metal probe scans the ferroelectric material layer in the second direction, the equivalent electric field of the first closed loop is downward, the input is the low-level logic value "0", the domain wall is disconnected, and the storage state and output value of the ferroelectric domain wall device are recorded as the high-level logic value "1".

[0010] In a specific embodiment, the first direction includes a fast scanning direction and a first slow scanning direction; the second direction includes a fast scanning direction and a second slow scanning direction, wherein,

[0011] The fast scanning direction is an alternating scan from left to right and from right to left; the first slow scanning direction is from bottom to top; and the second slow scanning direction is from top to bottom.

[0012] In a second aspect, the present application proposes a logic device manufactured based on the control method described in the first aspect, comprising a first logic component and a second logic component, wherein the equivalent electric field of the first logic component is a first electric field, and the equivalent electric field of the second logic component is a second electric field, wherein:

[0013] The first logic component is electrically connected to the second logic component to form a second closed loop, wherein the second closed loop includes a first input terminal, a second input terminal and an output terminal, wherein:

[0014] The first input terminal is electrically connected to the first logic component and is used to input a first input signal;

[0015] The second input terminal is electrically connected to the second logic component and is used to input a second input signal;

[0016] The output end is electrically connected to the first input end and the second input end, and is used to output the output signal of the second closed loop according to the first input signal and the second input signal, wherein

[0017] The first input signal is related to the first electric field, and the second input signal is related to the second electric field.

[0018] In a specific embodiment, the first logic component includes a first ferroelectric domain wall device, the second logic component includes a second ferroelectric domain wall device, the domain wall morphology of the first ferroelectric domain wall device and the second ferroelectric domain wall device is a first domain wall morphology, the first ferroelectric domain wall device and the second ferroelectric domain wall device are connected in parallel to realize "NOR" logic, wherein,

[0019] When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a low level logic value "0";

[0020] When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a low level logic value "0";

[0021] When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a low level logic value "0";

[0022] When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a high-level logic value "1".

[0023] In a specific embodiment, the first logic component includes a third ferroelectric domain wall device, the second logic component includes a fourth ferroelectric domain wall device, the domain wall morphology of the third ferroelectric domain wall device and the fourth ferroelectric domain wall device is the first domain wall morphology, and the third ferroelectric domain wall device and the fourth ferroelectric domain wall device are connected in series to realize "NAND" logic, wherein,

[0024] When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a low level logic value "0";

[0025] When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a high-level logic value "1";

[0026] When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a high-level logic value "1";

[0027] When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a high-level logic value "1".

[0028] In a specific embodiment, the first logic component includes a fifth ferroelectric domain wall device, the second logic component includes a sixth ferroelectric domain wall device, the fifth ferroelectric domain wall device and the sixth ferroelectric domain wall device are connected in series to realize "OR" logic, wherein,

[0029] When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a high-level logic value "1";

[0030] When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a high-level logic value "1";

[0031] When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a high-level logic value "1";

[0032] When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a low level logic value "0".

[0033] In a specific embodiment, the first logic component includes a seventh ferroelectric domain wall device, the second logic component includes an eighth ferroelectric domain wall device, the seventh ferroelectric domain wall device and the eighth ferroelectric domain wall device are connected in parallel to realize "AND" logic, wherein,

[0034] When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a high-level logic value "1";

[0035] When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a low level logic value "0";

[0036] When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a low level logic value "0";

[0037] When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a low level logic value "0".

[0038] In a specific embodiment, the first logic component includes a ninth ferroelectric domain wall device and a tenth ferroelectric domain wall device, and the second logic component includes an eleventh ferroelectric domain wall device and a twelfth ferroelectric domain wall device, wherein:

[0039] The ninth ferroelectric domain wall device and the eleventh ferroelectric domain wall device are connected in series to form a first intermediate logic component;

[0040] The tenth ferroelectric domain wall device and the twelfth ferroelectric domain wall device are connected in series to form a second intermediate logic component;

[0041] The first intermediate logic component and the second intermediate logic component are connected in parallel to implement an exclusive-OR logic, wherein:

[0042] When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a high-level logic value "1";

[0043] When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a low level logic value "0";

[0044] When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a low level logic value "0";

[0045] When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a high-level logic value "1".

[0046] In a specific embodiment, the first logic component includes a thirteenth ferroelectric domain wall device, a fourteenth ferroelectric domain wall device, a fifteenth ferroelectric domain wall device and a sixteenth ferroelectric domain wall device, and the second logic component includes a seventeenth ferroelectric domain wall device, an eighteenth ferroelectric domain wall device, a nineteenth ferroelectric domain wall device and a twentieth ferroelectric domain wall device.

[0047] The thirteenth ferroelectric domain wall device and the fourteenth ferroelectric domain wall device are connected in series to form a third intermediate logic component, the seventeenth ferroelectric domain wall device and the eighteenth ferroelectric domain wall device are connected in series to form a fourth intermediate logic component; the third intermediate logic component and the fourth intermediate logic component are connected in parallel to form a fifth intermediate logic component;

[0048] The fifteenth ferroelectric domain wall device and the sixteenth ferroelectric domain wall device are connected in series to form a sixth intermediate logic component, the nineteenth ferroelectric domain wall device and the twentieth ferroelectric domain wall device are connected in series to form a seventh intermediate logic component; the sixth intermediate logic component and the seventh intermediate logic component are connected in parallel to form an eighth intermediate logic component;

[0049] The fifth intermediate logic component and the eighth intermediate logic component are connected in series to implement "XOR" logic, wherein,

[0050] When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a low level logic value "0";

[0051] When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a high-level logic value "1";

[0052] When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a high-level logic value "1";

[0053] When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a low level logic value "0".

[0054] In a specific embodiment, it is characterized in that the domain wall morphology of the fifth ferroelectric domain wall device to the twentieth ferroelectric domain wall device is the second domain wall morphology.

[0055] The beneficial effects of this application are as follows:

[0056] In response to the current existing problems, the present application proposes a logic control method and logic device of a ferroelectric domain wall device, which realizes a device integrating storage and logic operations based on a controllable ferroelectric conductive domain wall network, and further realizes logic function devices such as AND, OR, NOT, AND-NON, OR-NON, XOR and XNOR, which makes up for the problems of the prior art and has broad application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0058] Figure 1 A schematic diagram showing a logic control method of a ferroelectric domain wall device according to an embodiment of the present application.

[0059] Figure 2 A schematic diagram showing the current when the domain wall is connected and disconnected according to an embodiment of the present application.

[0060] Figure 3 A schematic diagram showing the connection and disconnection of domain walls when the electric field is switched according to an embodiment of the present application.

[0061] Figure 4 A schematic structural diagram of an OR-NOT logic device according to an embodiment of the present application is shown.

[0062] Figure 5 A schematic structural diagram of a NAND logic device according to an embodiment of the present application is shown.

[0063] Figure 6 A schematic diagram showing a second domain wall morphology according to an embodiment of the present application.

[0064] Figure 7 A schematic diagram of the structure of an OR logic device according to an embodiment of the present application is shown.

[0065] Figure 8 A schematic structural diagram of an AND logic device according to an embodiment of the present application is shown.

[0066] Fig. 9 A schematic structural diagram of an XNOR logic device according to an embodiment of the present application is shown.

[0067] Fig.10 A schematic structural diagram of an XOR logic device according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0068] In order to more clearly illustrate the present application, the present application is further described below in conjunction with preferred embodiments and drawings. Similar components in the drawings are represented by the same reference numerals. It should be understood by those skilled in the art that the content described below is illustrative rather than restrictive, and should not be used to limit the scope of protection of the present application.

[0069] The latest ferroelectric domain wall-based logic function unit is the ferroelectric domain wall transistor, which uses the gate voltage to generate and eliminate the conductive domain wall between the source and the drain, and uses the presence or absence of the conductive domain wall to achieve high and low resistance states. Although this method can achieve the regulation of the two resistance states of "0" and "1", it still cannot achieve basic logical operations such as "and", "or" and "not".

[0070] To this end, an embodiment of the present application proposes a logic control method for a ferroelectric domain wall device, such as Figure 1 As shown, from bottom to top, the ferroelectric domain wall device includes a single crystal substrate layer 3, a bottom electrode layer 2 and a ferroelectric material layer 1, wherein the single crystal substrate layer 3 can be lanthanum aluminate LaAlO3, strontium titanate SrTiO3, the bottom electrode layer can be (La, Sr)MnO3, SrRuO3, and the ferroelectric material layer is BiFeO3. The method includes the following steps:

[0071] First, the ferroelectric domain wall device, a voltage meter and a power supply are electrically connected to form a Figure 1 C and Figure 1 The first closed loop shown in E.

[0072] Furthermore, the charged metal probe realizes an equivalent electric field upward or downward in the plane on the ferroelectric material layer through different scanning methods to realize the input of high-level logic value "1" or low-level logic value "0"; the voltage of the two domain wall resistors is measured by a voltmeter to realize the storage and output of low-level logic value "0" or high-level logic value "1".

[0073] When the metal probe scans the ferroelectric material layer in a first direction, the equivalent electric field of the first closed loop is upward, the input is the high-level logic value "1", the domain wall is connected, and the storage state and output value of the ferroelectric domain wall device are recorded as the low-level logic value "0";

[0074] When the metal probe scans the ferroelectric material layer in the second direction, the equivalent electric field of the first closed loop is downward, the input is the low-level logic value "0", the domain wall is disconnected, and the storage state and output value of the ferroelectric domain wall device are recorded as the high-level logic value "1".

[0075] Among them, Figure 1 As shown, the first direction includes a fast scanning direction and a first slow scanning direction; the second direction includes a fast scanning direction and a second slow scanning direction, wherein the fast scanning direction is an alternating scan from left to right and from right to left; the first slow scanning direction is from bottom to top; and the second slow scanning direction is from top to bottom.

[0076] For details, see Figure 2A, when the metal probe scans alternately from left to right and from right to left, and from bottom to top, the equivalent electric field is upward, and the upward equivalent electric field is recorded as the

[110] electric field. The input is regarded as the high-level logic value "1", the domain wall is connected, and the domain wall between the two electrodes has high conductivity. The equivalent current of the first closed loop is a large current, wherein the value of the equivalent current can be obtained by Figure 1 The current meter in the Figure 2 C shows about 12nA. At this time, the storage state and output value of the ferroelectric domain wall device are the low-level logic value "0". Figure 2 B, when the metal probe scans alternately from left to right and from right to left,

[0077] When scanning from top to bottom, the equivalent electric field is downward, and the downward equivalent electric field is recorded as , the input is regarded as the low-level logic value "0", the electric field domain wall is disconnected, there is low conductivity between the two electrodes, and the equivalent current of the first closed loop is a small current, such as Figure 2 D shows that it is approximately 2 nA. At this time, the storage state and output value of the ferroelectric domain wall device are the high-level logic value "1".

[0078] That is, the metal probe is adjusted by different scanning methods such as Figure 1 The connection or disconnection of a single domain wall is shown, thereby achieving regulation of the conductivity of a single ferroelectric domain wall device.

[0079] Further, if Figure 3 As shown, a metal probe is used to repeatedly switch the direction of the electric field on the ferroelectric material layer through different scanning methods to realize the input of low-level logic value "0" and high-level logic value "1". When the metal probe scans on the ferroelectric material layer in a first direction, the equivalent electric field of the first closed loop is upward, the input is the high-level logic value "1", the domain wall is connected, and the storage state and output value of the ferroelectric domain wall device are recorded as the low-level logic value "0"; when the metal probe scans on the ferroelectric material layer in a second direction, the equivalent electric field of the first closed loop is downward, the input is the low-level logic value "0", the domain wall is disconnected, and the storage state and output value of the ferroelectric domain wall device are recorded as the high-level logic value "1".

[0080] Specifically, Figure 3 A domain wall is connected. When the electric field Figure 3 B domain wall is disconnected; further, when the

[110] electric field is applied, Figure 3 C domain wall is connected, based on similar principles, Figure 3 D. Figure 3 E

[0081] and Figure 3F will not be described in detail. The metal probe is applied alternately in the plane The equivalent electric field in the

[110] direction can effectively control the “connectivity” and “disconnectivity” of different conductive domain walls.

[0082] In this embodiment, the metal probe is scanned in different ways on the ferroelectric material layer to generate equivalent electric fields in different directions, thereby realizing the connection and disconnection of the domain wall. That is to say, for the ferroelectric domain wall device, when the generated equivalent electric field is regarded as the input, the voltage value of the domain wall resistance corresponding to the connection and disconnection of the domain wall is recorded as the output, where different inputs correspond to different outputs, for example, Figure 1 As shown in C, when the equivalent electric field is upward, the input is regarded as a high-level logic value "1", the domain wall is connected, and the two electrodes of the domain wall have high conductivity. The closed loop generates a large current and a small voltage, and the output is regarded as a low-level logic value "0"; Figure 1 As shown in E, when the equivalent electric field is downward, the input is regarded as a low-level logic value "0", the domain wall is disconnected, and the two electrodes of the domain wall have low conductivity. The closed loop generates a small current and a large voltage, and the output is regarded as a high-level logic value "1". In other words, one input can correspond to one output, realizing the logic operation function and achieving the purpose of integrating logic and storage.

[0083] Based on this, the above-mentioned method for regulating the conductivity of ferroelectric domain walls can be used to design logic units, and can realize "not", "not-or", "not-and", "or", "and", "xor" and "xor" logical operations.

[0084] To this end, another embodiment of the present application proposes a logic device manufactured based on the control method described in the above embodiment, the logic device includes a first logic component and a second logic component, the equivalent electric field of the first logic component is a first electric field, and the equivalent electric field of the second logic component is a second electric field, wherein,

[0085] The first logic component is electrically connected to the second logic component to form a second closed loop, wherein the second closed loop includes a first input terminal, a second input terminal and an output terminal, wherein:

[0086] The first input terminal is electrically connected to the first logic component and is used to input a first input signal;

[0087] The second input terminal is electrically connected to the second logic component and is used to input a second input signal;

[0088] The output end is electrically connected to the first input end and the second input end, and is used to output an output signal of the second closed loop according to the first input signal and the second input signal.

[0089] Those skilled in the art can understand that the first input signal is related to the first electric field, and the second input signal is related to the second electric field.

[0090] This embodiment realizes the design of logic devices by connecting ferroelectric domain wall devices in series or in parallel under electric fields in different directions.

[0091] In an alternative approach, Figure 4 As shown, the first logic component includes a first ferroelectric domain wall device, the second logic component includes a second ferroelectric domain wall device, the domain wall morphology of the first ferroelectric domain wall device and the second ferroelectric domain wall device is a first domain wall morphology, wherein the first ferroelectric domain wall morphology is as follows Figure 2 As shown in A, this embodiment takes the connection and disconnection of the domain wall in the

[100] direction as an example for explanation. The first ferroelectric domain wall device and the second ferroelectric domain wall device are connected in parallel to realize the "NOR" logic, wherein,

[0092] like Figure 4 A, when the first electric field is upward and the second electric field is upward, the first input signal E1 is "1", the second input signal E2 is "1", and the output signal V is a low level logic value "0";

[0093] like Figure 4 B, when the first electric field is upward and the second electric field is downward, the first input signal E1 is "1", the second input signal E2 is "0", and the output signal V is a low level logic value "0";

[0094] like Figure 4 C, when the first electric field is downward and the second electric field is upward, the first input signal E1 is "0", the second input signal E2 is "1", and the output signal V is a low level logic value "0";

[0095] like Figure 4 D. When the first electric field is downward and the second electric field is downward, the first input signal E1 is "0", the second input signal E2 is "0", and the output signal V is a high-level logic value "1".

[0096] Specifically, the truth table logic of the "NOR" logic device is shown in Table 1.

[0097] Table 1

[0098] Domain wall morphology The first input signal E1 The second input signal E2 Output signal V Figure A 1 1 0 Figure B 1 0 0 Figure C 0 1 0 Figure D 0 0 1

[0099] In yet another alternative, if Figure 5As shown, the first logic component includes a third ferroelectric domain wall device, the second logic component includes a fourth ferroelectric domain wall device, the domain wall morphology of the third ferroelectric domain wall device and the fourth ferroelectric domain wall device is the first domain wall morphology, and the third ferroelectric domain wall device and the fourth ferroelectric domain wall device are connected in series to realize "NAND" logic, wherein,

[0100] like Figure 5 A, when the first electric field is upward and the second electric field is upward, the first input signal E1 is "1", the second input signal E2 is "1", and the output signal V is a low level logic value "0";

[0101] like Figure 5 B, when the first electric field is upward and the second electric field is downward, the first input signal E1 is "1", the second input signal E2 is "0", and the output signal V is a high-level logic value "1";

[0102] like Figure 5 C, when the first electric field is downward and the second electric field is upward, the first input signal E1 is "0", the second input signal E2 is "1", and the output signal V is a high-level logic value "1";

[0103] like Figure 5 D. When the first electric field is downward and the second electric field is downward, the first input signal E1 is "0", the second input signal E2 is "0", and the output signal V is a high-level logic value "1".

[0104] Specifically, the truth table logic of the "NAND" logic device is shown in Table 2.

[0105] Table 2

[0106]

[0107]

[0108] For the four-lobed domains of BiFeO3 nanoislands, by applying The electric field in the

[110] direction can effectively control the "connection" and "disconnection" of the two conductive paths. At this time, the domain wall of the ferroelectric domain wall device is Figure 6 The second domain wall morphology is shown.

[0109] See also Figure 6 , nano-ferroelectric domain wall in electric field The conductive state diagrams of "on" and "off" between different electrodes are realized under

[110] and

[110] respectively. Figure 6 A is the high resistance state corresponding to when all polarizations in the ferroelectric nano-islands are facing downward. Figure 6 B. Figure 6C and Figure 6 Figure D corresponds to the morphology of the conductive domain wall network in the ferroelectric nano-island after applying electric fields in different directions. Figure 6 B means that all electrodes (A'B', C'D', A'C' and B'D') are in conduction state; Figure 6 C means the A'B' electrodes are in a conducting state, and the other electrodes (C'D', A'C' and B'D') are in a non-conducting state; Figure 6 D is the conductive state between C'D', and the non-conductive state between the other electrodes (A'B', A'C' and B'D'). It should be noted that the ferroelectric domain wall devices in the following examples can all be equivalent to the second domain wall form, thereby realizing the connection or disconnection of the two conductive paths.

[0110] In yet another alternative, if Figure 7 As shown, the first logic component includes a fifth ferroelectric domain wall device, the second logic component includes a sixth ferroelectric domain wall device, the fifth ferroelectric domain wall device and the sixth ferroelectric domain wall device are connected in series to realize "OR" logic, wherein,

[0111] like Figure 7 A, when the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a high-level logic value "1";

[0112] like Figure 7 B, when the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a high-level logic value "1";

[0113] like Figure 7 C, when the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a high-level logic value "1";

[0114] like Figure 7 D. When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a low level logic value "0".

[0115] Specifically, the truth table logic of the "OR" logic device is shown in Table 3.

[0116] Table 3

[0117] Domain wall morphology The first input signal E1 The second input signal E2 Output signal V Figure A 1 1 1 Figure B 1 0 1 Figure C 0 1 1 Figure D 0 0 0

[0118] In yet another alternative, if Figure 8As shown, the first logic component includes a seventh ferroelectric domain wall device, the second logic component includes an eighth ferroelectric domain wall device, the seventh ferroelectric domain wall device and the eighth ferroelectric domain wall device are connected in parallel to realize "AND" logic, wherein,

[0119] like Figure 8 A, when the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a high-level logic value "1";

[0120] like Figure 8 B, when the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a low level logic value "0";

[0121] like Figure 8 C, when the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a low level logic value "0";

[0122] like Figure 8 D. When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a low level logic value "0".

[0123] Specifically, the truth table logic of the “AND” logic device is shown in Table 4.

[0124] Table 4

[0125] Domain wall morphology The first input signal E1 The second input signal E2 Output signal V Figure A 1 1 1 Figure B 1 0 0 Figure C 0 1 0 Figure D 0 0 0

[0126] In yet another alternative, if Fig. 9 As shown, the first logic component includes a ninth ferroelectric domain wall device and a tenth ferroelectric domain wall device, and the second logic component includes an eleventh ferroelectric domain wall device and a twelfth ferroelectric domain wall device,

[0127] Wherein, the ninth ferroelectric domain wall device and the eleventh ferroelectric domain wall device are connected in series to form a first intermediate logic component;

[0128] The tenth ferroelectric domain wall device and the twelfth ferroelectric domain wall device are connected in series to form a second intermediate logic component;

[0129] The first intermediate logic component and the second intermediate logic component are connected in parallel to implement an exclusive-OR logic.

[0130] like Fig. 9A, when the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a high-level logic value "1";

[0131] like Fig. 9 B, when the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a low level logic value "0";

[0132] like Fig. 9 C, when the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a low level logic value "0";

[0133] like Fig. 9 D. When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a high-level logic value "1".

[0134] Specifically, the truth table logic of the "XOR" logic device is shown in Table 5.

[0135] Table 5

[0136] Domain wall morphology The first input signal E1 The second input signal E2 Output signal V Figure A 1 1 1 Figure B 1 0 0 Figure C 0 1 0 Figure D 0 0 1

[0137] In yet another alternative, if Fig.10 As shown, the first logic component includes a thirteenth ferroelectric domain wall device, a fourteenth ferroelectric domain wall device, a fifteenth ferroelectric domain wall device and a sixteenth ferroelectric domain wall device, and the second logic component includes a seventeenth ferroelectric domain wall device, an eighteenth ferroelectric domain wall device, a nineteenth ferroelectric domain wall device and a twentieth ferroelectric domain wall device,

[0138] The thirteenth ferroelectric domain wall device and the fourteenth ferroelectric domain wall device are connected in series to form a third intermediate logic component, the seventeenth ferroelectric domain wall device and the eighteenth ferroelectric domain wall device are connected in series to form a fourth intermediate logic component; the third intermediate logic component and the fourth intermediate logic component are connected in parallel to form a fifth intermediate logic component;

[0139] The fifteenth ferroelectric domain wall device and the sixteenth ferroelectric domain wall device are connected in series to form a sixth intermediate logic component, the nineteenth ferroelectric domain wall device and the twentieth ferroelectric domain wall device are connected in series to form a seventh intermediate logic component; the sixth intermediate logic component and the seventh intermediate logic component are connected in parallel to form an eighth intermediate logic component;

[0140] The fifth intermediate logic component and the eighth intermediate logic component are connected in series to implement "XOR" logic, wherein,

[0141] like Fig.10 A, when the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a low level logic value "0";

[0142] like Fig.10 B, when the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a high-level logic value "1";

[0143] like Fig.10 C, when the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a high-level logic value "1";

[0144] like Fig.10 D. When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a low level logic value "0".

[0145] Specifically, the truth table logic of the "XOR" logic device is shown in Table 6

[0146] Table 6

[0147] Domain wall morphology The first input signal E1 The second input signal E2 Output signal V Figure A 1 1 0 Figure B 1 0 1 Figure C 0 1 1 Figure D 0 0 0

[0148] In the description of the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements limited by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0149] Obviously, the above embodiments of the present application are merely examples for clearly illustrating the present application, and are not limitations on the implementation methods of the present application. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present application are still within the scope of protection of the present application.

Claims

1. A logic control method for a ferroelectric domain wall device, wherein the ferroelectric domain wall device comprises a single crystal substrate layer, a bottom electrode layer and a ferroelectric material layer, characterized in that: include: The charged metal probe realizes an equivalent electric field upward in the plane or downward in the plane on the ferroelectric material layer through different scanning modes, so as to realize the input of a high-level logic value "1" or a low-level logic value "0"; The ferroelectric domain wall device, the voltmeter and the power supply are electrically connected to form a first closed loop; When the metal probe scans the ferroelectric material layer in a first direction, the equivalent electric field of the first closed loop is upward, the input is the high-level logic value "1", the domain wall is connected, and the storage state and output value of the ferroelectric domain wall device are recorded as the low-level logic value "0"; When the metal probe scans the ferroelectric material layer in the second direction, the equivalent electric field of the first closed loop is downward, the input is the low-level logic value "0", the domain wall is disconnected, and the storage state and output value of the ferroelectric domain wall device are recorded as the high-level logic value "1".

2. The method according to claim 1, characterized in that The first direction includes a fast scanning direction and a first slow scanning direction; the second direction includes a fast scanning direction and a second slow scanning direction, wherein, The fast scanning direction is an alternating scan from left to right and from right to left; the first slow scanning direction is from bottom to top; and the second slow scanning direction is from top to bottom.

3. A logic device manufactured based on the control method according to any one of claims 1 to 2, characterized in that: It includes a first logic component and a second logic component, the equivalent electric field of the first logic component is a first electric field, and the equivalent electric field of the second logic component is a second electric field, wherein: The first logic component is electrically connected to the second logic component to form a second closed loop, wherein the second closed loop includes a first input terminal, a second input terminal and an output terminal, wherein: The first input terminal is electrically connected to the first logic component and is used to input a first input signal; The second input terminal is electrically connected to the second logic component and is used to input a second input signal; The output end is electrically connected to the first input end and the second input end, and is used to output the output signal of the second closed loop according to the first input signal and the second input signal, wherein The first input signal is related to the first electric field, and the second input signal is related to the second electric field.

4. The logic device according to claim 3, characterized in that: The first logic component includes a first ferroelectric domain wall device, the second logic component includes a second ferroelectric domain wall device, the domain wall morphology of the first ferroelectric domain wall device and the second ferroelectric domain wall device is the first domain wall morphology, the first ferroelectric domain wall device and the second ferroelectric domain wall device are connected in parallel to realize "NOR" logic, wherein, When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a low level logic value "0"; When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a low level logic value "0"; When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a low level logic value "0"; When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "0", and the output signal is a high-level logic value "1".

5. The logic device according to claim 3, characterized in that: The first logic component includes a third ferroelectric domain wall device, the second logic component includes a fourth ferroelectric domain wall device, the domain wall morphology of the third ferroelectric domain wall device and the fourth ferroelectric domain wall device is the first domain wall morphology, the third ferroelectric domain wall device and the fourth ferroelectric domain wall device are connected in series to realize "NAND" logic, wherein, When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a low level logic value "0"; When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a high-level logic value "1"; When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a high-level logic value "1"; When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "0", and the output signal is a high-level logic value "1".

6. The logic device according to claim 3, characterized in that: The first logic component includes a fifth ferroelectric domain wall device, the second logic component includes a sixth ferroelectric domain wall device, the fifth ferroelectric domain wall device and the sixth ferroelectric domain wall device are connected in series to realize "OR" logic, wherein, When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a high-level logic value "1"; When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a high-level logic value "1"; When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a high-level logic value "1"; When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a low level logic value "0".

7. The logic device according to claim 3, characterized in that: The first logic component includes a seventh ferroelectric domain wall device, the second logic component includes an eighth ferroelectric domain wall device, the seventh ferroelectric domain wall device and the eighth ferroelectric domain wall device are connected in parallel to realize "AND" logic, wherein, When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a high-level logic value "1"; When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a low level logic value "0"; When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a low level logic value "0"; When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a low level logic value "0".

8. The logic device according to claim 3, characterized in that: The first logic component includes a ninth ferroelectric domain wall device and a tenth ferroelectric domain wall device, and the second logic component includes an eleventh ferroelectric domain wall device and a twelfth ferroelectric domain wall device, wherein: The ninth ferroelectric domain wall device and the eleventh ferroelectric domain wall device are connected in series to form a first intermediate logic component; The tenth ferroelectric domain wall device and the twelfth ferroelectric domain wall device are connected in series to form a second intermediate logic component; The first intermediate logic component and the second intermediate logic component are connected in parallel to implement an exclusive-OR logic, wherein: When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a high-level logic value "1"; When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a low level logic value "0"; When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a low level logic value "0"; When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "0", and the output signal is a high-level logic value "1".

9. The logic device according to claim 3, characterized in that: The first logic component includes a thirteenth ferroelectric domain wall device, a fourteenth ferroelectric domain wall device, a fifteenth ferroelectric domain wall device and a sixteenth ferroelectric domain wall device, and the second logic component includes a seventeenth ferroelectric domain wall device, an eighteenth ferroelectric domain wall device, a nineteenth ferroelectric domain wall device and a twentieth ferroelectric domain wall device, The thirteenth ferroelectric domain wall device and the fourteenth ferroelectric domain wall device are connected in series to form a third intermediate logic component, the seventeenth ferroelectric domain wall device and the eighteenth ferroelectric domain wall device are connected in series to form a fourth intermediate logic component; the third intermediate logic component and the fourth intermediate logic component are connected in parallel to form a fifth intermediate logic component; The fifteenth ferroelectric domain wall device and the sixteenth ferroelectric domain wall device are connected in series to form a sixth intermediate logic component, the nineteenth ferroelectric domain wall device and the twentieth ferroelectric domain wall device are connected in series to form a seventh intermediate logic component; the sixth intermediate logic component and the seventh intermediate logic component are connected in parallel to form an eighth intermediate logic component; The fifth intermediate logic component and the eighth intermediate logic component are connected in series to implement "XOR" logic, wherein, When the first electric field is upward and the second electric field is upward, the first input signal is "1", the second input signal is "1", and the output signal is a low level logic value "0"; When the first electric field is upward and the second electric field is downward, the first input signal is "1", the second input signal is "0", and the output signal is a high-level logic value "1"; When the first electric field is downward and the second electric field is upward, the first input signal is "0", the second input signal is "1", and the output signal is a high-level logic value "1"; When the first electric field is downward and the second electric field is downward, the first input signal is "0", the second input signal is "0", and the output signal is a low level logic value "0".

10. The logic device according to claim 6, characterized in that: The domain wall morphology of the fifth ferroelectric domain wall device and the sixth ferroelectric domain wall device is the second domain wall morphology.

11. The logic device according to claim 7, characterized in that: The domain wall morphology of the seventh ferroelectric domain wall device and the eighth ferroelectric domain wall device is the second domain wall morphology.

12. The logic device according to claim 8, characterized in that: The domain wall morphology of the ninth ferroelectric domain wall device, the tenth ferroelectric domain wall device, the eleventh ferroelectric domain wall device and the twelfth ferroelectric domain wall device is the second domain wall morphology.

13. The logic device according to claim 9, characterized in that: The domain wall morphology of the thirteenth ferroelectric domain wall device, the fourteenth ferroelectric domain wall device, the fifteenth ferroelectric domain wall device, the sixteenth ferroelectric domain wall device, the seventeenth ferroelectric domain wall device, the eighteenth ferroelectric domain wall device, the nineteenth ferroelectric domain wall device and the twentieth ferroelectric domain wall device is the second domain wall morphology.

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